Power consumption determination method and device, chip, equipment, storage medium and program product

Abstract

The invention provides a power consumption determination method and device, a chip, equipment, a storage medium and a program product. The power consumption determination method comprises the following steps: acquiring process parameters, current operating voltage and current operating temperature of a chip; determining first static power consumption of the chip under a reference voltage and a reference temperature based on the process parameters; compensating the first static power consumption based on the difference between the current operating voltage and the reference voltage to obtain second static power consumption of the chip under the current operating voltage and the reference temperature; and obtaining equivalent activation energy under the current operation voltage, and determining target static power consumption of the chip under the current operation voltage and the current operation temperature based on the equivalent activation energy under the current operation voltage, the second static power consumption and the current operation temperature.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip technical field, and particularly to a power consumption determination method and device, a chip, an equipment, a storage medium and a computer program product. BACKGROUND

[0002] In modern integrated circuit design, power consumption management is an important link to improve chip energy efficiency and system stability. Static power consumption, as an important part of total chip power consumption, is significantly affected by factors such as process, voltage (PVT) during chip operation. Especially in high-performance chips such as GPUs, with the wide application of dynamic voltage frequency adjustment (DVFS) technology, static power consumption fluctuates with the change of operating conditions, which brings challenges to power consumption prediction and management.

[0003] In the prior art, a common method is to uniformly estimate based on the maximum static power consumption under the worst working condition. This method is simple to implement, but ignores the influence of chip individual differences and operating state changes, which may easily lead to power consumption evaluation deviation. Another solution is to use a prediction method based on a machine learning model, which estimates static power consumption by inputting chip feature parameters. Although it has high precision in theory, it has high model complexity and large computing resource occupation, which is difficult to meet the real-time and lightweight requirements of embedded systems. SUMMARY

[0004] The embodiments of the present application provide a power consumption determination method, device, chip, equipment, storage medium and computer program product, which can simplify the power consumption prediction path, reduce the computing complexity and improve the deployment flexibility.

[0005] The technical solutions of the embodiments of the present application are as follows: The embodiments of the present application provide a power consumption determination method, which comprises: obtaining process parameters, current operating voltage and current operating temperature of a chip; determining a first static power consumption of the chip under a reference voltage and a reference temperature based on the process parameters; compensating the first static power consumption based on the difference between the current operating voltage and the reference voltage to obtain a second static power consumption of the chip under the current operating voltage and the reference temperature; obtaining an equivalent activation energy under the current operating voltage, and determining a target static power consumption of the chip under the current operating voltage and the current operating temperature based on the equivalent activation energy under the current operating voltage, the second static power consumption and the current operating temperature.

[0006] The embodiment of the present application provides a power consumption determination device, the device comprises: an acquisition module, used for acquiring process parameters, a current running voltage and a current running temperature of a chip; a power consumption determination module, used for determining a first static power consumption of the chip under a reference voltage and a reference temperature based on the process parameters; compensating the first static power consumption based on a difference between the current running voltage and the reference voltage to obtain a second static power consumption of the chip under the current running voltage and the reference temperature; acquiring an equivalent activation energy under the current running voltage, and determining a target static power consumption of the chip under the current running voltage and the current running temperature based on the equivalent activation energy under the current running voltage, the second static power consumption and the current running temperature.

[0007] The embodiment of the present application provides a chip, which is used for executing the power consumption determination method.

[0008] The embodiment of the present application provides a computer device, comprising a memory and a processor, the memory stores a computer program capable of running on the processor, and the processor implements part or all steps of the above method when executing the program.

[0009] The embodiment of the present application provides a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement part or all steps of the above method.

[0010] The embodiment of the present application provides a computer program product, comprising a computer program or instructions, and the computer program or instructions are executed by a processor to implement part or all steps of the above method.

[0011] The embodiment of the present application has the following beneficial effects: through a three-stage modeling method (reference power consumption fitting, voltage compensation modeling and temperature correction modeling), high-precision and low-complexity prediction of chip static power consumption is realized. The power consumption determination method provided by the embodiment of the present application not only considers chip individual differences (such as SIDD), but also can adapt to dynamic changes of voltage and temperature, and has good engineering practicability and deployment flexibility. Compared with the prior art, the power consumption determination method provided by the embodiment of the present application has significant advantages in prediction accuracy, calculation efficiency, deployment cost and the like, and is suitable for application scenarios such as GPU, AI chip and the like which have high requirements for power consumption control. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 The implementation flowchart of the power consumption determination method provided by the embodiment of the present application is shown Figure 1 ; Figure 2 The construction flowchart of the static power consumption model provided by the embodiment of the present application is shown Figure 3A data model schematic diagram of a first model provided for an embodiment of the present application; Figure 4 A data model schematic diagram of a second model provided for an embodiment of the present application; Figure 5 A data model schematic diagram of a third model provided for an embodiment of the present application; Figure 6 A component structure schematic diagram of a power consumption determination device provided for an embodiment of the present application; Figure 7 A hardware entity schematic diagram of a computer device provided for an embodiment of the present application. DETAILED DESCRIPTION

[0013] In order to make the purpose, technical scheme and advantages of the present application clearer, the present application will be described in further detail below with reference to the drawings, and the described embodiments should not be regarded as limiting the present application, and all other embodiments obtained by those of ordinary skill in the art without making creative efforts fall within the scope of protection of the present application.

[0014] The above is only an embodiment of the present application and is not used to limit the protection scope of the present application. Any modification, equivalent replacement and improvement made within the spirit and scope of the present application shall fall within the protection scope of the present application.

[0015] The mainstream methods of current chip static power consumption prediction mainly include two types: One is to use a fixed maximum static power consumption value as a reference, that is, in the chip design or tape-out test stage, the leakage power obtained by simulation or actual test at the worst working point (for example, 125℃, 1.0V) is selected as a unified reference value in the chip power consumption management strategy. This method is simple to implement and low in cost, but it cannot reflect the process differences between individual chips and cannot adapt to the dynamic changes of chip runtime voltage and temperature, so it is easy to cause power consumption evaluation deviation and resource waste in actual application, especially in GPU chips with large power consumption, which will lead to excessive performance waste.

[0016] The other is to construct a static power consumption prediction model based on a machine learning model, to realize the prediction of leakage power by taking a plurality of chip feature parameters as input. This method has high prediction accuracy in theory and is suitable for various PVT conditions, but its model is complex, the calculation amount is large, and the delay is high, which will occupy a large amount of resources when deployed in the chip firmware, affecting the real-time performance and scalability of the power consumption management system.

[0017] In summary, the existing solutions show a polarized tendency in engineering deployment: either simple but conservative, with low prediction accuracy; or accurate but high in computational resource consumption, making it difficult to balance the lightweight, real-time and individualized requirements in actual use scenarios.

[0018] The embodiment of the present application provides a power consumption determination method, which can be executed by a processor of a computer device. The computer device can be a server, a notebook computer, a tablet computer, a desktop computer, a smart television, a set-top box, a mobile device (such as a mobile phone, a portable video player, a personal digital assistant, a dedicated message device, a portable game device) and the like.

[0019] Figure 1 An implementation process of the power consumption determination method provided by the embodiment of the present application is shown Figure 1 As shown in the method, the following steps S101 to S104 are included: Figure 1 Step S101, obtaining process parameters, a current running voltage and a current running temperature of a chip. Step S101, obtaining process parameters, a current running voltage and a current running temperature of a chip.

[0020] The process parameters are parameters reflecting the individual manufacturing process characteristics of the chip in the chip manufacturing process, such as source-drain breakdown current (SIDD) and the like. The process parameters can reflect the different characteristics of the chip due to process differences during manufacturing, which has an impact on the static power consumption of the chip. The current running voltage is the real-time voltage value provided by the power supply circuit of the chip during actual work. The voltage value dynamically changes with factors such as the working mode of the chip, the load condition and the power management strategy. The current running temperature is the real-time temperature value reached by the chip inside or on the surface during operation. The chip generates heat when current passes through transistors and other elements during operation, causing the temperature to rise.

[0021] In some embodiments, the process parameters, the current running voltage and the current running temperature can be obtained by a processing unit in the chip (processor), and the target static power consumption is calculated. The voltage sensor, the temperature sensor and the circuit module for storing and transmitting the process parameters are integrated in the chip in advance. The voltage sensor monitors the power supply voltage of the chip in real time and transmits the voltage signal to the processing unit. The temperature sensor senses the temperature of the chip in real time and also transmits the temperature signal to the processing unit. The process parameters can be directly stored in a specific storage area of the chip after the chip manufacturing is completed, and the processing unit reads the process parameters from the specific storage area.

[0022] Step S102, determining a first static power consumption of the chip at a reference voltage and a reference temperature based on the process parameters.

[0023] The reference voltage is a standard voltage value used for calculation and reference in the embodiments of the present application, and can be a fixed voltage representative in the chip working range, for example, 700 mV, used to establish an initial reference model of the chip static power consumption, facilitating subsequent calculation and derivation of the static power consumption under different working conditions. The reference temperature is a standard temperature value used for calculation and reference in the embodiments of the present application, and can be a common chip working environment temperature, for example, 25 DEG C, used to construct an initial reference model of the chip static power consumption, providing a basis for calculating the chip static power consumption under different temperature conditions.

[0024] In some embodiments, the static power consumption (including the first static power consumption, the second static power consumption, etc.) mentioned in the embodiments of the present application refers to the power consumption of the chip in a static state, i.e., when no data operation and processing is performed, also known as leakage power (Leakage Power), mainly caused by the leakage current of the transistor, and will change with the change of the process, working voltage and temperature of the chip and other factors.

[0025] In some embodiments, a mathematical model of the process parameters and the static power consumption can be established as the first model by analyzing the static power consumption of the chip under the reference voltage and the reference temperature under different process parameters through a large amount of experimental data in advance. Then, after obtaining the process parameters of the chip, the process parameters are substituted into the established first model, and the first static power consumption of the chip under the reference voltage and the reference temperature is calculated. For example, assuming that the SIDD of a certain chip is 10 mA, the first static power consumption of the chip under 700 mV and 25 DEG C is calculated as 5 W according to the first model.

[0026] In step S103, the first static power consumption is compensated based on the difference between the current operating voltage and the reference voltage, to obtain the second static power consumption of the chip under the current operating voltage and the reference temperature.

[0027] Here, the second static power consumption is the static power consumption value of the chip under the current operating voltage and the reference temperature, which is obtained by compensating the first static power consumption considering the difference between the current operating voltage and the reference voltage. It can be understood that the first static power consumption of the reference is adjusted according to the difference between the current operating voltage and the reference voltage, so that the compensation step can reflect the influence of the voltage change on the static power consumption.

[0028] In some embodiments, the function relationship between the static power consumption change rate caused by unit voltage change and the process parameters can be determined in advance through experiments. After the current operating voltage and the reference voltage are obtained, the voltage difference between the current operating voltage and the reference voltage is calculated. According to the process parameters and the above function relationship, the static power consumption change corresponding to the voltage difference is calculated. The first static power consumption is added (or subtracted, depending on the positive or negative of the change rate) by the change to obtain the second static power consumption of the chip at the current operating voltage and the reference temperature.

[0029] Exemplarily, it is assumed that through experiments, the relationship between the static power consumption increase and SIDD is ΔP = k × SIDD (where k is a coefficient) when the unit voltage is increased by 1 millivolt. When the reference voltage is 700 millivolts, the current operating voltage is 800 millivolts, the difference is 100 millivolts, and the SIDD value of the chip is X, the calculated static power consumption increase is k × X × 100. If the first static power consumption is P1, then the second static power consumption P2 = P1 + k × X × 100.

[0030] In step S104, the equivalent activation energy at the current operating voltage is obtained, and the target static power consumption of the chip at the current operating voltage and the current operating temperature is determined based on the equivalent activation energy at the current operating voltage, the second static power consumption, and the current operating temperature.

[0031] The equivalent activation energy (Ea) is an intermediate variable obtained by fitting using the Arrhenius equation, which is used to describe the degree of influence of temperature on the static power consumption of the chip. The equivalent activation energy (Ea) value of each chip at different voltages can be obtained by fitting experimental data and stored in the chip firmware. In implementation, the temperature correction of the static power consumption can be completed by combining the equivalent activation energy (Ea) values at the current operating temperature and the current operating voltage, so as to obtain the final target static power consumption.

[0032] Based on the above embodiments disclosed in the present application, through the three-stage modeling method (reference power consumption fitting, voltage compensation modeling, and temperature correction modeling), high-precision and low-complexity prediction of the static power consumption of the chip is realized. The power consumption determination method provided in the embodiments of the present application not only considers the individual differences of the chip (such as SIDD), but also can adapt to the dynamic changes of voltage and temperature, and has good engineering practicability and deployment flexibility. Compared with the prior art, the power consumption determination method provided in the embodiments of the present application has significant advantages in prediction accuracy, calculation efficiency, deployment cost, and the like, and is suitable for application scenarios such as GPU, AI chip, and the like which have high requirements for power consumption control.

[0033] In some embodiments, the process of determining the first static power consumption of the chip at a reference voltage and a reference temperature based on the process parameter is implemented by a first function relationship; and the first function relationship is constructed by: obtaining a plurality of first sample data; the first sample data comprises measured power consumption of a chip manufactured with a sample process parameter at the reference voltage and the reference temperature; fitting the first function relationship based on the plurality of first sample data; and the first function relationship is used to represent the mapping relationship between power consumption and process parameter at the reference voltage and the reference temperature.

[0034] The first sample data is the actual static power consumption data of a chip manufactured with different sample process parameters at a pre-set reference voltage and reference temperature, which is obtained by accurate measurement. Correspondingly, the first function relationship is a mathematical function used to describe the mapping relationship between the static power consumption of the chip and the process parameter at the reference voltage and the reference temperature. According to the known process parameter of the chip, the static power consumption of the chip at a specific reference voltage and reference temperature can be calculated by the first function relationship.

[0035] In some embodiments, the sample process parameter refers to a physical or electrical characteristic parameter used to describe the individual difference of the chip, such as SIDD (short circuit current), which is one of the key indicators for measuring the leakage characteristics of the chip. Different chips, even if they belong to the same model, may have different SIDD values due to process deviation during the manufacturing process, thereby causing differences in the static power consumption of the chips.

[0036] In some possible implementations, the plurality of first sample data can be obtained by: after determining the reference voltage and the reference temperature, for example, the reference voltage is 700 mV and the reference temperature is 25℃. Obtain a plurality of chip samples with different sample process parameters. Place each chip sample with a sample process parameter in a set 700 mV voltage and 25℃ temperature test environment, use a high-precision power consumption measurement device to accurately measure the static power consumption of each chip sample, and record the sample process parameter value corresponding to each chip sample and the measured static power consumption. The combination of the sample process parameter and the static power consumption constitutes the first sample data.

[0037] In some embodiments, fitting refers to finding the best function form by mathematical method according to the existing first sample data set, and the mathematical method can accurately describe the relationship between the input variable and the output variable. In this embodiment, the goal of fitting is to find a first function relationship that can reflect the corresponding relationship between the chip process parameter and the static power consumption.

[0038] In some embodiments, the process of fitting the first function relationship based on the plurality of first sample data can be implemented in the following way: based on the distribution characteristics of the first sample data and / or the complexity of the expected mapping relationship, a suitable mathematical function model can be determined, which can be a polynomial function, an exponential function, a logarithmic function, or a more complex combined function, etc. Then, the first sample data can be substituted into the selected function model through a curve fitting method, such as the least squares method, and by continuously adjusting the parameters in the function model, the sum of squared errors between the function curve and the sample data is minimized, i.e. the fitted function is as close as possible to the actual measured data points, and finally the specific expression of the first function relationship is determined.

[0039] Exemplarily, the first function relationship can be represented as W = k11 x SIDD + k12, where W is the power consumption, SIDD is the process parameter, and k11 and k12 are the fitted coefficients. Alternatively, the first function relationship can be represented as W = k11 x SIDD + k12 x SIDD + k13, where W is the power consumption, SIDD is the process parameter, and k11, k12 and k13 are the fitted coefficients. 2

[0040] For example, the first function relationship of SIDD and can be represented by formula (1): where the reference voltage is 700 mV, the reference temperature is 25°C, is the first static power consumption, is the process parameter, and a and b are two coefficients of the first function relationship, which can be determined after the fitting process.

[0041] Based on the above embodiments disclosed in the present application, by obtaining the actual static power consumption accurately measured at a pre-set reference voltage and reference temperature of chips manufactured with different sample process parameters as the first sample data, data reflecting the real situation of chip static power consumption under different process parameters can be obtained, providing a basis for subsequent construction of an accurate function relationship. At the same time, by fitting the first function relationship based on these first sample data for representing the mapping relationship between power consumption and process parameter at the reference voltage and reference temperature, a mathematical model that can approximately and accurately describe the relationship between the two can be found, making it possible to calculate the static power consumption of the chip according to the known process parameter. Based on the embodiments provided in the present application, the static power consumption of the chip under specific reference conditions can be predicted more conveniently and effectively according to the process parameter of the chip.

[0042] ​​In some embodiments, compensating the first static power consumption based on the difference between the current operating voltage and the reference voltage to obtain the second static power consumption at the reference temperature comprises: determining a power consumption compensation parameter corresponding to the chip based on a process parameter of the chip; the power consumption compensation parameter is used to represent the degree of influence of the operating voltage on the power consumption; determining a voltage difference between the current operating voltage and the reference voltage; determining a compensated power consumption at the current operating voltage based on the voltage difference and the power consumption compensation parameter; and compensating the first static power consumption by using the compensated power consumption at the current operating voltage to obtain the second static power consumption at the reference temperature.

[0043] The power consumption compensation parameter is a value related to the chip manufacturing process, reflecting the trend of the chip static power consumption (leakage power) under different voltage conditions. From the perspective of voltage, the power consumption compensation parameter represents the degree of influence of the operating voltage on the power consumption, and can be used to calculate the compensation amount of the first static power consumption under different operating voltages, so as to more accurately reflect the power consumption of the chip under the actual operating voltage.

[0044] The voltage difference is the difference between the current operating voltage and the reference voltage. By calculating the voltage difference, the deviation of the actual operating voltage of the chip from the preset reference voltage can be determined, and then the power consumption can be compensated according to the voltage change. Correspondingly, the compensated power consumption is a power consumption value calculated according to the voltage difference and the power consumption compensation parameter, which is used to compensate the first static power consumption, so as to correct the power consumption deviation caused by the difference between the operating voltage and the reference voltage, thereby obtaining a power consumption value that is more in line with the actual situation, i.e. the second static power consumption.

[0045] In some embodiments, different chips have different power consumption characteristics due to differences in process parameters (such as SIDD), and using a unified power consumption model for evaluation will result in a large error. Therefore, the embodiments of the present application determine the variation law of the chip power consumption under different SIDD values by analyzing the relationship between the chip process parameter (SIDD) and the power consumption, establish a corresponding mathematical model or function, and thus determine the power consumption compensation parameter that can accurately reflect the degree of influence of the process parameter on the power consumption.

[0046] In some possible implementations, the power consumption compensation parameter is obtained by fitting a large amount of measured data in advance and is pre-stored in the chip firmware or hardware logic as a basis for subsequent calculation. In actual application, the power consumption compensation parameter can reflect the process differences between individual chips, thereby realizing more accurate static power consumption prediction.

[0047] In some embodiments, the power consumption compensation parameter can be expressed in a way of modeling by a formula, such as a linear relationship, a polynomial fitting, or an exponential function, etc. Different chip structures and process nodes can correspond to different model forms, and by adopting different model forms, the flexibility and adaptability of the model can be ensured. By measuring and recording the power consumption data of the chip under different voltage conditions, the power consumption variation characteristics of the chip can be effectively reflected. This way of obtaining the power consumption variation characteristics provides a basis for subsequent voltage difference calculation and compensation. In this way, the prediction accuracy of the static power consumption can be improved, and ultimately a more fine-grained power consumption management strategy can be realized.

[0048] In some embodiments, determining the compensation power consumption under the current running voltage based on the voltage difference and the power consumption compensation parameter can include: substituting the calculated voltage difference and the determined power consumption compensation parameter into a pre-set compensation power consumption calculation formula, for example, compensation power consumption = voltage difference x power consumption compensation parameter, to calculate the compensation power consumption under the current running voltage.

[0049] In some embodiments, compensating the first static power consumption with the compensation power consumption under the current running voltage to obtain the second static power consumption under the reference temperature can include: performing an addition operation on the calculated compensation power consumption under the current running voltage and the measured first static power consumption under the reference voltage, i.e., second static power consumption = first static power consumption + compensation power consumption, to obtain the second static power consumption under the reference temperature.

[0050] For example, the second static power consumption can be determined by formula (3).

[0051] Formula (3); wherein the represents the second static power consumption of the chip under the current running voltage and the reference temperature , the is a power consumption compensation coefficient, is a voltage difference between the current running voltage and the reference voltage, is the first static power consumption (under the reference voltage and the reference temperature).

[0052] Based on the above embodiments disclosed in the present application, by determining the corresponding power consumption compensation parameter based on the chip process parameter, the different influence degrees of the operating voltage on the power consumption caused by the manufacturing process difference of different chips can be accurately reflected, and an accurate basis is provided for subsequent power consumption compensation. At the same time, by determining the voltage difference between the current operating voltage and the reference voltage, the deviation of the actual working voltage of the chip relative to the reference can be clearly known, which helps to calculate the compensation amount specifically. Based on the voltage difference and the power consumption compensation parameter, the compensation power consumption under the current operating voltage is determined, which can accurately calculate the power consumption value that needs to be compensated for the first static power consumption in combination with the voltage change. The first static power consumption is compensated by using the compensation power consumption under the current operating voltage to obtain the second static power consumption under the reference temperature, which can correct the power consumption deviation caused by the difference between the operating voltage and the reference voltage, and obtain the power consumption value that is more consistent with the actual operating state.

[0053] In some embodiments, the process of determining the corresponding power consumption compensation parameter of the chip based on the process parameter of the chip is implemented through a second function relationship; the construction method of the second function relationship includes: obtaining a plurality of second sample data; the second sample data includes the measured power consumption of the chip using sample process parameters at a preset voltage interval and the reference temperature; the preset voltage interval is determined by the reference voltage and the dynamic voltage; fitting the second function relationship based on the plurality of second sample data; the second function relationship is used to represent the mapping relationship between the change amount of power consumption and the process parameter with the voltage at the reference temperature.

[0054] Among them, the above-mentioned power consumption compensation parameter can be the ratio of the power consumption change amount to the voltage change amount, and the power consumption compensation parameter can represent the rate of change of the static power consumption of the chip with the voltage.

[0055] Among them, the above-mentioned preset voltage interval refers to the voltage interval with the reference voltage as the minimum value and the dynamic voltage as the maximum value. For example, in the case of a reference voltage of 700 mV, the preset voltage interval can be represented as [700, 700+ΔV] (unit: mV), where 700+ΔV is the dynamic voltage.

[0056] Correspondingly, the second sample data can include the measured power consumption of the chip using sample process parameters at the reference voltage and the reference temperature, and the measured power consumption of the chip using sample process parameters at the dynamic voltage and the reference temperature. Based on the difference between the two measured power consumptions (i.e. the power consumption change amount) and the difference between the two voltages (the voltage change amount), the rate of change of the static power consumption of the chip with the voltage of the current sample process parameter can be obtained.

[0057] Thus, the obtained second sample data can be a sample process parameter and a corresponding sample compensation parameter, the sample compensation parameter being a ratio of a power consumption difference value and a voltage difference value, the power consumption difference value being a difference between a measured power consumption of a chip using the sample process parameter at a reference voltage and a reference temperature and a measured power consumption of the chip using the sample process parameter at a dynamic voltage and the reference temperature, and the voltage difference value being a difference between the reference voltage and the dynamic voltage.

[0058] In some embodiments, the second function relationship can be fitted based on the obtained sample process parameters and the corresponding sample compensation parameters. In the embodiments of the present application, the target of the fitting is to find a second function relationship that can reflect the corresponding relationship between the chip process parameter and the power consumption compensation parameter.

[0059] It can be understood that the second function relationship can be a polynomial function, an exponential function, a logarithmic function, or a more complex combined function, etc. The sample process parameters and the corresponding sample compensation parameters can be substituted into a selected function model by a curve fitting method, for example, a least square method, and the parameters in the function model are adjusted constantly so that the error sum of squares of the function curve and the sample data is minimized, that is, the fitted function is as close as possible to the actually measured data points, and finally the specific expression of the second function relationship is determined.

[0060] Exemplarily, the second function relationship can be expressed as =k21×SIDD+k22, wherein is the sample compensation parameter, SIDD is the process parameter, and k21 and k22 are coefficients fitted. 2 =k21×SIDD +k22×SIDD+ k23, wherein is the sample compensation parameter, SIDD is the process parameter, and k21, k22 and k23 are coefficients fitted.

[0061] For example, the second function relationship between c and SIDD can be expressed as formula (2): wherein, is the power consumption compensation parameter, is the process parameter, and c and d are two coefficients of the second function relationship, which can be determined after the fitting process.

[0062] ​Based on the embodiments provided in the present application, the process of determining the corresponding power consumption compensation parameter based on the chip process parameter is realized through the second function relationship, so that the power consumption compensation parameter of the chip can be quickly and effectively obtained, and the parameter can represent the rate of change of the chip static power consumption with voltage.

[0063] In some embodiments, the process of obtaining the equivalent activation energy under the current operating voltage is realized through a third function relationship; and the construction method of the third function relationship comprises: obtaining a plurality of third sample data; the third sample data comprises measured power consumption of the chip under different temperatures and different voltages; based on the third sample data under the reference temperature and the third sample data under a plurality of other temperatures, determining a first equivalent activation energy corresponding to the third sample data under each of the other temperatures when taking the reference temperature as a base point; for each voltage-temperature point, based on the first equivalent activation energy of all chips at the voltage-temperature point, determining a second equivalent activation energy corresponding to the voltage-temperature point; the voltage-temperature point is a combination of one voltage and one temperature; among the second equivalent activation energies corresponding to each voltage-temperature point, for each voltage, based on the second equivalent activation energies of all temperatures corresponding to the voltage, determining a third equivalent activation energy corresponding to the voltage; based on the third equivalent activation energies corresponding to each voltage, fitting the third function relationship; and the third function relationship is used to represent the mapping relationship between the equivalent activation energy and the voltage.

[0064] In the third sample data, the static power consumption data of the chip under different working conditions (such as different temperatures and different voltages) is actually measured through experiments or tests. By collecting a plurality of sets of third sample data, the power consumption characteristics of the chip under different PVT (process, voltage, temperature) conditions can be more comprehensively reflected, thereby providing support for establishing a high-precision third function relationship.

[0065] In order to facilitate understanding of the above scheme, the following will be exemplarily illustrated based on an actual example.

[0066] Please refer to Table 1, which shows 20 sets of third sample data of a chip.

[0067] Table 1

[0068] As shown in Table 1, Table 1 includes 20 sets of third sample data with serial numbers 1 to 20.

[0069] The determining, based on the third sample data at the reference temperature and the third sample data at a plurality of other temperatures, of the first equivalent activation energy corresponding to the third sample data at each of the other temperatures with the reference temperature as a base point includes: for each voltage, obtaining the third sample data of the chip at the voltage and the reference temperature, and the third sample data of the chip at the voltage and the other temperature; and calculating the first equivalent activation energy corresponding to each other temperature at the voltage based on the Arrhenius equation.

[0070] For example, for v1 in Table 1, assuming t1 is the reference temperature, the first equivalent activation energy corresponding to t2, t3 and t5 can be calculated respectively.

[0071] In some embodiments, the first equivalent activation energy can be determined by formula (4).

[0072] Formula (4); wherein, represents the first equivalent activation energy corresponding to the other temperature T2 with T1 as the reference temperature at the current voltage. T1 represents the reference temperature, and T2 represents the other temperature, represents the measured power consumption of the chip at the current voltage and the reference temperature T1, represents the measured power consumption of the chip at the current voltage and the other temperature T2, and k is the thermodynamic constant.

[0073] For example, taking the voltage v1 and the temperature t3 in Table 1 as an example, the first equivalent activation energy of the chip at the voltage v1 and the temperature t3 with t1 as the base point can be represented as .

[0074] The determining, for each voltage-temperature point, of the second equivalent activation energy corresponding to the voltage-temperature point based on the first equivalent activation energies of all chips at the voltage-temperature point includes: taking the average of the first equivalent activation energies of all chips at a voltage and a temperature corresponding to the voltage-temperature point as the second equivalent activation energy corresponding to the voltage-temperature point.

[0075] For example, taking the voltage v1 and the temperature t3 in Table 1 as an example, the first equivalent activation energy of a chip at the voltage v1 and the temperature t3 can be determined based on the data in Table 1. Based on the same processing manner, the first equivalent activation energies of all other chips at the voltage v1 and the temperature t3 can be obtained. The second equivalent activation energy corresponding to the voltage-temperature point can be obtained by averaging these first equivalent activation energies. It can be understood that the second equivalent activation energy eliminates the difference in process parameters.

[0076] The third equivalent activation energy corresponding to each voltage is determined based on the second equivalent activation energies corresponding to all temperatures of the voltage, including: taking the average of the second equivalent activation energies corresponding to all temperatures of the voltage as the third equivalent activation energy corresponding to the voltage.

[0077] For example, based on the above example, after obtaining the second equivalent activation energy corresponding to each voltage-temperature point, for voltage v1, the second equivalent activation energy corresponding to voltage v1 and temperature t2, the second equivalent activation energy corresponding to voltage v1 and temperature t3, and the second equivalent activation energy corresponding to voltage v1 and temperature t3 can be averaged to obtain the third equivalent activation energy corresponding to the voltage v1.

[0078] At this point, the third equivalent activation energy corresponding to voltage v1 can be obtained. Based on the same method, the third equivalent activation energy corresponding to voltage v2-v4 can be obtained respectively.

[0079] The third function relationship is fitted based on the third equivalent activation energy corresponding to each voltage, including: In some embodiments, the third function relationship can be fitted based on the obtained voltages and the third equivalent activation energy corresponding to each voltage. In the embodiments of the present application, the target of fitting is to find a third function relationship that can reflect the corresponding relationship between the equivalent activation energy and the voltage.

[0080] It can be understood that the third function relationship can be a polynomial function, an exponential function, a logarithmic function, or a more complex combination function, etc. The voltages and the third equivalent activation energy corresponding to each voltage can be substituted into the selected function model by the curve fitting method, such as the least square method, and the parameters in the function model are adjusted continuously to make the error sum of squares of the function curve and the sample data reach the minimum, that is, the fitted function is as close as possible to the actual measured data points, and finally the specific expression of the third function relationship is determined.

[0081] For example, the third function relationship can be expressed as =k31×V+k32, where is the third equivalent activation energy, V is the voltage, and k31 and k32 are the fitted coefficients. Or, the third function relationship can be expressed as =k31×V 2 +k32×V+ k33, where is the third equivalent activation energy, V is the voltage, and k31, k32 and k33 are the fitted coefficients.

[0082] For example, The third function relationship with V can be expressed as formula (5): Formula (5); wherein, , e, f and g are three coefficients of the third function relationship, which can be determined after the fitting process.

[0083] Based on the above embodiments disclosed in the present application, by acquiring a plurality of third sample data including the actual power consumption of the chip at different temperatures and different voltages, the power consumption characteristics of the chip under different PVT conditions can be comprehensively reflected, providing rich and reliable data basis for subsequent analysis; at the same time, by determining the first equivalent activation energy based on the third sample data at the reference temperature and other temperatures, the difference in the influence of different temperatures on the chip power consumption can be quantified initially; based on the first equivalent activation energy of all chips at the voltage temperature point, the second equivalent activation energy can be determined, which can eliminate the influence of process parameter difference, so that the obtained equivalent activation energy can more accurately reflect the joint action of temperature and voltage on chip power consumption; in the second equivalent activation energy corresponding to each voltage temperature point, the third equivalent activation energy is determined for each voltage, which further integrates the information at different temperatures, so that the third equivalent activation energy can more represent the overall characteristics of the chip power consumption affected by temperature at this voltage; based on the third equivalent activation energy corresponding to each voltage, the third function relationship is fitted, which can establish the mapping relationship between the equivalent activation energy and the voltage, and provide an effective method for obtaining the equivalent activation energy under the current running voltage.

[0084] In some embodiments, the determining the target static power consumption of the chip at the current running voltage and the current running temperature based on the equivalent activation energy at the current running voltage, the second static power consumption and the current running temperature comprises: determining a power consumption adjustment coefficient based on the current running temperature, the reference temperature and the equivalent activation energy at the current running voltage; adjusting the second static power consumption based on the power consumption adjustment coefficient to obtain the target static power consumption of the chip at the current running voltage and the current running temperature.

[0085] Here, the power consumption adjustment coefficient of the chip at the current running voltage and the current running temperature can be determined based on the above formula (4) of the first equivalent activation energy as formula (6): Formula (6); wherein, the reference temperature and the equivalent activation energy at the current running voltage, is the power consumption adjustment coefficient at the current running temperature, the reference temperature and the current running voltage, is the current running temperature, is the current running voltage; 298 is the conversion of the reference temperature 25℃ to Kelvin temperature, that is, 273+25, Ea is the equivalent activation energy at the current operating voltage; k is the thermodynamic constant.

[0086] Correspondingly, the target static power consumption of the chip at the current operating voltage and the current operating temperature can be determined by formula (7).

[0087] Formula (7); wherein, is the second static power consumption; is the target static power consumption of the chip at the current operating voltage and the current operating temperature.

[0088] In some embodiments, the first static power consumption is determined by a first functional relationship, the second static power consumption is determined by a second functional relationship, and the target static power consumption is determined by a third functional relationship; wherein the first functional relationship and the second functional relationship are linear functions, and the third functional relationship is a quadratic function; function parameters of the first functional relationship, the second functional relationship, and the third functional relationship are stored in the chip firmware.

[0089] In some possible implementations, the first static power consumption is determined by a first functional relationship, the first functional relationship is a linear function, and function parameters of the first functional relationship are stored in the chip firmware. In this embodiment, the first functional relationship is used to calculate the static power consumption (Baseleakage) of the chip at a reference voltage and a reference temperature (such as 25°C and 700mV). The first functional relationship is in the form of a linear function, and model parameters (a and b) in the first functional relationship are pre-fitted by measured data and written into the chip firmware. By inputting the SIDD into the first functional relationship, the static power consumption value of the current chip at the standard working point can be quickly calculated. This method avoids complex table lookup or machine learning inference process, greatly improves the calculation efficiency, and supports deployment on low-power hardware. By using the first functional relationship for modeling, high-precision static power consumption estimation can be achieved with a small number of parameters, while ensuring the lightweight of the model, reducing resource consumption and delay.

[0090] In some possible implementation manners, the second static power consumption is determined through a second function relationship, the second function relationship is a linear function, and function parameters of the second function relationship are stored in the chip firmware. In this embodiment, the second function relationship is used to linearly compensate the reference static power consumption according to a difference between the current operating voltage and the reference voltage, so as to obtain an estimated value of the static power consumption under the current voltage. Model parameters (c and d) in the second function relationship are pre-fitted through measured data and written into the chip firmware. The second function relationship combines the relationship between the current voltage and the reference voltage, calculates a static power consumption offset caused by voltage change, and then superimposes the offset on the reference static power consumption, so as to obtain the static power consumption under the current voltage. By introducing the second function relationship, the static power consumption at any voltage point can be extended without relying on full-voltage-domain table lookup, the storage resource occupation is greatly reduced, and meanwhile, a higher prediction accuracy is maintained.

[0091] In some possible implementation manners, the target static power consumption is determined through a third function relationship, the third function relationship is a quadratic function, and function parameters of the third function relationship are stored in the chip firmware. The third function relationship is used to combine an equivalent activation energy (Ea) under the current operating voltage, a current operating temperature, and the second static power consumption calculated according to the foregoing method, and comprehensively calculate the target static power consumption of the chip under actual operating conditions. Model parameters (e, f, and g) in the third function relationship are pre-fitted through measured data and written into the chip firmware. The model parameters are all stored in the chip firmware. By using the third function relationship, a nonlinear correction of temperature influence can be completed, so as to realize accurate estimation of the static power consumption of the chip under any PVT condition. By introducing the third function relationship for modeling, the rationality of the physical mechanism (such as the Arrhenius equation) is retained, and the prediction ability of the model under complex working conditions is significantly improved. Meanwhile, since all the parameters in the third function relationship have been fitted in advance and fixed in the chip firmware, the execution efficiency is very high.

[0092] To sum up, in the embodiments of the present application, the three-stage modeling manner composed of the first function relationship, the second function relationship, and the third function relationship simplifies the static power consumption prediction path into a series of low-complexity mathematical expressions, and the power prediction can be realized through simple function relationships. This method reduces the structural complexity of the prediction path. Correspondingly, since the first function relationship and the second function relationship are linear functions, and the third function relationship is a quadratic function, the number of parameters required for prediction is only one digit, which significantly reduces the deployment cost of the prediction algorithm in the chip. Therefore, while reducing the deployment cost, the embodiments of the present application improve the deployment flexibility and calculation efficiency of the model, and provide high-precision, low-delay real-time static power consumption estimation support for the chip power consumption management system.

[0093] In actual implementation, the first function relationship, the second function relationship and the third function relationship correspond to basic power consumption modeling of the chip under the reference condition, power consumption compensation modeling caused by voltage change, and nonlinear correction modeling caused by temperature change, respectively. The first function relationship, the second function relationship and the third function relationship are progressive, gradually refining the power consumption estimation result, and finally realizing the static power consumption estimation of the chip under any PVT condition. In the modeling process, the first function relationship is the basis of the entire modeling, the second function relationship introduces the influence of voltage deviation on this basis, and the third function relationship further considers the nonlinear effect of temperature, forming a complete power consumption estimation link.

[0094] In some embodiments, the method further comprises: in response to the current operating temperature changing, determining a target static power consumption of the chip under the current operating voltage and the changed operating temperature based on the equivalent activation energy under the current operating voltage, the second static power consumption and the changed operating temperature.

[0095] Compared with Figure 1 The scheme provided by the embodiments does not need to recalculate the first static power consumption of the chip under the reference voltage and the reference temperature, nor the second static power consumption of the chip under the current operating voltage and the reference temperature when the current operating temperature changes. At the same time, in the process of determining the target static power consumption, the equivalent activation energy under the current operating voltage also does not need to be obtained again. Only the equivalent activation energy under the original current operating voltage and the second static power consumption are needed to update the target static power consumption based on the above formula (6) and formula (7).

[0096] Based on the above embodiments disclosed in the present application, by responding to the change of the current operating temperature and directly using the equivalent activation energy under the original current operating voltage and the second static power consumption, the calculation amount caused by repeated calculation of the first static power consumption and the second static power consumption when the temperature changes can be reduced, and the calculation complexity can be reduced. At the same time, by directly using the existing equivalent activation energy without reacquiring, the time and resource consumption for acquiring the parameter can be saved, and the calculation efficiency can be improved.

[0097] In some embodiments, the method further comprises: in response to the current operating voltage changing, compensating the first static power consumption based on the difference between the changed operating voltage and the reference voltage to obtain a third static power consumption of the chip under the changed operating voltage and the reference temperature; acquiring the equivalent activation energy under the changed operating voltage, and determining a target static power consumption of the chip under the changed operating voltage and the current operating temperature based on the equivalent activation energy under the changed operating voltage, the third static power consumption and the current operating temperature.

[0098] Compared withFigure 2 The scheme provided by the embodiment can, in the case where the current operating voltage changes, update the target static power consumption based on the changed operating voltage, the third static power consumption re-determined based on the changed operating voltage and the formula (3), the corresponding equivalent activation energy determined based on the formula (5), and the current operating temperature.

[0099] Alternatively, in the case where both the current operating voltage and the current operating temperature change, the first static power consumption can be compensated based on the difference between the changed operating voltage and the reference voltage to obtain a third static power consumption of the chip under the changed operating voltage and the reference temperature; the equivalent activation energy under the changed operating voltage is obtained, and the target static power consumption of the chip under the changed operating voltage and the changed operating temperature is determined based on the equivalent activation energy under the changed operating voltage, the third static power consumption, and the changed operating temperature.

[0100] It can be seen that, in the case where the current operating voltage changes, or in the case where both the current operating voltage and the current operating temperature change, the first static power consumption does not need to be re-calculated, and the calculation efficiency can be improved.

[0101] The application of the power consumption determination method provided by the embodiment of the application in an actual scene is described below.

[0102] Based on a large amount of measured data of static power consumption (leakage) of GPU chips, the application proposes a modeling method for chip-level power consumption prediction and management. The method takes the process characteristic parameters (such as SIDD) of the chip individual, the operating voltage, and the temperature as input variables, constructs a mathematical modeling path that can efficiently predict the leakage power consumption, and aims to realize high-precision, low-complexity, and strong-applicability static power consumption estimation capability.

[0103] During the operation of the chip, the static power consumption will fluctuate nonlinearly with PVT (process, operating voltage, and temperature) conditions. Especially in chips such as GPUs that support dynamic voltage and frequency scaling (DVFS), the voltage and temperature change rapidly and greatly, which directly challenges the power consumption management strategy. Existing methods either use fixed limit values for conservative estimation, leading to performance waste and resource redundancy, or rely on complex machine learning models, although the accuracy is high, but due to the large occupation of computing resources, it is difficult to deploy and implement in firmware or embedded systems.

[0104] To this end, the application proposes a three-stage modeling method based on measured data driving. First, a model 1 between SIDD and Base Leakage is established under standard working conditions, serving as a normalized benchmark for static power consumption; then, a function relationship (model 2) between AW / AV (leakage rate of change under unit voltage) and SIDD is defined and fitted, realizing the extension of leakage from the benchmark point to any voltage point; finally, by establishing a model (model 3) of different voltage points and variable Ea, and combining the Arrhenius equation for temperature correction, the static power consumption estimation under any PVT condition is completed.

[0105] The modeling method proposed by the application has clear structure, few parameters, and low computational burden, is suitable for lightweight deployment in GPU chip firmware, and can also be pre-installed as a hardware auxiliary unit in the chip design stage. Through the application, real-time prediction and dynamic response of chip-level static power consumption can be realized without relying on complex models, significantly improving the comprehensive performance of the power management system in terms of accuracy, efficiency and implementation flexibility The technical solution proposed by the application includes the following key components: Static power consumption model: The static power consumption model is a pre-trained model based on deep learning, and the core data is extracted from the power consumption of GPU under different corner conditions in actual work. After the model is successfully built, it is used to generate the data required in the subsequent steps under specific SIDD, temperature and voltage. As shown in Figure 3 , measured data 121 can be collected, and a static power consumption model 122 is obtained based on the measured data 121 through a machine learning algorithm. The measured data 121 can include measured GPU static power consumption and chip parameters 1 to 3 corresponding to the GPU static power consumption and specific GPU configurations.

[0106] Chip static power consumption modeling module: This module is used to build a leakage power consumption model of the chip under different process, voltage and temperature conditions. The modeling process includes three stages: fitting of SIDD and Base Leakage (model 1, M1), fitting of AW / AV and SIDD (model 2, M2), and fitting of activation energy Ea and voltage (model 3, M3).

[0107] System management unit: SMC (system management control) control unit composed of CPU, responsible for receiving SIDD, temperature, voltage, function variables and other data, and performing real-time operation according to the implanted model.

[0108] Voltage and temperature monitoring unit: The GPU working temperature and voltage are obtained through the sensor inside the GPU, and the SMC can obtain the current temperature and voltage in real time. ​

[0109] The application will be described in the following steps: Step 1, static power consumption model data modeling: collect GPU chip measured data under multiple corner conditions, train and model the measured data, set and combine specific chip parameters (such as SIDD, voltage, temperature), form a data set containing three-dimensional input (SIDD, voltage, temperature) and one-dimensional output (leakage power).

[0110] Step 2, first model construction (Base Leakage fitting): first define the base static power (Base leakage) point, under the standard working condition (here defined as the base temperature 25℃, the base voltage 700mV), according to the data set obtained in step 1, the function relationship between SIDD and of different GPU chips is constructed. This first model is also called M1 model, which corresponds to the first function relationship in the above embodiment; as Figure 4 shown, the data model of this M1 model describes the data relationship between input data 131 (base voltage, base temperature and different SIDD) and base static power 132.

[0111] Among them, the function relationship between SIDD and can be expressed as formula (1).

[0112] Step 3, second model construction (voltage change modeling): the defined standard working condition is 25℃, here the fixed temperature point is 25℃, according to the leakage power change (defined as ΔW) of different chips in the working voltage range (here the voltage working range can be defined as [700, 700+ΔV]) in the data set, the function relationship between and SIDD is constructed. This second model is also called M2 model, which corresponds to the second function relationship in the above embodiment; as Figure 5 shown, the data model of this M2 model describes the data relationship between input data 141 (maximum voltage under base temperature, base voltage under base temperature and different SIDD), power consumption data 142 (power consumption under maximum voltage and power consumption under base voltage) and 143.

[0113] Among them, and SIDD can be expressed as formula (2).

[0114] Then according to this formula (2), the power of any voltage point (V) under 25℃ can be calculated, which is defined as the base point (V0), and the calculation method is formula (3). ​​Step 4, third model construction (temperature change modeling): according to the leakage power data of each voltage point at 25°C obtained in step 3, define it as the base point of model 3. According to the data generated in the data set, first, it is necessary to rely on the Arrhenius equation to calculate the Ea (defined as equivalent activation energy) value of each chip at each voltage, with 25°C as the base point at different temperatures, defined as . The third model is also called M3 model, which corresponds to the third function relationship in the above embodiment; as shown in Figure 6 , the data model of the M3 model describes the data relationship of the input data 151 (different voltages, different temperatures and different SIDD), static power consumption 152 and equivalent activation energy 153 to , and is the power consumption compensation parameter in the above embodiment.

[0115] wherein can be determined by formula (4). Based on formula (4), the of each chip at each voltage temperature point can be determined. is the first equivalent activation energy in the above embodiment.

[0116] For a voltage temperature point (i.e. a combination of one voltage and one temperature), obtain the average value of the of all chips at this voltage temperature point. Taking 700mv 25°C as an example, it can be defined as Ea_700mV_25°C ( ), is the second equivalent activation energy in the above embodiment.

[0117] For each voltage, take the average of the values of all temperature points at this voltage, and define the average Ea value as Ea_700mV( ). Thus, the data describing the relationship between voltage and Ea value can be obtained, i.e. the corresponding to each voltage, is the third equivalent activation energy in the above embodiment.

[0118] For each voltage corresponding to the , function fitting can be performed to obtain the function relationship between Ea value and voltage, as formula (5).

[0119] Step 5, execute the prediction process: when the chip is running, the system obtains SIDD, voltage, temperature through the parameter input unit, and sequentially executes the following processes: 5.1, calculate using the M1 model.

[0120] For example, chip A at 700mv, 25C power consumption: .

[0121] 5.2, use M2 model to calculate the leakage of any voltage point at 25C .

[0122] 800mV : .

[0123] 5.3, use M3 model to fit the value of Ea, and then calculate the current static power consumption according to the current temperature T2.

[0124] For example, first determine the value of Ea: . Then, based on the transformation of the above formula (4), determine the current static power consumption, which can refer to formula (8).

[0125] Formula (8); The following is an example of a prediction process diagram: Step 1, input parameter collection.

[0126] Here, during the startup or running of the chip, the system obtains the following parameter inputs through EFUSE and GPU internal sensors: SIDD (chip process parameters), (current chip running voltage) and T2 (current chip running temperature).

[0127] Step 2, use the above formula (1) to calculate , where a, b parameters are already fitted and determined parameters stored in the chip firmware (SMC), which can be read during calculation.

[0128] Step 3, use M2 model to extend to target voltage .

[0129] Based on the obtained SIDD, use formula (2) to get the chip's ; then, using the obtained , the calculated in step 2 and , use formula (3) to get the leakage value at target voltage (still at 25C).

[0130] Step 4, use M3 model to extend to any temperature.

[0131] Based on the target voltage, use formula (5) to get the at the target voltage; then according to the obtained And the current running temperature T2 of the chip, the real-time leakage power consumption of the current voltage + the current temperature is calculated by formula (8).

[0132] Step 5, when the temperature changes, only step 3 needs to be repeated.

[0133] Step 6, when the voltage changes, steps 2 to 3 can be repeated.

[0134] Based on the above embodiment, the present application can bring the following beneficial effects: (1) Simplify power consumption modeling and prediction path: through the three-stage function modeling method (M1, M2, M3), the static power consumption prediction is simplified from complex lookup table logic or high-dimensional machine learning model to a small number of mathematical expressions, which greatly reduces the structural complexity of the prediction path, and is convenient for firmware integration or hardware implementation.

[0135] (2) High calculation efficiency and low delay: all models are parameter-fitted function expressions, and the chip only needs to perform basic multiplication, addition and exponential operation at runtime, avoiding the resource burden brought by deep model reasoning, and supporting real-time deployment in SMC or low-power hardware.

[0136] (3) Predictive accuracy and individuality: by introducing chip-specific parameters for individual modeling, high accuracy and low complexity can be achieved, solving the dilemma of large error setting of traditional maximum value and difficult deployment of machine learning model. (4) Strong universality, easy to migrate across chips: this method has no strong dependence on input range and chip architecture, and only needs to collect data of new chips and re-fit parameters to migrate to any GPU, AI chip or SoC platform, with good scalability.

[0137] (5) Beneficial to power management system integration: this scheme can be used as a key prediction module in the chip power control system, providing high-precision static power support for DVFS, power strategy and temperature control strategy, and improving the responsiveness and robustness of overall energy efficiency control.

[0138] The common implementation of chip static power consumption prediction currently mainly includes fixed value estimation, table lookup interpolation and machine learning model inference. Among them, the fixed value method is simple to calculate, but the precision is low due to the lack of individual difference modeling; the table lookup method can improve the accuracy to a certain extent, but it needs to store power consumption data under multiple temperature and voltage conditions, which consumes a lot of resources; the machine learning scheme has certain prediction ability, but the model structure is complex and the operation resource occupation is high. In addition, some systems also realize dynamic adjustment by integrating multiple sensors and combining control logic, but its implementation path relies heavily on hardware redundancy and complex scheduling logic, and the debugging and expansion cost is high. Compared with the above, the modeling and prediction method provided in the present application not only realizes high precision, but also greatly reduces the runtime calculation overhead, and has good universality and deployment flexibility. It is one of the most balanced and practical ways to achieve the goal among the known technical solutions, and because it is based on sufficient chip measurement data analysis and fitting modeling in the early stage, the scheme provided in the present application has effectiveness.

[0139] The present application aims to realize high-precision prediction and light-weight modeling of chip static power consumption. The key innovation of the present application lies not only in the simplicity and deployability of the modeling method, but also in the individual difference modeling realized by chip characteristic parameters. Compared with the prior art, the present application has essential differences in the following aspects, which are also the core technical points to be protected, as follows: (1) A three-stage modeling path is proposed: M1, M2, M3 function model decouples power consumption prediction calculation chain: the power consumption prediction process is divided into three mathematical function models, which are used for benchmark leakage estimation, voltage expansion and temperature expansion, respectively, and has the advantages of clear structure and easy embedded deployment.

[0140] (2) Voltage fitting Ea and Arrhenius equation are used for temperature correction and expansion, which has physical rationality and high efficiency: the physical activation energy is added to the modeling, which realizes low calculation burden on the basis of maintaining physical interpretability.

[0141] (3) Function relationship modeling of AW / AV and SIDD: by constructing the linear relationship between AW / AV and SIDD, the present application does not need to store the leakage table of the whole voltage domain, which greatly compresses the storage resources and improves the model response speed, and is suitable for fast execution in SMC firmware.

[0142] (4) Chip characteristic parameter SIDD is used as the core of modeling to construct a static power consumption estimation method for individual differences of chips: the present application breaks through the traditional way of modeling with average value or uniform corner, and describes the characteristics of each chip through SIDD parameter, realizes individual static power consumption modeling, and effectively improves the estimation accuracy and application range.

[0143] (5) The model structure has strong adaptability and is suitable for multiple implementation modes such as firmware, lookup table or hardware logic: The proposed model does not depend on high computing resources, can be directly packaged as a deployable module at the initial stage of chip design, can be calculated or driven by SMC in real time at runtime, and has good cross-platform portability.

[0144] (6) It has strong engineering practicability and can be directly connected to system modules such as power consumption budget, DVFS strategy and power protection: The leakage prediction capability provided by the application not only supports analysis, but also can be directly linked to system control processes, which is a system-level closed-loop capability that current lookup table or offline modeling schemes cannot achieve.

[0145] Correspondingly, compared with the closest prior art, the application has the following technical advantages: (1) The model structure is lightweight and suitable for deployment in chip firmware or low-computing-power environment: The application adopts a three-section function (M1, M2, M3) modeling structure to replace the existing complex neural network or regression model, and only a small amount of multiplication and addition and exponential operation is needed to complete the prediction of power consumption. The three-section function modeling structure significantly reduces the computing resource overhead, improves the deployability and response speed of the model in the SMC embedded environment, which is achieved by replacing the black box inference mechanism with function fitting.

[0146] (2) Full PVT space coverage, considering the adaptability of voltage and temperature dynamic changes: Compared with the fixed leakage maximum value method which ignores the dynamic fluctuations of chip runtime temperature and voltage, the application realizes leakage expansion at any voltage through the M2 model, and completes temperature correction through the M3 model and the Arrhenius formula, thereby realizing power consumption prediction at any PVT point, and having stronger runtime adaptability and temperature control adjustment support capability.

[0147] (3) Support for chip individual modeling to realize the unification of precision and generalization capability: The application introduces the SIDD of the chip as one of the modeling core variables to build a dedicated leakage calculation path for each chip. Compared with the traditional scheme using a unified fixed value, the application can more accurately reflect the process differences between chips and the real power consumption performance under the running state.

[0148] (4) Does not depend on large-scale lookup table or hardware sensor, simplifies the deployment architecture: Compared with the lookup table method which needs to store a large amount of power consumption points at specific voltages and temperatures or sensor calibration data, the application only needs to input three parameters (SIDD, V, T) to perform power consumption prediction, saving hardware resources and firmware capacity. The application uses a function processing method to complete the extrapolation across points.

[0149] (5) Engineering flexibility, easy to iterate and cross-chip migration: the proposed model structure is universal, and the fitting coefficients can be updated according to the chip data without reconstructing the overall architecture. Compared with the problem of difficult migration and retraining of machine learning models, the method only needs to re-fit a small number of parameters to quickly reuse in different chips or process nodes.

[0150] Based on the foregoing embodiments, the embodiments of the present application provide a power consumption determination device, which comprises various units and various modules included in the units, and can be realized by a processor in a computer device. Of course, it can also be realized by a specific logic circuit. In the implementation process, the processor can be a central processing unit (CPU), a microprocessor unit (MPU), a digital signal processor (DSP), or a field programmable gate array (FPGA).

[0151] Figure 6 The constituent structure of a power consumption determination device provided by the embodiments of the present application is shown in FIG. 2. As shown in FIG. 2, the power consumption determination device 200 comprises an acquisition module 210 and a power consumption determination module 220. Figure 7 The acquisition module 210 is configured to acquire process parameters, a current operating voltage, and a current operating temperature of a chip. The power consumption determination module 220 is configured to determine a first static power consumption of the chip at a reference voltage and a reference temperature based on the process parameters; compensate the first static power consumption based on a difference between the current operating voltage and the reference voltage to obtain a second static power consumption of the chip at the current operating voltage and the reference temperature; acquire an equivalent activation energy at the current operating voltage, and determine a target static power consumption of the chip at the current operating voltage and the current operating temperature based on the equivalent activation energy at the current operating voltage, the second static power consumption, and the current operating temperature. In some embodiments, the process of determining the first static power consumption of the chip at the reference voltage and the reference temperature based on the process parameters is realized by a first function relationship. The device further comprises a function construction module configured to acquire a plurality of first sample data. The first sample data comprises a measured power consumption of a chip using sample process parameters at the reference voltage and the reference temperature. The first function relationship is fitted based on the plurality of first sample data, and is used to represent the mapping relationship between power consumption and process parameters at the reference voltage and the reference temperature.

[0152] In some embodiments, the process of determining the first static power consumption of the chip at the reference voltage and the reference temperature based on the process parameters is realized by a first function relationship. The device further comprises a function construction module configured to acquire a plurality of first sample data. The first sample data comprises a measured power consumption of a chip using sample process parameters at the reference voltage and the reference temperature. The first function relationship is fitted based on the plurality of first sample data, and is used to represent the mapping relationship between power consumption and process parameters at the reference voltage and the reference temperature.

[0153] In some embodiments, the power consumption determination module is further configured to determine, based on a process parameter of the chip, a power consumption compensation parameter corresponding to the chip, the power consumption compensation parameter being used to represent an influence degree of an operating voltage on power consumption; determine a voltage difference between the current operating voltage and the reference voltage; determine a compensated power consumption under the current operating voltage based on the voltage difference and the power consumption compensation parameter; and compensate the first static power consumption by using the compensated power consumption under the current operating voltage to obtain a second static power consumption under the reference temperature.

[0154] In some embodiments, the process of determining, based on a process parameter of the chip, a power consumption compensation parameter corresponding to the chip is implemented by a second function relationship; the apparatus further comprises a function construction module configured to obtain a plurality of second sample data, the second sample data comprising measured power consumption of a chip using a sample process parameter at a preset voltage interval and the reference temperature, the preset voltage interval being determined by the reference voltage and a dynamic voltage; and fit the second function relationship based on the plurality of second sample data, the second function relationship being used to represent a mapping relationship between a variation of power consumption with voltage and a process parameter at the reference temperature.

[0155] In some embodiments, the process of obtaining the equivalent activation energy under the current operating voltage is implemented by a third function relationship; the apparatus further comprises a function construction module configured to obtain a plurality of third sample data, the third sample data comprising measured power consumption of a chip at different temperatures and different voltages; determine, based on the third sample data at the reference temperature and the third sample data at a plurality of other temperatures, a first equivalent activation energy corresponding to the third sample data at each of the other temperatures with the reference temperature as a base point; for each voltage-temperature point, determine a second equivalent activation energy corresponding to the voltage-temperature point based on the first equivalent activation energy of all chips at the voltage-temperature point, the voltage-temperature point being a combination of a voltage and a temperature; and among the second equivalent activation energy corresponding to each voltage-temperature point, determine a third equivalent activation energy corresponding to each voltage based on the second equivalent activation energy of all temperatures corresponding to the voltage; and fit the third function relationship based on the third equivalent activation energy corresponding to each voltage, the third function relationship being used to represent a mapping relationship between equivalent activation energy and voltage.

[0156] In some embodiments, the power consumption determination module is further configured to determine, based on the current operating temperature, the reference temperature, and the equivalent activation energy under the current operating voltage, a power consumption adjustment coefficient; and adjust the second static power consumption based on the power consumption adjustment coefficient to obtain a target static power consumption of the chip under the current operating voltage and the current operating temperature.

[0157] In some embodiments, the first function relationship, the second function relationship and the third function relationship are linear or nonlinear functions; wherein the first function relationship and the second function relationship are linear functions, and the third function relationship is a quadratic function; function parameters of the first function relationship, the second function relationship and the third function relationship are stored in a chip firmware.

[0158] In some embodiments, the power consumption determination module is further configured to, in response to a change in the current operating temperature, determine a target static power consumption of the chip at the current operating voltage and the changed operating temperature based on the equivalent activation energy at the current operating voltage, the second static power consumption and the changed operating temperature.

[0159] In some embodiments, the power consumption determination module is further configured to, in response to a change in the current operating voltage, compensate the first static power consumption based on a difference between the changed operating voltage and the reference voltage to obtain a third static power consumption of the chip at the changed operating voltage and the reference temperature; obtain an equivalent activation energy at the changed operating voltage, and determine a target static power consumption of the chip at the changed operating voltage and the current operating temperature based on the equivalent activation energy at the changed operating voltage, the third static power consumption and the current operating temperature.

[0160] The above device embodiments are similar to the above method embodiments in description, and have similar beneficial effects to the method embodiments. In some embodiments, the device provided by the embodiments of the present application has functions or includes modules that can be used to execute the methods described in the above method embodiments. For technical details not disclosed in the device embodiments of the present application, please refer to the description of the method embodiments of the present application.

[0161] It should be noted that, in the embodiments of the present application, if the power consumption determination method described above is realized in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the embodiments of the present application can be embodied in the form of a software product, which is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in the embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a magnetic disk or an optical disk, and various storage media that can store program codes. Thus, the embodiments of the present application are not limited to any specific hardware, software or firmware, or any combination of hardware, software and firmware.

[0162] This application provides a computer device including a memory and a processor. The memory stores a computer program that can run on the processor. When the processor executes the program, it implements some or all of the steps in the above-described method.

[0163] This application provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements some or all of the steps in the above-described method. The computer-readable storage medium can be transient or non-transient.

[0164] This application provides a computer program including computer-readable code, wherein when the computer-readable code is executed in a computer device, a processor in the computer device performs some or all of the steps in the above-described method.

[0165] This application provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program. When the computer program is read and executed by a computer, it implements some or all of the steps in the above-described method. This computer program product can be implemented specifically through hardware, software, or a combination thereof. In some embodiments, the computer program product is specifically embodied as a computer storage medium; in other embodiments, the computer program product is specifically embodied as a software product, such as a software development kit (SDK), etc.

[0166] It should be noted that the descriptions of the various embodiments above tend to emphasize the differences between them, while their similarities or commonalities can be referred to interchangeably. The descriptions of the above embodiments of the device, storage medium, computer program, and computer program product are similar to the descriptions of the above method embodiments and have similar beneficial effects. For technical details not disclosed in the embodiments of the device, storage medium, computer program, and computer program product of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0167] Figure 7 This application provides a hardware entity diagram of a computer device as an embodiment of the present application, such as... ​ As shown, the hardware entity of the computer device 300 includes a processor 301 and a memory 302, wherein the memory 302 stores a computer program that can run on the processor 301, and the processor 301 executes the program to implement the steps in the method of any of the above embodiments.

[0168] The memory 302 stores computer programs executable on the processor, and is configured to store instructions and applications executable by the processor 301, and can also cache data (for example, image data, audio data, voice communication data and video communication data) to be processed by the processor 301 and modules in the computer device 300, and can be implemented by a FLASH or a Random Access Memory (RAM).

[0169] The processor 301 implements the steps of any of the power consumption determination methods described above when executing the program. The processor 301 generally controls the overall operation of the computer device 300.

[0170] The processor described above can be at least one of an Application Specific Integrated Circuit (ASIC), a Digital Signal Processor (DSP), a Digital Signal Processing Device (DSPD), a Programmable Logic Device (PLD), a Field Programmable Gate Array (FPGA), a Central Processing Unit (CPU), a controller, a microcontroller, or a microprocessor. It can be understood that the electronic device implementing the functions of the processor described above can also be other, and the embodiments of the present application are not limited specifically.

[0171] The computer storage medium / memory can be a Read Only Memory (ROM), a Programmable Read-Only Memory (PROM), an Erasable Programmable Read-Only Memory (EPROM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), a Ferromagnetic Random Access Memory (FRAM), a Flash Memory, a magnetic surface storage, an optical disc, a Compact Disc Read-Only Memory (CD-ROM), or the like memory; or can be various terminals including one or any combination of the above memories, such as a mobile phone, a computer, a tablet device, a personal digital assistant, and the like.

[0172] It should be understood that every monetary term referred to throughout the specification means that the specific feature, structure or characteristic related to the embodiment is included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that the size of the serial number of each step / process in various embodiments of the present application does not mean the order of execution, and the execution order of each step / process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above-mentioned serial number of the embodiments of the present application is only for description, not representing the advantages and disadvantages of the embodiments.

[0173] It should be noted that in this document, the terms "comprise", "comprise", or any other variant thereof are intended to cover non-exclusive inclusion, so that processes, methods, articles or devices including a series of elements not only include those elements, but also include other elements not explicitly listed, or include elements inherent to such processes, methods, articles or devices. Without more limitations, the element defined by the statement "comprises a" does not exclude the presence of another identical element in the process, method, article or device including the element.

[0174] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other manners. The described device embodiments are merely schematic. For example, the division of the units is only a logical function division. There can be another division manner for the actual implementation, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed coupling, or direct coupling or communication connection between the components can be indirect coupling or communication connection through some interfaces, devices, or units, and can be electrical, mechanical, or in other forms.

[0175] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units; they can be located in one place, or distributed on multiple network units; and some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0176] In addition, each functional unit in each embodiment of the present application can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in the form of hardware, or in the form of hardware plus software functional units. Those skilled in the art can understand that all or part of the steps of the above-mentioned method embodiments can be completed by program instruction related hardware, and the foregoing program can be stored in a computer readable storage medium, and the program is executed to perform the steps of the above-mentioned method embodiments; and the foregoing storage medium includes mobile storage devices, read-only memories (ROM), magnetic discs or optical discs, and various storage media that can store program codes.

[0177] Alternatively, the integrated units of the present application, if implemented in the form of software functional modules and sold or used as independent products, can also be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application can be embodied in the form of software products, and the computer software products are stored in a storage medium, including a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in the embodiments of the present application. The foregoing storage medium includes mobile storage devices, ROM, magnetic discs or optical discs, and various storage media that can store program codes.

[0178] The above merely provides the implementation of the present application, but the protection scope of the present application is not limited thereto, any person skilled in the art can easily think of the change or replacement within the technical range disclosed by the present application, which should be covered in the protection scope of the present application.

Claims

1. A power consumption determination method, characterized by, The method comprises: obtaining process parameters, a current operating voltage and a current operating temperature of a chip; determining a first static power consumption of the chip at a reference voltage and a reference temperature based on the process parameters; compensating the first static power consumption based on a difference between the current operating voltage and the reference voltage to obtain a second static power consumption of the chip at the current operating voltage and the reference temperature; obtaining an equivalent activation energy at the current operating voltage, and determining a target static power consumption of the chip at the current operating voltage and the current operating temperature based on the equivalent activation energy at the current operating voltage, the second static power consumption and the current operating temperature.

2. The method of claim 1, wherein, The process of determining the first static power consumption of the chip at the reference voltage and the reference temperature based on the process parameters is implemented through a first function relationship; The construction method of the first function relationship comprises: obtaining a plurality of first sample data; the first sample data comprises a measured power consumption of a chip using sample process parameters at the reference voltage and the reference temperature; fitting the first function relationship based on the plurality of first sample data; the first function relationship is used to represent a mapping relationship between power consumption and process parameters at the reference voltage and the reference temperature.

3. The method of claim 1, wherein, The process of compensating the first static power consumption based on a difference between the current operating voltage and the reference voltage to obtain a second static power consumption at the reference temperature comprises: determining a power consumption compensation parameter corresponding to the chip based on the process parameters of the chip; the power consumption compensation parameter is used to represent an influence degree of an operating voltage on power consumption; determining a voltage difference between the current operating voltage and the reference voltage; determining a compensated power consumption at the current operating voltage based on the voltage difference and the power consumption compensation parameter; compensating the first static power consumption by using the compensated power consumption at the current operating voltage to obtain a second static power consumption at the reference temperature.

4. The method of claim 3, wherein, The process of determining a power consumption compensation parameter corresponding to the chip based on the process parameters of the chip is implemented through a second function relationship; The construction method of the second function relationship comprises: obtaining a plurality of second sample data; the second sample data comprises a measured power consumption of a chip using sample process parameters at a preset voltage interval and the reference temperature; the preset voltage interval is determined by the reference voltage and a dynamic voltage; fitting the second function relationship based on the plurality of second sample data; the second function relationship is used to represent a mapping relationship between a variation amount of power consumption with voltage and process parameters at the reference temperature.

5. The method of claim 1, wherein, The process of obtaining an equivalent activation energy at the current operating voltage is implemented through a third function relationship; the construction method of the third function relationship comprises: obtaining a plurality of third sample data; the third sample data comprises a measured power consumption of a chip at different temperatures and different voltages; determining a first equivalent activation energy corresponding to third sample data at each of a plurality of other temperatures based on the third sample data at the reference temperature and the third sample data at the plurality of other temperatures, when the reference temperature is taken as a base point. For each voltage-temperature point, a second equivalent activation energy corresponding to the voltage-temperature point is determined based on the first equivalent activation energy of all the chips at the voltage-temperature point; the voltage-temperature point is a combination of one voltage and one temperature; In the second equivalent activation energy corresponding to each voltage-temperature point, for each voltage, a third equivalent activation energy corresponding to the voltage is determined based on the second equivalent activation energy of all the temperatures corresponding to the voltage; The third function relationship is fitted based on the third equivalent activation energy corresponding to each voltage; the third function relationship is used to represent the mapping relationship between the equivalent activation energy and the voltage.

6. The method of claim 1, wherein, The target static power consumption of the chip at the current running voltage and the current running temperature is determined based on the equivalent activation energy at the current running voltage, the second static power consumption, and the current running temperature, including: A power consumption adjustment coefficient is determined based on the current running temperature, the reference temperature, and the equivalent activation energy at the current running voltage; The second static power consumption is adjusted based on the power consumption adjustment coefficient to obtain the target static power consumption of the chip at the current running voltage and the current running temperature.

7. The method according to any one of claims 1 to 6, characterized in that, The first static power consumption is determined by a first function relationship, the second static power consumption is determined by a second function relationship, and the target static power consumption is determined by a third function relationship; function parameters of the first function relationship, the second function relationship, and the third function relationship are stored in the chip firmware.

8. The method according to any one of claims 1 to 6, characterized in that, The method further includes: In response to a change in the current running temperature, the target static power consumption of the chip at the current running voltage and the changed running temperature is determined based on the equivalent activation energy at the current running voltage, the second static power consumption, and the changed running temperature.

9. The method according to any one of claims 1 to 6, characterized in that, The method further includes: In response to a change in the current running voltage, the first static power consumption is compensated based on the difference between the changed running voltage and the reference voltage to obtain a third static power consumption of the chip at the changed running voltage and the reference temperature; The equivalent activation energy at the changed running voltage is obtained, and the target static power consumption of the chip at the changed running voltage and the current running temperature is determined based on the equivalent activation energy at the changed running voltage, the third static power consumption, and the current running temperature.

10. A power consumption determination apparatus characterized by comprising: The device includes: An acquisition module is configured to acquire process parameters, a current running voltage, and a current running temperature of a chip; A power consumption determination module is configured to determine a first static power consumption of the chip at a reference voltage and a reference temperature based on the process parameters; compensate the first static power consumption based on the difference between the current running voltage and the reference voltage to obtain a second static power consumption of the chip at the current running voltage and the reference temperature; obtain an equivalent activation energy at the current running voltage; and determine a target static power consumption of the chip at the current running voltage and the current running temperature based on the equivalent activation energy at the current running voltage, the second static power consumption, and the current running temperature.

11. A chip, characterized by The chip is configured to perform the power consumption determination method of any one of claims 1 to 9.

12. A computer device comprising a memory and a processor, the memory storing a computer program capable of running on the processor, characterized in that, The processor implements the steps of the method of any one of claims 1 to 9 when executing the program.

13. A computer readable storage medium having stored thereon a computer program, characterized in that The computer program, when executed by a processor, implements the steps of the method of any one of claims 1 to 9.

14. A computer program product comprising computer programs or instructions, characterized in that, The computer program or instructions, when executed by a processor, implement the steps of the method of any one of claims 1 to 9.

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