Constraint generation method and device, electronic equipment and readable storage medium

Abstract

The embodiment of the invention provides a constraint generation method and device, electronic equipment and a readable storage medium. The method comprises the following steps: acquiring a clock source of a to-be-tested design according to a design netlist of the to-be-tested design, and acquiring input and output port information; the design netlist comprises the circuit topology of the to-be-tested design; generating a clock definition for the to-be-tested design based on the clock source, and loading the clock definition into the design netlist; generating a boundary constraint for the to-be-tested design based on the input and output port information; and generating a clock relationship for the to-be-tested design according to the clock definition and the boundary constraint. In this way, automatic generation of the time sequence constraint including the clock definition, the boundary constraint and the clock relation can be achieved only through the design netlist of the to-be-tested design, and compared with a mode of manually compiling the time sequence constraint, the generation efficiency can be greatly improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a constraint generation method, apparatus, electronic device, and readable storage medium. Background Technology

[0002] With the development of integrated circuit technology, in order to improve the performance of integrated circuits, it is often necessary to test the circuit's operating capability at a specified frequency. Currently, static timing analysis is usually used to quickly test the timing of the circuit to ensure that the circuit meets the requirements under specified operating conditions, thereby enabling the integrated circuit to meet frequency specifications.

[0003] Static timing analysis primarily tests whether the circuit meets timing constraints; therefore, timing constraints are particularly important in static timing analysis. Currently, timing constraints are often manually written by designers, but this method is inefficient. Summary of the Invention

[0004] The purpose of this invention is to provide a constraint generation method, apparatus, electronic device, and readable storage medium to solve the problem of high cost for multi-application operation. The specific technical solution is as follows: In a first aspect of this invention, a constraint generation method is provided, the method comprising: Based on the design netlist of the design under test, obtain the clock source of the design under test and the input / output port information; the design netlist includes the circuit topology of the design under test. Based on the clock source, a clock definition is generated for the design under test, and the clock definition is loaded into the design netlist; Based on the input / output port information, boundary constraints are generated for the design under test; Based on the clock definition and the boundary constraints, a clock relationship is generated for the design under test.

[0005] In a second aspect of the invention, a constraint generation apparatus is also provided, the apparatus comprising: The first acquisition module is used to acquire the clock source of the design under test and the input / output port information based on the design netlist of the design under test; the design netlist includes the circuit topology of the design under test. The first generation module is used to generate a clock definition for the design under test based on the clock source, and load the clock definition into the design netlist; The second generation module is used to generate boundary constraints for the design under test based on the input / output port information. The third generation module is used to generate clock relationships for the design under test based on the clock definition and the boundary constraints.

[0006] In a third aspect of the present invention, an electronic device is also provided, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus. Memory, used to store computer programs; When a processor executes a program stored in memory, it implements the method described in the first aspect above.

[0007] In a fourth aspect of the invention, a computer-readable storage medium is also provided, wherein instructions are stored therein, which, when executed on a computer, cause the computer to perform the method described in the first aspect.

[0008] In a fifth aspect of the invention, a computer program product comprising instructions is also provided, which, when run on a computer, causes the computer to perform the method described in the first aspect above.

[0009] The constraint generation method provided in this invention obtains the clock source and input / output port information of the design under test (DUT) based on the design netlist. The design netlist includes the circuit topology of the DUT. Based on the clock source, a clock definition is generated for the DUT and loaded into the design netlist. Boundary constraints are generated for the DUT based on the input / output port information. Clock relationships are generated for the DUT based on the clock definition and the boundary constraints. Thus, this invention can automatically generate timing constraints, including clock definitions, boundary constraints, and clock relationships, using only the design netlist of the DUT, significantly improving generation efficiency compared to manually writing timing constraints. Furthermore, generating timing constraints based on the design netlist of the DUT avoids omissions caused by human factors during manual constraint writing, ensuring the accuracy of timing constraint generation to a certain extent. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below.

[0011] Figure 1 This is a flowchart illustrating the steps of a constraint generation method in an embodiment of the present invention; Figure 2 This is a schematic diagram of a candidate clock source in an embodiment of the present invention; Figure 3 This is a schematic diagram of another candidate clock source in an embodiment of the present invention; Figure 4 This is a schematic diagram of another candidate clock source in an embodiment of the present invention; Figure 5 This is a schematic diagram of clock creation in an embodiment of the present invention; Figure 6 This is a schematic diagram illustrating the creation of boundary constraints in an embodiment of the present invention; Figure 7 This is a schematic diagram illustrating another method for creating boundary constraints in an embodiment of the present invention. Figure 8 This is a schematic diagram illustrating the creation of a clock relationship in an embodiment of the present invention; Figure 9 A flowchart illustrating another constraint generation method in an embodiment of the present invention; Figure 10 This is a schematic diagram of the structure of a constraint generation device according to an embodiment of the present invention; Figure 11 This is a schematic diagram of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0012] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0013] The terms "first," "second," etc., used in the specification and claims of this invention are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, the first object can be one or more. Furthermore, the term "and / or" in the specification and claims is used to describe the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. In embodiments of this invention, the term "multiple" refers to two or more, and other quantifiers are similar.

[0014] Figure 1 This is a flowchart illustrating the steps of a timing constraint method according to an embodiment of the present invention, as follows: Figure 1 As shown, the method includes: Step 101: Based on the design netlist of the design under test, obtain the clock source of the design under test and the input / output port information; the design netlist includes the circuit topology of the design under test.

[0015] Step 102: Based on the clock source, generate a clock definition for the design under test and load the clock definition into the design netlist.

[0016] Step 103: Based on the input / output port information, generate boundary constraints for the design under test.

[0017] Step 104: Generate clock relationships for the design under test based on the clock definition and the boundary constraints.

[0018] Regarding steps 101-104 above, the embodiments of the present invention can be performed during the chip design stage or before chip tape-out; the embodiments of the present invention do not impose any limitations on this. The design under test can be an integrated circuit design or a chip design that requires static timing analysis. The design netlist refers to the circuit design netlist, which includes the circuit topology of the circuit design and is used to describe the connection relationships between circuit elements.

[0019] Optionally, embodiments of the present invention can be applied to Electronic Design Automation (EDA) tools. Further, the design netlist of the design under test can be obtained through input information from relevant personnel, or it can be obtained by accessing a designated storage device; embodiments of the present invention do not impose limitations on this.

[0020] The aforementioned clock source refers to the starting point of the clock signal. In this embodiment of the invention, the design netlist can be traversed to determine the root node as the clock source. The aforementioned input / output port information refers to the input and output ports included in the design under test (DUT). Both the clock source and the input / output port information can be obtained from the circuit topology in the design netlist. Specifically, the design netlist can be parsed to obtain the connection structure and timing path of each device in the DUT, and then the aforementioned clock source and input / output port information can be obtained from the connection structure and timing path.

[0021] The aforementioned timing constraints (TCs) can include clock definitions, boundary constraints, and clock relationships. They can serve as checking rules for static timing analysis, establishing frequency standards before chip fabrication, and can also guide core control placement and routing tools for optimized design. Furthermore, a clock definition can be generated for the design under test based on the aforementioned clock source, and the generated clock definition can be loaded into the design netlist. Specifically, the aforementioned clock definition (Clock Denifination, CD) can include a source clock and a generated clock. The source clock is the primary clock signal source, which can be a clock generated by an external crystal oscillator or other clock generation devices such as a phase-locked loop. The aforementioned generated clock refers to the clock generated through frequency division, frequency multiplication, or other logic operations of the source clock. Specifically, the operation of generating the aforementioned clock definition can be implemented using the clock creation command (create_clock).

[0022] The aforementioned boundary constraints (BC) define the timing relationships between the chip's input / output ports and the external environment. Timing constraints including boundary constraints can prevent setup time or hold time violations caused by signal transmission delays. This embodiment of the invention can determine each timing path based on input / output port information, and then select the timing paths from which boundary constraints need to be constructed, generating boundary constraints for them.

[0023] The aforementioned clock relationships (CRs) define the interaction rules between different clock signals in the design, guiding timing analysis tools to correctly handle paths across clock domains. They also constrain the synchronization or asynchronicity of clock signals. Specifically, embodiments of the present invention can generate synchronous or asynchronous relationships for different clocks based on the generated clock definitions and boundary constraints.

[0024] It's important to note that operating clock frequency is often considered a characteristic of high-performance integrated circuits. To test a circuit's ability to operate at a specified clock speed, it's necessary to measure delays at different operating stages during the design process. Furthermore, delay calculations need to be performed within the timing optimization program at various design stages (e.g., logic synthesis, placement, routing, and subsequent stages). While rigorous SPICE circuit simulation can be used for such timing measurements, this method is extremely time-consuming in practice. Therefore, static timing analysis plays a crucial role in the fast and accurate measurement of circuit timing.

[0025] Before chip tape-out, static timing analysis is often performed using EDA tools to check whether the designed circuit meets timing constraints. Timing constraints can be seen as the checking rules for static timing analysis. The objects of timing constraint checking are all paths within the chip, and the content of the check is setup time and hold time. Setup time refers to the time the data signal needs to remain stable before the arrival of the valid edge of the clock signal. If the setup time requirement is not met, metastability may occur, resulting in a setup time violation. If a setup time violation occurs, the chip can be restored to normal operation by reducing its operating frequency. Hold time refers to the time the data signal needs to remain stable after the arrival of the valid edge of the clock to prevent the valid edge from sampling the data of the current clock cycle. If a hold time violation occurs, the chip will not function properly.

[0026] Currently, to improve design efficiency, chip back-end design often employs a hierarchical physical design approach. This approach divides the design into several segments, and then performs independent placement, routing, and other flattening processes on each segment until the corresponding modeling is completed, at which point the assembly design is finalized at the top level. However, the segmentation and timing optimization of submodules require multiple iterations. If timing constraints are written by relevant personnel during this process, it will significantly impact the design progress of the submodules.

[0027] The constraint generation method provided in this embodiment of the invention obtains the clock source and input / output port information of the design under test (DUT) based on the design netlist. The design netlist includes the circuit topology of the DUT. Based on the clock source, a clock definition is generated for the DUT and loaded into the design netlist. Boundary constraints are generated for the DUT based on the input / output port information. Clock relationships are generated for the DUT based on the clock definition and the boundary constraints. Thus, this embodiment of the invention can automatically generate timing constraints, including clock definitions, boundary constraints, and clock relationships, using only the design netlist of the DUT, significantly improving generation efficiency compared to manually writing timing constraints. Furthermore, generating timing constraints based on the design netlist of the DUT avoids omissions caused by human factors during manual constraint writing, ensuring the accuracy of timing constraint generation to a certain extent.

[0028] Optionally, the operation of obtaining the clock source of the design under test based on the design netlist of the design under test may specifically include, in this embodiment of the invention: S21. Traverse the design netlist of the design under test to obtain the clock signal input terminal, the output terminal of the timing unit, and the output terminal of each input port of the timing unit included in the design under test.

[0029] S22. Based on the clock signal input terminal, the output terminal of the timing unit, and the output terminals of each input port, determine the candidate clock source.

[0030] S23. Based on the timing path between each of the candidate clock sources and the timing unit, select the candidate clock source that meets the requirements as the clock source of the design under test.

[0031] In this context, the aforementioned timing unit refers to a circuit element with state storage functionality, whose output depends not only on the current input but also on the circuit's historical states. This timing unit can be a flip-flop (FF), random access memory (RAM), etc. Correspondingly, the aforementioned clock signal input terminal refers to the port of the timing unit used to receive clock signals, and the aforementioned timing unit output terminal refers to the port of the timing unit used to transmit data states externally. Specifically, the aforementioned input port refers to the port used to receive signals transmitted from external circuits or devices, which can be the input terminal of a flip-flop or the output port of other modules. Correspondingly, the output terminal of the input port refers to the port that transmits the received clock signal; specifically, the output terminal of the input port is used to directly output the clock signal received from the input port without storage, i.e., input clock -> output clock.

[0032] Specifically, embodiments of the present invention can parse and traverse the design netlist to obtain timing units and input ports. Further, based on the input and output paths of the timing units and the output paths of the input ports, the aforementioned clock signal input terminals, output terminals, and the output terminals of each input port can be obtained.

[0033] Furthermore, in this embodiment of the invention, the clock signal input terminal, the output terminal of the timing unit, and the output terminal of each input port can be used to determine the candidate clock source, and based on the timing path between each candidate clock source and the timing unit, the candidate clock source that meets the requirements can be selected as the clock source of the design under test, i.e., the actual clock source.

[0034] Optionally, the operation of determining the candidate clock source based on the clock signal input terminal, the output terminal of the timing unit, and the output terminals of each input port, as described above, may specifically include the following in this embodiment of the invention: S221. Determine the starting node of the clock signal input terminal as the candidate clock source.

[0035] S222. If the clock signal input terminal of the timing unit exists at the end node of the output terminal of the timing unit, the output terminal of the timing unit is determined as the candidate clock source.

[0036] S223. For any of the input ports, if there is a clock signal input terminal of a timing unit at the end node of the output port, the input port is determined as a candidate clock source.

[0037] The above-described operation of selecting a suitable clock source as the clock source for the design under test based on the timing paths between each of the candidate clock sources and the timing unit can be specifically included in the following embodiments of the present invention: S231. If the timing path between the candidate clock source and the timing unit only includes a clock selection device and / or a clock switching device, the candidate clock source is determined as the clock source of the design under test.

[0038] Here, the aforementioned start node refers to the logical starting point of the signal input to the timing unit. Correspondingly, the aforementioned end node refers to the logical ending point of the output signal from the output terminal or input port of the timing unit.

[0039] Specifically, the aforementioned starting node can be obtained by traversing and searching the root node of the timing unit. Correspondingly, the aforementioned ending node can be obtained by traversing and searching the leaf nodes of the timing unit or input port.

[0040] Specifically, Figure 2 This is a schematic diagram of a candidate clock source in an embodiment of the present invention, such as... Figure 2 As shown, FF refers to a flip-flop, i.e., a sequential unit; source_bk represents the selectable clock source corresponding to the input of the sequential unit; CK represents the clock signal input; and D represents the data signal input. Figure 2 As shown, the starting node of the clock signal input terminal can be determined as the candidate clock source.

[0041] Specifically, Figure 3 This is a schematic diagram of another candidate clock source in an embodiment of the present invention, such as... Figure 3 As shown, FF refers to the flip-flop, i.e., the sequential unit; Q represents the data signal output of the flip-flop; and source_reg represents the candidate clock source corresponding to the output of the sequential unit, such as... Figure 3 As shown, if the clock signal input terminal of the timing unit exists at the end node of the timing unit's output, the output terminal of the timing unit can be determined as the candidate clock source, thereby... Figure 3 The triggers marked with circles are the candidate clock sources.

[0042] Specifically, in this embodiment of the invention, the existence of a clock signal input terminal for a timing unit can be determined based on the library unit name used by the end node.

[0043] Specifically, Figure 4This is a schematic diagram of another candidate clock source in an embodiment of the present invention, such as... Figure 4 As shown, FF refers to a flip-flop, i.e., a sequential unit; CK represents the clock signal input; D represents the data signal input; input represents the input port; and source_port represents the candidate clock source corresponding to the input port. Figure 4 As shown, if the clock signal input terminal of the timing unit exists at the end node of the output terminal of the input port, the input port can be determined as the candidate clock source, thereby... Figure 4 The input ports marked with circles are the candidate clock sources.

[0044] Furthermore, after obtaining the candidate clock sources, a candidate clock source that meets the requirements can be selected from the candidate clock sources as the clock source for the design under test.

[0045] The aforementioned clock switching device refers to a gated clock, used to dynamically turn the clock signal on or off. The aforementioned clock selection device refers to a clock signal selection unit, used to dynamically switch the valid clock among multiple clock sources. Specifically, the timing path between each candidate clock source and the timing unit can be obtained. If the timing path only includes the clock selection device and / or clock switching device, then this timing path can be determined as a clock path, and the candidate clock source meets the requirements and can be identified as the clock source for the design under test.

[0046] For example, if the timing path between the candidate clock source and the timing unit includes a clock signal selection unit mux(.D0(), .D1(), S()), where the S terminal controls the selection of the clock signal from D0 or D1, and if S originates from the output of another flip-flop, then the timing path includes not only the clock signal selection unit but also the flip-flop. In this case, the timing path is not a clock path, and correspondingly, the candidate clock source is not the clock source of the design under test.

[0047] As another example, if the timing path between the candidate clock source and the timing unit includes a gated clock CG (.CK(), .EN(), .Q()), and the EN terminal controls whether the clock signal of CK can be output through Q, and if EN comes from the output of another flip-flop, then the timing path includes not only the gated clock but also the flip-flop. In this case, the timing path is not a clock path, and correspondingly, the candidate clock source is not the clock source of the design under test.

[0048] In this embodiment of the invention, the clock source of the design under test can be obtained by designing a netlist, and the actual clock source of the design under test can be obtained from it through timing units and input ports, which facilitates the subsequent generation of clock definitions.

[0049] Optionally, the above clock definition includes a source clock and a generated clock; the operation of generating a clock definition for the design under test based on the clock source may specifically include, in embodiments of the present invention: S31. For any of the clock sources, if the clock source is an input port or a clock generation structure in the design under test, create a source clock at the clock source.

[0050] Alternatively, S32, if the clock source is the output of a timing unit in the design under test, a generated clock is created at the clock source.

[0051] The aforementioned clock generation structure refers to clock generation devices such as phase-locked loops (PLLs). Accordingly, when the clock source is an input port or a clock generation structure in the design under test, indicating that the clock source can generate a clock, a source clock can be created at that clock source.

[0052] Accordingly, when the clock source is the output of a timing unit in the design under test, since some distributed clocks are often generated by the timing unit, the clock at the output of that timing unit is a clock signal derived from the source clock. Therefore, embodiments of the present invention can create a generated clock at this clock source. The generated clock can be used for distribution or phase adjustment, etc.

[0053] Specifically, the operation of creating a source clock can be implemented using the source clock creation command (create_clock). The operation of creating a generated clock can be implemented using the generated clock creation command (create_generated_clock).

[0054] Specifically, Figure 5 This is a schematic diagram of clock creation in an embodiment of the present invention, such as... Figure 5 As shown, based on the above Figures 2-4 After obtaining the candidate clock sources (source_bk*, source_port*, source_reg*), each candidate clock source can be filtered. Specifically, the timing path between the candidate clock source and the timing unit can be determined by whether it only passes through a gating unit or other clock units. If so, it can be identified as a true clock source, resulting in several true clock sources (source_0~source_n). Further, for any true clock source, if it is an input port or a PLL, a source clock can be created at that true clock source. Conversely, if the true clock source is neither an input port nor a PLL, it is an output of the timing unit. In this case, a generated clock can be created at that true clock source, specifically based on the already created source clock.

[0055] In this embodiment of the invention, for any of the clock sources, if the clock source is an input port or a clock generation structure in the design under test, a source clock is created at the clock source; or, if the clock source is an output of a timing unit in the design under test, a generated clock is created at the clock source. This allows for the creation of source clocks and generated clocks according to the type of each clock source, ensuring the accuracy of the clock definition.

[0056] Optionally, the operation of generating boundary constraints for the design under test based on the input / output port information described above may specifically include, in embodiments of the present invention: S41. Obtain the target port of the design under test based on the input / output port information. S42. For any of the target ports, obtain the path endpoint of the target port in the design netlist.

[0057] S43. If the path endpoint belongs to the first end of the timing unit, obtain the source clock and generated clock associated with the path endpoint based on the clock definition in the design netlist, and use them as associated clocks.

[0058] S44. Create a virtual clock for the path endpoint based on the associated clock, and add a delay constraint to the path endpoint.

[0059] Wherein, the target port is an input port, the path endpoint is a path end point, and the first end is a data input end; or, the target port is an output port, the path endpoint is a path start point, and the first end is a data output end.

[0060] Specifically, the target port can be either an input port or an output port. When the target port is an input port, the path endpoint refers to the end point of the path, and the first end refers to the data input end. Correspondingly, when the target port is an output port, the path endpoint refers to the start point of the path, and the first end refers to the data output end.

[0061] Optionally, embodiments of the present invention may further include: If the path endpoint belongs to the second end, a delay constraint of not less than a preset threshold is added to the target timing path; the target timing path is the timing path formed by the path endpoint to the second end.

[0062] Wherein, the target port is an input port and the second end is an output end; or, the target port is an output port and the second end is an input end.

[0063] Specifically, when the target port is an input port, the second terminal mentioned above is an output terminal. Correspondingly, when the target port is an output port, the second terminal mentioned above is an input terminal.

[0064] The virtual clock mentioned above refers to a clock that does not contain a clock source. The preset threshold can be set according to actual needs, and this embodiment of the invention does not impose any restrictions on it. Specifically, the operation of adding a delay constraint can be implemented using the delay setting command (set_input_delay). The operation of adding a delay constraint not less than the preset threshold can be implemented using the maximum delay setting command (set_max_delay).

[0065] Specifically, Figure 6 This is a schematic diagram of creating boundary constraints in an embodiment of the present invention, such as... Figure 6 As shown, after traversing the design netlist, the input ports (input0~inputN) contained in the input / output port information can be obtained. For each input port, the end points of all timing paths of the input port are obtained, that is, the end points of all paths starting from input*. If the end point is a timing unit (data input), the source clock and the generated clock associated with the end point can be obtained as associated clocks based on the created clock definition, a corresponding virtual clock can be created, and the input delay of the corresponding virtual clock can be set for the input port. If the end point is an output port, a delay constraint of a maximum delay (i.e., a delay not less than a preset threshold) is added to the timing path from the input to the output.

[0066] Specifically, Figure 7 This is a schematic diagram of another method for creating boundary constraints in an embodiment of the present invention, such as... Figure 7 As shown, after traversing the design netlist, the output ports (output0~outputN) included in the input / output port information can be obtained. For each output port, the starting point of all timing paths of the output port is obtained, that is, the ending point of all paths starting from input*. If the ending point is a timing unit (data output terminal), the source clock and generated clock associated with the starting point can be obtained as associated clocks based on the created clock definition, a corresponding virtual clock can be created, and the input delay of the corresponding virtual clock can be set for the output port. If the ending point is an input port, a delay constraint of a maximum delay (i.e., a delay not less than a preset threshold) is added to the timing path from the input terminal to the output terminal.

[0067] In this embodiment of the invention, the target port of the design under test is obtained based on the input / output port information; for any target port, the path endpoint of the target port in the design netlist is obtained; if the path endpoint belongs to the first end of a timing unit, the source clock and the generated clock associated with the path endpoint are obtained based on the clock definition in the design netlist, and used as associated clocks; a virtual clock is created for the path endpoint based on the associated clocks, and delay constraints are added to the path endpoint; wherein, the target port is an input port, the path endpoint is the end point of the path, and the first end is a data input end; or, the target port is an output port, the path endpoint is the start point of the path, and the first end is a data output end. In this way, a virtual clock can be created for the target port and delay constraints can be added to it, and delay presets can be added to the path endpoints of the target port, thereby generating boundary constraints.

[0068] Optionally, the operation of generating clock relationships for the design under test based on the clock definition and the boundary constraints described above may specifically include, in this embodiment of the invention: S51. Group the source clocks and generated clocks included in the clock definition to obtain multiple source clock groups; each source clock group includes one source clock and the corresponding generated clock.

[0069] S52. For any virtual clock included in the boundary constraints, assign the virtual clock to the source clock group where the associated clock of the virtual clock is located.

[0070] S53. Set synchronization constraint rules for each of the source clock groups, and set asynchronous constraint rules for different source clock groups.

[0071] Specifically, in this embodiment of the invention, the source clock, the generated clock, and the virtual clock can be grouped. Different source clocks can be assigned to different source clock groups. Correspondingly, the generated clock is assigned to the source clock group where its corresponding source clock is located, and the virtual clock is assigned to the source clock group where its corresponding associated clock is located.

[0072] Specifically, Figure 8 This is a schematic diagram illustrating the creation of a clock relationship in an embodiment of the present invention, such as... Figure 8 As shown, Figure 8 The table shows source clock groups (Group1~M). A source clock group can include a source clock (clk), its corresponding generated clock (clk_gen), a virtual clock (v_clk), and a virtual clock (v_clk_gen) corresponding to each generated clock.

[0073] Furthermore, such as Figure 8As shown, in a source clock group, the source clock can be used as the parent node, and the corresponding other generated clocks and virtual clocks can be used as leaf nodes based on the association relationship.

[0074] Specifically, when creating a generated clock in the above steps, its association with the source clock can be recorded accordingly. Similarly, when creating a virtual clock, its association with the associated clock can also be recorded. Therefore, in this embodiment of the invention, the grouping of generated clocks and virtual clocks can be based on the recorded associations. Optionally, different clocks can be distinguished by their clock identifiers within the aforementioned association relationships.

[0075] The aforementioned synchronization constraint rule is used to set the clocks to a synchronous relationship, while the aforementioned asynchronous constraint rule is used to set the clocks to an asynchronous relationship.

[0076] Specifically, since the setup and hold times of the design under test need to be tested through timing constraints, this embodiment of the invention can set clocks from the same source (i.e., clocks belonging to the same source clock group) to a synchronous relationship, thereby verifying their setup and hold times. Correspondingly, clocks from different sources (i.e., clocks belonging to different source clock groups) do not need to have their setup and hold times tested, and therefore can be set to an asynchronous relationship.

[0077] Optionally, clock selection constraints can be set. For clock selection units where different clocks intersect, during timing analysis, the launch and capture trigger clocks on the same path can be set to select only one clock signal. This can be achieved using the clock selection command (set_case_analysis).

[0078] In this embodiment of the invention, the source clocks and generated clocks included in the clock definition are grouped to obtain multiple source clock groups; each source clock group contains one source clock and its corresponding generated clock; for any virtual clock included in the boundary constraints, the virtual clock is assigned to the source clock group containing its associated clock; synchronization constraint rules are set for each source clock group, and asynchronous constraint rules are set for different source clock groups. Thus, by grouping the created clocks and setting synchronization or asynchronous constraint rules for the groups, clock relationships can be generated, facilitating subsequent static timing analysis.

[0079] For example, Figure 9 A flowchart for another constraint generation in an embodiment of the present invention, such as... Figure 9As shown, this embodiment of the invention can read the netlist of the design under test and find the clock source by traversing the timing units in the netlist. The found clock sources are filtered to determine the source clock and the generated clock, and the generated clock definition is loaded into the netlist. Further, all input / output ports can be scanned based on the netlist to determine the virtual clock and add corresponding boundary delay constraints, and the virtual clock definition and boundary constraints are loaded into the netlist. Further, the source clock, generated clock, and virtual clock are grouped, and constraints for synchronization within the group and asynchronous operation of components are set.

[0080] In summary, the constraint generation method provided by the embodiments of the present invention can automatically generate constraints based on netlists. This can avoid the possible omissions that may occur when manually writing constraints, and it also facilitates backend designers to start the evaluation and iteration of the design in a timely manner. Even when the hardware description code is uncertain in the early stages of the design, the automatically generated constraints can be used for design evaluation.

[0081] Figure 10 This is a schematic diagram of the structure of a constraint generation device according to an embodiment of the present invention, such as... Figure 10 As shown, device 20 includes: The first acquisition module 201 is used to acquire the clock source of the design under test and the input / output port information based on the design netlist of the design under test; the design netlist includes the circuit topology of the design under test. The first generation module 202 is used to generate a clock definition for the design under test based on the clock source, and load the clock definition into the design netlist; The second generation module 203 is used to generate boundary constraints for the design under test based on the input / output port information. The third generation module 204 is used to generate clock relationships for the design under test based on the clock definition and the boundary constraints.

[0082] Optionally, the first acquisition module includes: The traversal submodule is used to traverse the design netlist of the design under test and obtain the clock signal input terminal, the output terminal of the timing unit and the output terminal of each input port of the timing unit included in the design under test. The first determining submodule is used to determine the candidate clock source based on the clock signal input terminal, the output terminal of the timing unit, and the output terminals of each input port; The selection submodule is used to select a clock source that meets the requirements as the clock source of the design under test based on the timing path between each of the candidate clock sources and the timing unit.

[0083] Optionally, the first determining submodule is specifically used for: The starting node of the clock signal input terminal is determined as the candidate clock source; If the clock signal input terminal of the timing unit exists at the end node of the output terminal of the timing unit, the output terminal of the timing unit is determined as the candidate clock source; For any of the input ports, if there is a clock signal input terminal of a timing unit at the end node of the output port, the input port is determined as a candidate clock source. The selection submodule is specifically used for: If the timing path between the candidate clock source and the timing unit only includes a clock selection device and / or a clock switching device, the candidate clock source is determined as the clock source of the design under test.

[0084] Optionally, the clock definition includes a source clock and a generated clock; the first generation module includes: The first creation submodule is used to create a source clock at any of the clock sources, provided that the clock source is an input port or a clock generation structure in the design under test. Alternatively, a second creation submodule is configured to create a generating clock at the clock source if the clock source is the output of a timing unit in the design under test.

[0085] Optionally, the second generation module includes: The second acquisition submodule is used to acquire the target port of the design under test based on the input / output port information. The third acquisition submodule is used to acquire the path endpoint of any of the target ports in the design netlist; The fourth acquisition submodule is used to acquire the source clock and generated clock associated with the path endpoint based on the clock definition in the design netlist when the path endpoint belongs to the first end of the timing unit, and use them as associated clocks. The third creation submodule is used to create a virtual clock for the path endpoint based on the associated clock and add delay constraints to the path endpoint; Wherein, the target port is an input port, the path endpoint is a path end point, and the first end is a data input end; or, the target port is an output port, the path endpoint is a path start point, and the first end is a data output end.

[0086] Optionally, the device further includes: An addition module is used to add a delay constraint of not less than a preset threshold to the target time-series path when the path endpoint belongs to the second end; the target time-series path is the time-series path formed by the path endpoint to the second end; Wherein, the target port is an input port and the second end is an output end; or, the target port is an output port and the second end is an input end.

[0087] Optionally, the third generation module includes: The grouping submodule is used to group the source clocks and generated clocks contained in the clock definition to obtain multiple source clock groups; each source clock group contains one source clock and the corresponding generated clock. The partitioning submodule is used to partition any virtual clock contained in the boundary constraints into the source clock group where the associated clock of the virtual clock is located; The configuration submodule is used to set synchronization constraint rules for each of the source clock groups, and to set asynchronous constraint rules for different source clock groups.

[0088] In summary, the constraint generation apparatus provided in this embodiment of the invention obtains the clock source and input / output port information of the design under test (DUT) based on the design netlist of the DUT; the design netlist includes the circuit topology of the DUT; a clock definition is generated for the DUT based on the clock source, and the clock definition is loaded into the design netlist; boundary constraints are generated for the DUT based on the input / output port information; and clock relationships are generated for the DUT based on the clock definition and the boundary constraints. Thus, this embodiment of the invention can automatically generate timing constraints, including clock definitions, boundary constraints, and clock relationships, using only the design netlist of the DUT, significantly improving generation efficiency compared to manually writing timing constraints. Furthermore, generating timing constraints based on the design netlist of the DUT avoids omissions caused by human factors during manual constraint writing, ensuring the accuracy of timing constraint generation to a certain extent.

[0089] As the device embodiment is basically similar to the method embodiment, the description is relatively simple, and relevant parts can be found in the description of the method embodiment.

[0090] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0091] Regarding the request processing apparatus in the above embodiments, the specific manner in which each module performs its operations has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0092] This invention also provides an electronic device, including: a processor and a memory for storing processor-executable instructions, wherein the processor is configured to execute the above-described constraint generation method.

[0093] Reference Figure 11 This is a schematic diagram of the structure of the electronic device provided in an embodiment of the present invention. Figure 11 As shown, the electronic device includes: a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface communicate with each other through the communication bus. The memory is used to store at least one executable instruction, which causes the processor to execute the constraint generation method of the aforementioned embodiment.

[0094] It should be noted that the electronic devices in the embodiments of this application include mobile electronic devices and non-mobile electronic devices.

[0095] The processor can be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), a FPGA (Field Programmable Gate Array), or other programmable devices, transistor logic devices, hardware components, or any combination thereof. The processor can also be a combination that implements computational functions, such as a combination of one or more microprocessors, or a combination of a DSP and a microprocessor.

[0096] The communication bus may include a path for transmitting information between the memory and the communication interface. The communication bus may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 3 The symbol is represented by only one line, but this does not mean that there is only one bus or one type of bus.

[0097] The memory may be ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or it may be EEPROM (Electrically Erasable Programmable Read Only Memory), CD-ROM (Compact Disk Read Only), magnetic tape, floppy disk and optical data storage devices, etc.

[0098] This invention also provides a non-transitory computer-readable storage medium that, when instructions in the storage medium are executed by a processor of an electronic device (server or terminal), enables the processor to perform... Figure 1 The constraint generation method is shown.

[0099] This invention also provides a computer program product containing instructions that, when run on a computer, cause the computer to perform... Figure 1 The constraint generation method is shown.

[0100] This application also provides a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is used to run programs or instructions to implement the various processes of the above-described constraint generation method embodiments and achieve the same technical effect. To avoid repetition, it will not be described again here.

[0101] It should be understood that the chip mentioned in the embodiments of this application may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0102] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0103] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, apparatus, or computer program products. Therefore, embodiments of the present invention can be implemented wholly or partially by software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented wholly or partially as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device such as a server or data center that integrates one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid state disks (SSDs)).

[0104] Embodiments of the present invention are described with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0105] These computer program instructions may also be stored in a computer-readable storage medium capable of directing a computer or other programmable data processing terminal device to operate in a predictive manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0106] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal equipment, causing a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0107] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.

[0108] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0109] It should be noted that the various data-related processes in the embodiments of this application are carried out in compliance with the relevant data protection laws and policies of the country where the location is located, and with the authorization granted by the owner of the corresponding device.

[0110] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0111] The foregoing has provided a detailed description of the constraint generation method, apparatus, electronic device, and readable storage medium provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A constraint generation method, characterized in that, The method includes: Based on the design netlist of the design under test, obtain the clock source of the design under test and the input / output port information; the design netlist includes the circuit topology of the design under test. Based on the clock source, a clock definition is generated for the design under test, and the clock definition is loaded into the design netlist; Based on the input / output port information, boundary constraints are generated for the design under test; Based on the clock definition and the boundary constraints, a clock relationship is generated for the design under test.

2. The method according to claim 1, characterized in that, The step of obtaining the clock source of the design under test based on the design netlist of the design under test includes: The design netlist of the design under test is traversed to obtain the clock signal input terminal, the output terminal of the timing unit, and the output terminal of each input port of the timing unit contained in the design under test. Based on the clock signal input terminal, the output terminal of the timing unit, and the output terminals of each input port, the candidate clock source is determined; Based on the timing path between each candidate clock source and the timing unit, a candidate clock source that meets the requirements is selected as the clock source for the design under test.

3. The method according to claim 2, characterized in that, The process of determining the candidate clock source based on the clock signal input terminal, the output terminal of the timing unit, and the output terminals of each input port includes: The starting node of the clock signal input terminal is determined as the candidate clock source; If the clock signal input terminal of the timing unit exists at the end node of the output terminal of the timing unit, the output terminal of the timing unit is determined as the candidate clock source; For any of the input ports, if there is a clock signal input terminal of a timing unit at the end node of the output port, the input port is determined as a candidate clock source. The step of selecting a suitable clock source as the clock source for the design under test based on the timing path between each of the candidate clock sources and the timing unit includes: If the timing path between the candidate clock source and the timing unit only includes a clock selection device and / or a clock switching device, the candidate clock source is determined as the clock source of the design under test.

4. The method according to claim 2, characterized in that, The clock definition includes the source clock and the generated clock; The step of generating a clock definition for the design under test based on the clock source includes: For any of the clock sources, if the clock source is an input port or a clock generation structure in the design under test, a source clock is created at the clock source; Alternatively, if the clock source is the output of a timing unit in the design under test, a generated clock is created at the clock source.

5. The method according to claim 1, characterized in that, The step of generating boundary constraints for the design under test based on the input / output port information includes: The target port of the design under test is obtained based on the input / output port information. For any of the target ports, obtain the path endpoints of the target port in the design netlist; If the path endpoint belongs to the first end of the timing unit, the source clock and the generated clock associated with the path endpoint are obtained based on the clock definition in the design netlist, and used as the associated clock; A virtual clock is created for the path endpoint based on the associated clock, and a delay constraint is added to the path endpoint; Wherein, the target port is an input port, the path endpoint is a path end point, and the first end is a data input end; or, the target port is an output port, the path endpoint is a path start point, and the first end is a data output end.

6. The method according to claim 5, characterized in that, The method further includes: If the path endpoint belongs to the second end, a delay constraint of not less than a preset threshold is added to the target timing path; the target timing path is the timing path formed by the path endpoint to the second end. Wherein, the target port is an input port and the second end is an output end; or, the target port is an output port and the second end is an input end.

7. The method according to claim 5, characterized in that, The step of generating clock relationships for the design under test based on the clock definition and the boundary constraints includes: The source clocks and generated clocks included in the clock definition are grouped to obtain multiple source clock groups; each source clock group contains one source clock and the corresponding generated clock. For any virtual clock included in the boundary constraints, the virtual clock is assigned to the source clock group where the associated clock of the virtual clock is located; Synchronization constraint rules are set for each of the source clock groups, and asynchronous constraint rules are set for different source clock groups.

8. A constraint generation device, characterized in that, The device includes: The first acquisition module is used to acquire the clock source of the design under test and the input / output port information based on the design netlist of the design under test; the design netlist includes the circuit topology of the design under test. The first generation module is used to generate a clock definition for the design under test based on the clock source, and load the clock definition into the design netlist; The second generation module is used to generate boundary constraints for the design under test based on the input / output port information. The third generation module is used to generate clock relationships for the design under test based on the clock definition and the boundary constraints.

9. An electronic device, characterized in that, It includes a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; Memory, used to store computer programs; A processor, when executing a program stored in memory, implements the method described in any one of claims 1-7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the method as described in any one of claims 1-7.

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