Novel integrated circuit de-bonding process method

Abstract

The invention discloses a novel integrated circuit de-bonding process method, and belongs to the technical field of integrated circuits. Comprising the following steps: preparing a glass substrate; an LAL layer is arranged on the glass substrate; coating and curing a first dielectric layer on the LAL layer; exposing and developing the first dielectric layer to form a windowing part; the windowing part retains part of the first dielectric layer; constructing an RDL layer; welding a chip on the RDL layer in a flip-chip manner; performing plastic packaging on the chip through a plastic packaging material; and stripping the plastic-packaged product from the glass substrate. According to the invention, the exposure condition of the first photosensitive dielectric layer is adjusted, so that the dielectric layer less than 0.3 [mu] m is remained at the bottom of the window to replace a Base dielectric layer for isolation, the coating process is omitted, and the technological process is greatly simplified.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of integrated circuits, and particularly relates to a novel integrated circuit debonding process method. BACKGROUND

[0002] As a leading packaging technology, the RDL-first process first completes wiring on a carrier sheet, and then performs a unique process flow for chip packaging, effectively avoiding packaging defects that may be caused in the wiring process, significantly improving packaging yield, and laying a solid foundation for realizing high-performance and high-reliability packaging of integrated circuits.

[0003] The LAL structure plays a key role in glass substrate-related processes. The specific process steps are as follows: first, a layer of LAL is precisely applied on the glass carrier, which provides the necessary foundation and specific functions for subsequent processes. Next, a layer of Base (priming) dielectric layer is coated on the LAL layer, which has multiple functions such as isolation, buffering, and optimizing subsequent process conditions. After completing the Base dielectric layer coating, the RDL (Redistribution Layer) preparation link is entered, and through a series of complex and precise process operations, an RDL layer that meets the performance requirements of integrated circuits is constructed. Subsequently, chip flip-chip or mounting, wire bonding, encapsulation, and other process steps are carried out on the top layer, which are interrelated and closely connected, and together complete the packaging process of the chip. Finally, by applying a specific light source to irradiate the LAL layer, the LAL layer absorbs light energy and converts it into heat energy, causing the adjacent dielectric layer to be heated and carbonized, thereby realizing the debonding of the glass substrate and separating the packaged product from the glass substrate.

[0004] However, the above-mentioned traditional process has obvious drawbacks. Among them, the coating of the Base dielectric layer not only increases the complexity of the process, prolongs the overall process flow, and increases the difficulty and cost of process control, but also lengthens the production cycle, which is not conducive to large-scale and efficient integrated circuit manufacturing. SUMMARY

[0005] In view of the above situation, in order to overcome the defects of the prior art, the present application optimizes the process steps, effectively avoids the many problems brought about by the coating of the Base dielectric layer in the traditional process, greatly simplifies the process flow, reduces production costs, shortens the production cycle, significantly improves the efficiency and benefit of integrated circuit manufacturing, and opens up a new path for the development of integrated circuit packaging technology.

[0006] In order to achieve the above-mentioned purpose, the following technical solutions are adopted: the present application provides a novel integrated circuit debonding process method, comprising: preparing a glass substrate; providing an LAL layer on the glass substrate; coating and curing a first layer of medium on the LAL layer; exposing and developing the first layer of medium to form a windowed portion; the windowed portion retains part of the first layer of medium; constructing an RDL layer; flip-chip bonding a chip on the RDL layer; encapsulating the chip with encapsulating material; peeling the encapsulated product from the glass substrate.

[0007] Further, the first layer of medium of the windowed portion does not need to be completely developed, and a layer of medium less than 0.3 μm is retained at the bottom of the windowed portion.

[0008] Further, the first layer of medium is a photosensitive medium layer.

[0009] The present application has the following beneficial effects: the present application adjusts the exposure conditions of the first layer of photosensitive medium layer, so that a layer of medium less than 0.3 μm is retained at the bottom of the windowed portion to replace the Base medium layer to serve as an isolation function, and the coating process is omitted, thereby greatly simplifying the process flow. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 FIG. 1 is a structural schematic diagram of the present application after sputtering the LAL layer on the glass substrate; Figure 2 FIG. 2 is a structural schematic diagram of the present application after coating and curing the first layer of medium; Figure 3 FIG. 3 is a structural schematic diagram of the present application after exposing and developing the first layer of medium to form a windowed portion; Figure 4 FIG. 4 is a structural schematic diagram of the present application after the RDL layer is constructed; Figure 5 FIG. 5 is a structural schematic diagram of the present application after flip-chip bonding a chip on the RDL layer; Figure 6 FIG. 6 is a structural schematic diagram of the present application after encapsulating the chip with encapsulating material; Figure 7 FIG. 7 is a structural schematic diagram of the present application after peeling the encapsulated product from the glass substrate.

[0011] Legend: 1, glass substrate; 2, LAL layer; 3, first layer of medium; 4, windowed portion; 5, RDL layer; 6, chip; 7, encapsulating material.

[0012] The accompanying drawings are included to provide a further understanding of the present application, and constitute a part of the specification, illustrate the present application and explain the present application together with the embodiments of the present application, and do not constitute a limitation of the present application. DETAILED DESCRIPTION

[0013] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, and not all embodiments based on the embodiments in the present application. All other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0014] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. In addition, any method and material similar or equivalent to those described herein can be used in the present application. The preferred implementation methods and materials described herein are only for demonstration, but cannot limit the content of the present application.

[0015] In the following examples, the experimental methods are all conventional methods unless otherwise specified. The test materials used in the following examples are all purchased from commercial channels unless otherwise specified. Embodiments

[0016] Reference Figures 1-7 An embodiment provided by the present application is a new integrated circuit debonding process method, and the specific steps are as follows: Prepare the substrate: Prepare the glass substrate 1, and the size of the glass substrate 1 needs to be selected according to the actual packaging requirements to ensure that it can meet the size accuracy requirements of subsequent process steps. Before use, the glass substrate 1 can be cleaned and dried to remove possible dust, oil stains and other pollutants on the surface to avoid interference with subsequent processes. Set the LAL layer 2 on the glass substrate 1, and the setting method is realized by a sputtering process: A sputtering process is used to uniformly sputter a layer of LAL layer 2 on the cleaned glass substrate 1. During the sputtering process, the sputtering parameters such as sputtering power, sputtering time, gas flow rate, etc. need to be accurately controlled to ensure the thickness uniformity and quality stability of the LAL layer 2, and the structure as shown in Figure 1 is obtained. In this structure, the LAL layer 2 is tightly attached to the surface of the glass substrate 1 to provide a specific functional basis for subsequent processes.

[0017] Coat and solidify the first layer of medium layer 3: On the sputtered LAL layer 2, a professional coating device is used to uniformly coat a layer of photosensitive medium material to form the first layer of medium layer 3. During the coating process, factors such as coating speed, coating amount, and environmental temperature and humidity need to be strictly controlled to ensure the thickness uniformity and surface flatness of the first layer of medium layer 3. Through a suitable solidification process, the first layer of medium layer 3 forms a stable solid structure, and the structure as shown in Figure 2 is obtained.

[0018] Exposure and development of the first layer of dielectric layer 3 to form the windowed portion 4: After curing the first layer of dielectric layer 3, exposure treatment is performed using ultraviolet light of a specific wavelength, and the mask with a specific pattern is used for irradiation. During exposure, the exposure intensity, exposure time and uniformity of ultraviolet light need to be accurately controlled to ensure the accuracy and clarity of the exposure pattern. It is worth noting that the first dielectric layer 3 of the windowed portion 4 does not need to be completely developed, and a layer of dielectric less than 0.3 μm remains at the bottom of the windowed portion 4. This residual first dielectric layer 3 plays the role of isolation in the subsequent process, resulting in a structure as shown in Figure 3 .

[0019] RDL layer 5 is constructed: On the first layer of dielectric layer 3 forming the windowed portion 4, the RDL layer 5 (RDL layer: Redistribution Layer) is constructed through a series of complex and precise process operations. This process usually includes multiple steps such as metal deposition, photolithography, etching, etc. First, physical vapor deposition (PVD) or chemical vapor deposition (CVD) method is used to deposit a thin layer of metal, such as copper, aluminum and other metal materials, on the surface of the first dielectric layer 3. The deposition thickness is accurately controlled according to design requirements. Then, through photolithography process, photoresist and mask are used for patterned treatment of the metal film, and the required circuit pattern is transferred to the metal film. During the photolithography process, the parameters such as photoresist coating, exposure and development are controlled to ensure the accuracy of the pattern. Finally, through etching process, the metal parts not protected by photoresist are removed, thus forming the RDL layer 5 structure meeting the performance requirements of integrated circuits, resulting in a structure as shown in Figure 4 .

[0020] Flip-chip chip 6 on the RDL layer 5: The tested and sorted chip 6 is accurately flip-chip on the RDL layer 5 according to the design requirements. Flip-chip process is used to pre-apply solder (such as solder balls, solder paste, etc.) on the pads of the chip 6, then align the chip 6 with the corresponding pads of the RDL layer 5, and use heating or other methods to melt the solder, realizing the electrical connection and mechanical fixation between the chip 6 and the RDL layer 5. During flip-chip process, the parameters such as soldering temperature, soldering time and pressure need to be accurately controlled to ensure the reliability and consistency of the soldering quality, resulting in a structure as shown in Figure 5 . The chip 6 and the RDL layer 5 realize good electrical and mechanical connection.

[0021] The chip 6 is encapsulated by the encapsulation material 7: In order to protect the chip 6 and the connecting structure between the chip 6 and the RDL layer 5, the chip 6 is packaged by using a plastic packaging process. The plastic packaging material 7 (such as epoxy resin) is filled around the chip 6 by injection molding or the like to form a complete plastic package. During the plastic packaging process, the temperature, pressure, flow rate and the like of the plastic packaging material 7 are controlled so that the plastic packaging material 7 can be uniformly filled around the chip 6 and air bubbles, cavities and the like are avoided. After the plastic packaging is completed, a solidification treatment is performed to make the plastic packaging material 7 form a firm protective structure, and the structure shown in FIG. 8 is obtained, and the chip 6 is effectively protected. Figure 6

[0022] The product after the plastic packaging is peeled off from the glass substrate 1: The small than 0.3 μm medium remaining at the bottom of the windowed portion 4 plays a good isolation role during the peeling of the LAL layer 2 and the RDL layer 5, and prevents the peeling / bonding failure of the LAL layer 2 and the RDL layer 5 caused by the bonding of the two.

[0023] In summary, by adjusting the exposure conditions of the first layer of photosensitive first medium layer 3, the first medium layer 3 with a thickness less than 0.3 μm remaining at the bottom of the window replaces the Base first medium layer 3 to play an isolation role, and the coating process is omitted, the process flow is greatly simplified, the process cost is reduced, the production efficiency is improved, and the application value is significant.

[0024] Although the embodiments of the present application have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and variations can be made thereto without departing from the principles and spirit of the present application, and the scope of the present application is defined by the appended claims and their equivalents.

[0025] The above describes the present application and its embodiments, which are not limited, and the embodiments shown in the drawings are only one of the embodiments of the present application, and the actual application is not limited thereto. In summary, if a person skilled in the art is inspired by it, without departing from the purpose of the present application, without creative design, similar ways and embodiments of the technical solution are not included in the protection scope of the present application.​

Claims

1. A novel debonding process for integrated circuits, characterized in that: include: Prepare the glass substrate (1); A LAL layer (2) is disposed on the glass substrate (1); A first dielectric layer (3) is coated and cured on the LAL layer (2); The first dielectric layer (3) is exposed and developed to form a windowed portion (4); The windowed portion (4) retains a portion of the first medium layer (3); Construct the RDL layer (5); A flip-chip (6) is bonded onto the RDL layer (5); The chip (6) is encapsulated using encapsulation material (7); The encapsulated product is peeled off from the glass substrate (1).

2. The novel integrated circuit debonding process method according to claim 1, characterized in that: The first medium layer (3) of the windowed portion (4) does not need to be fully exposed, and a medium layer of less than 0.3 μm remains at the bottom of the windowed portion (4).

3. The novel integrated circuit debonding process method according to claim 1, characterized in that: The first dielectric layer (3) is a photosensitive dielectric layer.

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