Amplifier based on dual ldo and control method thereof

Abstract

The application relates to the technical field of circuit devices, and particularly provides an amplifier based on double LDOs and a control method thereof, which comprises two LDOs and two OPAs; an input end of the LDO1 is connected with VDD, an adjusting end is connected with the output end of the OPA1, an output end is connected with an output end Vout, and a positive forward current is output; an input end of the LDO2 is connected with the output end, an adjusting end is connected with the output end of the OPA2, and an output end is connected with a compensation voltage end V4 and absorbs a negative forward current; the OPA1 is used for voltage following processing on input Vset so as to transmit Vset to the adjusting end of the LDO1 and the inverting input end of the OPA2; and the OPA2 is used for collecting a voltage difference between the output end and Vset and transmitting the voltage difference to the adjusting end of the LDO2. Thus, the problems of low universality, high cost and unstable manufacturing efficiency of the amplifier based on integrated circuits in the related art are solved.

Description

Technical Field

[0001] This invention relates to the field of circuit device technology, and in particular to an amplifier based on dual LDOs and its control method. Background Technology

[0002] The variety of integrated circuits (ICs) for amplifiers is limited, and their versatility is low. Common amplifier IC models with voltage specifications above 100V typically have current specifications in the milliampere range. Amplifier IC solutions with even higher current specifications (such as 500mA) are relatively rare, leading to high costs and unstable supply. Generally, solutions involve building the amplifier from scratch using multiple components.

[0003] For amplifiers, existing solutions all rely on dedicated high-voltage operational amplifier ICs. Multiple ICs can be connected in parallel to form a dedicated IC to increase the current. However, dedicated ICs are still scarce in terms of high current specifications and have low versatility. They generally need to be customized, which leads to high manufacturing costs and unstable supply. Summary of the Invention

[0004] The present invention provides an amplifier based on dual LDOs and its control method, which at least solves the problems of low versatility, high cost and unstable manufacturing efficiency of integrated circuit-based amplifiers in related technologies.

[0005] This invention provides an amplifier based on dual LDOs, comprising: a first low-dropout linear regulator LDO1, a second low-dropout linear regulator LDO2, a first operational amplifier OPA1, and a second operational amplifier OPA2; the amplifier has a positive power supply terminal VDD, a negative power supply terminal VSS, an external setting voltage terminal Vset, and an output terminal Vout; both LDO1 and LDO2 have a built-in reference voltage source Vref; the input terminal of LDO1 is connected to the positive power supply terminal VDD, the adjustment terminal of LDO1 is connected to the output terminal of OPA1, and the output terminal of LDO1 is connected to the output terminal Vout, and LDO1 is used to output a positive current to the output terminal Vout; the input terminal of LDO2 is connected to the output terminal Vout, the adjustment terminal of LDO2 is connected to the output terminal of OPA2, and the output terminal of LDO2 is connected to a compensation voltage terminal V4. V4 is VSS + 2 × Vref. The LDO2 is used to absorb negative current from the output terminal Vout. The non-inverting input terminal of the OPA1 is connected to the external set voltage terminal Vset. The inverting input terminal of the OPA1 is connected to the output terminal of the OPA1. The output terminal of the OPA1 is also connected to the inverting input terminal of the OPA2. The OPA1 is used to perform voltage following processing on the input Vset to transmit the Vset to the adjustment terminal of the LDO1 and the inverting input terminal of the OPA2. The inverting input terminal of the OPA2 is connected to the output terminal of the OPA1. The non-inverting input terminal of the OPA2 is connected to the output terminal Vout. The output terminal of the OPA2 is connected to the adjustment terminal of the LDO2. The OPA2 is used to collect the voltage difference between the output terminal Vout and the output terminal Vset of the OPA1 and transmit the voltage difference to the adjustment terminal of the LDO2.

[0006] As an optional embodiment, both LDO1 and LDO2 include the reference voltage source Vref, an error amplifier, and a MOS transistor; the adjustment terminals of LDO1 and LDO2 are connected to one end of the reference voltage source Vref; the other end of the reference voltage source Vref is connected to the first input terminal of the error amplifier, the second input terminal of the error amplifier is connected to the output terminal of the corresponding LDO, and the output terminal of the error amplifier is connected to the gate of the MOS transistor; the source and drain of the MOS transistor are connected to the output terminal and input terminal of the corresponding LDO, respectively.

[0007] As an optional solution, an amplifier circuit is also included, comprising a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4; one end of the first resistor R1 is connected to the output terminal of OPA1, and the other end of the first resistor R1 is connected to the non-inverting input terminal of OPA2; one end of the second resistor R2 is connected to the output terminal Vout, and the other end of the second resistor R2 is connected to the inverting input terminal of OPA2; one end of the third resistor R3 is connected to the non-inverting input terminal of OPA2, and the other end of the third resistor R3 is connected to the negative power supply terminal VSS; one end of the fourth resistor R4 is connected to the inverting input terminal of OPA2, and the other end of the fourth resistor R4 is connected to the output terminal of OPA2.

[0008] As an alternative, the resistance values ​​of the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 are equal.

[0009] As an optional solution, a first capacitor C1 is also provided between the first resistor R1 and the second resistor R2; one end of the first capacitor C1 is connected to both the first resistor R1 and the second resistor R2, and the other end of the first capacitor C1 is grounded; a second capacitor C2 is provided between the inverting input terminal of the OPA2 and the output terminal Vout, and the two ends of the second capacitor C2 are respectively connected to the inverting input terminal and the output terminal of the OPA2; a third capacitor C3 is provided at the compensation voltage terminal V4, one end of the third capacitor C3 is connected to the compensation voltage terminal V4, and the other end of the third capacitor C3 is grounded.

[0010] As an optional solution, a fifth resistor R5 is provided between the output terminal of LDO1 and the input terminal of LDO2. One end of the fifth resistor R5 is connected to the output terminal of LDO1, and the other end of the fifth resistor R5 is connected to the input terminal of LDO2.

[0011] As an alternative, the resistance values ​​of the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 are equal and range from 1 to 100 kΩ; the resistance value of the fifth resistor R5 is in the range of 0 Ω < R5 ≤ 20 Ω.

[0012] As an optional solution, a sampling resistor Rs is also provided on the output terminal Vout; one end of the sampling resistor Rs is connected to the output terminal Vout, and the other end of the sampling resistor Rs is connected to the load of the amplifier; current detection terminals are led out from both ends of the sampling resistor, and voltage detection terminals are led out from both ends of the load.

[0013] As an alternative, the total voltage span of the power supply terminals of the amplifier is ≥120V, and the absolute value of the output / absorption current of the amplifier is ≥500mA.

[0014] As an optional solution, the value range of the external setting voltage terminal Vset is VSS+Vref≤Vset≤VDD-Vref, and the output voltage range of the output terminal Vout is VSS+2×Vref≤Vout≤VDD.

[0015] This invention also provides a control method for an amplifier based on dual LDOs, applied to any of the aforementioned amplifiers based on dual LDOs, comprising: when the amplifier is outputting positive current, an external set voltage terminal Vset is input to the non-inverting input terminal of OPA1; based on the voltage follower characteristic of OPA1, a reference voltage of equal amplitude to Vset is generated at the output terminal of OPA1 and transmitted to the adjustment terminal of LDO1; LDO1 obtains an output voltage of magnitude Vset + Vref based on a reference voltage source Vref and the reference voltage at the adjustment terminal, converts the positive power supply terminal VDD into a positive current, and transmits it to the output terminal Vout of the amplifier to supply power to an external load; the input current at the input terminal of LDO2 is zero, and LDO2 is in standby mode; when the load change causes a change in the voltage at the output terminal Vout, OPA1 maintains the reference voltage at the adjustment terminal of LDO1 at Vset and adjusts the conduction capability to maintain the voltage stability of the output terminal Vout; when the amplifier is absorbing negative current, LDO2... The input current at the input terminal of LDO1 is zero, and LDO1 is in standby mode. The external setting voltage terminal Vset is input to the non-inverting input terminal of OPA1. Based on the voltage following characteristic of OPA1, a reference voltage with the same amplitude as Vset is generated at the output terminal of OPA1 and transmitted to the inverting input terminal of OPA2. The non-inverting input terminal of OPA2 obtains the actual voltage through the output terminal Vout, calculates the voltage deviation between the reference voltage and the actual voltage, and outputs a voltage deviation signal to the adjustment terminal of LDO2. The adjustment terminal of LDO2, based on the voltage deviation signal and the compensation voltage terminal V4 connected to the output terminal of LDO2, absorbs negative current through the input terminal of LDO2 and discharges the negative current sequentially to the compensation voltage terminal and the negative power supply terminal. When the voltage at the output terminal Vout changes due to load changes, the voltage deviation signal output by OPA2 changes accordingly. The adjustment terminal of LDO2 adjusts the conduction capability and the magnitude of the absorbed negative current according to the changing voltage deviation signal to stabilize the voltage at the output terminal Vout.

[0016] The semiconductor structure provided by this invention utilizes a general-purpose high-voltage, high-current LDO to construct an amplifier with bidirectional voltage and current capabilities, solving the technical problems of limited amplifier IC variety, high cost, and unstable supply in related technologies. Simultaneously, through circuit design, it overcomes the inherent limitations of LDOs in not supporting bidirectional voltage / current and thus not being directly usable as general-purpose amplifiers, achieving high-specification output in terms of voltage range and current. Furthermore, leveraging the high shipment volume of general-purpose LDOs, it balances the economic efficiency and supply stability of the solution. Attached Figure Description

[0017] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the accompanying drawings used in the embodiments will be briefly introduced below.

[0018] Figure 1 This is a schematic diagram of the structure of an amplifier based on dual LDOs in an embodiment of the present invention.

[0019] Figure 2 This is a schematic diagram of the structure of an amplifier based on dual LDOs in an embodiment of the present invention.

[0020] Figure 3 This is a schematic diagram of the amplifier outputting the positive current in an embodiment of the present invention.

[0021] Figure 4 This is a schematic diagram of the amplifier absorbing negative current in an embodiment of the present invention.

[0022] Figure 5 This is a schematic diagram of the output voltage detection result of the amplifier in an embodiment of the present invention.

[0023] Figure 6 This is a schematic diagram of the output current detection result of the amplifier in an embodiment of the present invention. Detailed Implementation

[0024] Embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. It should be understood that the drawings and embodiments of the present invention are for illustrative purposes only and are not intended to limit the scope of protection of the present invention.

[0025] To address the technical issues of poor versatility and high cost associated with custom high-voltage, high-current amplifiers, high-voltage LDOs are used to build amplifiers. These high-voltage LDOs are readily available, inexpensive, and readily supplied, with current ratings exceeding 500mA, offering significant application advantages. However, LDOs themselves do not support bidirectional voltage or current, and therefore cannot be directly used as general-purpose amplifiers.

[0026] Therefore, this embodiment provides an amplifier based on dual LDOs, such as... Figure 1As shown, it includes: a first low-dropout linear regulator LDO1, a second low-dropout linear regulator LDO2, a first operational amplifier OPA1, and a second operational amplifier OPA2; the amplifiers are provided with a positive power supply terminal VDD, a negative power supply terminal VSS, an external setting voltage terminal Vset, and an output terminal Vout. Both LDO1 and LDO2 have a built-in reference voltage source Vref.

[0027] The non-inverting input of OPA1 is connected to the external set voltage Vset, and the inverting input of OPA1 is connected to the output of OPA1, forming a voltage follower. Therefore, the output voltage of OPA1 is always equal to Vset.

[0028] The output of OPA1 is also connected to the inverting input of OPA2. OPA1 is used to perform voltage follower processing on the input Vset to transmit Vset to the regulating terminal of LDO1 and the inverting input of OPA2. This reference voltage is simultaneously sent to the regulating terminal of LDO1 and the inverting input of OPA2.

[0029] The input terminal of LDO1 is connected to the positive power supply terminal VDD, and the adjustment terminal of LDO1 is connected to the output terminal of OPA1, namely Vset. The output terminal OUT of LDO1 is connected to the output terminal Vout, and LDO1 is used to output positive current to the output terminal Vout.

[0030] According to the inherent characteristics of an LDO: Vout = VADJ + Vref, therefore the output voltage of LDO1 is: Vout = Vset + Vref. When the load requires forward current (Iout > 0), LDO1 provides current from VDD to Vout.

[0031] The inverting input of OPA2 is connected to the output of OPA1, and the non-inverting input of OPA2 is connected to its output Vout. The output of OPA2 is connected to the regulating terminal of LDO2. OPA2 is used to acquire the voltage difference between its output Vout and the output Vset of OPA1, and transmit this voltage difference to the regulating terminal of LDO2. OPA2 acquires and amplifies the voltage difference between Vset and Vout in real time, and sends the difference signal to the regulating terminal of LDO2.

[0032] The input terminal of LDO2 is connected to the output terminal Vout. The adjustment terminal of LDO2 is connected to the output terminal of OPA2. The output terminal of LDO2 is connected to the compensation voltage terminal V4, which is VSS+2×Vref. LDO2 is used to absorb negative current from the output terminal Vout.

[0033] When the load generates a negative current (Iout < 0), the current flows from Vout into the input terminal of LDO2, and then through LDO2 to V4 and VSS, thus discharging the negative current. At the same time, OPA2 adjusts the conduction strength of LDO2 according to the deviation between Vout and Vset, so that Vout is stabilized at: Vout = Vset + Vref.

[0034] The set voltage Vset is followed by OPA1 to provide a precise reference for LDO1 and OPA2; LDO1 provides positive current to the output terminal Vout based on VDD so that the output voltage satisfies Vout=Vset+Vref; OPA2 collects the voltage difference between Vout and Vset in real time and controls LDO2; LDO2 absorbs negative current from the output terminal Vout under the compensation potential of V4=VSS+2Vref, realizing bidirectional current output and negative voltage discharge.

[0035] LDO1 and LDO2 automatically divide the work. When the amplifier outputs positive current, LDO1 automatically turns on and LDO2 turns off and goes into standby mode. When the amplifier draws negative current, LDO2 automatically turns on and LDO1 turns off and goes into standby mode. No mode switching is required; bidirectional current operation is automatically achieved through circuit principles.

[0036] The dual LDOs automatically divide their functions under the coordinated control of OPA1 and OPA2, achieving high voltage span, bidirectional high current, and high-precision stable output without switching.

[0037] LDO1 and LDO2 employ high-voltage components, with high-voltage power supplies at the positive terminal VDD and the negative terminal VSS. LDO1 uses VDD as its input and directly outputs high voltage to Vout; LDO2 uses VSS as its negative voltage reference and absorbs negative high-voltage current. This allows the amplifier's output voltage range to cover the area from near VSS to near VDD, achieving a high voltage span of ≥120V.

[0038] It should be noted that the high voltage in this embodiment is a higher voltage specification than that of IC amplifiers in related technologies, and can generally achieve ≥120V.

[0039] LDO1 handles the positive current path from VDD to Vout; LDO2 handles the negative current path from Vout to V4, and then to VSS. This enables the amplifier to operate with high bidirectional current, driving demanding loads such as capacitive and inductive components. In this embodiment, the high current can be above 500mA.

[0040] OPA1 transmits the Vset reference without distortion or attenuation; OPA2 compares Vout with Vset in real time to form an error signal; LDO1 and LDO2 maintain Vout = Vset + Vref under both positive and negative current conditions, so that the amplifier's output voltage can maintain high accuracy and low drift regardless of changes in load current.

[0041] LDO1 has an inherent offset +Vref, while LDO2 automatically cancels its own Vref offset through the V4 compensation structure, so that the two LDOs together satisfy Vout=Vset+Vref in the closed loop. This prevents the dual LDOs from having offset superposition and output inaccuracy issues, and achieves high-voltage amplification with zero offset error.

[0042] The amplifier in this embodiment mainly consists of two general-purpose high-voltage LDOs and two general-purpose operational amplifiers. It eliminates the need for dedicated high-voltage power operational amplifier chips, achieving professional-grade high-voltage amplifier performance through the combined operation of general-purpose components. It is low-cost, highly reliable, and easy to mass-produce.

[0043] In addition, the value V4 = VSS + 2 × Vref is the only compensation value derived by the built-in Vref bias characteristics of the dual LDOs and the differential closed-loop logic of OPA2. If it exceeds twice Vref, it will directly destroy the voltage balance of the circuit, causing the core output formula Vout = Vset + Vref to fail, and the amplifier will not be able to achieve accurate voltage output.

[0044] Based on the inherent characteristics of LDO2, the output voltage (V4) of LDO2 = the voltage at the LDO2 regulation terminal (V1) + the built-in Vref. Therefore, V1 = V4 − Vref;

[0045] According to the voltage divider logic of OPA2, since R1=R2=R3=R4, combined with virtual short (V2=V3) and virtual open (no current at the input terminal), the voltage divider formula is derived as follows: V2=(Vout+VSS) / 2, V3=(Vset+V1) / 2;

[0046] Solving the equations simultaneously to find V4: Substitute V1=V4-Vref into the V3 formula, and combine V2=V3 and the final objective Vout=Vset+Vref, we get: Vset+Vref+VSS=Vset+V4−Vref. After elimination and simplification, the unique solution is: V4=VSS+2×Vref.

[0047] Therefore, V4 = VSS + 2 × Vref is the only mathematically valid value that satisfies the core output formula, and it can precisely cancel out the double Vref bias of the dual LDOs. Essentially, it reserves 1 Vref for the bias of LDO2, while matching the 1 Vref bias of LDO1, so that the bias errors of the two LDOs cancel each other out. Finally, through the closed loop of OPA2, the voltage balance of the entire circuit returns to Vout = Vset + Vref.

[0048] As an optional embodiment, both LDO1 and LDO2 include a reference voltage source Vref, an error amplifier, and a MOSFET; the adjustment terminal of LDO1 and LDO2 is connected to one end of the reference voltage source Vref; the other end of the reference voltage source Vref is connected to the first input terminal of the error amplifier, the second input terminal of the error amplifier is connected to the output terminal of the corresponding LDO, and the output terminal of the error amplifier is connected to the gate of the MOSFET; the source and drain of the MOSFET are connected to the output terminal OUT and the input terminal IN of the corresponding LDO, respectively.

[0049] The reference voltage source Vref provides a constant reference voltage for the error amplifier. One end of Vref is connected to the LDO adjustment terminal (ADJ), and the other end is connected to the first input terminal of the error amplifier, which is used to calibrate the voltage output of the entire LDO.

[0050] The error amplifier acquires the LDO output voltage Vout in real time through the second input terminal and the reference voltage Vref through the first input terminal. It calculates the difference between the output voltage Vout and the reference voltage, amplifies the difference signal, and outputs it to the gate of the MOS transistor.

[0051] As a power switching element, the MOSFET receives the control signal from the error amplifier at its gate and dynamically adjusts the conduction level between the source and drain to adjust the conduction level of the input terminal IN and the output terminal OUT of LDO1 / LDO2. This allows for real-time calibration of the LDO output terminal Vout voltage, ensuring it always matches the target value determined by Vref and the input voltage at the adjustment terminal.

[0052] The aforementioned MOSFET can be an N-type MOSFET or a P-type MOSFET. The source and drain of the MOSFET are connected to the output terminal OUT and the input terminal IN of the corresponding LDO, respectively. It is necessary to ensure that when the MOSFET is turned on, the current can flow effectively from the input terminal IN to the output terminal OUT of the LDO.

[0053] In this embodiment, an N-type MOS transistor is preferred, such as... Figures 1 to 4 As shown, the source of the N-type MOSFET is connected to the input terminal IN of the LDO, and the drain of the N-type MOSFET is connected to the output terminal OUT of the LDO.

[0054] As an optional embodiment, an amplifier circuit is also included, comprising a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4; one end of the first resistor R1 is connected to the output terminal of OPA1, and the other end of the first resistor R1 is connected to the non-inverting input terminal of OPA2; one end of the second resistor R2 is connected to the output terminal Vout, and the other end of the second resistor R2 is connected to the inverting input terminal of OPA2; one end of the third resistor R3 is connected to the non-inverting input terminal of OPA2, and the other end of the third resistor R3 is connected to the negative power supply terminal VSS; one end of the fourth resistor R4 is connected to the inverting input terminal of OPA2, and the other end of the fourth resistor R4 is connected to the output terminal of OPA2.

[0055] As an optional embodiment, the resistance values ​​of the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 are equal.

[0056] R1-R4 with equal resistance form a differential amplifier circuit with OPA2 and gain = 1. Combining the virtual short (V2=V3) and virtual open (no current at the input) characteristics of the op-amp, the signal calibration of the adjustment terminal of LDO2 is completed. The overall operation is divided into three steps: signal acquisition, signal processing, and signal output, as detailed below.

[0057] Signal acquisition: R1 acquires the Vset signal output from OPA1, R2 acquires the real-time voltage of the amplifier's total output terminal Vout, R3 pulls the Vset signal down to the negative power supply terminal VSS, and R4 feeds back the real-time Vout signal to the output terminal of OPA2.

[0058] Signal calculation: Since R1=R2=R3=R4 and the op-amp is virtually open, the voltage at the non-inverting input of OPA2 is V2=(Vset+VSS) / 2, and the voltage at the inverting input is V3=(Vout+VSS) / 2; then, from the op-amp's virtual short V2=V3, we can deduce that Vout=Vset (this signal provides a calibration reference for the LDO2 adjustment terminal).

[0059] Signal output: OPA2 sends the calculated calibration signal to the adjustment terminal of LDO2, triggering the internal adjustment action of LDO2, so that the voltage at the input terminal (connected to Vout) of LDO2 satisfies Vout'=Vset+Vref (Vout' is the target output voltage of LDO2 from the perspective of view).

[0060] By combining the differentiated operation of LDO1 / LDO2 with the closed-loop adjustment of the amplifier circuit, voltage coordinated calibration under positive / negative current conditions can be achieved. When Iout > 0 (positive current): LDO1 takes the lead, directly outputting Vout = Vset + Vref. LDO2 does not operate; the amplifier circuit only acquires the signal in real time and does not interfere with the output adjustment of LDO1. When Iout < 0 (negative current): LDO2 takes the lead. Under the closed-loop calibration of the amplifier circuit, LDO2 internally adjusts its input voltage to Vout' = Vset + Vref, ensuring that the amplifier's total output Vout under negative current conditions is consistent with the target voltage output of LDO1 in the positive direction.

[0061] Achieving bidirectional voltage capability allows the voltage output of LDO2 under negative current conditions to maintain the same target value Vset+Vref as the voltage output of LDO1 under positive current conditions, enabling the amplifier output voltage to be continuously adjusted between VDD and VSS, thus overcoming the limitation of LDO itself not having bidirectional voltage capability.

[0062] The differential amplifier circuit composed of resistors R1, R2, R3, and R4 of equal resistance values ​​has a stable gain of 1, avoiding attenuation or distortion during signal transmission. This ensures that the calibration signal of LDO2 remains highly consistent with Vset, guaranteeing the voltage output accuracy of the amplifier across the entire current direction. Furthermore, it achieves conflict-free coordination between LDO1 and LDO2, avoiding current conflicts caused by the simultaneous operation of the two power components LDO1 and LDO2, thus improving the reliability of the circuit.

[0063] As an optional embodiment, a first capacitor C1 is also provided between the first resistor R1 and the second resistor R2; one end of the first capacitor C1 is connected to both the first resistor R1 and the second resistor R2, and the other end of the first capacitor C1 is grounded; a second capacitor C2 is provided between the inverting input terminal and the output terminal Vout of the OPA2, and the two ends of the second capacitor are connected to the inverting input terminal and the output terminal of the OPA2, respectively; a third capacitor C3 is provided at the compensation voltage terminal V4, one end of the third capacitor C3 is connected to the compensation voltage terminal V4, and the other end of the third capacitor C3 is grounded.

[0064] The first capacitor C1 can filter out high-frequency noise at this node, preventing noise in the Vset signal collected by the first resistor R1 and the Vout real-time signal collected by the second resistor R2 from entering the input of OPA2 and causing calculation errors.

[0065] The second capacitor C2 forms a voltage feedback filter circuit, which filters out high-frequency voltage fluctuations at the Vout terminal and performs phase compensation for the closed-loop control of OPA2 to prevent the circuit from oscillating due to high-frequency signals.

[0066] The third capacitor C3 is mainly used to stabilize the voltage of V4, filter out power supply noise and voltage fluctuations at the V4 terminal, and ensure the stability of the reference voltage for the internal regulation action of LDO2.

[0067] like Figure 2 As shown, in an optional embodiment, a fifth resistor R5 is provided between the output terminal of LDO1 and the input terminal of LDO2. One end of the fifth resistor R5 is connected to the output terminal of LDO1, and the other end of the fifth resistor R5 is connected to the input terminal of LDO2.

[0068] Ideally, Vout = Vout', but in reality, due to device precision issues such as LDO reference voltage error and resistor tolerance, there will be a voltage deviation between Vout and Vout'. A fifth resistor R5 is placed between the output of LDO1 and the input of LDO2 to limit invalid circulating current across the LDO and protect the power devices.

[0069] When Vout>Vout' occurs under actual operating conditions, an invalid circulating current will be generated that flows directly from VDD through LDO1, R5, and LDO2 to VSS without passing through the load. This current has no actual amplification effect and will also cause additional power consumption or even overheating damage to LDO1 / LDO2.

[0070] The series connection of R5 forms a current-limiting impedance through its own resistance voltage drop, limiting the invalid circulating current within a safe range, preventing power devices from failing due to overcurrent or overheating, and improving the reliability of the circuit under actual operating conditions.

[0071] As an optional embodiment, the resistance values ​​of the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 are equal and range from 1 to 100 kΩ; the resistance value of the fifth resistor R5 is in the range of 0 Ω < R5 ≤ 20 Ω.

[0072] R1-R4 are the external matching resistors for OPA2. If the resistance value is too small (<1kΩ), it will create a large load current, causing overload at the OPA2 output and signal distortion. If the resistance value is too large (>100kΩ), it is susceptible to external electromagnetic interference and will generate an additional voltage drop due to the op-amp input bias current, resulting in operational errors. The range of 1-100kΩ provides the optimal matching load for OPA2, ensuring high accuracy in signal processing, avoiding op-amp overload, and reducing the impact of external interference.

[0073] The core function of R5 is current limiting and voltage deviation compensation. If the resistance is too large (>20Ω), even under normal operating positive / negative current, a significant series voltage drop will be generated, causing the amplifier output voltage to deviate from the target value Vset+Vref, reducing output accuracy. The range of 0Ω<R5≤20Ω can effectively limit the invalid circulating current and ensure that the voltage drop under normal operating current is negligible, thus balancing safety protection and output accuracy.

[0074] As an optional embodiment, a sampling resistor Rs is also provided on the output terminal Vout; one end of the sampling resistor Rs is connected to the output terminal Vout, and the other end of the sampling resistor Rs is connected to the load of the amplifier; current detection terminals are led out from both ends of the sampling resistor, and voltage detection terminals are led out from both ends of the load.

[0075] Adding a sampling resistor Rs between the output Vout and the load, and bringing out the current detection terminal Isense and the voltage detection terminal Vsense, expands the function of the amplifier, allowing the core amplification function to be combined with real-time voltage / current detection capability, realizing real-time and accurate detection of output voltage / current, and supporting closed-loop control.

[0076] The sampling resistor Rs can be a high-precision, low-resistance resistor. The voltage drop generated when the load current flows through Rs is proportional to the current. The real-time value of the output current can be directly acquired through the current detection terminal. The actual voltage value of the load terminal can be directly acquired through the voltage detection terminal across the load.

[0077] This enables the amplifier to have real-time voltage / current monitoring capabilities, providing accurate detection signals for subsequent external closed-loop control (such as constant voltage / constant current control, overvoltage / overcurrent protection), thereby expanding the amplifier's application scenarios.

[0078] As an optional embodiment, the total voltage span of the amplifier's power supply terminals is ≥120V, and the absolute value of the amplifier's output / absorption current is ≥500mA.

[0079] exist Figure 2 In the implemented circuit, the amplifier's Vset is -40~80V, R1=R2=R3=R4=33KΩ, R5=1Ω, C1=33nF, C2=33nF, and C3=330nF. Both LDO1 and LDO2 are TL783 microcontrollers with a built-in Vref=1.27V. Testing results show that the voltage range can reach 120V, and the absolute current can reach 500mA.

[0080] Specifically, such as Figure 5 As shown, the yellow curve (Vout) represents the output voltage variation of the amplifier. The blue curve (Vset) represents the externally set voltage variation. VF1, VF2, VF3, and VF4 correspond to... Figure 2The voltages of key nodes V1, V2, V3, and V4 inside the circuit.

[0081] Depend on Figure 5 It can be seen that the peak value of Vout is approximately +80V, and the valley value is approximately -40V, with a voltage span of 80V − (−40V) = 120V, achieving a total power supply voltage span ≥ 120V. Combining Vout = Vset + Vref, theoretically, when Vset = -40~80V, Vout should be -38.73~81.27V. The slight deviation between the actual measured value and the theoretical value is caused by the tolerance of the voltage divider resistors in the circuit, the slight drift of the LDO device's reference voltage, and the measurement accuracy error of the testing equipment. This deviation is within the allowable error range of industrial circuits and does not affect the core performance of the circuit.

[0082] Based on this Figure 5 The Vset and Vout curves appear to overlap almost completely. This is because the vertical axis scaling of the test waveform is relatively large, and the voltage difference of Vref=1.27V cannot be intuitively reflected under this scaling scale. It does not mean that there is no difference between Vout and Vset in the actual circuit. In actual testing, a high-precision multimeter can detect that Vout is always 1.27V higher than Vset, which is completely consistent with the core formula Vout=Vset+Vref. This fully verifies that the output voltage Vout can be precisely and linearly controlled by Vset.

[0083] like Figure 6 As shown, the green curve (Iout) represents the change in the total output current of the amplifier. The yellow curve (I_ldo1) represents the change in the output current of LDO1. The red curve (I_ldo2) represents the change in the output current of LDO2.

[0084] The peak forward current is approximately 520mA (>500mA) for both the Iout and I_ldo1 curves, which meets the requirement that the absolute value of the output current is ≥500mA.

[0085] Negative current peak: The valley of the Iout curve reaches about -220mA. At this time, the I_ldo2 curve starts to move, indicating that the LDO2 is absorbing current and realizing bidirectional current capability.

[0086] When Iout > 0, I_ldo1 and Iout almost overlap, with LDO1 dominating the positive output; when Iout < 0, I_ldo2 takes action, with LDO2 dominating the negative absorption, verifying the design of dual LDO time-sharing operation.

[0087] This addresses the application requirements of high voltage (over 120V) and high current (over 500mA), solving the problem that most high voltage amplifier ICs above 100V provide milliampere-level current, while high voltage amplifier ICs above 500mA are limited in variety, cost, and have unstable supply. It directly fills the market gap for general-purpose high voltage and high current amplifiers, meeting the practical application needs of industrial control, high-power drives, and high-voltage power supplies.

[0088] As an optional embodiment, the value range of the external setting voltage terminal Vset is VSS+Vref≤Vset≤VDD-Vref, and the output voltage range of the output terminal Vout is VSS+2×Vref≤Vout≤VDD.

[0089] Based on the circuit principles V1=VSS+Vref and Vout=Vset+Vref, and the voltage division relationship of OPA2, we derive Vout=Vset+Vref. Combining this with the power supply voltage range, we derive the theoretical ranges for each voltage parameter:

[0090] The theoretical range of the external set voltage Vset is: VSS + Vref ≤ Vset ≤ VDD − Vref. The lower limit is: Vset ≥ VSS + Vref, ensuring that the voltage at the LDO2 adjustment terminal is VSS + Vref, allowing LDO2 to normally absorb negative current. The upper limit is: Vset ≤ VDD - Vref, ensuring that the voltage at the LDO1 output terminal does not exceed VDD, preventing LDO1 from operating under overvoltage. Vset supports bidirectional adjustment, covering the range from negative high voltage to positive high voltage, and is the control basis for achieving bidirectional high-voltage output of the amplifier.

[0091] From Vout = Vset + Vref, substituting into the range of Vset, we derive the theoretical range of the amplifier output voltage Vout: VSS + 2 × Vref ≤ Vout ≤ VDD. The lower limit is: Vout_min = VSS + 2 × Vref (corresponding to Vset = VSS + Vref), which is the minimum negative high-voltage output of the amplifier; the upper limit is: Vout_max = VDD (corresponding to Vset = VDD - Vref), which is the maximum positive high-voltage output of the amplifier; the output voltage span of Vout = VDD - (VSS + 2 × Vref) ≈ VDD - VSS ≥ 120V (Vref is 1~2V, which can be ignored), achieving a bidirectional high-voltage output of ≥ 120V.

[0092] The value range of Vset is limited to VSS+Vref to VDD-Vref, and the corresponding Vout range is VSS+2×Vref to VDD. This range is completely matched with the rated voltage operating range of LDO1 / LDO2 and OPA1 / OPA2, which avoids the LDO or operational amplifier from operating beyond its voltage range due to excessively large / small Vset setting, which may cause device breakdown, distortion or failure, and ensures the safety and stability of the circuit in operation within the full voltage regulation range.

[0093] Another aspect of this embodiment provides a control method for an amplifier based on dual LDOs, applied to any of the dual LDO-based amplifiers described above, including:

[0094] like Figure 3 As shown, when the amplifier is outputting a positive current, the amplifier current Iout > 0. The external setting voltage Vset is input to the non-inverting input of OPA1. Based on the voltage follower characteristic of OPA1, a reference voltage with the same amplitude as Vset is generated at the output of OPA1 and transmitted to the adjustment terminal of LDO1.

[0095] The LDO1 obtains an output voltage of magnitude Vset + Vref based on the reference voltage source Vref and the reference voltage at the adjustment terminal. It converts the positive power supply terminal VDD into a positive current, which is transmitted to the amplifier's output terminal Vout to supply power to the external load.

[0096] When the input current at the input terminal of the LDO2 is zero, the LDO2 is in standby mode. It should be noted that zero input current means there is no effective operating current in the actual circuit, not an absolute zero current. This is because there may be a slight leakage current in the circuit, causing a small current to flow at the LDO2's input terminal IN even without effective operating current.

[0097] When the output voltage Vout changes due to load changes, OPA1 maintains the reference voltage Vset at the LDO1 regulation terminal and adjusts the conduction capability to maintain the voltage stability of the output Vout.

[0098] like Figure 4 As shown, when the amplifier absorbs negative current, the amplifier current Iout < 0. The input current at the input terminal of LDO1 is zero, and LDO1 is in standby mode. The external setting voltage terminal Vset is input to the non-inverting input terminal of OPA1. Based on the voltage follower characteristic of OPA1, a reference voltage with the same amplitude as Vset is generated at the output terminal of OPA1 and transmitted to the non-inverting input terminal of OPA2.

[0099] The inverting input of OPA2 obtains the actual voltage through the output Vout, calculates the voltage deviation between the reference voltage and the actual voltage, and outputs the voltage deviation signal to the adjustment terminal of LDO2.

[0100] The LDO2's regulating terminal, based on the voltage deviation signal and the compensation voltage terminal V4 connected to the LDO2's output terminal, absorbs negative current through the LDO2's input terminal and sequentially flows the negative current to the compensation voltage terminal and the negative power supply terminal for negative current discharge.

[0101] When the load changes and the voltage at the output terminal Vout changes, the voltage deviation signal output by OPA2 changes accordingly. The adjustment terminal of LDO2 adjusts its conduction capability and the magnitude of the absorbed negative current according to the changing voltage deviation signal, so as to stabilize the voltage at the output terminal Vout.

[0102] Another scenario exists where the current Iout = 0, the load has no current input / output, both LDOs are in standby mode, the op-amp maintains the reference and deviation detection, and Vout stabilizes at Vset + Vref.

[0103] OPA1 still transmits the Vset reference, LDO1's adjustment terminal is Vset, and LDO2's adjustment terminal is the deviation signal output by OPA2, both maintaining the voltage reference; the load has no current demand, LDO1 has no positive current output, LDO2 has no negative current absorption, no current flows at the amplifier output terminal Vout, and the voltage is stable at Vset+Vref.

[0104] At this time, both operational amplifiers (OPA) and both LDOs are in low-power standby mode. Once the load changes (Iout>0 or Iout<0), they immediately switch to the corresponding operating condition with no response delay.

[0105] In practical engineering, the protection resistor R5 will achieve voltage correction through current voltage drop compensation, avoiding static leakage current without load, and ensuring that Vout is stable at Vset + Vref. Specifically, there are two deviation scenarios.

[0106] The first scenario is caused by the superposition of positive biases in the devices, resulting in Vout > Vout', which is a common bias. The bias causes an additional current to flow sequentially through VDD, LDO1, Vout, R5, LDO2, V4, and finally to VSS. When this current flows through R5, it generates a positive voltage drop ΔV(R5) = I_R5 × R5.

[0107] The forward voltage drop ΔV(R5) exactly cancels out the voltage deviation of Vout-Vout', making the actual voltage Vout' of the LDO2 input terminal IN equal to Vout-ΔV(R5), thus restoring it to Vset+Vref.

[0108] The second case is the reverse deviation where Vout < Vout’. Under this deviation, no current flows through R5, that is, ΔV(R5) = 0, and R5 cannot achieve active compensation. At this time, the amplifier's final Vout is determined by the direction of the load current.

[0109] If the load is Iout > 0 (positive): then LDO1 takes the lead in control and pulls Vout back to Vset + Vref. If the load is Iout < 0 (negative): then LDO2 takes the lead in control and pulls Vout back to Vset + Vref.

[0110] Since the device selection of the LDO is generally of the same specification and high-precision devices, this reverse deviation is extremely small and can be ignored. The amplifier can still maintain its core output characteristics.

[0111] Through the above control method of the amplifier based on dual LDOs, the following advantages are achieved.

[0112] The amplifier has a non-switching dynamic closed-loop: all control actions of the amplifier are real-time dynamic responses, automatically adjusted according to the changes in load current and voltage, without any hardware / software mode switching. The response speed is determined by the bandwidth of the operational amplifier and the LDO, meeting the fast adjustment requirements of high-voltage and high-current scenarios.

[0113] The operational amplifier is responsible for signal reference transmission and deviation detection (without power output), and the LDO is responsible for power execution and bidirectional current implementation (without signal detection). They each perform their own functions, taking into account the accuracy of signal transmission and the high-current capacity of power output.

[0114] Regardless of the operating conditions, the control objective of the amplifier is to maintain Vout = Vset + Vref, and all device actions are carried out around this formula, ensuring the linearity and accuracy of the output voltage.

[0115] It should be noted that the term "including" and its variants used in the embodiments of the present invention are open-ended, that is, "including but not limited to". The descriptions of terms such as "first", "second", etc. are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly specifying the quantity of the indicated technical features.

[0116] The term "embodiment" appearing in various positions in the specification does not necessarily mean the same embodiment, nor does it mean being independent or alternative to other embodiments and mutually exclusive. The various embodiments in this specification are described in a related manner, and the same or similar parts between the various embodiments can be referred to each other.

Claims

1. An amplifier based on dual LDOs, characterized in that, include: The system comprises a first low-dropout linear regulator LDO1, a second low-dropout linear regulator LDO2, a first operational amplifier OPA1, and a second operational amplifier OPA2. Each amplifier has a positive power supply terminal VDD, a negative power supply terminal VSS, an external setting voltage terminal Vset, and an output terminal Vout. Both LDO1 and LDO2 have a built-in reference voltage source Vref. The input terminal of LDO1 is connected to the positive power supply terminal VDD, the adjustment terminal of LDO1 is connected to the output terminal of OPA1, and the output terminal of LDO1 is connected to the output terminal Vout. LDO1 is used to output a positive current to the output terminal Vout. The input terminal of LDO2 is connected to the output terminal Vout, the adjustment terminal of LDO2 is connected to the output terminal of OPA2, the output terminal of LDO2 is connected to the compensation voltage terminal V4, the compensation voltage terminal V4 is VSS+2×Vref, and LDO2 is used to absorb negative current from the output terminal Vout. The non-inverting input terminal of OPA1 is connected to the external set voltage terminal Vset, the inverting input terminal of OPA1 is connected to the output terminal of OPA1, and the output terminal of OPA1 is also connected to the inverting input terminal of OPA2. OPA1 is used to perform voltage following processing on the input Vset to transmit Vset to the adjustment terminal of LDO1 and the inverting input terminal of OPA2. The inverting input terminal of OPA2 is connected to the output terminal of OPA1, the non-inverting input terminal of OPA2 is connected to the output terminal Vout, and the output terminal of OPA2 is connected to the adjustment terminal of LDO2. OPA2 is used to collect the voltage difference between the output terminal Vout and the output terminal Vset of OPA1, and transmit the voltage difference to the adjustment terminal of LDO2.

2. The amplifier based on dual LDOs according to claim 1, characterized in that, Both LDO1 and LDO2 include the reference voltage source Vref, an error amplifier, and a MOS transistor; The adjustment terminals of LDO1 and LDO2 are connected to one end of the reference voltage source Vref; The other end of the reference voltage source Vref is connected to the first input terminal of the error amplifier, the second input terminal of the error amplifier is connected to the output terminal of the corresponding LDO, and the output terminal of the error amplifier is connected to the gate of the MOS transistor. The source and drain of the MOS transistor are connected to the output and input terminals of the corresponding LDO, respectively.

3. The amplifier based on dual LDOs according to claim 2, characterized in that, It also includes an amplifier circuit, which includes a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4; One end of the first resistor R1 is connected to the output terminal of the OPA1, and the other end of the first resistor R1 is connected to the non-inverting input terminal of the OPA2. One end of the second resistor R2 is connected to the output terminal Vout, and the other end of the second resistor R2 is connected to the inverting input terminal of the OPA2; One end of the third resistor R3 is connected to the non-inverting input terminal of the OPA2, and the other end of the third resistor R3 is connected to the negative power supply terminal VSS. One end of the fourth resistor R4 is connected to the inverting input terminal of the OPA2, and the other end of the fourth resistor R4 is connected to the output terminal of the OPA2.

4. The amplifier based on dual LDOs according to claim 3, characterized in that, The resistance values ​​of the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 are equal.

5. The amplifier based on dual LDOs according to claim 4, characterized in that, A first capacitor C1 is also provided between the first resistor R1 and the second resistor R2; one end of the first capacitor C1 is connected to both the first resistor R1 and the second resistor R2, and the other end of the first capacitor C1 is grounded. A second capacitor C2 is provided between the inverting input terminal of the OPA2 and the output terminal Vout, and the two ends of the second capacitor C2 are respectively connected to the inverting input terminal and the output terminal of the OPA2. The compensation voltage terminal V4 is equipped with a third capacitor C3. One end of the third capacitor C3 is connected to the compensation voltage terminal V4, and the other end of the third capacitor C3 is grounded.

6. The amplifier based on dual LDOs according to claim 1, characterized in that, A fifth resistor R5 is provided between the output terminal of LDO1 and the input terminal of LDO2. One end of the fifth resistor R5 is connected to the output terminal of LDO1, and the other end of the fifth resistor R5 is connected to the input terminal of LDO2.

7. The amplifier based on dual LDOs according to claim 6, characterized in that, The resistance values ​​of the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 are equal and range from 1 to 100 kΩ. The resistance value of the fifth resistor R5 is in the range of 0Ω < R5 ≤ 20Ω.

8. The amplifier based on dual LDOs according to claim 1, characterized in that, A sampling resistor Rs is also provided on the output terminal Vout; one end of the sampling resistor Rs is connected to the output terminal Vout, and the other end of the sampling resistor Rs is connected to the load of the amplifier. The sampling resistor has current detection terminals at both ends, and the load has voltage detection terminals at both ends.

9. The amplifier based on dual LDOs according to claim 1, characterized in that, The total voltage span of the power supply terminals of the amplifier is ≥120V, and the absolute value of the output / absorption current of the amplifier is ≥500mA.

10. The amplifier based on dual LDOs according to claim 9, characterized in that, The value range of the external set voltage terminal Vset is VSS+Vref≤Vset≤VDD-Vref, and the output voltage range of the output terminal Vout is VSS+2×Vref≤Vout≤VDD.

11. A control method for an amplifier based on dual LDOs, characterized in that, An amplifier based on a dual LDO as described in any one of claims 1 to 10, comprising: When the amplifier is outputting a positive current, the external set voltage terminal Vset is input to the non-inverting input terminal of OPA1. Based on the voltage follower characteristic of OPA1, a reference voltage with the same amplitude as Vset is generated at the output terminal of OPA1 and transmitted to the adjustment terminal of LDO1. The LDO1 obtains an output voltage of magnitude Vset+Vref based on the reference voltage source Vref and the reference voltage at the adjustment terminal. It converts the positive power supply terminal VDD into a positive current, which is transmitted to the output terminal Vout of the amplifier to supply power to the external load. The input current at the input terminal of the LDO2 is zero, and the LDO2 is in standby mode. When the voltage at the output terminal Vout changes due to load changes, the OPA1 maintains the reference voltage at the adjustment terminal of the LDO1 at Vset and adjusts the conduction capability to maintain the voltage at the output terminal Vout stable. When the amplifier is absorbing negative current, the input current at the input terminal of LDO1 is zero, and LDO1 is in standby mode; the external setting voltage terminal Vset is input to the non-inverting input terminal of OPA1, and based on the voltage follower characteristic of OPA1, a reference voltage with the same amplitude as Vset is generated at the output terminal of OPA1 and transmitted to the inverting input terminal of OPA2; The non-inverting input of the OPA2 obtains the actual voltage through the output Vout, calculates the voltage deviation between the reference voltage and the actual voltage, and outputs the voltage deviation signal to the adjustment terminal of the LDO2. The adjustment terminal of LDO2, based on the voltage deviation signal and the compensation voltage terminal V4 connected to the output terminal of LDO2, absorbs negative current through the input terminal of LDO2 and discharges the negative current sequentially to the compensation voltage terminal and the negative power supply terminal. When the load change causes a change in the voltage at the output terminal Vout, the voltage deviation signal output by the OPA2 changes accordingly. The adjustment terminal of the LDO2 adjusts its conduction capability and the magnitude of the absorbed negative current according to the changing voltage deviation signal, so as to stabilize the voltage at the output terminal Vout.

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