Multi-board RFSoC (radio frequency system on chip) cooperation and LFM (linear frequency modulation) calibration super multi-channel synchronous transmitting system

Abstract

The invention provides a multi-board RFSoC cooperation and LFM calibration super multi-channel synchronous transmission system. The multi-board RFSoC cooperation and LFM calibration super multi-channel synchronous transmission system comprises an upper computer and a lower computer, wherein the lower computer comprises N + 1 embedded board cards. All the embedded board cards are interconnected through an external Ethernet switch and share the same external clock source; the upper computer writes IQ waveform data into each embedded board card, and the master embedded board card calculates propagation delays of the master embedded board card and the slave embedded board cards; each embedded board card sends and receives IQ waveform data of each channel in a self-transmitting and self-receiving mode, and calculates a phase difference corresponding to each channel in combination with the upper computer; and the master embedded board card pulls up an SYNC signal according to propagation delay, and each slave embedded board card compensates IQ waveform data to be sent according to the corresponding phase difference and then sends out the IQ waveform data. According to the invention, the limitation of the number of channels of a single board can be broken through, high time synchronism and phase consistency of output signals of the whole system are ensured, and the calibration precision of closed-loop calibration is improved.

Description

Technical Field

[0001] This application belongs to the field of hardware design technology, specifically relating to a multi-board RFSoC collaborative and LFM calibration multi-channel synchronous transmission system. Background Technology

[0002] In modern radar, wireless communication, and electronic countermeasures systems, dozens of radio frequency (RF) signals often need to maintain high consistency in frequency, phase, and time to achieve beamforming, coherent synthesis, or multi-channel parallel testing. Although Xilinx Zynq UltraScale+ RFSoC series chips (such as ZU47DR and ZU48DR) integrate high-performance RF digital-to-analog converters (RFDACs), they are limited by packaging and pin resources, and a single chip can only support a maximum of 8 RF output channels, which is difficult to meet the needs of large-scale channel applications.

[0003] To expand the number of channels, existing solutions typically employ parallel deployment of multiple RFSoC boards, but still face significant synchronization challenges: (1) Although each embedded board can share the same 10MHz reference clock, due to factors such as differences in PCB trace length, connector insertion delay, power supply noise, and temperature drift, there are uncontrollable static phase deviations and start-up jitters between each RF channel, which cannot meet the coherence requirements (e.g., phase error > 5°, time jitter > 200ps); (2) Some systems attempt to use the SYSREF mechanism of JESD204BSubclass1 or the IEEE1588 precision time protocol to achieve multi-board alignment. Such solutions rely on high-speed SerDes links, dedicated switching equipment, and complex software protocol stacks, which are not only costly and power-consuming, but also severely occupy FPGA logic resources, making it difficult to achieve sub-nanosecond synchronization accuracy in embedded scenarios.

[0004] Furthermore, existing systems often lack effective closed-loop calibration capabilities. Phase consistency typically relies on idealized PCB length designs, which cannot compensate for drift introduced by manufacturing tolerances, device aging, or environmental changes. Local FPGA resources are limited, making it difficult to execute high-precision phase estimation algorithms (such as pulse compression), resulting in insufficient calibration accuracy. Summary of the Invention

[0005] To address the aforementioned problems in the existing technology, this application provides a multi-board RFSoC collaborative and LFM calibration ultra-multi-channel synchronous transmission system. The technical problem to be solved by this application is achieved through the following technical solution: A multi-board RFSoC collaborative and LFM calibration ultra-multi-channel synchronous transmission system includes a host computer and a slave computer. The slave computer includes N+1 embedded boards, one of which is a master embedded board and the N are slave embedded boards. All embedded boards are interconnected through an external Ethernet switch and share the same external clock source. The host computer writes IQ waveform data to each embedded board through the Ethernet switch. The master embedded board calculates its own and each slave embedded board's propagation delay by sending and receiving SYNC signals with each slave embedded board and writes it into its register. Each embedded board sends and receives IQ waveform data of each channel in a self-transmitting and self-receiving manner, and calculates the corresponding phase difference for each channel in conjunction with the host computer, which then sends the data to each embedded board. The master embedded board pulls up the SYNC signal according to the propagation delay of each slave embedded board and sends it to each slave embedded board. Each slave embedded board compensates for its own IQ waveform data to be sent according to the corresponding phase difference before sending it out.

[0006] Beneficial effects: This application provides a multi-board RFSoC collaborative and LFM calibration ultra-multi-channel synchronous transmission system, including a host computer and a slave computer. The slave computer includes N+1 embedded boards, one of which is a master embedded board and the N are slave embedded boards. All embedded boards are interconnected through an external Ethernet switch and share the same external clock source. The host computer writes IQ waveform data to each embedded board through the Ethernet switch. The master embedded board calculates its own and each slave embedded board's propagation delay by sending and receiving SYNC signals with each slave embedded board and writes it into its own register. Each embedded board sends and receives IQ waveform data of each channel in a self-transmitting and self-receiving manner, and calculates the corresponding phase difference of each channel in conjunction with the host computer, which then sends the data to each embedded board. The master embedded board raises the SYNC signal according to the propagation delay of each slave embedded board and sends it to each slave embedded board. Each slave embedded board compensates for its own IQ waveform data to be sent according to the corresponding phase difference before sending it out. This application presents a low-cost, high-precision multi-RFSoC board radio frequency synchronous transmission system that supports self-calibration and closed-loop calibration. It can overcome the limitation of the number of channels on a single board and ensure that the output signal of the entire system has high time synchronization and phase consistency, thereby improving the calibration accuracy of closed-loop calibration.

[0007] The present application will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0008] Figure 1This is a schematic diagram of the multi-board RFSoC collaborative and LFM calibration ultra-multi-channel synchronous transmission system provided in this application; Figure 2 This is a schematic diagram of the workflow of the multi-board RFSoC collaborative and LFM calibration multi-channel synchronous transmission system provided in this application. Detailed Implementation

[0009] The present application will be described in further detail below with reference to specific embodiments, but the implementation of the present application is not limited thereto.

[0010] The purpose of this application is to provide a multi-board Xilinx RFSoC radio frequency signal synchronous transmission system and method based on an external reference clock, hardware synchronization trigger line and LFM loop phase calibration, to solve the shortcomings of the prior art in terms of channel scalability, time synchronization accuracy, phase consistency and environmental adaptability.

[0011] like Figure 1 As shown, this application provides a multi-board RFSoC collaborative and LFM calibration ultra-multi-channel synchronous transmission system, including a host computer and a slave computer. The slave computer includes N+1 embedded boards, one of which is a master embedded board and N are slave embedded boards. All embedded boards are interconnected through an external Ethernet switch and share the same external clock source. The host computer writes IQ waveform data to each embedded board through the Ethernet switch. The master embedded board calculates its own and each slave embedded board's propagation delay by sending and receiving SYNC signals with each slave embedded board and writes it into its register. Each embedded board sends and receives IQ waveform data of each channel in a self-transmitting and self-receiving manner, and calculates the corresponding phase difference for each channel in conjunction with the host computer, which then sends the data to each embedded board. The master embedded board pulls up the SYNC signal according to the propagation delay of each slave embedded board and sends it to each slave embedded board. Each slave embedded board compensates for its own IQ waveform data to be sent according to the corresponding phase difference before sending it out.

[0012] refer to Figure 1As shown, the host computer in this application includes a first gigabit network port and an RDMA network port; wherein, the host computer writes the IQ waveform data and system parameters to the external Ethernet switch through the first gigabit network port; the external Ethernet switch transmits the IQ waveform data and system parameters to the corresponding embedded boards, which then write them into their own registers. An external data line exists between the main embedded board and each of the slave embedded boards. Each embedded board includes a frequency synthesizer, a memory, an RFSoC, a transceiver interface, a second gigabit Ethernet port, a first optical module interface, and a second optical module interface. The RFSoC is connected to the frequency synthesizer, the memory, the transceiver interface, the second gigabit Ethernet port, and the second gigabit Ethernet port. The second gigabit Ethernet port is connected to the external Ethernet switch. The second optical module interface of the nth slave embedded board is connected to the first optical module interface of the (n+1)th slave embedded board, where n ranges from 1 to N. The host computer is connected to the external Ethernet switch. The frequency synthesizer is connected to an external clock source and generates multiple clock sources of different frequencies based on the external clock source, which are then provided to the RFSoC.

[0013] In its specific design, this application can utilize an external 10MHz clock source. Each embedded board is equipped with a Xilinx Zynq UltraScale+ RFSoC chip (such as the ZU48DR), and the memory uses 2GB of DDR4 memory. The first optical module interface uses 100G, and the second optical module interface uses 200G. This application's system breaks through the limitation of a single RFSoC with 8 channels, supporting 16 / 32 / 64+ RF outputs to meet the requirements of large-scale arrays.

[0014] The system of this application adopts a dual-channel heterogeneous communication architecture. The host computer accesses the registers of the main embedded board and all the slave embedded boards in parallel through the gigabit / 10-gigabit electrical ports of each embedded board via a common Ethernet switch to complete the download of IQ waveform data and system parameters. All baseband IQ sampling data (such as calibration or monitoring data) that need to be uploaded are transmitted back to the host computer through a switchless cascaded link built by the onboard 100G optical port.

[0015] refer to Figure 1As shown, in this application, the second optical module interface of the nth slave embedded board is connected to the first optical module interface of the (n+1)th slave embedded board. That is, the first optical module interface (100G1) of the nth embedded board is connected to the second optical module interface (100G2) of the (n-1)th slave embedded board. The first optical module interface (100G1) of the (n-2)th slave embedded board is connected to the second optical module interface (100G2) of the (n-2)th slave embedded board. The 100G1 of the first slave embedded board is connected to the second optical module interface 100G2 of the main embedded board, and the 100G1 of the first optical module interface of the main embedded board is connected to the host computer.

[0016] The registers include an EMMC and a DDR4 register. The EMMC stores the system parameters sent by the host computer. The system parameters are used to configure the frequency of IQ waveform data sent by each channel in each embedded board, the number of each embedded board, the designation of the master embedded board and slave embedded boards, the frequency of the external clock source, and the frequencies of multiple clock sources generated based on the external clock source. The DDR4 register of the master embedded board stores the propagation delay of each slave embedded board, the IQ waveform data of each channel of its own, and the phase difference of each channel of its own. The DDR4 register of the slave embedded board stores the IQ waveform data of each channel of its own and the phase difference of each channel of its own.

[0017] The host computer functions of this application include configuring system operating parameters, such as center frequency, bandwidth, and waveform type. It generates multi-channel IQ waveform data and writes it to the DDR4 memory of the main embedded board and each slave embedded board via a common Ethernet switch. It initiates calibration mode, receives down-converted IQ data from each embedded board via a 100G cascaded link, performs LFM pulse compression processing on the IQ data, and extracts the phase difference of each channel relative to the first channel of the main embedded board. The calculated phase difference is then sent to the main embedded board via a low-speed control channel (such as a gigabit Ethernet port or UART). It also starts / stops synchronous transmission tasks and reads system status and logs.

[0018] Each embedded board is based on the Xilinx Zynq UltraScale+ RFSoC, integrating high-speed ADC / DAC, hard-core DDC / DUC, and programmable logic (PL), specifically including: (1) Reference clock and synchronization management: All boards receive an external, stable 10MHz clock from the same source via the REFCLK pin, which is then used by the on-chip PLL to generate a global sampling clock. The master embedded board outputs a hardware synchronization signal (SYNC) via the GPIO pin, which is connected to the SYNCIN pin of each slave embedded board via physical jumpers. During the initialization phase, the system performs a synchronous transmission test. The host computer calculates the actual propagation delay Δt_i for each path based on the retrieval data and stores it in the configuration register of the slave embedded board.

[0019] (2) Data storage and loading: Each board is equipped with 2GB DDR4 memory to cache IQ waveform data sent by the host computer; the starting address of the waveform frame is uniformly planned by the host computer to ensure logical alignment.

[0020] (4) Calibration data acquisition and transmission: In calibration or monitoring mode, each embedded board loops back a certain RF output to the ADC input via a directional coupler; after sampling by the on-chip high-speed ADC, the data is down-converted to baseband I / Q data by the DDC module; each slave embedded board sends its local I / Q data to the 100G2 port of the next-level board through its 100G1 port; the data is aggregated step by step along the cascaded optical link and finally uploaded to the host computer by the main embedded board through its 100G1 interface.

[0021] (5) Formal synchronous launch: The main embedded board raises the SYNC signal; after each slave embedded board detects the rising edge of SYNC, it starts a countdown compensation mechanism based on the pre-stored Δt_i (e.g., setting the initial counter value to -Δt_i × f_clk); when the counter reaches zero, all boards simultaneously trigger the DAC to start playing the waveform; the transmitted signal is phase-shifted by -Δφ_i through the NCO module to ensure that the output phase is aligned with the reference of the first channel of the main embedded board. Δφ_i represents the phase difference between the i-th channel and the first channel of the main embedded board.

[0022] The link connection method in this application is designed specifically for high-throughput IQ data, making full use of 100G bandwidth and avoiding the use of expensive 100G switching equipment.

[0023] In one specific embodiment of this application, the master embedded board calculates its own and each slave embedded board's propagation delay by sending and receiving SYNC signals with each slave embedded board, and writes the result into its own register, including: The master embedded board generates a first SYNC signal and transmits it to each slave embedded board. Each slave embedded board receives the first SYNC signal and feeds back a second SYNC signal with the same frequency as the first SYNC signal. The master embedded board records the transmission time of the second SYNC signal sent by each slave embedded board, calculates the propagation delay based on the transmission time of the first SYNC signal sent by the master embedded board and the transmission time of the second SYNC signal, and writes the propagation delay into its own register.

[0024] In one specific embodiment of this application, the master embedded board generates a first SYNC signal and transmits it to each slave embedded board. Each slave embedded board receives the first SYNC signal and feeds back a second SYNC signal with the same frequency as the first SYNC signal. The master embedded board records the transmission time of the second SYNC signal sent by each slave embedded board, calculates the propagation delay based on the transmission time of the first SYNC signal sent by the master embedded board and the transmission time of the second SYNC signal, and writes the propagation delay into its own register, including: Each embedded board's RFSoC receives IQ waveform data sent by the external Ethernet switch through its corresponding second gigabit Ethernet port and stores it in the corresponding memory; The RFSoC in the main embedded board generates a first SYNC signal and transmits it to each of the slave embedded boards via the external data line. After receiving the first SYNC signal from each embedded board, a second SYNC signal with the same frequency as the first SYNC signal is generated and transmitted to the main embedded board via the external data line. The RFSoC in the main embedded board records the transmission time of the second SYNC signal sent by each slave embedded board, and calculates the propagation delay of each slave embedded board based on its own transmission time of the first SYNC signal and the transmission time of the second SYNC signal, and writes the propagation delay of each slave embedded board into its own register.

[0025] refer to Figure 2 As shown, during the initialization and delay calibration phase: 1. The host computer sends system parameters to each embedded board through a common Ethernet switch; all boards are phase-locked to the same 10MHz external reference clock; the master embedded board outputs a SYNC signal, and each slave embedded board records its local trigger time; the system performs a test transmission, and the host computer calculates the path propagation delay Δt_i of each embedded board based on the returned IQ data and writes it to the corresponding slave embedded board register. This application can automatically calibrate the delay during the initialization and delay calibration phase, and can handle scenarios such as temperature drift, aging, and cable replacement. In one specific embodiment of this application, each embedded board transmits and receives IQ waveform data of each channel in a self-transmitting and self-receiving manner, and calculates the phase difference corresponding to each channel in conjunction with the host computer, and then sends the data from the host computer to each embedded board, including: Each embedded board transmits and receives IQ waveform data of its respective channel via a self-transmitting and self-receiving mechanism; it then uploads the IQ waveform data of each channel to the host computer; the host computer calculates the phase difference between each channel of each embedded board and the first channel of the main embedded board; the host computer sends the phase difference down to each embedded board, and each embedded board stores its corresponding phase difference in its own register.

[0026] refer to Figure 2 As shown, during the LFM loopback calibration phase: all channels synchronously transmit the same LFM signal; each embedded board loops its RF output back to the ADC via a directional coupler; the FPGA performs DDC downconversion to generate IQ waveform data; the IQ waveform data is transmitted back to the host computer via a 100G cascaded optical link (from embedded board N → … → main embedded board); the host computer performs LFM pulse compression to extract the phase difference Δφ_i of each channel relative to the first channel of the main embedded board; Δφ_i is sent down to the main embedded board via a low-speed control channel and distributed to each slave embedded board. This application uses a common Ethernet switch for control and waveform transmission, which is low-cost and highly compatible; the IQ waveform data backhaul uses a switchless 100G cascaded optical link, saving the overhead of 100G switching equipment. Furthermore, through a forward compensation mechanism based on the measured Δt_i, <50ps-level transmission timing alignment is achieved, and LFM pulse compression is performed using the high-performance computing resources of the host computer, with a phase estimation accuracy better than 0.5°.

[0027] In one specific embodiment of this application, each embedded board transmits and receives IQ waveform data of its channels in a self-transmitting and self-receiving manner; the IQ waveform data of each channel is uploaded to the host computer; the host computer calculates the phase difference between each channel of each embedded board and the first channel of the main embedded board; the host computer sends the phase difference down to each embedded board, and each embedded board stores its corresponding phase difference in its own register, including: The host computer sends a first transmission signal to the external Ethernet switch through the first gigabit network port, and the external Ethernet switch forwards the first transmission signal to the RFSoC in the main embedded board through the second gigabit network port. After receiving the first transmit signal, the RFSoC in the main embedded board determines the transmission time of the IQ waveform data sent by each slave embedded board according to the propagation delay corresponding to each slave embedded board, and feeds it back to each slave embedded board. The RFSoC in each embedded board reads IQ waveform data from its own registers, transmits the IQ waveform data according to its own corresponding transmission time and through its own transmit RF interface; and receives the IQ waveform data of each channel it transmits through its own receive RF interface. Each slave embedded board receives the IQ waveform data of each channel and transmits it sequentially to the second optical module interface of the previous slave embedded board through its own first optical module interface until it reaches the main embedded board; the main embedded board uploads its own and the IQ waveform data transmitted by each slave embedded board to the host computer through the first optical module interface; The host computer receives the IO waveform data corresponding to each channel in all embedded boards through its own RDMA, and calculates the phase difference between each channel of each embedded board and the first channel of the main embedded board based on the IO waveform data corresponding to each channel. The host computer sends the phase difference corresponding to each channel in each embedded board to the RFSoC in each embedded board through the external Ethernet switch, and the RFSoC stores the phase difference corresponding to each of its own channels into its own register.

[0028] In one specific embodiment of this application, the master embedded board pulls up the SYNC signal according to the propagation delay of each slave embedded board and sends it to each slave embedded board. Each slave embedded board compensates for its own IQ waveform data to be transmitted according to the corresponding phase difference before transmitting it. The master embedded board pulls up the first SYNC signal according to the propagation delay corresponding to each slave embedded board and sends it to each slave embedded board; after receiving the first SYNC signal after it is pulled up, each slave embedded board reads the IQ waveform data and the corresponding phase difference from its own register, compensates the corresponding phase difference for the read IQ waveform data, and then sends it out through each channel.

[0029] refer to Figure 2 As shown, during the formal synchronous transmission phase: 1. The main embedded board raises the SYNC signal; 2. After each slave embedded board detects the rising edge of SYNC, it starts countdown compensation based on Δt_i; when the counter returns to zero, all DACs simultaneously begin playing the waveform; the NCO module applies... The Δφ_i phase offset ensures phase alignment of the entire system's RF output. In this application, waveform playback and synchronization triggering are entirely handled by the lower-level hardware, while the upper-level computer is only responsible for configuration and calibration, resulting in strong system stability.

[0030] In one specific embodiment of this application, the master embedded board pulls up the first SYNC signal according to the propagation delay corresponding to each slave embedded board and sends it to each slave embedded board; after receiving the pulled-up first SYNC signal, each slave embedded board reads the IQ waveform data and the corresponding phase difference from its own register, compensates for the corresponding phase difference in the read IQ waveform data, and then sends it out through each channel, including: The host computer sends a second transmission signal to the external Ethernet switch through the first gigabit network port; The external Ethernet switch forwards the second transmission signal to the RFSoC in the main embedded board through the second gigabit network port; After receiving the second transmit signal, the RFSoC in the main embedded board pulls up the first SYNC signal according to the propagation delay corresponding to each slave embedded board, and sends it to each slave embedded board through an external data line. After receiving the first SYNC signal pulled high from the embedded board, each board reads the IQ waveform data and the corresponding phase difference of each channel from its own register, compensates for the corresponding phase difference of the read IQ waveform data, and then sends it out through each channel in its own transmit RF interface.

[0031] It is worth noting that the terms "first" and "second" in this application are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0032] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications or substitutions should be considered within the scope of protection of this application.

Claims

1. A multi-board RFSoC collaborative and LFM calibration ultra-multi-channel synchronous transmission system, characterized in that, It includes a host computer and a slave computer. The slave computer includes N+1 embedded boards, one of which is a master embedded board and the N are slave embedded boards. All embedded boards are interconnected via an external Ethernet switch and share the same external clock source; The host computer writes IQ waveform data to each embedded board through the Ethernet switch. The master embedded board calculates its own and each slave embedded board's propagation delay by sending and receiving SYNC signals with each slave embedded board and writes it into its own register. Each embedded board sends and receives IQ waveform data of each channel in a self-transmitting and self-receiving manner, and calculates the phase difference corresponding to each channel in conjunction with the host computer, which then sends the data down to each embedded board. The master embedded board pulls up the SYNC signal according to the propagation delay of each slave embedded board and sends it to each slave embedded board. Each slave embedded board compensates for its own IQ waveform data according to the corresponding phase difference before sending it out.

2. The multi-board RFSoC collaborative and LFM calibration ultra-multi-channel synchronous transmission system according to claim 1, characterized in that, The host computer includes a first gigabit network port and an RDMA network port; The host computer writes the IQ waveform data and system parameters to the external Ethernet switch through the first gigabit network port; the external Ethernet switch transmits the IQ waveform data and system parameters to the corresponding embedded boards, which then write them into their own registers.

3. The multi-board RFSoC collaborative and LFM calibration ultra-multi-channel synchronous transmission system according to claim 2, characterized in that, An external data line exists between the main embedded board and each of the slave embedded boards. Each embedded board includes a frequency synthesizer, a memory, an RFSoC, a transceiver interface, a second gigabit Ethernet port, a first optical module interface, and a second optical module interface. The RFSoC is connected to the frequency synthesizer, the memory, the transceiver interface, the second gigabit Ethernet port, and the second gigabit Ethernet port. The second gigabit Ethernet port is connected to the external Ethernet switch. The second optical module interface of the nth slave embedded board is connected to the first optical module interface of the (n+1)th slave embedded board, where n ranges from 1 to N. The host computer is connected to the external Ethernet switch. The frequency synthesizer is connected to an external clock source and generates multiple clock sources of different frequencies based on the external clock source, which are then provided to the RFSoC.

4. The multi-board RFSoC collaborative and LFM calibration ultra-multi-channel synchronous transmission system according to claim 3, characterized in that, The master embedded board calculates its own and each slave embedded board's propagation delay by sending and receiving SYNC signals with each slave embedded board, and writes the result into its own register, including: The master embedded board generates a first SYNC signal and transmits it to each slave embedded board. Each slave embedded board receives the first SYNC signal and feeds back a second SYNC signal with the same frequency as the first SYNC signal. The master embedded board records the transmission time of the second SYNC signal sent by each slave embedded board, calculates the propagation delay based on the transmission time of the first SYNC signal sent by the master embedded board and the transmission time of the second SYNC signal, and writes the propagation delay into its own register.

5. The multi-board RFSoC collaborative and LFM calibration ultra-multi-channel synchronous transmission system according to claim 4, characterized in that, The master embedded board generates a first SYNC signal and transmits it to each slave embedded board. Each slave embedded board receives the first SYNC signal and feeds back a second SYNC signal with the same frequency as the first SYNC signal. The master embedded board records the transmission time of the second SYNC signal sent by each slave embedded board, calculates the propagation delay based on the transmission time of the first SYNC signal and the transmission time of the second SYNC signal, and writes the propagation delay into its own register, including: Each embedded board's RFSoC receives IQ waveform data sent by the external Ethernet switch through its corresponding second gigabit Ethernet port and stores it in the corresponding memory; The RFSoC in the main embedded board generates a first SYNC signal and transmits it to each of the slave embedded boards via the external data line. After receiving the first SYNC signal from each embedded board, a second SYNC signal with the same frequency as the first SYNC signal is generated and transmitted to the main embedded board via the external data line. The RFSoC in the main embedded board records the transmission time of the second SYNC signal sent by each slave embedded board, and calculates the propagation delay of each slave embedded board based on its own transmission time of the first SYNC signal and the transmission time of the second SYNC signal, and writes the propagation delay of each slave embedded board into its own register.

6. The multi-board RFSoC collaborative and LFM calibration ultra-multi-channel synchronous transmission system according to claim 3, characterized in that, Each embedded board transmits and receives IQ waveform data from each channel in a self-transmitting and self-receiving manner, and, in conjunction with the host computer, calculates the phase difference corresponding to each channel. The host computer then sends the data to each embedded board, including: Each embedded board transmits and receives IQ waveform data of its respective channel via a self-transmitting and self-receiving mechanism; it then uploads the IQ waveform data of each channel to the host computer; the host computer calculates the phase difference between each channel of each embedded board and the first channel of the main embedded board; the host computer sends the phase difference down to each embedded board, and each embedded board stores its corresponding phase difference in its own register.

7. The multi-board RFSoC collaborative and LFM calibration ultra-multi-channel synchronous transmission system according to claim 6, characterized in that, Each embedded board transmits and receives IQ waveform data of its respective channel in a self-transmitting and self-receiving manner; it then uploads the IQ waveform data of each channel to the host computer; the host computer calculates the phase difference between each channel of each embedded board and the first channel of the main embedded board. The host computer sends the phase difference to each embedded board, and each embedded board stores its corresponding phase difference into its own register, including: The host computer sends a first transmission signal to the external Ethernet switch through the first gigabit network port, and the external Ethernet switch forwards the first transmission signal to the RFSoC in the main embedded board through the second gigabit network port. After receiving the first transmit signal, the RFSoC in the main embedded board determines the transmission time of the IQ waveform data sent by each slave embedded board according to the propagation delay corresponding to each slave embedded board, and feeds it back to each slave embedded board. The RFSoC in each embedded board reads IQ waveform data from its own registers, transmits the IQ waveform data according to its own corresponding transmission time and through its own transmit RF interface; and receives the IQ waveform data of each channel it transmits through its own receive RF interface. Each slave embedded board receives the IQ waveform data of each channel and transmits it sequentially to the second optical module interface of the previous slave embedded board through its own first optical module interface until it reaches the main embedded board; the main embedded board uploads its own and the IQ waveform data transmitted by each slave embedded board to the host computer through the first optical module interface; The host computer receives the IO waveform data corresponding to each channel in all embedded boards through its own RDMA, and calculates the phase difference between each channel of each embedded board and the first channel of the main embedded board based on the IO waveform data corresponding to each channel. The host computer sends the phase difference corresponding to each channel in each embedded board to the RFSoC in each embedded board through the external Ethernet switch, and the RFSoC stores the phase difference corresponding to each of its own channels into its own register.

8. The multi-board RFSoC collaborative and LFM calibration ultra-multi-channel synchronous transmission system according to claim 3, characterized in that, The master embedded board pulls up the SYNC signal according to the propagation delay of each slave embedded board and sends it to each slave embedded board. Each slave embedded board compensates for its own IQ waveform data to be transmitted according to the corresponding phase difference before transmitting it. The master embedded board pulls up the first SYNC signal according to the propagation delay corresponding to each slave embedded board and sends it to each slave embedded board; after receiving the first SYNC signal after it is pulled up, each slave embedded board reads the IQ waveform data and the corresponding phase difference from its own register, compensates the corresponding phase difference for the read IQ waveform data, and then sends it out through each channel.

9. The multi-board RFSoC collaborative and LFM calibration ultra-multi-channel synchronous transmission system according to claim 8, characterized in that, The master embedded board pulls up the first SYNC signal according to the propagation delay corresponding to each slave embedded board and sends it to each slave embedded board; after receiving the pulled-up first SYNC signal, each slave embedded board reads the IQ waveform data and the corresponding phase difference from its own register, compensates for the corresponding phase difference in the read IQ waveform data, and then sends it out through each channel, including: The host computer sends a second transmission signal to the external Ethernet switch through the first gigabit network port; The external Ethernet switch forwards the second transmission signal to the RFSoC in the main embedded board through the second gigabit network port; After receiving the second transmit signal, the RFSoC in the main embedded board pulls up the first SYNC signal according to the propagation delay corresponding to each slave embedded board, and sends it to each slave embedded board through an external data line. After receiving the first SYNC signal pulled high from the embedded board, each board reads the IQ waveform data and the corresponding phase difference of each channel from its own register, compensates for the corresponding phase difference of the read IQ waveform data, and then sends it out through each channel in its own transmit RF interface.

10. The multi-board RFSoC collaborative and LFM calibration ultra-multi-channel synchronous transmission system according to claim 3, characterized in that, The registers include an EMMC and a DDR4 register. The EMMC stores the system parameters sent by the host computer. The system parameters are used to configure the frequency of IQ waveform data sent by each channel in each embedded board, the number of each embedded board, the designation of the master embedded board and slave embedded board, the frequency of the external clock source, and the frequency of multiple clock sources generated based on the external clock source. The DDR4 of the main embedded board stores the propagation delay of each slave embedded board, the IQ waveform data of each channel, and the phase difference of each channel. The DDR4 of the slave embedded board stores the IQ waveform data of each channel and the phase difference of each channel.

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