Semiconductor structure and forming method thereof
By first etching the top silicon layer to form the first and second regions in the silicon-based optoelectronic integration process, and then using a dielectric layer to repair lattice damage, the quality problem of germanium detectors caused by silicon surface lattice damage is solved, and the reliability of the device is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SEMICON TECH INNOVATION CENT(BEIJING) CORP
- Filing Date
- 2024-10-14
- Publication Date
- 2026-04-14
AI Technical Summary
In silicon-based optoelectronic integration processes, etching silicon to form germanium trenches can easily cause lattice damage to the silicon surface, affecting the penetration dislocation density of the germanium epitaxial layer and leading to dark current problems in germanium detectors.
The process involves first etching the top silicon layer to form the first and second regions, then simultaneously etching to form the first opening, and finally forming the second opening in the dielectric layer. Anisotropic dry etching and isotropic wet etching processes are used to repair lattice damage on the silicon surface, ensuring the quality of the germanium epitaxial layer.
By repairing lattice damage on the silicon surface, the quality of the germanium epitaxial layer was improved, thereby enhancing the reliability of the device.
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Figure CN121865723A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology
[0002] Silicon-based optoelectronic integration processes can be used to fabricate silicon-based optical devices, including strip waveguides, ridge waveguides, edge couplers, vertically coupled gratings, directional couplers, microring resonators, star couplers, arrayed waveguide gratings, germanium detectors, and polarization beam splitters.
[0003] Current silicon-based optoelectronic integration processes typically involve first forming waveguide and grating structures, followed by the formation of the germanium detector structure. During the formation of the germanium detector structure, silicon is first etched to create germanium trenches, and then a germanium epitaxial layer is grown within these trenches based on silicon. However, etching silicon to form germanium trenches can easily cause lattice damage to the silicon surface, affecting the through-dislocation density (TDD) of the germanium epitaxial layer, and consequently leading to dark current problems in the germanium detector.
[0004] Therefore, it is necessary to provide a more effective and reliable technical solution to improve the quality of germanium epitaxial layers, thereby improving device reliability. Summary of the Invention
[0005] This application provides a semiconductor structure and a method for forming the same, which can improve the quality of germanium epitaxial layers and thus improve device reliability.
[0006] One aspect of this application provides a method for forming a semiconductor structure, comprising: providing an SOI substrate, the SOI substrate including a top silicon layer; etching the top silicon layer to divide the top silicon layer into a first region and a second region, the first region being used to form a first device and the second region being used to form a germanium detector; etching the top silicon layer of the first region to form the first device and simultaneously etching the top silicon layer of the second region to form a first opening; forming a dielectric layer on the SOI substrate covering the SOI substrate and filling the first opening, the top surface of the dielectric layer being higher than the top surface of the top silicon layer; forming a second opening in the dielectric layer, the second opening including the first opening; and forming an epitaxial layer in the second opening.
[0007] In some embodiments of this application, the method for forming the second opening includes: performing a first etching process to etch the dielectric layer of the second region into the first opening to form the second opening, wherein the second opening coincides with the first opening in the vertical direction; and performing a second etching process to etch the dielectric layer at the bottom of the second opening into the top silicon layer.
[0008] In some embodiments of this application, the first etching process includes anisotropic dry etching, and the second etching process includes isotropic wet etching.
[0009] In some embodiments of this application, after performing the second etching process, the width of the portion of the second opening above the top silicon layer is greater than the width of the portion of the second opening located in the top silicon layer.
[0010] In some embodiments of this application, after performing the first etching process, the thickness of the remaining dielectric layer in the first opening is 10% to 50% of the depth of the first opening.
[0011] In some embodiments of this application, a method for forming a dielectric layer on the SOI substrate that covers the SOI substrate and fills the first opening includes: forming a first dielectric layer on the SOI substrate that covers the SOI substrate and fills the first opening, wherein the top surface of the first dielectric layer is higher than the top surface of the top silicon layer; and forming a second dielectric layer on the surface of the first dielectric layer.
[0012] In some embodiments of this application, after forming the first dielectric layer, the method further includes forming a first doped region and a second doped region with opposite doping types in the top silicon layers on both sides of the first opening.
[0013] Another aspect of this application provides a semiconductor structure comprising: an SOI substrate, the SOI substrate including a top silicon layer, the top silicon layer being divided into a first region and a second region, a first device being formed in the top silicon layer of the first region, and a first opening being formed in the top silicon layer of the second region; a dielectric layer covering the SOI substrate and filling the first opening, the top surface of the dielectric layer being higher than the top surface of the top silicon layer; a second opening penetrating the dielectric layer of the second region and extending to the bottom of the first opening, the second opening coinciding with the first opening in the vertical direction; and an epitaxial layer located in the second opening.
[0014] In some embodiments of this application, the width of the portion of the second opening above the top silicon layer is greater than the width of the portion of the second opening located in the top silicon layer.
[0015] In some embodiments of this application, the dielectric layer includes a first dielectric layer and a second dielectric layer, wherein the first dielectric layer covers the SOI substrate and fills the first opening and its top surface is higher than the top surface of the top silicon layer, and the second dielectric layer is located on the surface of the first dielectric layer.
[0016] In some embodiments of this application, a first doped region and a second doped region with opposite doping types are formed in the top silicon layer on both sides of the first opening.
[0017] This application provides a semiconductor structure and a method for forming the same, which can improve the quality of germanium epitaxial layers and thus improve device reliability. Attached Figure Description
[0018] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale.
[0019] in:
[0020] Figures 1 to 9 This is a schematic diagram of each step in the method for forming a semiconductor structure according to the embodiments of this application. Detailed Implementation
[0021] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.
[0022] The technical solution of the present invention will be described in detail below with reference to the embodiments and accompanying drawings.
[0023] Figures 1 to 9 This is a schematic diagram of each step in the method for forming a semiconductor structure according to an embodiment of this application. The method for forming a semiconductor structure according to an embodiment of this application will be described in detail below with reference to the accompanying drawings.
[0024] refer to Figure 1 As shown, an SOI substrate 100 is provided, the SOI substrate 100 including a bottom silicon layer 101, an insulating layer 102 and a top silicon layer 103.
[0025] In some embodiments of this application, the semiconductor structure of this application is, for example, a silicon-based optoelectronic integrated device based on an SOI substrate.
[0026] In some embodiments of this application, the bottom silicon layer 101 is made of silicon, the insulating layer 102 is made of silicon dioxide, and the top silicon layer 103 is made of silicon. Silicon-on-insulator (SOI) substrates are common substrate structures in semiconductor structures; therefore, the formation process and detailed structure of the SOI substrate 100 will not be described here.
[0027] refer to Figure 2As shown, the top silicon layer 103 is etched to the surface of the insulating layer 102 to divide the top silicon layer 103 into a first region 110 and a second region 120, the first region 110 being used to form a first device and the second region 120 being used to form a germanium detector.
[0028] In some embodiments of this application, the number of the first region 110 may be multiple; for the sake of brevity, only one first region 110 is shown here. The first region 110 is used to form a first device, which includes one or more active or passive devices in silicon photonics processes other than germanium detectors, such as grating structures, ridge waveguide structures, strip waveguide structures, and modulators.
[0029] In some embodiments of this application, there may be multiple second regions 120; for the sake of brevity, only one second region 120 is shown here. The second region 120 is used to form a germanium detector in a silicon photonics process.
[0030] refer to Figure 3 As shown, the top silicon layer 103 of the first region 110 is etched to form the first device 130, and the top silicon layer 103 of the second region 120 is simultaneously etched to form the first opening 140.
[0031] In the accompanying drawings of this application, the first device 130 is shown as a grating structure only as an example. In practice, the first device 130 can also be a ridge waveguide structure, a strip waveguide structure, etc. For example, in some embodiments of this application, there are multiple first regions 110, and different first devices 130 are formed in the multiple first regions 110, such as grating structures, ridge waveguide structures, strip waveguide structures, etc.
[0032] In some embodiments of this application, the structures and methods of forming various first devices 130 are conventional structures and methods well known to those skilled in the art, and therefore will not be described in detail here.
[0033] In some embodiments of this application, the first device 130 and the first opening 140 may also be formed by step etching. The technical solution of this application is to form the first opening 140 before forming the dielectric layer, so as to repair the lattice damage of the first opening 140 through the dielectric layer. Therefore, it is sufficient as long as the first opening 140 is formed before forming the dielectric layer. The first opening 140 can be formed before the first device 130, simultaneously with the first device 130, or after the first device 130 and before the dielectric layer.
[0034] refer to Figures 4 to 6As shown, a dielectric layer 150 is formed on the SOI substrate 100, covering the SOI substrate 100 and the active device 130 and filling the first opening 140, and the top surface of the dielectric layer 150 is higher than the top surface of the top silicon layer 103.
[0035] Specifically, refer to Figure 4 As shown, a first dielectric layer 151 is formed on the SOI substrate 100, covering the SOI substrate 100 and the active device 130 and filling the first opening 140. The top surface of the first dielectric layer 151 is higher than the top surface of the top silicon layer 103.
[0036] In some embodiments of this application, the material of the first dielectric layer 151 includes silicon oxide. The method for forming the first dielectric layer 151 includes a thermal oxidation process. The thermal oxidation process can repair lattice damage to the silicon surface caused during etching of the top silicon layer 103. In some embodiments of this application, the method for forming the first dielectric layer 151 can also be any other process that can both form a film and repair lattice damage.
[0037] In some embodiments of this application, an additional process for repairing silicon surface lattice damage may be added before or after the step of forming the first dielectric layer 151.
[0038] refer to Figure 5 As shown, after the first dielectric layer 151 is formed, a first doped region 141 and a second doped region 142 with opposite doping types are formed in the top silicon layer 103 on both sides of the first opening 140.
[0039] In some embodiments of this application, the method for forming the first doped region 141 and the second doped region 142 includes: performing an ion implantation process on the top silicon layers 103 on both sides of the first opening 140 with the first dielectric layer 151 as a protection to form the first doped region 141 and the second doped region 142.
[0040] refer to Figure 6 As shown, a second dielectric layer 152 is formed on the surface of the first dielectric layer 151.
[0041] In some embodiments of this application, the material of the second dielectric layer 152 includes silicon oxide. Methods for forming the second dielectric layer 152 include chemical vapor deposition (CVD) or physical vapor deposition (PVD).
[0042] refer to Figure 7 and Figure 8 As shown, a second opening 160 is formed in the dielectric layer 150, and the second opening 160 includes the first opening 140.
[0043] refer to Figure 7As shown, a first etching process is performed to etch the dielectric layer 150 (including a first dielectric layer 151 and a second dielectric layer 152) of the second region 120 into the first opening 140 to form a second opening 160. The second opening 160 coincides with the first opening 140 in the vertical direction. The dielectric layer 150 (i.e., the first dielectric layer 151) in the first opening 140 is not completely etched.
[0044] In some embodiments of this application, after performing the first etching process, the thickness of the remaining dielectric layer 150 (i.e., the first dielectric layer 151) in the first opening 140 is 10% to 50% of the depth of the first opening 140.
[0045] In some embodiments of this application, the first etching process includes anisotropic dry etching. Since the second opening 160 is relatively deep, to avoid creating a large opening laterally during the etching process, anisotropic dry etching capable of stable downward etching needs to be selected.
[0046] refer to Figure 8 As shown, a second etching process is performed to etch the dielectric layer 150 (i.e., the first dielectric layer 151) at the bottom of the second opening 160 down to the top silicon layer 103. At this time, the second opening 160 covers the first opening 140, that is, the second opening 160 completely includes the first opening 140.
[0047] Considering the inherent errors in the manufacturing process, particularly the accuracy of the first etching process, the second opening 160 may not be perfectly aligned with the first opening 140. If the second opening 160 deviates to some extent or its size fails to completely cover the first opening 140, a portion of the dielectric layer 150 (i.e., the first dielectric layer 151) will remain on the sidewall of the first opening 140, affecting subsequent germanium epitaxial growth. Therefore, the technical solution of this application adds an additional second etching process to further etch the dielectric layer 150, ensuring that the second opening 160 completely covers the first opening 140 so that there are no residues on the bottom and sidewalls of the first opening 140.
[0048] In some embodiments of this application, the second etching process includes isotropic wet etching. Since the purpose is to etch in all directions to ensure that no dielectric layer remains in the first opening 140, isotropic wet etching, which can etch in all directions, is chosen.
[0049] In some embodiments of this application, after performing the second etching process, the width of the portion of the second opening 160 above the top silicon layer 103 is greater than the width of the portion of the second opening 160 located in the top silicon layer 103. To ensure that dielectric layer residue in the first opening 140 can be completely removed, the second etching process requires slight over-etching, such that the width of the portion of the second opening 160 above the top silicon layer 103 is greater than the width of the portion of the second opening 160 located in the top silicon layer 103.
[0050] In some embodiments of this application, it is necessary to ensure that the amount of etching for the slight over-etching is as small as possible. In some embodiments of this application, the width of the portion of the second opening 160 above the top silicon layer 103 is 100% to 105% (excluding 100%) of the width of the portion of the second opening 160 located in the top silicon layer 103.
[0051] refer to Figure 9 As shown, an epitaxial layer 170 is formed in the second opening 160. The top silicon layer 130, the first doped region 141, the second doped region 42, and the epitaxial layer 170 of the second region 120 constitute a germanium detector.
[0052] In some embodiments of this application, the material of the epitaxial layer 170 includes germanium. The method of forming the epitaxial layer 170 includes an epitaxial growth process.
[0053] In some embodiments of this application, the epitaxial layer 170 further extends to the surface of the dielectric layer 150 (second dielectric layer 152).
[0054] In the technical solution of this application, since the silicon surface lattice damage of the top silicon layer 103 in the second region 120 is repaired, a high-quality epitaxial layer 170 can be epitaxially grown, thereby improving the device reliability.
[0055] In the technical solution of this application, the second opening is formed by two etching processes: the first etching process and the second etching process. This ensures that there is no dielectric layer residue on the silicon surface at the bottom and sidewalls of the second opening, thereby further improving the quality of epitaxial growth.
[0056] In the technical solution of this application, a first opening is formed in the second region in advance when forming the first device, and then the formation of the dielectric layer is used to repair the silicon surface lattice damage. The repair of silicon surface lattice damage is achieved without adding any additional processes and does not affect the original processes.
[0057] This application provides a method for forming a semiconductor structure, which can improve the quality of the germanium epitaxial layer and thus improve the reliability of the device.
[0058] Embodiments of this application also provide a semiconductor structure, referencing Figure 9 As shown, the system includes: an SOI substrate 100, the SOI substrate 100 including a top silicon layer 103, the top silicon layer 103 being divided into a first region 110 and a second region 120, a first device 130 being formed in the top silicon layer 103 of the first region 110, and a first opening 140 being formed in the top silicon layer 103 of the second region 120; a dielectric layer 150 covering the SOI substrate 100 and filling the first opening 140, the top surface of the dielectric layer 150 being higher than the top surface of the top silicon layer 103; a second opening 160 penetrating the dielectric layer 150 of the second region 120 and extending to the bottom of the first opening 140, the second opening 160 coinciding with the first opening 140 in the vertical direction; and an epitaxial layer 170 located in the second opening 160.
[0059] In some embodiments of this application, the semiconductor structure of this application is, for example, a silicon-based optoelectronic integrated device based on an SOI substrate.
[0060] In some embodiments of this application, the SOI substrate 100 includes a bottom silicon layer 101, an insulating layer 102, and a top silicon layer 103.
[0061] In some embodiments of this application, the bottom silicon layer 101 is made of silicon, the insulating layer 102 is made of silicon dioxide, and the top silicon layer 103 is made of silicon. Silicon-on-insulator (SOI) substrates are common substrate structures in semiconductor structures; therefore, the formation process and detailed structure of the SOI substrate 100 will not be described here.
[0062] In some embodiments of this application, the number of the first region 110 may be multiple; for the sake of brevity, only one first region 110 is shown here. The first region 110 is used to form a first device, which includes one or more active or passive devices in silicon photonics processes other than germanium detectors, such as grating structures, ridge waveguide structures, strip waveguide structures, and modulators.
[0063] In some embodiments of this application, there may be multiple second regions 120; for the sake of brevity, only one second region 120 is shown here. The second region 120 is used to form a germanium detector in a silicon photonics process.
[0064] In the accompanying drawings of this application, the first device 130 is shown as a grating structure only as an example. In practice, the first device 130 can also be a ridge waveguide structure, a strip waveguide structure, etc. For example, in some embodiments of this application, there are multiple first regions 110, and different first devices 130 are formed in the multiple first regions 110, such as grating structures, ridge waveguide structures, strip waveguide structures, etc.
[0065] In some embodiments of this application, the structures and methods of forming various first devices 130 are conventional structures and methods well known to those skilled in the art, and therefore will not be described in detail here.
[0066] In some embodiments of this application, the dielectric layer 150 includes a first dielectric layer 151 and a second dielectric layer 152. The first dielectric layer 151 covers the SOI substrate 100 and the active device 130 and fills the first opening 140, with its top surface higher than the top surface of the top silicon layer 103. The second dielectric layer 152 is located on the surface of the first dielectric layer 151.
[0067] In some embodiments of this application, the material of the first dielectric layer 151 includes silicon oxide.
[0068] In some embodiments of this application, the material of the second dielectric layer 152 includes silicon oxide.
[0069] In some embodiments of this application, a first doped region 141 and a second doped region 142 with opposite doping types are formed in the top silicon layer 103 on both sides of the first opening 140.
[0070] In some embodiments of this application, the second opening 160 covers the first opening 140, that is, the second opening 160 completely includes the first opening 140.
[0071] In some embodiments of this application, the width of the portion of the second opening 160 above the top silicon layer 103 is greater than the width of the portion of the second opening 160 located in the top silicon layer 103.
[0072] In some embodiments of this application, the width of the portion of the second opening 160 above the top silicon layer 103 is 100% to 105% (excluding 100%) of the width of the portion of the second opening 160 located in the top silicon layer 103.
[0073] In some embodiments of this application, an epitaxial layer 170 is formed in the second opening 160. The top silicon layer 130, the first doped region 141, the second doped region 42, and the epitaxial layer 170 of the second region 120 constitute a germanium detector.
[0074] In some embodiments of this application, the material of the epitaxial layer 170 includes germanium.
[0075] In some embodiments of this application, the epitaxial layer 170 further extends to the surface of the dielectric layer 150 (second dielectric layer 152).
[0076] This application provides a semiconductor structure and a method for forming the same, which can improve the quality of germanium epitaxial layers and thus improve device reliability.
[0077] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.
[0078] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.
[0079] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," as used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.
[0080] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.
[0081] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: An SOI substrate is provided, the SOI substrate including a top silicon layer; Etching the top silicon layer divides it into a first region and a second region, the first region being used to form a first device and the second region being used to form a germanium detector. The top silicon layer of the first region is etched to form the first device, and the top silicon layer of the second region is simultaneously etched to form the first opening; A dielectric layer is formed on the SOI substrate, covering the SOI substrate and filling the first opening, wherein the top surface of the dielectric layer is higher than the top surface of the top silicon layer; A second opening is formed in the dielectric layer, the second opening including the first opening; An epitaxial layer is formed in the second opening.
2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the second opening includes: performing a first etching process to etch the dielectric layer of the second region into the first opening to form the second opening, wherein the second opening coincides with the first opening in the vertical direction; and performing a second etching process to etch the dielectric layer at the bottom of the second opening into the top silicon layer.
3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The first etching process includes anisotropic dry etching, and the second etching process includes isotropic wet etching.
4. The method for forming a semiconductor structure as described in claim 3, characterized in that, After the second etching process is performed, the width of the portion of the second opening above the top silicon layer is greater than the width of the portion of the second opening located in the top silicon layer.
5. The method for forming a semiconductor structure as described in claim 1, characterized in that, After performing the first etching process, the thickness of the remaining dielectric layer in the first opening is 10% to 50% of the depth of the first opening.
6. The method for forming a semiconductor structure as described in claim 1, characterized in that, A method for forming a dielectric layer on the SOI substrate that covers the SOI substrate and fills the first opening includes: A first dielectric layer is formed on the SOI substrate, covering the SOI substrate and filling the first opening, wherein the top surface of the first dielectric layer is higher than the top surface of the top silicon layer. A second dielectric layer is formed on the surface of the first dielectric layer.
7. The method for forming a semiconductor structure as described in claim 6, characterized in that, After forming the first dielectric layer, the method further includes forming a first doped region and a second doped region with opposite doping types in the top silicon layers on both sides of the first opening.
8. A semiconductor structure, characterized in that, include: The SOI substrate includes a top silicon layer, which is divided into a first region and a second region. A first device is formed in the top silicon layer of the first region, and a first opening is formed in the top silicon layer of the second region. A dielectric layer covers the SOI substrate and fills the first opening, wherein the top surface of the dielectric layer is higher than the top surface of the top silicon layer; The second opening penetrates the dielectric layer of the second region and extends to the bottom of the first opening, and the second opening coincides with the first opening in the vertical direction; The epitaxial layer is located in the second opening.
9. The semiconductor structure as described in claim 8, characterized in that, The width of the portion of the second opening above the top silicon layer is greater than the width of the portion of the second opening located within the top silicon layer.
10. The semiconductor structure as described in claim 8, characterized in that, The dielectric layer includes a first dielectric layer and a second dielectric layer. The first dielectric layer covers the SOI substrate and fills the first opening, and its top surface is higher than the top surface of the top silicon layer. The second dielectric layer is located on the surface of the first dielectric layer.
11. The semiconductor structure as described in claim 8, characterized in that, A first doped region and a second doped region with opposite doping types are formed in the top silicon layer on both sides of the first opening.