Semiconductor relay

Abstract

A semiconductor relay (100) is provided with a light-emitting element (10), a light-receiving element (20), first and second switching elements (31, 32), first and second die pads (51, 52), first and second terminals (41, 42), and a package (60) that accommodates the first and second terminals therein. The light receiving element (20) is located below the light emitting element (10) and between the first switching element (31) and the second switching element (32). One ends of the first and second terminals (41, 42) are connected to the first and second chip pads (51, 52), respectively, and the other ends are exposed outside the package (60). In a plan view, at least parts of the first and second chip pads (51, 52) overlap the first and second switching elements (31, 32), respectively.

Description

Technical Field

[0001] This disclosure relates to a semiconductor relay. Background Technology

[0002] Previously, semiconductor relays, also known as MOSFET output optocouplers or optoMOSFETs, were used as a means of signal transmission. Typically, these semiconductor relays miniaturized their components by sealing them in resin packages.

[0003] For example, Patent Document 1 discloses a semiconductor relay comprising: a light-emitting element; an input-side terminal electrically connected to the light-emitting element; a light-receiving element disposed opposite to the light-emitting element; a first switching element electrically connected to the light-receiving element; a first lead including a first mounting base on which the first switching element is mounted and a first output-side terminal electrically connected to the first switching element; and a resin encapsulation that seals the first mounting base of the light-emitting element, the light-receiving element, the first switching element, and the first lead.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 2022-126101 Summary of the Invention

[0007] In the conventional semiconductor relay disclosed in Patent Document 1, the switching element generates significant heat during operation. However, Patent Document 1 does not disclose any countermeasures for this heat generation.

[0008] A semiconductor relay according to one aspect of this disclosure is characterized by comprising: a light-emitting element; a light-receiving element located below and facing the light-emitting element; a first switching element adjacent to the light-receiving element; a second switching element adjacent to the light-receiving element; a first chip pad located above the first switching element; a second chip pad located above the second switching element; a first terminal, one end of which is connected to the first chip pad; a second terminal, one end of which is connected to the second chip pad; and a package, wherein the light-receiving element is located between the first switching element and the second switching element, the orientation of the first terminal and the second terminal is set as a first direction, the other end of the first terminal is exposed outside the package and extends downward from the package, the other end of the second terminal is exposed outside the package and extends downward from the package, the light-emitting element, the light-receiving element, the first switching element, the second switching element, the first chip pad, and the second chip pad are located inside the package, and in a top view, at least a portion of the first chip pad overlaps with the first switching element, and in a top view, at least a portion of the second chip pad overlaps with the second switching element.

[0009] Additionally, another aspect of the semiconductor relay disclosed herein includes: a light-emitting element; a light-receiving element located below and facing the light-emitting element; a first switching element adjacent to the light-receiving element; a second switching element adjacent to the light-receiving element; a first chip pad located above the first switching element; a second chip pad located above the second switching element; a first terminal, one end of which is connected to the first chip pad; a second terminal, one end of which is connected to the second chip pad; and a package, wherein the light-receiving element is located between the first switching element and the second switching element, the orientation of the first terminal and the second terminal is set as a first direction, the other end of the first terminal is exposed outside the package and extends downward from the package, the other end of the second terminal is exposed outside the package and extends downward from the package, and in a top view, at least a portion of the first chip pad overlaps with the first switching element, and in a top view, at least a portion of the second chip pad overlaps with the second switching element. Another aspect of the semiconductor relay disclosed herein further comprises: a third chip pad on which the first switching element is disposed; a fourth chip pad on which the second switching element is disposed; a third terminal on which one end is connected to the third chip pad; and a fourth terminal on which is disposed facing the third terminal in the first direction. The light-emitting element, the light-receiving element, the first switching element, the second switching element, the first chip pad, the second chip pad, and the third chip pad are located inside the package. The third terminal is composed of a third front portion, a third middle portion, and a third connecting portion, wherein the third middle portion and the third front portion are connected. The third connection portion connects the third intermediate portion to the third chip pad and is located inside the package. The third intermediate portion has: a first portion connected to the third connection portion; and a second portion extending downward from the first portion. When the direction in which the light-emitting element and the light-receiving element face each other is defined as the third direction, the shortest length of the third intermediate portion in the first direction is greater than the longest length of the third front end portion in the first direction. The distance of the first portion from the fourth terminal along the center line of the third direction, i.e., the first axis, is greater than the distance of the third front end portion from the fourth terminal along the center line of the third direction, i.e., the second axis, is greater.

[0010] According to this disclosure, heat dissipation can be improved by strengthening the path used to release heat generated during operation to the outside of the package. Attached Figure Description

[0011] Figure 1AThis is a perspective view of the semiconductor relay according to the first embodiment.

[0012] Figure 1B This is a side view of the semiconductor relay involved in the first embodiment, viewed from the right.

[0013] Figure 1C This is a side view of the semiconductor relay involved in the first embodiment, viewed from the left.

[0014] Figure 1D This is a top view of the semiconductor relay according to the first embodiment.

[0015] Figure 1E This is a perspective view of the semiconductor relay according to the first embodiment, omitting the package.

[0016] Figure 2 This is a top view of the semiconductor relay according to the first embodiment, omitting the package.

[0017] Figure 3 It is the semiconductor relay involved in the first embodiment. Figure 2 The cross-sectional view at line III-III is shown.

[0018] Figure 4 This is the equivalent circuit diagram of the semiconductor relay involved in the first embodiment.

[0019] Figure 5A This is a perspective view of the semiconductor relay according to the first embodiment from a low angle.

[0020] Figure 5B This is a top perspective view of the semiconductor relay according to the first embodiment.

[0021] Figure 6A This is a top view of the first chip pad according to the first embodiment.

[0022] Figure 6B This is a top view of the second chip pad according to the first embodiment.

[0023] Figure 6C This is a top view showing another example of the first chip pad.

[0024] Figure 6D This is a top view showing another example of the first chip pad.

[0025] Figure 7A This is a top view of the first chip pad and the first switching element.

[0026] Figure 7B This is a top view of the second chip pad and the second switching element.

[0027] Figure 8A This is a top view of the first terminal according to the first embodiment.

[0028] Figure 8B This is a side view of the first terminal according to the first embodiment.

[0029] Figure 9A This is a top view of the first terminal involved in the comparative example.

[0030] Figure 9B This is a side view of the first terminal involved in the comparative example.

[0031] Figure 10A yes Figure 1C An enlarged view of the portion enclosed by the dashed line XA.

[0032] Figure 10B yes Figure 1C An enlarged view of the portion enclosed by the dashed line XB.

[0033] Figure 11A It is the first variation involved, Figure 10A The corresponding diagram.

[0034] Figure 11B It is the first variation involved, Figure 10B The corresponding diagram.

[0035] Figure 12A This is a three-dimensional view of the semiconductor relay involved in the second variation.

[0036] Figure 12B This is a side view of the semiconductor relay involved in the second variation.

[0037] Figure 13 This is a perspective view of the semiconductor relay according to the second embodiment, omitting the package. Detailed Implementation

[0038] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. The following description of preferred embodiments is merely illustrative and is not intended to limit the invention, its application, or its uses.

[0039] Furthermore, in this disclosure, the terms "above" and "below" do not refer to the absolute spatial orientation of upward (vertically above) and downward (vertically below), but are used as terms defined by the relative positional relationship of the structures in the semiconductor relay. Additionally, the terms "above" and "below" apply not only to the case where two components are arranged spaced apart from each other and other components exist between them, but also to the case where two components are arranged close together and connected. Furthermore, in the following description, the view of the semiconductor relay 100 and its components from above will be shown as a top view.

[0040] (First Implementation)

[0041] [Overall structure of semiconductor relay 100]

[0042] The semiconductor relay 100 according to the first embodiment will be described below.

[0043] Use Figure 1 to Figure 3 A summary of the structure of the semiconductor relay 100 according to this embodiment will be described. Figure 1A This is a perspective view of the semiconductor relay according to the first embodiment. Figure 1B This is a side view of the semiconductor relay involved in the first embodiment, viewed from the right. Figure 1C This is a side view of the semiconductor relay involved in the first embodiment, viewed from the left. Figure 1D This is a top view of the semiconductor relay according to the first embodiment. Figure 1E This is a perspective view of the semiconductor relay according to the first embodiment, omitting the package. Figure 2 This is a top view of the semiconductor relay according to the first embodiment. Figure 3 It is the semiconductor relay involved in the first embodiment. Figure 2 The cross-sectional view of line Ⅲ-Ⅲ is shown.

[0044] Furthermore, for ease of explanation, in Figure 1A In the accompanying drawings and thereafter, the metal wires connecting the components of the semiconductor relay 100 are omitted from the illustrations and detailed descriptions. Furthermore, in Figure 1A as well as Figure 1D The diagram only shows the pad 502a in the wiring 502 of the external mounting substrate 500.

[0045] Furthermore, in the following descriptions, the front-back, left-right, and up-down directions shown in the figures are sometimes used to describe the arrangement and structure of each component. That is, the direction in which terminal 42 is positioned relative to terminal 41 is indicated as front or forward, and the direction in which terminal 41 is positioned relative to terminal 42 is indicated as rear or back. Additionally, the direction in which terminals 41-46 protrude is indicated as left or left-right, and the direction in which terminals 47 and 48 protrude is indicated as right or right-right. Furthermore, the front-back direction is sometimes indicated as a first direction. The left-right direction is sometimes indicated as a second direction. The up-down direction is sometimes indicated as a third direction. The first to third directions are orthogonal to each other.

[0046] In addition, sometimes "terminal 41" is referred to as "first terminal 41", "terminal 42" is referred to as "second terminal 42", "terminal 47" is referred to as "seventh terminal 47", and "terminal 48" is referred to as "eighth terminal 48".

[0047] Furthermore, the "seventh terminal 47" in the embodiment is equivalent to the "third terminal" in the present invention, and the "eighth terminal 48" in the embodiment is equivalent to the "fourth terminal" in the present invention.

[0048] Furthermore, in this application specification, "orthogonal," "parallel," or "identical" means orthogonal, parallel, or identical, including the semiconductor relay 100 and the processing tolerances and assembly tolerances of its constituent components, and does not mean that the comparison objects are orthogonal, parallel, or identical in a strict sense.

[0049] like Figures 1A to 3 As shown, the semiconductor relay 100 includes a light-emitting element 10, a light-receiving element 20, a first switching element 31 and a second switching element 32, first chip pads 51 to sixth chip pads 56, terminals 41 to 48, and a package 60. The first chip pads 51 to sixth chip pads 56 and terminals 41 to 48 are obtained by processing a metal plate such as copper.

[0050] The light-emitting element 10 is disposed on the lower surface of the fifth chip pad 55. The fifth chip pad 55 is connected to terminals 43 and 44. In this embodiment, the light-emitting element 10 is a light-emitting diode (LED).

[0051] Terminal 45 is electrically connected to the light-emitting element 10 via a metal wire. By applying a specified voltage between terminals 43 and 44 and terminal 45, the light-emitting element 10 emits light and outputs a light signal.

[0052] The light-receiving element 20 is located below the light-emitting element 10. The light-receiving element 20 is disposed on the upper surface of the sixth chip pad 56.

[0053] The first switching element 31 and the second switching element 32 are adjacent to the light-receiving element 20. The first switching element 31 and the second switching element 32 are spaced apart on both sides of the light-receiving element 20 along a first direction. That is, the light-receiving element 20 is located between the first switching element 31 and the second switching element 32. In this embodiment, the first switching element 31 and the second switching element 32 are MOSFETs (refer to...). Figure 4 However, it is not specifically limited to this.

[0054] The first switching element 31 is disposed on the upper surface of the third chip pad 53. In addition, the second switching element 32 is disposed on the upper surface of the fourth chip pad 54.

[0055] One end of the third chip pad 53 is connected to the seventh terminal 47. One end of the fourth chip pad 54 is connected to the eighth terminal 48.

[0056] The package 60 is made of insulating resin and seals the light-emitting element 10, the light-receiving element 20, the first switching element 31 and the second switching element 32, and the first chip pads 51 to the sixth chip pads 56. Additionally, a portion of the terminals 41 to 48 is also sealed inside the package 60. That is, the light-emitting element 10, the light-receiving element 20, the first switching element 31 and the second switching element 32, the first chip pads 51 to the sixth chip pads 56, and a portion of the terminals 41 to 48 are located inside the package 60.

[0057] like Figures 1A-1C As shown, the package 60 is rectangular in shape. Additionally, although not shown, protrusions or recesses may be provided on the sides of the package 60.

[0058] Although not shown, the package 60 is composed of an insulating light-transmitting resin and an insulating light-shielding resin. The light-transmitting resin covers a portion of the light-emitting element 10, the light-receiving element 20, the first switching element 31 and the second switching element 32, the first chip pads 51 to the sixth chip pads 56, and the terminals 41 to 48. The light-shielding resin is provided in such a way that it covers the entire surface of the light-transmitting resin.

[0059] The first switching element 31 and the second switching element 32 generate heat when the semiconductor relay 100 is activated. When the first switching element 31 and the second switching element 32 generate heat, the overall internal temperature of the package 60 rises. As a result, the package 60, being made of resin material, expands, causing the components to peel off from the package 60. Furthermore, this also causes the light-emitting element 10, the light-receiving element 20, the first switching element 31, and the second switching element 32 to peel off from the third chip pad 53 to the sixth chip pad 56. Additionally, due to the expansion of the package 60, thermal runaway may occur in some components, or the metal wires connecting the components to the third chip pad 53 to the sixth chip pad 56 may detach. Consequently, the reliability of the light-emitting element 10, the light-receiving element 20, the first switching element 31, and the second switching element 32 decreases.

[0060] [Operation of Semiconductor Relay 100]

[0061] Figure 4 This is the equivalent circuit diagram of the semiconductor relay involved in the first embodiment.

[0062] When an input signal is applied between terminals 43 and 45 or between terminals 44 and 45, the light-emitting element 10 outputs a light signal. The light signal generated by the light-emitting element 10 propagates inside the light-transmitting resin and is received by the light-receiving element 20.

[0063] The light-receiving element 20 consists of a photodiode array 21 and a control circuit 22 connected in parallel with it. In the photodiode array 21, current is generated through photoelectric conversion, and the control circuit 22 operates based on this current. A voltage signal, i.e., a drive signal, corresponding to the amount of light emitted by the light-emitting element 10 is applied via metal lines to the gate electrodes of the first switching element 31 and the second switching element 32, respectively.

[0064] When the voltage of the drive signal exceeds the threshold voltage of each of the first switching element 31 and the second switching element 32, the source (S)-drain (D) junction of the first switching element 31 and the source (S)-drain (D) junction of the second switching element 32 become closed. Furthermore, terminals 47 and 48 become connected via the first switching element 31 and the second switching element 32. Thus, signal transmission is possible between terminals 47 and 48.

[0065] In addition, "terminal 47 (third terminal)" is sometimes referred to as "seventh terminal 41" and "terminal 48 (fourth terminal)" is referred to as "eighth terminal 48".

[0066] When the input signal is stopped between terminals 43 and 45 or between terminals 44 and 45, the light emission of the light-emitting element 10 also stops. Correspondingly, no current is generated in the photodiode array 21, and the control circuit 22 stops.

[0067] As a result, the voltages of the drive signals applied to the gate electrodes of the first switching element 31 and the second switching element 32 decrease. When the voltage of the drive signal is lower than the threshold voltage, the source (S)-drain (D) junction of the first switching element 31 and the source (S)-drain (D) junction of the second switching element 32 become open. Furthermore, the seventh terminal 47 and the eighth terminal 48 become non-conductive. Thus, signal transmission between the seventh terminal 47 and the eighth terminal 48 is cut off.

[0068] [Summary structure of the first chip pad 51 and the second chip pad 52]

[0069] The first chip pad 51 is located above the first switching element 31. The second chip pad 52 is located above the second switching element 32. Figure 3 As shown, the semiconductor relay 100 is mounted on the external mounting substrate 500 located below.

[0070] like Figure 3 As shown, the external mounting substrate 500 comprises a main substrate 501, wiring 502, and a ground electrode 503. The main substrate 501 is made of dielectric material, and a plurality of wirings 502 are formed on the upper surface of the main substrate 501, while a ground electrode 503 is formed on the lower surface of the main substrate 501. One of the wirings 502, which has a pad 502a at one end, is a connection wiring for connecting to the semiconductor relay 100 or electronic components other than the semiconductor relay 100. The front ends of terminals 41-48, i.e., front ends 41a-48a, are connected to the pad 502a via a conductive adhesive material (not shown). When the semiconductor relay 100 is activated, heat generated by the semiconductor relay 100, particularly the first switching element 31 and the second switching element 32, is transmitted to the external mounting substrate 500, thereby causing the external mounting substrate 500 to heat up.

[0071] In addition, "front end portion 41a" is sometimes referred to as "first front end portion 41a", "front end portion 42a" as "second front end portion 42a", "front end portion 47a" as "seventh front end portion 47a", and "front end portion 48a" as "eighth front end portion 48a".

[0072] Furthermore, the "seventh front end portion 47a" in the embodiment is equivalent to the "third front end portion" in the specification, and the "eighth front end portion 48a" in the embodiment is equivalent to the "fourth front end portion" in the specification.

[0073] Here, the path for releasing the heat generated by the first switching element 31 and the second switching element 32 to the outside is described in further detail.

[0074] A portion of the heat generated by the first switching element 31 is released to the external mounting substrate 500 via the third chip pad 53 and the seventh terminal 47. Additionally, a portion of the heat generated by the first switching element 31 diffuses upwards through the package 60 and is absorbed by the first chip pad 51. A portion of the heat absorbed by the first chip pad 51 is released to the external mounting substrate 500 via the first terminal 41. Furthermore, a portion of the heat absorbed by the first chip pad 51 is released upwards through the package 60 and from the upper surface of the package 60 to the outside.

[0075] like Figure 2 As shown, one end of the first terminal 41 is connected to the first chip pad 51 inside the package 60. The other end of the first terminal 41 is exposed outside the package 60. According to this structure, the heat absorbed by the first chip pad 51 can be released to the outside of the package 60 through the first terminal 41.

[0076] A portion of the heat generated by the second switching element 32 is released to the external mounting substrate 500 via the fourth chip pad 54 and the eighth terminal 48. Additionally, a portion of the heat generated by the second switching element 32 diffuses upwards through the package 60 and is absorbed by the second chip pad 52. A portion of the heat absorbed by the second chip pad 52 is released to the external mounting substrate 500 via the second terminal 42. Furthermore, a portion of the heat absorbed by the second chip pad 52 is released upwards through the package 60 and outwards from the upper surface of the package 60.

[0077] like Figure 2 As shown, one end of the second terminal 42 is connected to the second chip pad 52. The other end of the second terminal 42 is exposed outside the package 60. According to this structure, the heat absorbed by the second chip pad 52 can be released to the outside of the package 60 through the second terminal 42.

[0078] Furthermore, the second chip pad 52 can also be connected to the terminal 46. This structure allows the heat absorbed by the second chip pad 52 to be released to the outside of the package 60 not only through the second terminal 42 but also through the terminal 46.

[0079] No electronic components constituting the semiconductor relay 100 are disposed on the first chip pad 51 and the second chip pad 52. According to this structure, even if the heat generated by the first switching element 31 and the second switching element 32 is absorbed by the first chip pad 51 and the second chip pad 52, it will not affect the operation of the semiconductor relay 100. Furthermore, it will not significantly affect the operational reliability of the semiconductor relay 100. Alternatively, metal wires can be connected to the first chip pad 51 and the second chip pad 52 respectively, serving as part of the path for the current flowing through the semiconductor relay 100.

[0080] In addition, LEDs generally have lower heat resistance than MOSFETs. Therefore, in this embodiment, the first chip pad 51 on which the light-emitting element 10 is disposed is located inside and above the package 60, i.e., on the side with higher heat dissipation.

[0081] like Figure 2 As shown, in a top view, at least a portion of the first chip pad 51 overlaps with the first switching element 31. According to this structure, the first chip pad 51 can be brought close to the first switching element 31, which is one of the heat sources. When the first switching element 31 heats up, the heat diffuses to the surroundings through the surrounding resin. By bringing the first switching element 31 and the first chip pad 51 closer together, the amount of heat that can be conducted from the first switching element 31 to the first chip pad 51 can be increased. As described above, the first chip pad 51 can efficiently absorb the heat generated by the first switching element 31. According to this structure, the path for releasing the heat generated during the operation of the first switching element 31 to the outside of the package 60 can be strengthened.

[0082] In particular, as in this embodiment, when each component constituting the semiconductor relay 100 is sealed with resin, the effect is significant because the resin has low thermal conductivity.

[0083] like Figure 2 As shown, in top view, at least a portion of the second chip pad 52 overlaps with the second switching element 32. According to this structure, the second chip pad 52 can be brought close to the second switching element 32, which is one of the heat sources. When the second switching element 32 heats up, the heat diffuses to the surroundings through the surrounding resin. By bringing the second switching element 32 and the second chip pad 52 closer together, the amount of heat that can be conducted from the second switching element 32 to the second chip pad 52 can be increased. As described above, the second chip pad 52 can efficiently absorb heat. According to this structure, the path for releasing the heat generated during the operation of the second switching element 32 to the outside of the package 60 can be strengthened.

[0084] In particular, as in this embodiment, when each component constituting the semiconductor relay 100 is sealed with resin, the effect is significant because the resin has low thermal conductivity.

[0085] [Detailed structure of the first chip pad 51 and the second chip pad 52]

[0086] Figure 5A This is a perspective view of the semiconductor relay involved in the implementation method from a bottom view. Figure 5B This is a top perspective view of the semiconductor relay according to the embodiment. Hereinafter, using... Figure 5A And what follows Figure 6A , Figure 6B The structure of the first chip pad 51 and the second chip pad 52 is described in detail.

[0087] Figure 5A The dashed line B shown is the boundary between the first chip pad 51 and the first terminal 41. That is, for the chip pad 51 and the first terminal 41, the part that starts to thicken is the boundary between the chip pad 51 and the first terminal 41.

[0088] Figure 5A The dashed line C shown is the boundary between the second chip pad 52 and the second terminal 42. That is, for the second chip pad 52 and the second terminal 42, the part that begins to thicken is the boundary between the second chip pad 52 and the second terminal 42.

[0089] The longest length L1 of the first chip pad 51 in the front-back direction (first direction) is greater than the longest length L2 of the first terminal 41 in the front-back direction (first direction). According to this structure, compared to the case where the first chip pad 51 and the first terminal 41 have the same thickness or the first chip pad 51 is thinner than the first terminal 41, the first chip pad 51 can be set wider.

[0090] The longest length L3 of the second chip pad 52 in the front-to-back direction is greater than the longest length L2 of the second terminal 42 in the front-to-back direction. That is, the second chip pad 52 is thicker than the second terminal 42. According to this structure, compared to the case where the second chip pad 52 and the second terminal 42 have the same thickness or the second chip pad 52 is thinner than the second terminal 42, the second chip pad 52 can be made wider.

[0091] The shortest distance W1 in the front-to-back direction between the first chip pad 51 and the second chip pad 52 is shorter than the shortest distance W2 in the front-to-back direction between the first terminal 41 and the second terminal 42. As in this embodiment, when the light-emitting element 10 is located between the first chip pad 51 and the second chip pad 52, the first chip pad 51 and the second chip pad 52 can be positioned close to the light-emitting element 10, which is one of the heat sources. According to this structure, the first chip pad 51 and the second chip pad 52 can efficiently absorb the heat generated by the light-emitting element 10 and diffused to the surrounding area.

[0092] The first chip pad 51 protrudes rearward beyond the first terminal 41. That is, the first chip pad 51 protrudes towards the second chip pad 52. Furthermore, Figure 5A The first chip pad 51 shown protrudes into an empty area in the package 60, that is, an area where no component of the semiconductor relay 100 is disposed. According to this structure, space can be effectively utilized in the package 60, and the first chip pad 51 is made wide.

[0093] The second chip pad 52 protrudes forward from the second terminal 42. That is, the second chip pad 52 protrudes in a direction closer to the first chip pad 51. Figure 5A The second chip pad 52 shown protrudes into the aforementioned empty area in the package 60. According to this structure, space can be effectively utilized in the package 60, and the second chip pad 52 can be made wide.

[0094] like Figure 5A As shown, the first chip pad 51 has a wide portion 51a. The wide portion 51a is configured such that the length of the first chip pad 51 in the front-to-back direction increases as it extends from the boundary between the first terminal 41 and the first chip pad 51 towards the end of the first chip pad 51. According to this structure, space can be effectively utilized in the package 60, and the first chip pad 51 can be made wide. Here, the wide portion 51a includes not only the portion extending from the boundary between the first terminal 41 and the first chip pad 51 towards the end of the first chip pad 51, but also... Figure 5A The portion from dashed line B to dashed line D shown also includes the portion from dashed line D to the end. Furthermore, in the following description, the wide portion 51a may sometimes be referred to as the width variation portion 51a.

[0095] The second chip pad 52 has a wide portion 52a. The wide portion 52a is configured such that, in the region from the boundary between the second terminal 42 and the second chip pad 52 toward the end of the second chip pad 52, the length of the second chip pad 52 increases in the front-to-back direction. According to this structure, space can be effectively utilized in the package 60, and the second chip pad 52 can be made wide. Furthermore, in the following description, the wide portion 52a will sometimes be referred to as a width variation portion 52a.

[0096] Figure 6A This is a top view of the first chip pad involved in this embodiment. Figure 6A As shown, the length of the first chip pad 51 at the end of the first chip pad 51 in the front-back direction is the longest length L1 of the first chip pad 51 in the front-back direction. The rectangular portion protruding in the front-back direction in the wide portion 51a is referred to as the protruding portion 51b.

[0097] Figure 6B This is a top view of the second chip pad involved in this embodiment. (Example) Figure 6B As shown, the length of the second chip pad 52 at its end in the front-to-back direction is the longest length L3 of the second chip pad 52 in the front-to-back direction. The rectangular portion of the second chip pad 52 that protrudes in the front-to-back direction is referred to as the protrusion portion 52b.

[0098] Furthermore, the shape of the first chip pad 51 is not particularly limited to Figure 1E , Figure 2 as well as Figure 5A The shape shown could also be, for example, Figure 6C , Figure 6D The shape shown.

[0099] Figure 6C This is a top view showing another example of the first chip pad 51. Figure 6A In the first chip pad 51, the length of the first chip pad 51 at its end in the front-to-back direction is the longest length L1 of the first chip pad 51 in the front-to-back direction. On the other hand, in Figure 6C In the first chip pad 151 shown, the length L4 of the first chip pad 151 at the end of the first chip pad 151 in the front-back direction is not the longest length L1 of the first chip pad 151 in the front-back direction. Figure 6C The wide portion 151a shown can also be represented as a protruding portion 151b that protrudes in the front-back or left-right direction.

[0100] Figure 6D This is a top view showing another example of the first chip pad. Figure 6D The width of the first chip pad 151 shown is different in stages in the front-to-back direction. Figure 6D The multiple wide portions 151a shown can be represented as multiple protruding portions 151b protruding along the front-back direction or the left-right direction. Figure 6D In the example shown, the length L5 of the first chip pad 151 at the right end of the first chip pad 151 in the front-back direction is shorter than the length L6 of the first chip pad 151 at the left end in the front-back direction. In addition, the length L6 is also shorter than the longest length L1 of the first chip pad 151 in the front-back direction.

[0101] Preferably, the first chip pad 51 (151) is kept at an insulating distance from surrounding components and is set to be as wide as possible. The wider the first chip pad 51 (151), the better the heat dissipation of the semiconductor relay 100. The reasons for this are explained in detail below.

[0102] By making the first chip pad 51 wider, compared to a narrower case, the surface area and volume of the metal-made first chip pad 51 can be increased inside the package 60. Therefore, the first chip pad 51 can efficiently absorb heat from inside the package 60. The heat absorbed by the first chip pad 51 is released to the outside of the package 60 through the first terminal 41. The first chip pad 51 absorbs more heat and conducts it further to the first terminal 41, thereby increasing the heat that can be released to the outside of the package 60 through the first terminal 41. Therefore, by making the first chip pad 51 wider, heat dissipation can be improved compared to a narrower case.

[0103] Furthermore, it is preferable that the second chip pad 52 maintains an insulating distance from surrounding components, and that this insulating distance is set to be as wide as possible. The wider the second chip pad 52, the better the heat dissipation of the semiconductor relay 100. The reasons for this are explained in detail below.

[0104] By making the second chip pad 52 wider, the surface area and volume of the metal inside the package 60 can be increased compared to a narrow second chip pad 52. Therefore, the second chip pad 52 can efficiently absorb heat from inside the package 60. The heat absorbed by the second chip pad 52 is released to the outside of the package 60 through the second terminal 42. The second chip pad 52 absorbs more heat and conducts it further to the second terminal 42, thereby increasing the heat released to the outside of the package 60 through the second terminal 42. Therefore, by making the second chip pad 52 wider, heat dissipation can be improved compared to a narrow second chip pad 52.

[0105] Figure 7A This is a top view of the first chip pad and the first switching element. Figure 7B This is a top view of the second chip pad and the second switching element. (Example) Figure 7A , Figure 7B As shown, when viewed from above, the area where the first chip pad 51 overlaps with the first switching element 31 is different from the area where the second chip pad 52 overlaps with the second switching element 32. Furthermore, the shape of the first chip pad 51 differs from the shape of the second chip pad 52. This structure allows for differences in the heat dissipation efficiency of the first chip pad 51 and the second chip pad 52.

[0106] For example, in this embodiment, the area where the first chip pad 51 overlaps with the first switching element 31 is smaller than the area where the second chip pad 52 overlaps with the second switching element 32. Therefore, the second chip pad 52 can absorb more heat than the first chip pad 51. Consequently, the temperature of the first switching element 31 facing the first chip pad 51 in the vertical direction is lower than the temperature of the first switching element 31 facing the first chip pad 51 in the vertical direction. According to this structure, when mounted on an external mounting substrate 500, a component with weaker heat resistance can be placed in front of the package 60.

[0107] [Structure of terminals 41-46]

[0108] like Figures 1A-2 As shown, terminals 41-46 are arranged along the first direction in the order of terminal 41, terminal 43, terminal 45, terminal 44, terminal 42, and terminal 46. Furthermore, according to... Figure 1A , 1E as well as Figure 2 As can be seen, terminals 41-46 are bent downwards inside the package 60, extend to the left, and are exposed outside the package 60. Furthermore, they extend downwards along the outer surface of the package 60. They are further bent to the left. In this embodiment, terminals 41-46 have the same shape after being bent downwards inside the package 60. The structure of terminals 41 and 42 will be described below.

[0109] Figure 8A This is a top view of the first terminal according to the first embodiment. Figure 8B This is a side view of the first terminal according to the first embodiment. (Example) Figure 1B , Figure 8A as well as Figure 8B As shown, the first terminal 41 is composed of a first front end portion 41a, a first middle portion 41b, and a first connecting portion 41c.

[0110] In addition, "front end portion 41a" is sometimes referred to as "first front end portion 41a", "middle portion 41b" is referred to as "first middle portion 41b", and "connecting portion 41c" is referred to as "first connecting portion 41c".

[0111] like Figures 1A-1D As shown, the first terminal 41 is mounted to the external mounting substrate 500 via a first front portion 41a. The first front portion 41a is the portion of the first terminal 41 that is exposed outside the package 60 and extends parallel to the lower surface of the package 60. The first intermediate portion 41b is the portion connected to the first front portion 41a and exposed outside the package 60. The first connecting portion 41c is the portion that connects the first intermediate portion 41b to the first chip pad 51 and is located inside the package 60.

[0112] Figure 9A This is a top view of the first terminal involved in the comparative example. Figure 9B This is a side view of the first terminal involved in the comparative example. Hereinafter, the shape of the first terminal 41 in this embodiment will be compared with the first terminal 141 of the comparative example and described in detail.

[0113] like Figure 8A As shown, in the first terminal 41, the shortest length D1 of the first connecting portion 41c in the front-rear direction is greater than the longest length D2 of the first front end portion 41a in the front-rear direction. Conversely, as... Figure 9A As shown, in the first terminal 141, the shortest length D11 of the first connecting portion 141c is equal to the longest length D12 of the first front end portion 141a in the front-rear direction. The lengths D2 and D12 of the first front end portion 41a and the first front end portion 141a in the front-rear direction correspond to the lengths of the pads of the external mounting substrate 500 in the front-rear direction, and the lengths D2 and D12 are equal.

[0114] That is, on the outside of the package 60, the first terminal 41 can improve heat dissipation compared to the first terminal 141.

[0115] Hereinafter, the heat dissipation performance of the first connection portion 41c of this disclosure will be described in more detail by comparing it with the first connection portion 141c of the comparative example.

[0116] The surface area of ​​the first connection portion 41c inside the package 60 in this disclosure is larger than that of the first connection portion 141c in the comparative example. Therefore, the first connection portion 41c of this disclosure can absorb heat inside the package 60 more efficiently than the first connection portion 141c of the comparative example. Because the first connection portion 41c absorbs more heat, the amount of heat that can be released to the outside of the package 60 is increased.

[0117] Furthermore, the volume of the first connection portion 41c inside the package 60 in this disclosure is larger than that of the first connection portion 141c in the comparative example. Therefore, the first connection portion 41c of this disclosure can have higher thermal conductivity than the first connection portion 141c of the comparative example. The heat absorbed by the first chip pad 51 is conducted through the first connection portion 41c to the first intermediate portion 41b exposed outside the package 60. Additionally, the heat absorbed by the first connection portion 41c is conducted to the first intermediate portion 41b exposed outside the package 60. Because the first connection portion 41c absorbs more heat and further conducts it to the first intermediate portion 41b exposed outside the package 60, the amount of heat that can be released to the outside of the package 60 is increased. Based on the above, the first connection portion 41c of this disclosure can improve heat dissipation compared to the first connection portion 141c of the comparative example.

[0118] like Figure 8B As shown, the shortest length D3 of the first intermediate portion 41b is greater than the longest length D2 of the first front portion 41a in the front-rear direction. Conversely, as... Figure 9B As shown, the shortest length D13 of the first intermediate portion 141b is equal to the longest length D12 of the first front end portion 141a in the front-rear direction. According to this structure, the first terminal 41 can improve heat dissipation compared to the first terminal 141.

[0119] The heat dissipation properties of the first intermediate portion 41b of this disclosure will be described in more detail below by comparing it with the first intermediate portion 141b of the comparative example.

[0120] Figure 8B The surface area of ​​the first intermediate portion 41b shown in this disclosure is greater than that of the first intermediate portion 41b. Figure 9B The comparative example shown has a larger surface area for the first intermediate portion 141b. In other words, the area of ​​the first intermediate portion 41b of this disclosure in contact with the external atmosphere is larger than that of the first intermediate portion 141b in the comparative example. Therefore, heat can be efficiently released from the first intermediate portion 41b to the external atmosphere.

[0121] Furthermore, the volume of the first intermediate portion 41b of this disclosure within the package 60 is larger than that of the first intermediate portion 141b of the comparative example. Therefore, the first intermediate portion 41b of this disclosure has higher thermal conductivity than the first intermediate portion 141b of the comparative example. Heat absorbed by the first chip pad 51 is conducted to the first intermediate portion 41b through the first connection portion 41c. Additionally, heat absorbed by the first connection portion 41c is conducted to the first intermediate portion 41b. Because the first intermediate portion 41b conducts more heat, the amount of heat that can be released to the outside of the package 60 increases. Therefore, the first intermediate portion 41b of this disclosure has improved heat dissipation compared to the first intermediate portion 141b of the comparative example.

[0122] like Figure 1B , Figure 8A as well as Figure 8B As shown, the second terminal 42 is composed of a second front end portion 42a, a middle portion 42b, and a connecting portion 42c.

[0123] In addition, "front end portion 42a" is sometimes referred to as "second front end portion 42a", "middle portion 42b" is referred to as "second middle portion 42b", and "connecting portion 42c" is referred to as "second connecting portion 42c".

[0124] like Figures 1A-1DAs shown, the second terminal 42 is mounted to the external mounting substrate 500 via a second front portion 42a. The second front portion 42a is the portion of the second terminal 42 that is exposed outside the package 60 and extends parallel to the lower surface of the package 60. The second middle portion 42b is the portion connected to the second front portion 42a and exposed outside the package 60. The second connecting portion 42c is the portion that connects the second middle portion 42b to the second chip pad 52 and is located inside the package 60.

[0125] Furthermore, the structure of the second terminal 42 is the same as that of the reference. Figure 8A and Figure 8B The first terminal 41 described has the same structure.

[0126] In the second terminal 42, the shortest length D1 of the second connecting portion 42c in the front-rear direction is greater than the longest length D2 of the second front end portion 42a in the front-rear direction. As described with respect to the first terminal 41, according to this structure, the second terminal 42 can improve heat dissipation.

[0127] The shortest length D3 of the second intermediate portion 42b in the front-rear direction is greater than the longest length D2 of the second front portion 42a in the front-rear direction. As described with respect to the first terminal 41, according to this structure, the second terminal 42 is able to improve heat dissipation.

[0128] [Structure of the seventh terminal 47 and the eighth terminal 48]

[0129] As described above, the first switching element 31 and the second switching element 32 generate heat. Additionally, as... Figure 1E , Figure 2 As shown, the first switching element 31 is mounted on the third chip pad 53, and the second switching element 32 is mounted on the fourth chip pad 54. The third chip pad is connected to the seventh terminal 47, and the fourth chip pad 54 is connected to the eighth terminal 48. According to this structure, the heat generated by the first switching element 31 and the second switching element 32 can also be released from the seventh terminal 47 and the eighth terminal 48 to the outside of the package 60. Figure 1C , Figure 5B As shown, the seventh terminal 47 is composed of a seventh front end portion 47a, a seventh middle portion 47b, and a seventh connecting portion 47c.

[0130] Furthermore, the "seventh terminal 47" in the implementation method is equivalent to the "third terminal" in the instruction manual, and the "eighth terminal 48" in the implementation method is equivalent to the "fourth terminal" in the instruction manual.

[0131] In addition, the "seventh front part 47a", "seventh middle part 47b" and "seventh connecting part 47c" in the embodiment are respectively equivalent to the "third front part", "third middle part" and "third connecting part" in the specification.

[0132] Furthermore, in the embodiments, "eighth front end portion 48a", "eighth middle portion 48b" and "eighth connecting portion 48c" are respectively equivalent to "fourth front end portion", "fourth middle portion" and "fourth connecting portion" in the specification.

[0133] like Figures 1A-1D As shown, the seventh terminal 47 is mounted to the external mounting substrate 500 via the seventh front portion 47a. The seventh front portion 47a is the portion exposed on the outside of the package 60 and extends parallel to the lower surface of the package 60. The seventh middle portion 47b is the portion connected to the seventh front portion 47a and exposed on the outside of the package 60. The seventh connecting portion 47c is the portion that connects the seventh middle portion 47b to the third chip pad 53 and is located inside the package 60.

[0134] like Figure 5B As shown, the shortest length D1 of the seventh connecting portion 47c in the front-rear direction is greater than the longest length D2 of the seventh front end portion 47a in the front-rear direction. As described with respect to the first terminal 41, according to this structure, the seventh terminal 47 can improve heat dissipation in the same way as the first terminal 41.

[0135] like Figure 1C As shown, the shortest length D3 of the seventh middle portion 47b in the front-rear direction is greater than the longest length D2 of the seventh front portion 47a in the front-rear direction. As described with respect to the first terminal 41, according to this structure, the seventh terminal 47 can improve heat dissipation.

[0136] like Figure 1C , Figure 5B As shown, the eighth terminal 48 is composed of an eighth front end portion 48a, an eighth middle portion 48b, and an eighth connecting portion 48c.

[0137] like Figures 1A-1D As shown, the eighth terminal 48 is mounted to the external mounting substrate 500 via the eighth front portion 48a. The eighth front portion 48a is the portion exposed on the outside of the package 60 and extending parallel to the lower surface of the package 60. The eighth middle portion 48b is the portion connected to the eighth front portion 48a and exposed on the outside of the package 60. The eighth connecting portion 48c is the portion that connects the eighth middle portion 48b to the fourth chip pad 54 and is located inside the package 60.

[0138] like Figure 5B As shown, the shortest length D1 of the eighth connecting portion 48c in the front-rear direction is greater than the longest length D2 of the eighth front end portion 48a in the front-rear direction. As described with respect to the first terminal 41, according to this structure, the eighth terminal 48 can improve heat dissipation.

[0139] like Figure 1CAs shown, the shortest length D3 of the eighth intermediate portion 48b in the front-rear direction is greater than the longest length D2 of the eighth front portion 48a in the front-rear direction. As described with respect to the first terminal 41, according to this structure, the eighth terminal 48 can improve heat dissipation.

[0140] In addition, such as Figure 1B As shown, the lower portion of the middle section 41b~46c widens to both sides in the front-to-back direction, and in contrast, as Figure 1C As shown, the lower portions of the seventh intermediate portion 47b and the eighth intermediate portion 48b widen only on one side in the front-back direction. Specifically, the lower portion of the seventh intermediate portion 47b widens rearward toward the side away from the eighth intermediate portion 48b. Conversely, the lower portion of the eighth intermediate portion 48b widens forward toward the side away from the seventh intermediate portion 47b.

[0141] To ensure sufficient insulation between the first switching element 31 and the second switching element 32, the creepage distance needs to be sufficiently large. Here, creepage distance refers to the shortest distance along the surface of the insulator located between two conductors. In the semiconductor relay 100, the discharge effect on the surface of the resin-made package 60 is significant. Therefore, the creepage distance W3 on the output side of the semiconductor relay 100 (refer to...) Figure 1C , Figure 5B This is equivalent to the shortest distance in the front-to-back direction between the seventh terminal 47 and the eighth terminal 48.

[0142] Because the pads 502a are evenly spaced in the front-to-back direction, the positions of the seventh front end portion 47a and the eighth front end portion 48a cannot be changed. Therefore, as Figure 1C As shown, by widening the lower portions of the seventh intermediate portion 47b and the eighth intermediate portion 48b only on the sides that are far apart from each other, the shortest distance in the front-rear direction between the seventh front end portion 47a and the eighth front end portion 48a can be made the same as the creepage distance W3. This suppresses the creepage distance W3 from becoming shorter, ensuring the insulation between the seventh terminal 47 and the eighth terminal 48, and further ensuring the insulation between the first switching element 31 and the second switching element 32.

[0143] In this embodiment, the semiconductor relay 100 is surface-mounted onto the external mounting substrate 500. Specifically, the front portions 41a to 48a extend along the exterior of the package 60, and the lower surface of the package 60 extends parallel to this lower surface, and are surface-mounted onto the external mounting substrate 500. Furthermore, to ensure the creepage distance W3, the shapes of the seventh terminal 47 and the eighth terminal 48 are specified in greater detail. Figure 10A yes Figure 1C An enlarged view of the portion enclosed by the dashed line XA. Figure 10B yes Figure 1C An enlarged view of the portion enclosed by the dashed line XB.

[0144] like Figure 10A As shown, at the seventh front end 47a of the seventh terminal 47, the side facing the eighth terminal 48 is referred to as the first surface 47a1, and the side facing the first surface 47a1 in the front-rear direction is referred to as the second surface 47a2.

[0145] Furthermore, the seventh intermediate portion 47b of the seventh terminal 47 is composed of multiple parts corresponding to its shape. Specifically, the seventh intermediate portion 47b is composed of a first portion 47ba, a second portion 47bb, and a third portion 47bc. The first portion 47ba is connected to the seventh connecting portion 47c, the second portion 47bb extends downward from the first portion 47ba, and the third portion 47bc extends downward from the second portion 47bb and is connected to the seventh front portion 47a. Figure 10A As shown, the length of the third part 47bc in the front-back direction is equivalent to the shortest length D3 of the seventh middle part 47b. In addition, in the third part 47bc, the side facing the eighth terminal 48 in the front-back direction is referred to as the third surface 47bc3, and the side facing the third surface 47bc3 is referred to as the fourth surface 47bc4.

[0146] Similarly, in the first part 47ba and the second part 47bb, the side facing the eighth terminal 48 in the front-rear direction is referred to as the third side 47ba3 and 47bb3, and the side facing the third side 47ba3 and 47bb3 is referred to as the fourth side 47ba4 and 47bb4.

[0147] In addition, such as Figure 10B As shown, in the eighth front end portion 48a of the eighth terminal 48, the side facing the seventh terminal 47 is referred to as the fifth surface 48a1, and the side facing the fifth surface 48a1 in the front-rear direction is referred to as the sixth surface 48a2.

[0148] Furthermore, the eighth intermediate portion 48b of the eighth terminal 48 is composed of multiple parts corresponding to its shape. Specifically, the eighth intermediate portion 48b is composed of a fourth portion 48ba, a fifth portion 48bb, and a sixth portion 48bc. The fourth portion 48ba is connected to the eighth connecting portion 48c, the fifth portion 48bb extends downward from the fourth portion 48ba, and the sixth portion 48bc extends downward from the fifth portion 48bb and is connected to the eighth front portion 48a. Figure 10BAs shown, the length of the sixth part 48bc in the front-back direction is equivalent to the shortest length D3 of the eighth middle part 48b. In addition, in the sixth part 48bc, the side facing the seventh terminal 47 in the front-back direction is called the seventh surface 48bc3, and the side facing the seventh surface 48bc3 is called the eighth surface 48bc4.

[0149] Similarly, in the fourth part 48ba and the fifth part 48bb, the side facing the eighth terminal 48 in the front-back direction is referred to as the seventh side 48ba3 and 48bb3, and the side facing the seventh side 48ba3 and 48bb3 is referred to as the eighth side 48ba4 and 48bb4.

[0150] like Figure 10A As shown, in the seventh terminal 47, the distance from the first portion 47ba along the vertical center line (i.e., the first axis A1) to the eighth terminal 48 in the front-to-back direction is greater than the distance from the seventh front portion 47a along the vertical center line (i.e., the second axis A2) to the eighth terminal 48. Therefore, the distance between the seventh middle portion 47b and the eighth terminal 48 in the front-to-back direction is not shorter than the distance between the seventh front portion 47a and the eighth terminal 48 in the front-to-back direction, thus ensuring the aforementioned creepage distance W3.

[0151] Furthermore, the shape of the seventh terminal 47 is designed such that the first surface 47a1 of the seventh front end portion 47a is flush with the third surface 47bc3 of the third portion 47bc of the seventh middle portion 47b. In this way, near the external mounting substrate 500, the distance between the seventh middle portion 47b and the eighth terminal 48 in the front-rear direction can be the same as the distance between the seventh front end portion 47a and the eighth terminal 48 in the front-rear direction, thus ensuring the aforementioned creepage distance W3.

[0152] In addition, such as Figure 10B As shown, in the eighth terminal 48, the distance from the seventh terminal 47 along the center line (third axis A3) of the fourth portion 48ba in the vertical direction is greater than the distance from the seventh terminal 47 along the center line (fourth axis A4) of the eighth front portion 48a in the vertical direction. Therefore, the distance between the eighth middle portion 48b and the seventh terminal 47 in the vertical direction is not shorter than the distance between the eighth front portion 48a and the seventh terminal 47 in the vertical direction, thus ensuring the aforementioned creepage distance W3.

[0153] Furthermore, the shape of the eighth terminal 48 is designed such that the fifth surface 48a1 of the eighth front end portion 48a is flush with the seventh surface 48bc3 of the sixth portion 48bc of the eighth middle portion 48b. Therefore, near the external mounting substrate 500, the distance between the eighth middle portion 48b and the seventh terminal 47 in the front-rear direction is the same as the distance between the eighth front end portion 48a and the seventh terminal 47 in the front-rear direction, ensuring the aforementioned creepage distance W3.

[0154] <First Variation>

[0155] Figure 11A It is the first variation involved, Figure 10A The corresponding diagram. Figure 11B It is the first variation involved, Figure 10B The corresponding diagram. Furthermore, in Figure 11A , 11B In the accompanying drawings shown thereafter, the same reference numerals are used for the same parts as in the first embodiment, and detailed descriptions are omitted.

[0156] and Figure 10A The difference between the semiconductor relay 100 of the first embodiment shown is that, Figure 11A The third surface 47ba3 of the first portion 47ba, the third surface 47bb3 of the second portion 47bb, and the third surface 47bc3 of the third portion 47bc of the seventh terminal 47 shown are flush. Additionally, with... Figure 10A The difference between the semiconductor relay 100 of the first embodiment shown is that, in Figure 11A In the seventh intermediate portion 47b of the seventh terminal 47 shown, the fourth surface 47ba4 of the first portion 47ba, the fourth surface 47bb4 of the second portion 47bb, and the 47bc4 of the third portion 47bc are flush.

[0157] That is, the first part 47ba, the second part 47bb, and the third part 47bc can be regarded as a single component having a common third surface 47bb3 and a fourth surface 47bb4. In this modified example, the seventh intermediate part 47b is also referred to as the seventh intermediate part 47bb. In addition, when viewed from the left and right direction, the third surface 47bb3 of the seventh intermediate part 47bb is flush with the first surface 47a1 of the seventh front part 47a.

[0158] In addition, with Figure 10A The difference between the semiconductor relay 100 of the first embodiment shown is that, in Figure 11B In the eighth intermediate portion 48b of the eighth terminal 48 shown, the seventh surface 48ba3 of the fourth portion 48ba, the seventh surface 48bb3 of the fifth portion 48bb, and the seventh surface 48bc3 of the sixth portion 48bc are flush with each other. Figure 10BThe difference between the semiconductor relay 100 of the first embodiment shown is that, in Figure 11B In the eighth intermediate portion 48b of the eighth terminal 48 shown, the eighth surface 48ba4 of the fourth portion 48ba, the eighth surface 48bb4 of the fifth portion 48bb, and the eighth surface 48bc4 of the sixth portion 48bc are flush.

[0159] That is, the fourth part 48ba, the fifth part 48bb, and the sixth part 48bc can be regarded as a single component having a common seventh surface 48bb3 and an eighth surface 48bb4. In this modified example, the eighth intermediate part 48b is also referred to as the eighth intermediate part 48bb. In addition, when viewed from the left and right direction, the seventh surface 48bb3 of the eighth intermediate part 48bb is flush with the fifth surface 48a1 of the eighth front part 48a.

[0160] By arranging the seventh intermediate portion 47b and the eighth intermediate portion 48b in this way, the distance between the seventh terminal 47 and the eighth terminal 48 in the front-rear direction can be made the same throughout the entire exposed portion of the package 60, thus sufficiently ensuring the aforementioned creepage distance W3. Furthermore, according to this modified example, the spatial insulation distance between the seventh terminal 47 and the eighth terminal 48 can be ensured.

[0161] <Second Variation>

[0162] Figure 12A This is a three-dimensional view of the semiconductor relay involved in the modified example. Additionally, Figure 12B This is a side view of the semiconductor relay involved in the variation example.

[0163] As shown in this variation, the semiconductor relay 200 can also be an insert-mount type, inserted and mounted on an external mounting substrate 500. In this variation, the front portions 41a to 48a extend outside the package 60 along the side of the package 60 in a manner parallel to the side. Furthermore, although not shown, in the semiconductor relay 200 of this variation, the internal structure of the package 60 is the same as that shown in the first embodiment.

[0164] According to this modification, the same effect as that achieved by the structure shown in the first embodiment can be achieved. That is, by providing the first chip pad 51 and the second chip pad 52, the heat generated by the first switching element 31, the second switching element 32, and the light-emitting element 10 during the operation of the semiconductor relay 200 can be efficiently absorbed and conducted to the outside of the package 60. In other words, heat dissipation is improved by strengthening the path for releasing the heat generated during the operation of the semiconductor relay 200 to the outside of the package 60.

[0165] Furthermore, generally speaking, surface-mount components have a larger contact area with the external mounting substrate 500 and better heat dissipation compared to insert-mount components. Therefore, the insert-mount type semiconductor relay 200 shown in this modified example has reduced heat dissipation compared to the semiconductor relay 100 of the first embodiment.

[0166] (Second Implementation)

[0167] Figure 13 This is a perspective view of the semiconductor relay according to the second embodiment, omitting the package.

[0168] The first terminal 341 and the second terminal 342 of the semiconductor relay 300 in the second embodiment are different from the first terminal 41 and the second terminal 42 of the semiconductor relay 100 in the first embodiment. Apart from this, the appearance of the semiconductor relay 300, including the package 60, as well as the structure and arrangement of the components inside the package 60, are the same as those of the semiconductor relay 100.

[0169] like Figure 13 As shown, the first terminal 341 extends from the middle portion of the package 60 in the vertical direction to the outside of the package 60 and bends, extends downward along the side of the package 60 and bends further, and extends along the lower surface of the package 60 in a manner substantially parallel to the lower surface. Furthermore, the first terminal 341 does not bend inside the package 60 and extends in a manner substantially parallel to the upper surface of the package 60. The second terminal 342 also has the same shape as the first terminal 341.

[0170] In this embodiment, compared to the case shown in the first embodiment, the distance between the first chip pad 51 and the third chip pad 53 is shorter than the distance between the fifth chip pad 55 and the sixth chip pad 56. Furthermore, the distance between the second chip pad 52 and the fourth chip pad 54 is shorter than the distance between the fifth chip pad 55 and the sixth chip pad 56.

[0171] According to this structure, the distance between the first switching element 31 and the first chip pad 51 is shorter than that in the first embodiment. When the first switching element 31 heats up, the heat diffuses to the surroundings through the surrounding resin. By bringing the distance between the first switching element 31 and the first chip pad 51 closer, the amount of heat that can be conducted from the first switching element 31 to the first chip pad 51 can be increased. In particular, since the components constituting the semiconductor relay 300 are sealed with resin, the thermal conductivity of the resin is low, so this effect is significant. As described above, in this embodiment, compared to the case shown in the first embodiment, the first chip pad 51 can absorb the heat generated by the first switching element 31 more efficiently and can conduct it to the outside of the package 60 through the first terminal 341.

[0172] Furthermore, in this embodiment, the distance between the second switching element 32 and the second chip pad 52 is shorter than that in the first embodiment. When the second switching element 32 heats up, the heat diffuses to the surroundings through the surrounding resin. By bringing the distance between the second switching element 32 and the second chip pad 52 closer, the amount of heat that can be conducted from the second switching element 32 to the second chip pad 52 can be increased. In particular, this effect is significant when the components constituting the semiconductor relay 300 are sealed with resin, as the resin has low thermal conductivity. As described above, in this embodiment, compared to the first embodiment, the second chip pad 52 can absorb the heat generated by the first switching element 31 more efficiently and can conduct it to the outside of the package 60 through the second terminal 342.

[0173] Based on these circumstances, the path for releasing the heat generated during the operation of the semiconductor relay 300 to the outside of the package 60 can be further enhanced to improve heat dissipation.

[0174] In addition, terminals 43 to 46 may also extend inside the package 60 without bending, and in a manner parallel to the upper surface of the package 60, just like terminal 341.

[0175] (Summarize)

[0176] The semiconductor relay 100 disclosed herein has the structure shown below.

[0177] The semiconductor relay 100 of the first embodiment includes at least: a light-emitting element 10; a light-receiving element 20 located below and facing the light-emitting element 10; a first switching element 31 adjacent to the light-receiving element 20; and a second switching element 32 adjacent to the light-receiving element 20. Additionally, the semiconductor relay 100 includes: a first chip pad 51 located above the first switching element 31; a second chip pad 52 located above the second switching element 32; a first terminal 41, one end of which is connected to the first chip pad 51; a second terminal 42, one end of which is connected to the second chip pad 52; and a package 60.

[0178] The light-receiving element 20 is located between the first switching element 31 and the second switching element 32. The first terminal 41 and the second terminal 42 are arranged in a first direction, with one end of the first terminal 41 exposed outside the package 60 and extending downward from the package 60, and the other end of the second terminal 42 exposed outside the package 60 and extending downward from the package 60. The light-emitting element 10, the light-receiving element 20, the first switching element 31, the second switching element 32, the first chip pad 51, and the second chip pad 52 are located inside the package 60. When viewed from above, at least a portion of the first chip pad 51 overlaps with the first switching element 31, and at least a portion of the second chip pad 52 overlaps with the second switching element 32.

[0179] In the second type of semiconductor relay 100, the longest length L1 of the first chip pad 51 in the first direction is greater than the longest length L2 of the first terminal 41 in the first direction, and the longest length L3 of the second chip pad 52 in the first direction is greater than the longest length L2 of the second terminal 42 in the first direction.

[0180] In the third-party semiconductor relay 100, the shortest distance W1 between the first chip pad 51 and the second chip pad in a first direction is shorter than the shortest distance W2 between the first terminal 41 and the second terminal 42 in the first direction.

[0181] In the semiconductor relay 100 of the fourth type, the first chip pad 51 has a wide portion (width variation portion) 51a, which is configured such that the length of the first chip pad 51 in the first direction increases as it moves from the boundary between the first terminal 41 and the first chip pad to the end of the first chip pad 51.

[0182] In the semiconductor relay 100 of the fifth type, when the direction in which each terminal of the first terminal 41 and the second terminal 42 protrudes, which is orthogonal to the first direction, is set as the second direction (left-right direction), the first chip pad 51 has a protrusion protruding in the first direction or the second direction.

[0183] In the semiconductor relay 100 of the sixth type, when viewed from above, the area where the first chip pad 51 overlaps with the first switching element 31 is different from the area where the second chip pad 52 overlaps with the second switching element 32.

[0184] In the semiconductor relay 100 of the seventh embodiment, the first terminal 41 is composed of a first front portion 41a, a first intermediate portion 41b, and a first connecting portion 41c. The first front portion 41a is connected to the first front portion 41a and exposed outside the package 60. The first intermediate portion 41b is connected to the first chip pad 51 and located inside the package 60. The shortest length D1 of the first connecting portion 41c in the first direction is greater than the longest length D2 of the first front portion 41a in the first direction. The second terminal 42 is composed of a second front portion 42a, a second intermediate portion 42b, and a second connecting portion 42c. The second intermediate portion 42b is connected to the second front portion 42a and exposed outside the package 60. The second connecting portion 42c is connected to the second chip pad 52 and located inside the package 60. The shortest length D1 of the second connecting portion 42c in the first direction is greater than the longest length D2 of the second front portion 42a in the first direction.

[0185] In the semiconductor relay 100 of the eighth type, the shortest length D3 of the first intermediate portion 41b in the first direction is greater than the longest length D2 of the first front portion 41a in the first direction, and the shortest length D3 of the second intermediate portion 42b in the first direction is greater than the longest length D2 of the second front portion 42a in the first direction.

[0186] The ninth type of semiconductor relay 100 further includes: a third chip pad 53 on which a first switching element 31 is disposed; a fourth chip pad 54 on which a second switching element 32 is disposed; a terminal 47, one end of which is connected to the third chip pad 53; and a terminal 48, one end of which is connected to the fourth chip pad 54. The terminal 47 is composed of a front portion 47a, a middle portion 47b, and a connecting portion 47c. The middle portion 47b is connected to the front portion 47a and is exposed outside the package 60. The connecting portion 47c connects the middle portion 47b to the first chip pad 51 and is located inside the package 60. The shortest length D1 of the connecting portion 47c in the first direction is greater than the longest length D2 of the front portion 47a in the first direction. Terminal 48 is composed of a front portion 48a, a middle portion 48b, and a connecting portion 48c. The middle portion 48b is connected to the front portion 48a and is exposed on the outside of the package 60. The connecting portion 48c connects the middle portion 48b to the second chip pad 52 and is located inside the package 60. The shortest length D1 of the connecting portion 48c in the first direction is greater than the longest length D2 of the front portion 48a in the first direction.

[0187] In the semiconductor relay 100 of the tenth method, the shortest length D3 of the middle portion 47b in the first direction is greater than the longest length D2 of the front portion 47a in the first direction, and the shortest length D3 of the middle portion 48b in the first direction is greater than the longest length D2 of the front portion 48a in the first direction.

[0188] The creepage distance W3 between the intermediate portion 47b and the intermediate portion 48b in the first direction is equal to the shortest distance between the front portion 47a and the front portion 48a in the first direction.

[0189] The semiconductor relay 200 is an insertion-mount type, in which the front ends 41a to 48a extend parallel to the side of the package 60 outside the package 60 and are inserted into the external mounting substrate 500. Apart from this, the structure of the semiconductor relay 200 is the same as that of the semiconductor relay 100.

[0190] The semiconductor relay 300 includes: a fifth chip pad 55 having a lower surface, wherein a light-emitting element 10 is disposed on the lower surface of the fifth chip pad 55; and a sixth chip pad 56 having an upper surface, wherein a light-receiving element 20 is disposed on the upper surface of the sixth chip pad 56.

[0191] Except for the points shown below, the structure of semiconductor relay 300 is the same as that of semiconductor relay 100. In semiconductor relay 300, the distance between the first chip pad 51 and the third chip pad 53 is shorter than the distance between the fifth chip pad 55 and the sixth chip pad 56, and the distance between the second chip pad 52 and the fourth chip pad 54 is shorter than the distance between the fifth chip pad 55 and the sixth chip pad 56.

[0192] Semiconductor relays 100, 200, and 300 can enhance heat dissipation by strengthening the path used to release heat generated during operation to the outside of the package 60.

[0193] Furthermore, while this application specification uses optocoupled semiconductor relays 100, 200, and 300 as examples, it is not specifically limited to these. The shapes and positional relationships of the first chip pad 51 to the sixth chip pad 56 and the terminals 41 to 48 can also be applied to magnetically coupled and capacitively coupled semiconductor relays. In this case, the heat dissipation of the semiconductor relay can be improved by strengthening the path for releasing heat generated during operation to the outside of the package 60.

[0194] Industrial availability

[0195] The semiconductor relay disclosed herein is useful for improving heat dissipation by enhancing the path used to release heat generated during operation to the outside of the package.

[0196] Explanation of reference numerals in the attached figures

[0197] 10: Light-emitting element; 20: Light-receiving element; 21: Photodiode array; 22: Control circuit; 31: First switching element; 32: Second switching element; 41: Terminal (first terminal); 41a: Front end (first front end); 41b: Middle part (first middle part); 41c: Connecting part (first connecting part); 42: Terminal (second terminal); 42a: Front end (second front end); 42b: Middle part (second middle part); 42c: Connecting part (second connecting part); 43: Terminal; 44: Terminal; 45: Terminal; 46: Terminal; 47: Terminal (third terminal in the instruction manual); 47a: Front end (third front end in the instruction manual); 47a1: First surface; 47a2: Second surface; 47b: Middle part (third middle part in the instruction manual); 47ba: First section; 47ba3: Third surface; 47ba4: Fourth surface; 47bb: Second section; 47bb3: Third surface; 47bb4: Fourth surface; 47bc: Third section; 47bc3: Third surface; 47bc4: Fourth surface; 47c: Connecting part (third connecting part in the instruction manual); 48: Terminal (fourth terminal in the instruction manual); 48a: Front end (fourth front end in the instruction manual); 48a1: Fifth surface; 48a2: Sixth surface; 48b: Middle part (fourth middle part in the instruction manual); 48ba: Fourth part; 48ba3: Seventh surface; 48ba4: Eighth surface; 48bb: Fifth part; 48bb3: Seventh surface; 48bb4: Eighth surface; 48bc: Sixth part; 48bc3: Seventh surface; 48bc4: Eighth surface; 48c: Connecting part (fourth connecting part in the instruction manual); 51, 151: First Chip pads; 51a, 151a: Wide portion (width variation section); 51b, 151b: Protrusion portion; 52: Second chip pad; 53: Third chip pad; 54: Fourth chip pad; 55: Fifth chip pad; 56: Sixth chip pad; 60: Package; 100: Semiconductor relay; 200: Semiconductor relay; 300: Semiconductor relay; 341: First terminal; 342: Second terminal; 500: External mounting substrate; 501: Main substrate; 502: Wiring; 502a: Pad; 503: Ground electrode.

Claims

1. A semiconductor relay, comprising: Light-emitting elements; A light-receiving element is located below the light-emitting element and faces the light-emitting element; A first switching element is adjacent to the light-receiving element; A second switching element is located adjacent to the light-receiving element; The first chip pad is located above the first switching element; The second chip pad is located above the second switching element; The first terminal, one end of which is connected to the first chip pad; The second terminal, one end of which is connected to the second chip pad; as well as Packaging, The light-receiving element is located between the first switching element and the second switching element. The orientation of the first terminal and the second terminal is defined as the first direction. The other end of the first terminal is exposed outside the package and extends downward from the package. The other end of the second terminal is exposed outside the package and extends downward from the package. The light-emitting element, the light-receiving element, the first switching element, the second switching element, the first chip pad, and the second chip pad are located inside the package. When viewed from above, at least a portion of the first chip pads overlaps with the first switching element. When viewed from above, at least a portion of the second chip pad overlaps with the second switching element.

2. The semiconductor relay according to claim 1, wherein, The longest length of the first chip pad in the first direction is greater than the longest length of the first terminal in the first direction. The longest length of the second chip pad in the first direction is greater than the longest length of the second terminal in the first direction.

3. The semiconductor relay according to claim 1 or 2, wherein, The shortest distance in the first direction between the first chip pad and the second chip pad is shorter than the shortest distance in the first direction between the first terminal and the second terminal.

4. The semiconductor relay according to any one of claims 1 to 3, wherein, The first chip pad has a width variation portion. The width variation portion is configured such that the length of the first chip pad in the first direction increases as it moves from the boundary between the first terminal and the first chip pad toward the end of the first chip pad.

5. The semiconductor relay according to any one of claims 1 to 4, wherein, When the direction in which each terminal of the first terminal and the second terminal protrudes, which is orthogonal to the first direction, is set as the second direction, the first chip pad has a protrusion protruding in the first direction or the second direction.

6. The semiconductor relay according to any one of claims 1 to 5, wherein, When viewed from above, the area where the first chip pad overlaps with the first switching element is different from the area where the second chip pad overlaps with the second switching element.

7. The semiconductor relay according to any one of claims 1 to 6, wherein, The first terminal is composed of a first front end portion, a first middle portion, and a first connecting portion, wherein, The first middle portion is connected to the first front portion and is exposed on the outside of the package. The first connecting portion connects the first intermediate portion to the first chip pad and is located inside the package. The shortest length of the first connecting portion in the first direction is greater than the longest length of the first front end portion in the first direction. The second terminal is composed of a second front end portion, a second middle portion, and a second connecting portion, wherein, The second middle portion is connected to the second front portion and is exposed on the outside of the package. The second connecting portion connects the second intermediate portion to the second chip pad and is located inside the package. The shortest length of the second connecting portion in the first direction is greater than the longest length of the second front end portion in the first direction.

8. The semiconductor relay according to claim 7, wherein, The shortest length of the first middle portion in the first direction is greater than the longest length of the first front end portion in the first direction. The shortest length of the second middle portion in the first direction is greater than the longest length of the second front end portion in the first direction.

9. The semiconductor relay according to any one of claims 1 to 8, further comprising: The third chip pad, wherein the first switching element is disposed on the third chip pad; The fourth chip pad, wherein the second switching element is disposed on the fourth chip pad; The third terminal, one end of which is connected to the third chip pad; as well as The fourth terminal, one end of which is connected to the fourth chip pad, The third terminal is composed of a third front end portion, a third middle portion, and a third connecting portion, wherein, The third middle portion is connected to the third front portion and is exposed on the outside of the package. The third connecting portion connects the third intermediate portion to the third chip pad and is located inside the package. The shortest length of the third connecting portion in the first direction is greater than the longest length of the third front end portion in the first direction. The fourth terminal is composed of a fourth front end portion, a fourth middle portion, and a fourth connecting portion, wherein, The fourth middle portion is connected to the fourth front portion and is exposed on the outside of the package. The fourth connecting portion connects the fourth intermediate portion to the fourth chip pad and is located inside the package. The shortest length of the fourth connecting portion in the first direction is greater than the longest length of the fourth front end portion in the first direction.

10. The semiconductor relay according to claim 9, wherein, The shortest length of the third middle portion in the first direction is greater than the longest length of the third front portion in the first direction. The shortest length of the fourth middle portion in the first direction is greater than the longest length of the fourth front portion in the first direction.

11. The semiconductor relay according to claim 9 or 10, wherein, The third intermediate portion has: The first part, which is connected to the third connecting part; and The second part extends downward from the first part. When the direction in which the light-emitting element and the light-receiving element face each other is set as a third direction, the distance from the first part to the fourth terminal along the center line of the third direction, i.e., the first axis, is greater than the distance from the third front end part to the fourth terminal along the center line of the third direction, i.e., the second axis.

12. A semiconductor relay, comprising: Light-emitting elements; A light-receiving element is located below the light-emitting element and faces the light-emitting element; A first switching element is adjacent to the light-receiving element; A second switching element is located adjacent to the light-receiving element; The first chip pad is located above the first switching element; The second chip pad is located above the second switching element; The first terminal, one end of which is connected to the first chip pad; The second terminal, one end of which is connected to the second chip pad; as well as Packaging, The light-receiving element is located between the first switching element and the second switching element. The orientation of the first terminal and the second terminal is defined as the first direction. The other end of the first terminal is exposed outside the package and extends downward from the package. The other end of the second terminal is exposed outside the package and extends downward from the package. When viewed from above, at least a portion of the first chip pads overlaps with the first switching element. When viewed from above, at least a portion of the second chip pad overlaps with the second switching element. The semiconductor relay also features: The third chip pad, wherein the first switching element is disposed on the third chip pad; The fourth chip pad, wherein the second switching element is disposed on the fourth chip pad; A third terminal, one end of which is connected to the third chip pad; and The fourth terminal is configured to face the third terminal in the first direction. The light-emitting element, the light-receiving element, the first switching element, the second switching element, the first chip pad, the second chip pad, and the third chip pad are located inside the package. The third terminal is composed of a third front end portion, a third middle portion, and a third connecting portion, wherein, The third middle portion is connected to the third front portion and is exposed on the outside of the package. The third connecting portion connects the third intermediate portion to the third chip pad and is located inside the package. The third intermediate portion has: The first part, which is connected to the third connecting part; and The second part extends downward from the first part. When the direction in which the light-emitting element and the light-receiving element face each other is set as the third direction. The shortest length of the third middle portion in the first direction is greater than the longest length of the third front portion in the first direction. The distance from the first part to the fourth terminal along the center line of the third direction, i.e., the first axis, is greater than the distance from the fourth terminal along the center line of the third front end part, i.e., the second axis, to the fourth terminal.

13. The semiconductor relay according to claim 12, wherein, The third front end portion has: The first surface faces the fourth terminal; and Secondly, in the first direction, the distance between the second surface and the fourth terminal is greater than the distance between the first surface and the fourth terminal. The third intermediate portion has: The third side faces the fourth terminal; as well as Fourthly, in the first direction, the distance between the fourth surface and the fourth terminal is greater than the distance between the third surface and the fourth terminal. The first surface is flush with the third surface.

14. The semiconductor relay according to claim 13, wherein, The third surface at the first part is flush with the third surface at the second part.

15. The semiconductor relay according to claim 13 or 14, wherein, The fourth surface at the first part is flush with the fourth surface at the second part.

16. The semiconductor relay according to any one of claims 9 to 15, further comprising: A fifth chip pad having a lower surface, wherein the light-emitting element is disposed on the lower surface; and The sixth chip pad has an upper surface on which the light-receiving element is disposed. The distance between the first chip pad and the third chip pad is shorter than the distance between the fifth chip pad and the sixth chip pad. The distance between the second chip pad and the fourth chip pad is shorter than the distance between the fifth chip pad and the sixth chip pad.

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