Semiconductor structure and method of manufacturing the same

Abstract

This application discloses a semiconductor structure and its manufacturing method. The semiconductor structure includes a substrate, a first insulating layer, a floating gate, an erase gate, and a second insulating layer. The first insulating layer forms an upwardly extending step at the end of the floating gate, lifting the end of the floating gate away from the substrate. The sidewall of the floating gate at the lifted end is recessed inward to form an outwardly extending sharp corner. The erase gate is disposed outside the sharp corner, and the second insulating layer is located between the floating gate and the erase gate. This application, by lifting the end of the floating gate with a step in the first insulating layer and forming a sharp sidewall, can enhance the local electric field concentration effect between the floating gate and the erase gate during the erase operation, effectively improving electron tunneling efficiency. The step structure can suppress the electric field interference of the floating gate sharp corner on the substrate, helping to extend the lifespan. This application can significantly improve the erase speed and operating efficiency without significantly increasing process complexity, and improve the durability and reliability of flash memory devices, and can be widely applied in the field of semiconductor technology.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for manufacturing the same. Background Technology

[0002] As semiconductor storage technology advances towards higher density, lower power consumption, and greater reliability, the importance of non-volatile memory, especially flash memory devices, is becoming increasingly prominent in various electronic systems. In fields with stringent requirements for data storage reliability, such as automotive electronics, industrial control, and data centers, the lifespan (i.e., durability) of flash memory devices directly affects the long-term stable operation of the system and data security, and has become one of the key indicators for evaluating their performance.

[0003] In related technologies, the durability of flash memory devices is primarily limited by the degradation of the tunneling oxide layer between the floating gate and the substrate in the transistor. During repeated programming and erasing operations, a large number of electrons tunnel through the tunneling oxide layer, causing defects within the layer and gradually compromising its structural integrity. This leads to a contraction of the storage threshold voltage window. When the window shrinks to a certain extent, it becomes impossible to accurately distinguish logic states, ultimately causing the flash memory device to fail. Therefore, how to delay the degradation of the tunneling oxide layer is a key issue that needs to be addressed to improve the durability of flash memory devices. Summary of the Invention

[0004] This application provides a semiconductor structure and its manufacturing method, which can significantly improve erasure speed and operating efficiency, and improve the durability and reliability of flash memory devices.

[0005] One aspect of this application provides a semiconductor structure, including: Substrate; A first insulating layer is disposed on the top of the substrate, and the end of the first insulating layer has a step extending away from the substrate; A floating gate is disposed on top of the first insulating layer. The end of the floating gate is raised away from the substrate by the step of the first insulating layer, and the sidewall of the raised end of the floating gate is recessed towards the center of the floating gate to form an outwardly extending sharp corner at the edge of the sidewall. The erasure grid is located on the outside of the sharp corner; A second insulating layer is disposed between the floating gate and the erasure gate.

[0006] Optionally, in some embodiments, the substrate includes an active region; On a first cross-section of the semiconductor structure, the main body portion of the floating gate covers the active region in a vertical direction; wherein, the first cross-section is a cross-section perpendicular to a first direction of the substrate in a top view and passing through the center point of the floating gate, and the main body portion of the floating gate is the portion other than the end that is raised by the step.

[0007] Optionally, in some embodiments, the semiconductor structure further includes: Shallow trench isolation grooves are formed between the substrate and the first insulating layer; The shallow trench isolation trench is used to isolate the active regions of multiple semiconductor structures.

[0008] Optionally, in some embodiments, the active region includes a doped region, the doped region leading out the source and drain of the semiconductor structure; On the second cross section of the semiconductor structure, the floating gate and the doped region do not overlap in the vertical direction; wherein, the second cross section is a cross section perpendicular to the substrate in the second direction under the top view and passing through the active region.

[0009] Optionally, in some embodiments, both ends of the first insulating layer have steps extending away from the substrate, and the sidewall edges of both ends of the floating gate form outwardly extending sharp corners; The number of erase gates is two, and each erase gate is located outside one of the corners.

[0010] Optionally, in some embodiments, the sharpness of the outwardly extending corners of the two sidewalls differs.

[0011] Optionally, in some embodiments, on a first cross-section of the semiconductor structure, the inner contour of the erase gate matches the sharp corner contour formed by the recessed sidewall edge of the end of the floating gate, and wraps around the sharp corner contour.

[0012] Optionally, in some embodiments, the bottom of the erasure grid extends toward the center of the floating grid to cover the lower edge sharp corner formed by the recess of the sidewall edge of the end of the floating grid.

[0013] This application also provides a method for manufacturing a semiconductor structure, including the following steps: Provide a substrate; A first insulating layer is formed on top of the substrate; wherein the end of the first insulating layer has a step extending away from the substrate; Polysilicon is deposited over the first insulating layer to form a floating gate; wherein the ends of the floating gate are raised away from the substrate by the steps of the first insulating layer; The sidewall of the raised end of the floating gate is etched to make the sidewall recessed toward the center of the floating gate, and to form an outwardly extending sharp corner at the edge of the sidewall. A second insulating layer is formed on the surface of the floating gate; Polysilicon is deposited on the outside of the sharp corner to form an erase gate.

[0014] Optionally, in some embodiments, forming a first insulating layer on top of the substrate includes: A first insulating dielectric layer is deposited on top of the substrate; The first insulating medium is etched to form the step; A second insulating medium is formed above the substrate and the step to obtain the first insulating layer.

[0015] Optionally, in some embodiments, depositing polysilicon over the first insulating layer to form a floating gate includes: Polycrystalline silicon is deposited above the first insulating layer; A photoresist with a predetermined pattern is coated on top of the polycrystalline silicon; Remove the polysilicon above the first insulating layer that is not covered by the photoresist to form the floating gate.

[0016] Optionally, in some embodiments, removing the polysilicon above the first insulating layer that is not covered by the photoresist includes: The polysilicon above the first insulating layer that was not covered by the photoresist was removed by a dry etching process. And / or, the etching of the sidewall of the raised end of the floating gate includes: The sidewalls of the raised end of the floating gate are etched using a wet etching process.

[0017] Optionally, in some embodiments, etching the sidewall of the raised end of the floating gate includes: The sidewalls at the two ends of the raised grid are etched for different durations so that the sharpness of the outwardly extending corners formed by the edges of the two sidewalls is different.

[0018] Optionally, in some embodiments, forming a second insulating layer on the surface of the floating gate includes: A third insulating medium is formed on the surface of the floating gate by a low-temperature oxidation process; A fourth insulating medium is deposited on the surface of the third insulating medium to obtain the second insulating layer.

[0019] Optionally, in some embodiments, the fourth insulating medium deposited on the surface of the third insulating medium includes: A silicon dioxide layer is generated on the surface of the third insulating medium by chemical vapor deposition. A silicon nitride layer is formed on the silicon dioxide layer by chemical vapor deposition to obtain the fourth insulating medium.

[0020] The embodiments of this application include at least the following unexpected effects: In this embodiment, the floating gate tip is raised by a step in the first insulating layer, forming a sharp sidewall corner. This enhances the local electric field concentration effect between the floating gate and the erase gate during the erase operation, effectively improving electron tunneling efficiency. Simultaneously, the stepped structure suppresses electric field interference from the floating gate sharp corner to the substrate, contributing to extended lifespan. Therefore, this application can significantly improve erase speed and operating efficiency, and enhance the durability and reliability of flash memory devices without significantly increasing process complexity. Attached Figure Description

[0021] The accompanying drawings are used to provide a further understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0022] Figure 1 A schematic cross-sectional view of a transistor for a flash memory device provided in an embodiment of this application is shown. Figure 2 A cross-sectional schematic diagram of a semiconductor structure provided in an embodiment of this application is shown; Figure 3 This illustration shows a top view of a 2T-eFlash memory cell provided in an embodiment of this application. Figure 4 This illustration shows a cross-sectional schematic diagram of the storage transistor region of a conventional 2T-eFlash provided in an embodiment of this application; Figure 5 A cross-sectional schematic diagram of the storage transistor region of an improved 2T-eFlash provided in an embodiment of this application is shown; Figure 6 This illustration shows a cross-sectional schematic diagram of the storage transistor region of another conventional 2T-eFlash provided in an embodiment of this application; Figure 7 A schematic diagram of a semiconductor structure with sharp corners of different degrees of sharpness provided in an embodiment of this application is shown; Figure 8 This illustration shows a schematic diagram of a semiconductor structure in an embodiment of the present application, in which an eraser gate can wrap around the sharp corner of the lower edge of a floating gate; Figure 9 A schematic flowchart of a semiconductor structure manufacturing method provided in an embodiment of this application is shown; Figure 10 This illustration shows a schematic diagram of a semiconductor structure after a first insulating dielectric is formed on the surface of a substrate, as provided in an embodiment of this application. Figure 11 This illustration shows a schematic diagram of a semiconductor structure after a photoresist with a preset pattern is coated on the surface of a first insulating medium, as provided in an embodiment of this application. Figure 12 This illustration shows a schematic diagram of a semiconductor structure after etching a first insulating medium, as provided in an embodiment of this application. Figure 13 This illustration shows a schematic diagram of a semiconductor structure after a second insulating dielectric is formed above a substrate and a step, according to an embodiment of this application. Figure 14 This illustration shows a schematic diagram of a semiconductor structure after polysilicon is deposited over a first insulating layer, as provided in an embodiment of this application. Figure 15 This illustration shows a schematic diagram of a semiconductor structure after a photoresist with a preset pattern is coated on the surface of polycrystalline silicon, as provided in an embodiment of this application. Figure 16 This illustration shows a schematic diagram of a semiconductor structure after etching polysilicon and a first insulating layer, as provided in an embodiment of this application. Figure 17 This illustration shows a schematic diagram of a semiconductor structure after etching the end sidewall of a floating gate, as provided in an embodiment of this application. Figure 18 This illustration shows a schematic diagram of a semiconductor structure after a third insulating dielectric is formed on the surface of a floating gate, as provided in an embodiment of this application. Figure 19 This illustration shows a schematic diagram of a semiconductor structure after a fourth insulating medium is deposited on the surface of a third insulating medium, as provided in an embodiment of this application. Figure 20 This illustration shows a schematic diagram of a semiconductor structure after polysilicon deposition on a second insulating layer, as provided in an embodiment of this application. Figure 21 This illustration shows another semiconductor structure after a photoresist with a preset pattern is coated on the surface of polysilicon, as provided in an embodiment of this application. Figure 22 This illustration shows a schematic diagram of a semiconductor structure after etching to obtain an erased gate, provided in an embodiment of this application. Figure 23 An embodiment provided in this application is shown. Figure 5 A schematic diagram of electron transfer that occurs during programming in the semiconductor structure shown; Figure 24 An embodiment provided in this application is shown. Figure 5 The diagram shows the electron transfer that occurs during the erasure of the semiconductor structure. Explanation of reference numerals in the attached figures: 110: Substrate; 120: First insulating layer; 130: Floating gate; 140: Second insulating layer; 150: Control gate; 121: Step; 131: First sharp corner; 160: Eraser gate; 310: Storage transistor region; 320: Select transistor region; 510: Tunneling region; 132: Second sharp corner; 133: Third sharp corner; 134: Fourth sharp corner; 1010: First insulating medium; 1020: First photoresist; 1011: Initial step; 1030: Second insulating medium; 1410: First polysilicon; 1420: Second photoresist; 1810: Third insulating medium; 1820: Fourth insulating medium; 2010: Second polysilicon; 2020: Third photoresist. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0024] It is understood that the terms “first,” “second,” etc., used in this application may be used to describe various concepts herein, but unless otherwise stated, these concepts are not limited by these terms. These terms are used only to distinguish one concept from another.

[0025] As used in this application, the terms "at least one", "multiple", "each", "any", etc., "at least one" includes one, two or more, "multiple" includes two or more, "each" refers to each of the corresponding multiples, and "any" refers to any one of the multiples.

[0026] Before providing a further detailed description of the embodiments of this application, the nouns and terms used in the embodiments of this application are explained, and the nouns and terms used in the embodiments of this application shall be interpreted as follows: 1) Tunneling, in the fields of semiconductor physics and microelectronics, refers to the quantum mechanical phenomenon in which charge carriers (such as electrons or holes) pass through a potential barrier that, according to classical physics, their energy is insufficient to overcome. This phenomenon is also known as the quantum tunneling effect.

[0027] 2) 2T-eFlash (Two-Transistor Embedded Flash) is an embedded non-volatile memory technology widely used in microcontrollers, smart cards, IoT chips, and automotive electronics. Its characteristic is that each memory bit consists of two transistors forming a memory cell, rather than a traditional single-transistor floating-gate cell. This architecture achieves a good balance between performance, reliability, and process integration.

[0028] As semiconductor storage technology advances towards higher density, lower power consumption, and greater reliability, the importance of non-volatile memory, especially flash memory devices, in various electronic systems is becoming increasingly prominent. In fields with stringent requirements for data storage reliability, such as automotive electronics, industrial control, and data centers, the durability of flash memory devices directly affects the long-term stable operation of the system and data security, and has become one of the key indicators for evaluating their performance.

[0029] Flash memory devices typically consist of a large number of basic memory cells. These basic memory cells often employ special metal-oxide-semiconductor field-effect transistors (MOSFETs). Unlike ordinary transistors, the transistors used in flash memory devices have an additional floating gate (FG) between the control gate (CG) and the channel. For example, please refer to... Figure 1 , Figure 1 This illustration shows a cross-sectional structural diagram of a transistor for a flash memory device provided in an embodiment of this application, as shown below. Figure 1 As shown, the transistor is constructed from bottom to top by stacking a substrate 110, a first insulating layer 120, a floating gate 130, a second insulating layer 140, and a control gate 150. Of course, Figure 1 The image only shows the main stacked structure of the transistor and does not imply any limitation on its actual configuration.

[0030] Specifically, the bottommost substrate 110 serves as the foundation of the device and is typically made of semiconductor materials such as silicon. Above the substrate 110, a first insulating layer 120 is formed, typically an oxide dielectric, constituting the tunneling oxide layer of the transistor. Above the first insulating layer 120 is a floating gate 130, made of a conductive material (such as polysilicon) and completely surrounded by an insulating dielectric. The floating gate 130 stores charge; its charge state determines the threshold voltage of the transistor, thus characterizing the stored data. Above the floating gate 130 is a second insulating layer 140, typically an oxide-nitride-oxide composite dielectric structure, serving as an interlayer dielectric layer isolating the floating gate 130 and the control gate 150, possessing a high dielectric constant and excellent charge retention characteristics. The topmost control gate 150, also typically made of a conductive material, serves as an electrode for applying an external control voltage. In operation, by applying a specific voltage to the control gate 150, the quantum tunneling effect can be used to allow charge to pass through the first insulating layer 120 and be injected into or discharged from the floating gate 130, thereby enabling data writing and erasure.

[0031] like Figure 1 In the transistor shown, the layers of the structure work together to achieve non-volatile control of the stored charge. Each storage bit of the flash memory device is implemented by at least one such transistor, which constitutes the physical basis for the data storage of the flash memory device.

[0032] It should be noted that currently, the durability of flash memory devices is mainly limited by the degradation of the tunneling oxide layer between the floating gate and the substrate in the transistor. Figure 1 For example, during the repeated programming and erasing operations of a transistor, electrons need to tunnel through the first insulating layer 120 (i.e., the tunneling oxide layer) between the floating gate 130 and the substrate 110. Each tunneling process can impact the atomic structure of the tunneling oxide layer. With the accumulation of operations, microscopic defects such as oxygen vacancies and dangling bonds gradually form within the oxide layer. These defects create localized charge traps within the oxide layer, which not only trap tunneling electrons, affecting the efficiency of charge injection and dissipation, but can also become channels for leakage current, compromising the insulating integrity of the oxide layer. Especially as memory process nodes continue to shrink and cell sizes continue to decrease, the physical thickness of the tunneling oxide layer is approaching its physical limit, making it even more sensitive to the aforementioned degradation effects.

[0033] Therefore, how to delay the loss of the tunneling oxide layer has become a key issue that needs to be addressed to improve the durability of flash memory devices.

[0034] In related technologies, to delay the wear of the tunneling oxide layer and improve the durability of flash memory devices, one strategy is to introduce a separate erase gate (EG) in the transistor. In this transistor structure, in addition to the layers serving as the control gate and floating gate, an additional erase gate is introduced to the side of the floating gate, separated from it by an insulating dielectric layer (e.g., a silicon oxide-silicon nitride-silicon oxide composite layer). In this case, the erase operation is no longer performed through the tunneling oxide layer between the floating gate and the substrate. Instead, a voltage is applied to the erase gate, and a strong electric field is induced on the floating gate using the capacitive coupling between the floating gate and the erase gate. This electric field causes electrons in the floating gate to tunnel through the insulating dielectric layer between the floating gate and the erase gate, and are extracted into the erase gate for discharge. Thus, the tunneling oxide layer, which originally performed the erase function, is only used for electron injection during programming in this structure.

[0035] In conventional structures, the tunneling oxide layer must withstand two high electric field stresses during each complete program / erase cycle. However, in transistors with an erase gate, the physical paths of the programming and erasing operations are separated, avoiding the dependence of all charge transfer on the tunneling oxide layer. This disperses the electric field stress and slows down its degradation and wear.

[0036] However, in practical applications, it has been found that although the structure of introducing an independent erase gate can transfer the erase path from the tunnel oxide layer to the insulating dielectric layer between the floating gate and the erase gate, the erase process may still cause significant secondary effects on the substrate and the tunnel oxide layer.

[0037] Specifically, during the erasure process, when a voltage is applied to the erase gate, this voltage not only acts on the floating gate through capacitive coupling but also affects the substrate. In this case, in addition to the expected electron tunneling through the insulating path between the floating gate and the erase gate, unexpected electron tunneling may occur in the tunneling oxide layer between the floating gate and the substrate (or the erase gate and the substrate). This unexpected tunneling phenomenon reduces the efficiency and controllability of the erasure operation, slowing down the erasure speed or increasing the erase voltage threshold. Furthermore, it still causes additional charge injection and electric field stress impact on the tunneling oxide layer, partially offsetting the protective effect of the erase gate. Over the long term, this accelerates the degradation of the tunneling oxide layer, limiting further improvements in device durability.

[0038] In view of this, this application provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a substrate, a first insulating layer, a floating gate, an erase gate, and a second insulating layer. The first insulating layer forms an upwardly extending step at the end of the floating gate, lifting the end of the floating gate away from the substrate. The sidewall of the floating gate at the lifted end is recessed inward to form an outwardly extending sharp corner. The erase gate is disposed outside the sharp corner, and the second insulating layer is located between the floating gate and the erase gate. An unexpected effect of this semiconductor structure is that the step in the first insulating layer lifts the end of the floating gate and forms a sharp sidewall, which enhances the local electric field concentration effect between the floating gate and the erase gate during the erase operation, effectively improving electron tunneling efficiency. Simultaneously, the step structure suppresses electric field interference from the floating gate sharp corner to the substrate, helping to extend the lifespan. Therefore, this application can significantly improve the erase speed and operating efficiency, and improve the durability and reliability of flash memory devices without significantly increasing process complexity.

[0039] Application scenario description of the embodiments of this application The semiconductor structure and manufacturing method provided in this application can be applied in various scenarios where there are high durability and high reliability requirements for non-volatile memory. The following is an exemplary description of this.

[0040] (a) Scenarios of automotive-grade storage and autonomous driving systems The semiconductor structure provided in this application embodiment can be applied to automotive-grade flash memory, especially in data storage scenarios for autonomous driving systems.

[0041] In autonomous driving systems, vehicle sensors (such as cameras and LiDAR) continuously generate massive amounts of data. This data not only needs to be processed in real time, but some high-value data used for model training or accident analysis also needs to be written to onboard solid-state drives (SSDs) for long-term, reliable storage. Traditional flash memory experiences accelerated degradation of its tunneling oxide layer during frequent data write / erase cycles, leading to a rapid decline in the durability of storage cells. Over a vehicle's lifespan of more than ten years, this can cause data errors or even storage block failures, posing a potential risk to driving safety.

[0042] By applying the semiconductor structure provided in this application, the erase operation in the memory cell is mainly completed via an efficient path between the sharp corner of the floating gate and the erase gate, significantly reducing the electrical stress borne by the tunneling oxide layer during the erase cycle. Simultaneously, the stepped structure effectively isolates the electric field interference of the floating gate sharp corner to the substrate, further protecting the tunneling oxide layer. This enables automotive flash memory to maintain an extremely low cell degradation rate and excellent data retention capability even when subjected to the high-intensity, continuous data write load generated by autonomous driving systems, meeting the stringent lifespan and reliability requirements of automotive-grade products and providing a robust data storage guarantee for the safe operation of autonomous driving systems.

[0043] (II) Scenarios of Industrial Internet of Things and Edge Computing Nodes The semiconductor structure provided in this application embodiment can be applied in embedded storage scenarios of industrial IoT terminal devices or edge computing nodes.

[0044] In Industrial Internet of Things (IIoT) and edge computing scenarios, numerous field devices (such as smart meters and controllers) need to operate independently for extended periods in harsh industrial environments (high temperature, high humidity, vibration) and frequently record device status, process parameters, or preprocessed data locally. These devices typically use embedded flash memory as the storage medium for programs and data. With frequent updates and erases, the threshold voltage window of traditional flash memory gradually shrinks, leading to decreased data reliability. This can cause device program malfunctions or loss of critical historical data, resulting in production interruptions or quality incidents.

[0045] By applying the semiconductor structure provided in this application embodiment, the optimized electric field distribution significantly delays the core wear mechanism of the memory cell while improving erasure efficiency and reducing operating voltage. This enables embedded flash memory to achieve faster erase and write speeds under more relaxed voltage conditions and possesses stronger fatigue resistance. Industrial equipment equipped with such memory can adapt to more frequent data recording needs, maintain extremely high storage reliability throughout the product's lifecycle, thereby ensuring the continuity and stability of industrial processes and reducing maintenance costs.

[0046] (III) High-performance data centers and enterprise-grade solid-state drives The semiconductor structure provided in this application embodiment can be applied in high-performance data centers and enterprise-level solid-state drives.

[0047] Data centers and enterprise-level storage place extreme demands on solid-state drives (SSDs) in terms of throughput, latency, and total bytes written. Traditional methods that prioritize erase speed by increasing erase voltage exacerbate damage to the tunneling oxide layer, limiting drive durability; conversely, overly conservative operating strategies sacrifice performance. Finding the optimal balance between erase efficiency and oxide layer protection is a core challenge in enterprise-level flash memory design.

[0048] By applying the semiconductor structure provided in this application, its unique floating gate tip design generates a strong local electric field concentration during erasure, enabling electrons to be extracted through the floating gate-erasure gate path with higher efficiency. This means that the erasure operation can be completed with a lower erase voltage or in a shorter time. Simultaneously, the effective protection of the tunneling oxide layer allows the solid-state drive controller to employ more powerful garbage collection and wear leveling algorithms, significantly improving the overall write performance and response speed of the storage system without significantly shortening device lifespan, thus meeting the combined requirements of data centers for high throughput, low latency, and high durability.

[0049] Of course, it is understood that the semiconductor structure and manufacturing method in the embodiments of this application are not limited to the application scenarios given in the above examples. The solutions in the embodiments of this application can also be applied in other fields with high requirements for memory durability, reliability and operating efficiency, such as aerospace electronics, medical devices, and high-end consumer electronics. This application does not impose any restrictions on this.

[0050] General Description of Embodiments in this Application Please refer to Figure 2 , Figure 2 A cross-sectional schematic diagram of a semiconductor structure provided in an embodiment of this application is shown. For example... Figure 2 As shown, the semiconductor structure mainly includes: Substrate 110; A first insulating layer 120 is disposed on the top of the substrate, and the end of the first insulating layer has a step 121 extending away from the substrate; A floating gate 130 is disposed on the top of the first insulating layer. The end of the floating gate is lifted away from the substrate by the step of the first insulating layer, and the sidewall of the lifted end of the floating gate is recessed towards the center of the floating gate to form a first sharp corner 131 extending outward at the edge of the sidewall. Erasure grid 160 is located on the outside of the sharp corner; The second insulating layer 140 is disposed between the floating gate and the erasure gate.

[0051] like Figure 2 The schematic cross-sectional view of the semiconductor structure provided in the embodiment of this application is shown. This semiconductor structure can be used as a storage cell in a flash memory device, such as a transistor. Its specific structure and related functions are detailed below: First, the substrate 110 forms the basic support and active region of the entire semiconductor structure. It is typically made of single-crystal silicon and may contain doped regions to define the source and drain regions of the transistor (not shown in the figure). The substrate 110 not only provides mechanical support, but its surface channel regions are also the key paths for carrier conduction.

[0052] A first insulating layer 120 is provided on the substrate 110. This layer is an insulating medium directly grown or deposited on the surface of the substrate 110, and its material is typically silicon dioxide, constituting the crucial tunneling oxide layer in flash memory devices. One of the key improvements of this application is that the end of the first insulating layer 120 is configured with a step 121 extending away from the substrate (i.e., vertically upward). This step structure is formed through a specific process, such that the thickness of the first insulating layer 120 increases in the end region. The presence of the step 121 raises the end of the subsequently formed floating gate, moving it away from the surface of the substrate 110.

[0053] The floating gate 130, serving as a charge storage node, is located on top of the first insulating layer 120. It is typically made of doped polysilicon. Due to the stepped structure 121 of the underlying first insulating layer 120, the corresponding end of the floating gate 130 is raised, thus creating a distance between it and the substrate 110. Furthermore, at this raised end, the sidewalls of the floating gate 130 are recessed towards the center using a special etching or shaping process, forming sharp protrusions at the upper and lower edges of the sidewalls, such as the first sharp corner 131 at the upper edge of the right end. The first sharp corner 131 is a geometric feature that enhances the local electric field, effectively improving the tunneling efficiency between the floating gate and the erase gate. The main body of the floating gate 130, excluding the stepped end, is used to store electrons (or holes) representing data information.

[0054] The erase gate 160 is located outside the first sharp corner 131 of the floating gate 130 (i.e., on the side away from the floating gate). It is also made of a conductive material (such as polysilicon) and serves as a separate control electrode. The function of the erase gate 160 is to establish an efficient charge discharge path by applying voltage during the erase operation, in conjunction with the floating gate 130.

[0055] Specifically, in this embodiment, the end edge of the floating gate 130 is provided with a sharp corner extending outward. During the erasure operation, when a positive high-voltage pulse is applied to the erasure gate 160, since the floating gate 130 itself is at a floating potential, the voltage will induce a strong electric field on the floating gate 130 through capacitive coupling between the floating gate 130 and the erasure gate 160. The sharp corner formed at the end of the floating gate 130, as a geometric field enhancer, will greatly concentrate and amplify the induced electric field in the tip region. Thus, the higher electric field strength can greatly reduce the potential barrier that electrons need to overcome for tunneling, allowing electrons stored in the floating gate 130 to penetrate the second insulating layer 140 with a higher probability and a faster rate, thereby being efficiently extracted to the erasure gate 160, which is beneficial to improving the erasure efficiency.

[0056] It is readily understood that, in this embodiment, the stepped structure of the first insulating layer 120 can lift a specific end of the floating gate 130 (especially the region with sharp corners) as a whole, creating a larger vertical distance between this portion of the floating gate and the first insulating layer 120 (i.e., the tunneling oxide layer) on the surface of the substrate 110. From the perspective of electric field distribution, this lifting significantly increases the distance and dielectric thickness between the sharp corner of the floating gate 130 and the substrate 110 below, effectively weakening the influence that the field enhancement effect at the sharp corner may have on the substrate 110. Thus, during the erasure process, the probability of electrons tunneling on the substrate 110 side will be greatly reduced, which can protect the tunneling oxide layer. Moreover, through the cooperation of the sharp corner and the erasure gate 160, the main charge transfer path of the erasure process can be clearly and efficiently guided to the second insulating layer 140 between the floating gate and the erasure gate, enhancing the directionality and controllability of the erasure operation path. In summary, the step and sharp corner structures in the embodiments of this application can minimize the possibility of unintended tunneling of electrons through the first insulating layer 120 (tunneling oxide layer) between the bottom of the floating gate 130 and the substrate 110 during the erasure process.

[0057] Between the floating gate 130 and the erase gate 160, a second insulating layer 140 is filled. This layer can be a single high-dielectric-constant material, or a more common composite stack structure, such as an oxide-nitride-oxide stack. Figure 2 In this structure, the second insulating layer 140 stacks two insulating dielectric layers: the first layer is silicon dioxide, and the second layer is a mixture of silicon dioxide and silicon nitride. The second insulating layer 140 serves a dual purpose: firstly, it acts as an insulating barrier between the floating gate 130 and the erase gate 160, preventing short circuits between them; secondly, it acts as a tunneling barrier for the erase operation, allowing electrons stored in the floating gate to tunnel through this dielectric layer and be extracted to the erase gate 160 under the erase voltage.

[0058] It should be noted that, in addition to the structures described above, the semiconductor structure of this application embodiment may further include other structures to achieve complete memory operation. These may include control gate 150, select gate, shallow trench isolation trench, source / drain regions, etc., and this application does not impose any limitations on these.

[0059] Specifically, in some embodiments, the semiconductor structure provided in this application may be a memory cell (or part thereof) of 2T-eFlash. The memory cell of 2T-eFlash generally includes a storage transistor and a selection transistor. The storage transistor may adopt the semiconductor structure provided in the embodiments of this application, while the selection transistor may be implemented using conventional technology, which will not be elaborated upon in this application.

[0060] For example, please refer to Figure 3 , Figure 3This illustration shows a top view of a 2T-eFlash memory cell provided in an embodiment of this application, as shown below. Figure 3 As shown, the overall structure of the memory cell is arranged in a rectangle along a first direction and a second direction. The first direction can be the length extension direction of the memory cell from a top-view perspective, and the second direction can be the width extension direction of the memory cell from a top-view perspective. The active region, the source / drain region of the transistor, and necessary electrical isolation are defined by different doped regions (such as "N+" and "P+") and shallow channel isolation trenches.

[0061] Figure 3 In this application, the memory cell includes a memory transistor region 310 and a select transistor region 320. The memory transistor region 310 is used to implement the memory transistor with a unique floating gate and erase gate structure described above. The label line A-A' indicates a typical cross-sectional view location, and the cross-sectional view obtained by cutting along this line (i.e., similar to...) Figure 2 A top view clearly shows the stacking details of the storage transistors in the vertical direction, such as the steps of the first insulating layer, the sharp corners of the floating gate, and the relative positions of the erase gate and the floating gate. The select transistor region 320 implements the aforementioned select transistor; it is connected in series with the storage transistor to select the storage cell. In a top view, it typically appears as a conventional gate intersecting the active region. Its gate structure is relatively simple, without complex stacking such as a floating gate, and can be identified by a separate polysilicon region. "N+" regions represent heavily doped N-type semiconductor regions, and "P+" regions represent heavily doped P-type semiconductor regions; they are typically used to form source / drain contacts or common source line potential contacts. Figure 3 In the diagram, the outer portion of the device represents a shallow trench isolation trench, used to physically and electrically isolate adjacent memory cells.

[0062] For example, please refer to Figure 4 , Figure 4 This illustration shows a cross-sectional schematic diagram of the storage transistor region of a conventional 2T-eFlash according to an embodiment of this application. This cross-sectional schematic diagram can be viewed through... Figure 3 The section marked A-A' is cut off, for example, along a direction perpendicular to the substrate in a top-view perspective and passing through the center point of the floating gate; the resulting cross-section is denoted as the first cross-section. Figure 4 As shown, the storage transistor region of a traditional 2T-eFlash has an overall structure and Figure 1 Similarly, the difference lies in the substrate 110. Specifically, in Figure 4In the conventional structure shown, the substrate 110 is constructed as a P-type silicon substrate (P-sub). During flash memory device manufacturing, to integrate multiple memory cells on the same substrate and achieve electrical isolation, shallow trench isolation (STI) trenches are formed in the substrate 110 using a shallow trench isolation process. These trenches typically consist of an insulating medium (such as silicon dioxide) filled within them, providing electrical isolation between adjacent memory cells and preventing crosstalk. The active regions of the memory transistors (i.e., the regions containing the source, drain, and channel regions) are defined within the areas separated by the shallow trench isolation. Well regions, such as N-type wells (NWs), can also be formed in the substrate 110. These N-type wells are locally doped regions formed by implanting N-type elements (such as phosphorus or arsenic) into specific areas of the P-type substrate and can serve as active regions.

[0063] It is easy to understand that, Figure 4 The diagram shows the structure of the storage transistor region in a traditional 2T-eFlash memory, which suffers from some of the technical problems described in the background section of this application. To address these issues, the technical solution provided in the embodiments of this application is adopted for improvement, resulting in a cross-sectional schematic diagram of the storage transistor region in the first section, as shown below. Figure 5 As shown. (Refer to...) Figure 5 The semiconductor structure provided in this application embodiment includes an active region in the substrate. The active region, acting as a channel in the semiconductor structure, can provide electrons tunneling into the floating gate during programming.

[0064] To maximize the utilization of the coupling capacitance and electric field distribution between the floating gate and the active region, thereby optimizing programming efficiency and ensuring stable charge storage, in this embodiment, the main body of the floating gate (i.e., the portion other than the end raised by the step) can be positioned to cover the active region. For example... Figure 5 As shown in tunneling region 510, this maximizes the coupling strength between the tunneling area and the capacitance, meaning that at the same programming voltage, more electrons can participate in the tunneling process simultaneously, directly increasing the charge injection per unit time and thus improving programming speed. Simultaneously, the larger overlap area also means a larger capacitance between the floating gate and the active region, enhancing the ability to modulate the channel potential by controlling the gate voltage, making threshold voltage regulation more sensitive and stable. Furthermore, this uniformity avoids excessive concentration of the electric field locally (especially at the floating gate edge), thereby reducing the impact damage of high-energy electrons on the tunneling oxide layer, helping to delay its degradation and improve the durability of the flash memory device.

[0065] In addition, such as Figure 5 As shown, the semiconductor structure in this embodiment may further include a shallow trench isolation trench formed between the substrate and the first insulating layer. In the manufacturing process, this trench can be formed by etching it into the substrate and then filling it with an insulating medium (typically silicon dioxide). Figure 5In the cross-sectional schematic shown, the shallow channel isolation trench appears as an insulating structure located on both sides of the active region and embedded within the substrate. Its function is to physically and electrically isolate the active region. Specifically, it completely separates the active region carrying the storage transistor channel and source / drain regions from the active regions of adjacent memory cells (semiconductor structures), preventing carrier leakage or crosstalk between different memory cells through the substrate, thereby ensuring that each memory cell can operate independently and reliably.

[0066] In addition, in comparison Figure 4 and Figure 5 In this application embodiment, the traditional control gate structure is also improved by using a large contact (large contact hole) made of metal (e.g., tungsten, aluminum, or copper or their alloys / silicides) to replace the traditional polysilicon layer as the control gate of the memory cell. Figure 5 As shown, the control gate, formed by this large metal contact hole, achieves reliable physical and electrical isolation from the underlying floating gate through an insulating dielectric layer, thus forming a capacitor structure of large metal contact hole / dielectric layer / floating gate. Using metal instead of polysilicon can effectively reduce the resistivity of the control gate, thereby reducing the parasitic resistance of the capacitor and increasing the uniformity of the electric field, providing a solid technical foundation for realizing high-speed, high-durability, and high-reliability flash memory devices.

[0067] Figure 3 The diagram also shows another line, B-B', and a cross-sectional view obtained by cutting along line B-B', which reveals the structural features of the memory cell from another perspective. In this embodiment, the cross-section obtained along line B-B' is referred to as the second cross-section. The second cross-section can be a cross-section perpendicular to a second direction of the substrate in a top-view perspective and passing through the active region. Figure 3 For example, the second section can simultaneously capture the storage transistor region 310 and the selection transistor region 320, visually showing the shared source / drain regions of the two, as well as how the two transistors are physically and electrically connected in series in the overall structure.

[0068] For example, please refer to Figure 6 , Figure 6 This illustration shows a cross-sectional schematic diagram of the storage transistor region of another conventional 2T-eFlash provided in an embodiment of this application. Figure 6 The cross-sectional diagram shown is based on the second cross-section. The semiconductor structure provided in the embodiments of this application can be referenced in design. Figure 6 The situation is illustrated. Specifically, the active region may include a well region and a doped region, such as... Figure 6 The N-type well and some "N+" and "P+" doped regions in the semiconductor can be used to bring out the source and drain of the semiconductor structure.

[0069] In particular, in the embodiments of this application, the floating gate and the doped region do not overlap in the vertical direction on the second cross section of the semiconductor structure. This can reduce the edge overlap area and coupling strength between the floating gate and the doped region, prevent interference with the storage state, and improve the reliability of the semiconductor structure.

[0070] It should be noted that, in the embodiments of this application, the steps on the first insulating layer 120 may be arranged only at one end, that is, only one end is provided with a step structure, or both ends are provided. Based on this, the floating gate may be raised away from the substrate by only one end by the step, or both ends may be raised away from the substrate by the step, and this application does not impose any restrictions on this.

[0071] Specifically, in some embodiments, reference is made to Figure 5 The first insulating layer has steps 121 extending away from the substrate at both ends, and the sidewall edges at both ends of the floating gate form outwardly extending sharp corners. Meanwhile, the number of erase gates can be set to two, with each erase gate located outside one of the sharp corners. This creates a symmetrical and high-performance dual erase gate structure.

[0072] It is easy to understand that, compared to an implementation with an erase gate on only one side of the floating gate, using two erase gates can double the erasure efficiency, thereby significantly shortening the erasure time. For example, during the erasure operation, voltages can be applied to the two erase gates simultaneously or alternately. Since the sharp corners at both ends of the floating gate generate a very strong local electric field concentration effect, this is equivalent to providing two efficient and symmetrical escape channels for the electrons stored in the floating gate. Electrons can be extracted from both sides of the floating gate simultaneously, thus greatly improving the overall charge erasure rate. This not only shortens the time required for a single erasure operation, meeting the needs of high-speed storage, but also means that more erasure operations can be completed in the same amount of time, or the same erasure effect can be achieved at a lower voltage, helping to reduce power consumption and alleviate the design pressure on high-voltage circuits.

[0073] Furthermore, in a single-ended erase gate structure, the erase electric field is applied to one end of the floating gate, which may lead to an uneven potential distribution within the floating gate. Electrons are preferentially and rapidly extracted at the end closer to the erase gate, while those at the far end are extracted relatively slowly. This asymmetrical erase process easily causes uneven distribution of residual charge within the floating gate, resulting in unstable threshold voltage after erasure, affecting read accuracy and inter-cell consistency. With a symmetrical structure using a dual erase gate, the electric field acts synchronously and symmetrically from both ends of the floating gate, forcing the charge within the floating gate to be extracted more quickly and evenly as a whole. This effectively narrows the threshold voltage distribution in the erase state, thereby expanding the effective storage window, enhancing the reliability of the read signal, and reducing the probability of abnormal stored data.

[0074] Specifically, based on the dual erase gate structure, the embodiments of this application further optimize the design by processing the edges of the two floating gates so that the sharpness of the outward-extending corners is different. For example, please refer to... Figure 7 , Figure 7 This illustration shows a schematic diagram of a semiconductor structure with sharp corners of varying degrees of sharpness in a floating gate, as provided in an embodiment of this application. Figure 7 As shown, the sidewall edges at both ends of the floating gate form outwardly extending sharp angles, namely a first sharp angle 131 at the right end and a second sharp angle 132 at the left end. From Figure 7 As can be seen, the two sharp corners have significantly different radii of curvature, with the second sharp corner 132 being more pointed and the other (the first sharp corner 131) being relatively gentler. This asymmetrical tip design brings greater flexibility and finer erase control to the operation of the semiconductor structure, enabling it to adapt to different erase voltages and further optimizing the applicability and reliability strategies of the device.

[0075] Specifically, the sharpness of the tip of the floating gate directly determines its local electric field strength. A sharper tip has a smaller radius of curvature, resulting in a stronger electric field concentration effect under the same applied voltage. Therefore, in this embodiment, this asymmetric tip design provides more optional modes for the operation of the semiconductor structure. For example, in some embodiments, a fast erase mode can be performed: that is, a voltage is applied to the erase gate corresponding to the sharper tip. In this case, the sharper tip plays a dominant role. It generates an extremely strong local electric field under voltage, which can efficiently drive electron tunneling and quickly extract a large number of electrons from the floating gate, achieving fast and thorough erasure. This is suitable for scenarios with stringent requirements for erase time. In some embodiments, for power consumption considerations, device reliability management, or when fine adjustment of the threshold voltage is required, a voltage can be applied to the erase gate corresponding to the less sharp tip. At this voltage, excessively sharp corners may cause over-erasing or excessive stress on the dielectric layer due to an overly strong electric field, while gentler corners can generate a sufficient electric field for effective tunneling, while ensuring that the erasing operation is carried out smoothly and in a controlled manner.

[0076] Furthermore, in other embodiments, the asymmetric tip design can also help the semiconductor structure adapt to different voltage levels. For example, in some scenarios, the voltage level that can be provided for the erase gate may be relatively low. In this case, it can be connected to the erase gate corresponding to the sharper tip to maximize the electric field strength. Conversely, in other scenarios, the voltage level that can be provided for the erase gate may be high, which could easily affect the stability of the device. In this case, it can be connected to the erase gate corresponding to the less sharp tip to stabilize the electric field strength as much as possible.

[0077] Of course, a semiconductor structure with two sharp corners of different degrees on such a floating gate can also have voltage applied to its two erase gates at the same time, and this application does not limit this.

[0078] It is readily understood that the combination of sharp corners with varying degrees of sharpness provided in the embodiments of this application essentially integrates two erase valves with different sensitivities into the semiconductor structure. This allows circuit designers or memory controllers to flexibly select different erase voltage schemes based on different operational requirements (such as speed priority or reliability priority), different device aging states, and even different memory block characteristics, thereby achieving a dynamic and optimal balance between erase speed, power consumption control, and oxide layer pressure.

[0079] Specifically, in some embodiments, on a first cross-section of the semiconductor structure, the inner contour of the erase gate can match and wrap around the sharp corner contour formed by the recessed sidewall edge of the end of the floating gate.

[0080] For example, please refer to Figure 7 Regarding the positional relationship between the first sharp corner 131, the second sharp corner 132, and the erase gate in this embodiment, it can be clearly observed from the first cross-section of the semiconductor structure that the inner contour of the erase gate and the sharp corner contour formed by the recessed edge of the floating gate end sidewall exhibit a highly matched and tightly wrapped relationship in geometry. That is, the inner surface of the erase gate is almost parallel to and closely attached to the bevel of the sharp corner, and a very small gap is formed near the top (the sharpest point) of the sharp corner, thus outlining a slit-like region with a matching shape between the two. The advantage of doing so is that, since the two conductor surfaces (the sharp corner and the inner side of the erase gate) are parallel to each other with a very small gap, according to the principle of parallel plate capacitors, under the erase voltage, the electric field will be almost completely uniform and vertically distributed between the two surfaces. At the tip of the sharp corner, due to the extremely small radius of curvature, the electric field lines will be highly concentrated here, producing a very strong local electric field enhancement effect. In this way, the concave profile of the erased gate ensures that this enhanced electric field is efficiently guided and applied to the tip of the floating gate as much as possible, thereby improving the probability and efficiency of electron tunneling.

[0081] It should be pointed out that, Figure 7In the current embodiment, at the same end of the floating gate, in addition to the first sharp corner 131 and the second sharp corner 132 formed at the upper edge, sharp corners are also formed at the lower edge of the sidewall recessed area due to abrupt geometric changes, namely the third sharp corner 133 and the fourth sharp corner 134. In this embodiment, the erase gate does not effectively wrap around or closely adhere to these two lower edge sharp corners. This means that during the erase operation, although a certain electric field enhancement may occur at the third sharp corner 133 and the fourth sharp corner 134 due to the curvature effect, the electric field at these locations is relatively weak and its distribution direction may be undesirable due to the lack of direct coupling and guidance from the erase gate electrodes at close range, resulting in a limited contribution to the overall erase efficiency.

[0082] In this regard, this application provides a preferred embodiment, for example, please refer to Figure 8 , Figure 8 This illustration shows a schematic diagram of a semiconductor structure in an embodiment of this application, where the erase gate can wrap around the sharp corner of the lower edge of the floating gate. Figure 8 As shown in the embodiment of this application, the bottom of the erase gate extends towards the center of the floating gate to wrap around the lower edge sharp corners (i.e., the third sharp corner 133 and the fourth sharp corner 134) formed by the recessed sidewall edge of the end of the floating gate. Thus, the outline of the erase gate is designed to not only wrap around the two sharp corners of the upper edge, but also extend downwards at its bottom, so that its inner surface is also closely and parallel to or wraps around the third sharp corner 133 and the fourth sharp corner 134 of the lower edge with a very small spacing. Under the erase voltage, multiple sharp corners of the upper and lower edges of the floating gate can simultaneously form a strong electric field coupling with the erase gate, which is equivalent to providing more parallel channels for electron tunneling. This enables higher overall erase efficiency at the same voltage, or the same erase speed at a lower voltage, further optimizing energy efficiency. It should be noted that, in order to maximize the erase effect of the erase gate, the structure extending towards the floating gate at its upper and lower ends can maintain a certain thickness, such as between half and two-thirds of the thickness of the main body of the floating gate. This application does not limit the specific value.

[0083] This application also provides a method for manufacturing a semiconductor structure, used to manufacture the semiconductor structure described in the foregoing embodiments. Please refer to... Figure 9 , Figure 9 A schematic flowchart illustrating a method for manufacturing a semiconductor structure according to an embodiment of this application is shown. Figure 9 As shown, the method mainly includes: Step 910: Provide a substrate; Step 920: Form a first insulating layer on top of the substrate; wherein the end of the first insulating layer has a step extending away from the substrate; Step 930: Deposit polysilicon over the first insulating layer to form a floating gate; wherein the ends of the floating gate are lifted away from the substrate by the steps of the first insulating layer; Step 940: Etch the sidewall of the raised end of the floating gate so that the sidewall is recessed toward the center of the floating gate, forming an outwardly extending sharp corner at the edge of the sidewall; Step 950: Form a second insulating layer on the surface of the floating gate; Step 960: Deposit polysilicon on the outside of the sharp corner to form an erase gate.

[0084] The semiconductor structure manufacturing method provided in this application embodiment is used to manufacture the aforementioned semiconductor structure as a memory cell of a flash memory device.

[0085] Reference Figure 9 The flowchart shown first illustrates the process of providing a semiconductor substrate, which can be P-type silicon (or N-type silicon). In some embodiments, necessary structures such as well regions and shallow trench isolation trenches can be pre-formed on the substrate. Next, an insulating layer, namely the first insulating layer, is formed on top of the substrate; this layer serves as a tunneling oxide layer. Unlike conventional practices, in this embodiment, the first insulating layer undergoes a special shaping process, with its ends intentionally configured to have a stepped structure extending away from the substrate. Exemplarily, this stepped structure can be achieved through processes such as local oxidation, selective etching and regrowth, or using a stacked dielectric with different etching selectivity followed by anisotropic etching; this application does not impose any limitations on this. The formation of the steps lays the foundation for the subsequent geometric deformation of the floating gate ends.

[0086] Subsequently, a polycrystalline silicon layer is deposited above the first insulating layer using methods such as chemical vapor deposition, and patterned by photolithography and etching to form a floating gate. Due to the presence of the step at the end of the first insulating layer below, the corresponding end of the formed floating gate is naturally lifted, thereby creating a vertical distance between it and the surface of the substrate. In this embodiment, the sidewalls of the lifted end of the floating gate are anisotropically or selectively etched to remove a portion of the material from the sidewalls, thus creating a recess towards the center of the floating gate. This recess will cause the edge of the end sidewall of the floating gate to form a sharp corner with a certain radius of curvature, extending outward (i.e., away from the main body of the floating gate). This sharp corner is the core shape for achieving efficient electric field concentration.

[0087] After forming the floating gate and its sharp corners, another insulating layer, the second insulating layer, is formed on its surface. This layer can employ a high-quality composite dielectric, such as a silicon oxide-silicon nitride-silicon oxide stacked structure, specifically formed sequentially through processes such as thermal oxidation and chemical vapor deposition. The second insulating layer serves as an insulating and tunneling barrier between the floating gate and the subsequent erase gate. On the surface where all the above structures have been completed, polysilicon is deposited and patterned again using photolithography and etching to form the erase gate on the outside of the sharp corners. The pattern of the erase gate is precisely designed so that its inner contour is as close as possible to and surrounds the sharp corners of the floating gate to maximize the capacitive coupling and electric field interaction between them. At this point, a memory cell containing a floating gate with raised ends, sharp sidewall corners, and a closely adjacent erase gate is manufactured.

[0088] The significant advantages and unexpected technical effects of this method lie in its ability to precisely control the three-dimensional geometry of the floating gate without significantly increasing process complexity, through ingenious step sequence and process integration. The synergistic manufacturing of steps and sharp corners optimizes the semiconductor structure's performance in simultaneously improving erase speed and operational efficiency, as well as enhancing the durability and reliability of flash memory devices. The entire manufacturing process is compatible with mainstream technologies, ensuring that the semiconductor structure can be efficiently and reliably integrated into various embedded chips.

[0089] Specifically, in some embodiments, a first insulating layer is formed on top of the substrate, including: A first insulating dielectric layer is deposited on top of the substrate; The first insulating medium is etched to form steps; A second insulating dielectric layer is formed above the substrate and the step to obtain the first insulating layer.

[0090] In this application embodiment, a specific implementation method for forming a first insulating layer on top of a substrate is provided. This method is a meticulously designed process sequence for constructing a composite dielectric layer with a specific step morphology stepwise, which aims to accurately achieve the requirements for step geometry and insulating layer quality in the aforementioned structure. The specific steps are as follows.

[0091] First, a first insulating dielectric layer is deposited on top of the substrate. This step is fundamental to the construction of the entire first insulating layer. The first insulating dielectric can be silicon dioxide or other insulating materials; this application does not limit this choice. Specifically, the first insulating dielectric can be generated on the surface of the substrate using methods such as thermal oxidation or chemical vapor deposition. This dielectric layer will constitute the main part of the subsequent step structure, and its initial thickness needs to be precisely controlled because it directly determines the height of the step. For example, please refer to... Figure 10 , Figure 10This illustration shows a schematic diagram of a semiconductor structure after a first insulating medium is generated on the surface of a substrate, as provided in an embodiment of this application. Figure 10 In the first insulating medium 1010, it is laid flat on the surface of the substrate and has a certain thickness.

[0092] Next, the first insulating medium is etched to form steps. In this embodiment, a pattern of the area to be retained can be defined on the deposited first insulating medium using photolithography. For example, please refer to... Figure 11 , Figure 11 This illustration shows a schematic diagram of a semiconductor structure after a photoresist with a preset pattern is coated on the surface of a first insulating medium, as provided in an embodiment of this application. Figure 11 The semiconductor structure shown requires the fabrication of two steps, therefore, a first photoresist 1020 is coated at both ends of the first insulating medium. The specific coverage area of ​​the first photoresist 1020 can be flexibly set according to requirements, and this application does not impose any restrictions on it.

[0093] Subsequently, the first insulating dielectric region not protected by photoresist is selectively removed. By precisely controlling the etching process, it can be ensured that the first insulating dielectric is completely etched through to expose the underlying substrate surface in specific end regions, while the dielectric is completely preserved in other regions. This creates a nearly vertical step sidewall with a significant height difference at the end of the first insulating dielectric. The height of this step is determined by the thickness of the first insulating dielectric deposited in the first step. For example, please refer to... Figure 12 , Figure 12 This illustration shows a schematic diagram of a semiconductor structure after etching a first insulating medium, as provided in an embodiment of this application. Figure 12 As shown, after etching the first insulating medium and removing the photoresist, the portion not covered by the first photoresist 1020 will be etched away, leaving a stepped structure, such as... Figure 12 The initial step is 1011.

[0094] After obtaining the step, a second insulating dielectric layer can be formed on top of the substrate and the step. The purpose of this step is to regenerate or deposit a completely new, continuous insulating material, i.e., the second insulating dielectric, on the entire structure that has been etched, exposing the substrate surface and the step. This second insulating dielectric can also be silicon dioxide, typically generated through processes such as thermal oxidation or in-situ vaporization (ISSG). When thermal oxidation is used, the exposed silicon substrate area is thermally grown to form high-quality silicon dioxide, while the step surface of the first insulating dielectric is further oxidized and thickened. The newly generated second insulating dielectric layer perfectly covers and conforms to the entire complex morphology of the step, including the top, vertical sidewalls, and bottom exposed substrate area of ​​the step, thus forming a continuous, seamless insulating layer. Finally, the previously retained first insulating dielectric (i.e., the step) and the newly grown second insulating dielectric together constitute the complete first insulating layer. In the step region, because the second insulating dielectric covers the etched step structure, the total insulating layer thickness is significantly increased, thereby achieving the goal of lifting the end of the subsequent floating gate away from the substrate. For example, please refer to... Figure 13 , Figure 13 This illustration shows a schematic diagram of a semiconductor structure after a second insulating dielectric is formed above the substrate and the step, as provided in an embodiment of this application. Figure 13 As shown, the second insulating medium 1030 covers the substrate and the steps in its entirety. The central region acts as a tunneling oxide layer. The original steps are covered by the second insulating medium 1030, forming a first insulating layer with a stepped structure.

[0095] It should be noted here that, Figures 10 to 13 In order to easily distinguish the first insulating medium and the second insulating medium, different pattern markings are used. In fact, the same material (such as silicon dioxide) can be used, only the forming process is different.

[0096] It is understood that the method for forming the first insulating layer provided in this application, through a three-step process of deposition-etching-regeneration growth, ingeniously constructs a composite insulating layer with steps at local ends. This method not only achieves the desired geometry, but also ensures, through the second growth step, that the medium serving as the tunneling oxide layer portion (i.e., the second insulating medium covering the substrate) has excellent quality and interface properties.

[0097] Specifically, in some embodiments, polysilicon is deposited over the first insulating layer to form a floating gate, including: Polycrystalline silicon is deposited above the first insulating layer; A pre-designed photoresist pattern is coated on top of the polycrystalline silicon. Remove the polysilicon above the first insulating layer that is not covered by photoresist to form a floating gate.

[0098] In this embodiment, the step of depositing polysilicon over the first insulating layer to form a floating gate can also be achieved through photolithography and etching patterning processes. This will be described and explained below.

[0099] After obtaining the first insulating layer, polycrystalline silicon is first deposited on top of the first insulating layer. In this step, a thin film of polycrystalline silicon is uniformly deposited on the entire surface of the completed first insulating layer using processes such as low-pressure chemical vapor deposition. This layer of polycrystalline silicon will serve as the conductive material for the floating gate. For example, please refer to... Figure 14 , Figure 14 This illustration shows a schematic diagram of a semiconductor structure after polysilicon deposition above a first insulating layer, as provided in an embodiment of this application. Figure 14 As shown, the first polysilicon 1410 is laid flat on the surface of the first insulating layer 120 and has a certain thickness. Since the end of the first insulating layer 120 has a step extending away from the substrate, the end of the first polysilicon 1410 is also lifted away from the substrate by the step of the first insulating layer.

[0100] Next, a photoresist with a pre-defined pattern is coated onto the polysilicon, defining the areas of the pattern to be retained on the deposited polysilicon. For example, please refer to... Figure 15 , Figure 15 This illustration shows a schematic diagram of a semiconductor structure after a photoresist with a preset pattern is coated on the surface of polycrystalline silicon, as provided in an embodiment of this application. Figure 15 In the first polysilicon 1410, the top middle area is coated with the second photoresist 1420, while the sides are not coated. By etching the sides, the position and space for making the erase gate can be reserved.

[0101] Etching the areas not covered by the second photoresist 1420 removes excess polysilicon and the outer portion of the first insulating layer, yielding a basic floating gate structure. It should be noted that, in this embodiment, to minimize the etching of the step structure of the first insulating layer, the second photoresist 1420 needs to completely cover the steps of the first insulating layer in the vertical direction. For example, in some embodiments, their edges may overlap in the vertical direction.

[0102] For example, please refer to Figure 16 , Figure 16 This illustration shows a schematic diagram of a semiconductor structure after etching polysilicon and a first insulating layer, as provided in an embodiment of this application. Figure 16 As shown, after etching the first polysilicon 1410, the basic floating gate 130 is obtained.

[0103] Specifically, in some embodiments, a dry etching process can be used when etching the first polysilicon 1410. Dry etching is an etching technique performed in a gas phase or plasma environment. Compared with traditional wet etching (using chemical solutions), it has outstanding advantages such as strong anisotropy, high resolution, precise process control, and good environmental compatibility. In the embodiments of this application, a specific reactive gas (e.g., using chlorine-based gas as the main etchant) can be used to etch the first polysilicon 1410. Because this etching method has good anisotropy, it can ensure that the planar pattern of the second photoresist 1420 mask is transferred to the first polysilicon 1410 with high fidelity, forming a floating gate 130 with clear boundaries and vertical sidewalls.

[0104] After dry etching, in this embodiment, the sidewalls of the raised end of the floating gate also need to be etched to form sharp corners at the sidewall edges. This process can be performed using wet etching, a process that utilizes a chemical solution to react with the material to be etched, selectively removing the material by generating soluble or volatile products. Unlike anisotropic dry etching, typical wet etching is isotropic, meaning its etching rate is essentially equal in all directions. In this embodiment, a predetermined amount of polysilicon material can be removed by etching the basic floating gate 130 structure, causing the originally vertical sidewalls to uniformly concave inwards (towards the center of the floating gate). As etching proceeds, at the sidewall edges, due to the convergence of corrosion in two directions, the material is rapidly removed, naturally forming a sharp shape with a small radius of curvature, thus obtaining the desired sharp corner.

[0105] For example, please refer to Figure 17 , Figure 17 This illustration shows a schematic diagram of a semiconductor structure after etching the end sidewalls of a floating gate, as provided in an embodiment of this application. For example... Figure 17 As shown, after etching the end sidewall of the base floating gate 130, outwardly extending sharp corners can be formed at the edge of the sidewall, such as the first sharp corner 131 at the upper edge of the right end.

[0106] It should be noted that, in some embodiments, the sidewalls at the two ends of the raised floating gate can be etched to different degrees, so that the sharpness of the outwardly extending corners formed by the edges of the two sidewalls is different, thereby obtaining a shape like... Figure 7 The structure shown. Here, different degrees of etching can be achieved by adjusting at least one of the concentration of the etching solution, temperature, or etching time. For example, a higher concentration solution can be used to etch one side to form a sharper corner, while a lower concentration solution can be used to etch the other side to form a relatively gentler corner. This application does not limit this.

[0107] Specifically, in some embodiments, a second insulating layer is formed on the surface of the floating gate, including: A third insulating dielectric layer is formed on the surface of the floating gate through a low-temperature oxidation process; A layer of mixed fourth insulating medium is deposited on the surface of the third insulating medium to obtain the second insulating layer.

[0108] In this embodiment, the step of forming a second insulating layer on the surface of the floating gate employs a composite process combining low-temperature oxidation and chemical vapor deposition to construct a high-quality composite dielectric layer. The advantage of this method is that a third insulating dielectric layer is first grown on the surface of the floating gate in a gentle manner with minimal impact on the edges, followed by the deposition of a dielectric layer with specific functions, together forming a second insulating layer that simultaneously satisfies excellent insulation, high dielectric constant, and good charge-blocking properties.

[0109] Specifically, in this embodiment, a third insulating dielectric layer is first formed on the surface of the floating gate using a low-temperature oxidation process. This low-temperature oxidation process refers to oxidizing the thin layer of polycrystalline silicon on the surface of the floating gate at a relatively low temperature (e.g., using thermal oxidation or oxidation assisted by oxygen-containing plasma), thereby growing a silicon dioxide film in situ. The reason for using a "low-temperature" process is to prevent excessively high temperatures (e.g., conventional high-temperature furnace oxidation) from adversely affecting the doping distribution and geometry of the already formed floating gate (especially newly formed fine sharp corners), such as impurity re-diffusion, stress-induced defects, or deformation. This in-situ grown silicon dioxide layer (third insulating dielectric) has good interface characteristics with the floating gate polycrystalline silicon, with few defects and strong adhesion. It provides a stable, high-quality surface for subsequent dielectric layer deposition and serves as the first charge barrier and insulating barrier. For example, please refer to... Figure 18 , Figure 18 This illustration shows a schematic diagram of a semiconductor structure after a third insulating dielectric is formed on the surface of a floating gate, as provided in an embodiment of this application. Figure 18 As shown, the third insulating medium 1810 is completely covered on the floating grid 130. The two have a good shape fit. The low-temperature oxidation process has little impact on the structural stress of the floating grid 130, which helps to maintain the sharp corners formed by the end sidewalls of the floating grid 130.

[0110] Next, a layered fourth insulating medium is deposited on the surface of the third insulating medium to obtain the second insulating layer (comprising the third and fourth insulating media). This step aims to further enhance the overall performance of the second insulating layer. Here, the layered fourth insulating medium refers to a composite dielectric film formed by chemical vapor deposition (CVD) with a non-monolithic chemical composition and structure. For example, the fourth insulating medium may include silicon dioxide and silicon nitride, with the atomic ratios of silicon, nitrogen, and oxygen adjustable within a certain range, thus combining the excellent interfacial properties of silicon dioxide with the high dielectric constant and strong resistance to charge penetration of silicon nitride. For instance, a silicon dioxide layer can be first formed on the surface of the third insulating medium using CVD, and then a silicon nitride layer can be formed on top of the silicon dioxide layer using CVD to obtain the fourth insulating medium. For example, please refer to... Figure 19 , Figure 19 This illustration shows a schematic diagram of a semiconductor structure after depositing a fourth insulating medium on the surface of a third insulating medium, as provided in an embodiment of this application. Figure 19 As shown, the fourth insulating dielectric 1820 completely covers the third insulating dielectric 1810, and the composite film formed by their stacking constitutes the complete second insulating layer. This composite structure design of a high-quality interface layer + a functionally adjustable layer ensures reliable interface quality with the floating gate 130, reducing energy barrier fluctuations during charge tunneling; and through the high dielectric constant of the upper dielectric layer, it achieves a larger effective capacitance at the same physical thickness, enhancing the capacitive coupling between the floating gate and the erase gate, which is beneficial for reducing the erase operation voltage. It should be noted that in this embodiment, the fourth insulating dielectric can also be stacked on the exposed surface of the substrate.

[0111] In the embodiments of this application, Figure 19 Based on the structure shown, the erase gate can be further fabricated by depositing polysilicon on the current second insulating layer. For example, please refer to... Figure 20 , Figure 20 This illustration shows a schematic diagram of a semiconductor structure after polysilicon deposition on a second insulating layer, as provided in an embodiment of this application. Figure 20 As shown, the second polysilicon 2010 is stacked on the second insulating layer.

[0112] Next, a photoresist with a preset pattern can be coated onto the second polysilicon 2010 to define the area pattern to be retained on the deposited polysilicon. For example, please refer to... Figure 21 , Figure 21 This illustration shows another semiconductor structure after coating a polycrystalline silicon surface with a pre-defined pattern of photoresist, as provided in an embodiment of this application. Figure 21In this embodiment, a third photoresist 2020 with a preset pattern is used to generate an erase gate. In this application embodiment, erase gates can be fabricated on both sides of the floating gate. Therefore, the third photoresist 2020 covers both sides of the second polysilicon 2010. By etching the second polysilicon 2010 not covered by the third photoresist 2020, the structure of the erase gate can be obtained. For example, please refer to... Figure 22 , Figure 22 This illustration shows a schematic diagram of a semiconductor structure after etching to obtain the erased gate, as provided in an embodiment of this application. Next, other dielectric layers and the control gate are formed using conventional sidewall processes, source / drain implantation processes, interlayer dielectric layer processes, and contact processes, resulting in a structure as shown below. Figure 2 The structure shown.

[0113] Specifically, in the embodiments of this application, if it is necessary to manufacture a structure as shown in the figure... Figure 8 The semiconductor structure shown can be formed by etching a shorter polysilicon layer on the step above the first insulating layer, away from the floating gate. When the control gate is fabricated in the subsequent process, the polysilicon stacked on the control gate and the polysilicon remaining on the step are connected together to obtain an erase gate structure that can wrap the lower edge sharp corner formed by the recess of the sidewall edge of the end of the floating gate.

[0114] The following describes and explains the usage method and working principle of the semiconductor structure provided in the embodiments of this application.

[0115] The semiconductor structure provided in this application embodiment can be used as a storage cell in a flash memory device to store or erase data. For example, the operating conditions for programming / erasing / reading of this semiconductor structure are shown in Table 1 below.

[0116] Table 1

[0117] In Table 1, WL (Word Line) represents the word line, used to control the select transistor (SG) in the memory cell, determining whether to select this memory cell for reading or writing. CG represents the control gate, and EG represents the erase gate. Bulk represents the body terminal, connected to the N-type well, used to apply a specific bias voltage (such as the positive voltage during erasure) to assist charge movement or suppress leakage current. BL (Bit Line) represents the bit line, which is the data transmission channel. During programming, it is usually connected to a negative voltage (such as -5V) to create a potential difference with the high voltage of the floating gate; during reading, it is used to sense current changes. Source represents the source, which is the source of the memory cell current.

[0118] Specifically, during programming, a 10V voltage is applied to the control gate of the semiconductor structure. Through capacitive coupling, a high voltage can be coupled out onto the floating gate. BL is connected to -5V, WL is open, and the BL potential is conducted to the drain of the floating gate. The drain is reverse-biased and depleted from the substrate, creating a lateral electric field in the depletion region. A longitudinal electric field of approximately 15V exists between the drain and the floating gate. Under the influence of these lateral and longitudinal electric fields, the energy bands at the drain junction surface bend. When the band bending exceeds the band gap of silicon, band-to-band tunneling (BTBT) occurs. The generated electrons are attracted by the strong electric field of the floating gate, overcome the potential barrier of the tunneling oxide layer, and are injected into the floating gate, thus completing the programming operation.

[0119] For example, please refer to Figure 23 , Figure 23 An embodiment provided in this application is shown. Figure 5 The diagram shows the electron transfer that occurs during programming in a semiconductor structure. The arrows in the diagram indicate the direction of electron migration. It can be seen that during the programming stage, electrons travel from the active region to the floating gate through the tunneling effect, thus realizing the writing of data.

[0120] During erasure, a voltage can be applied to the erasure gate. A strong electric field exists at the sharp corner of the area opposite the erasure gate and the floating gate. Under the action of the electric field, FN tunneling (Fowler-Nordheim tunneling) will occur at the sharp corner, which will remove the electrons stored in the floating gate and complete the erasure operation.

[0121] For example, please refer to Figure 24 , Figure 24 An embodiment provided in this application is shown. Figure 5 The diagram illustrates electron transfer during the erasure process in a semiconductor structure. The arrows indicate the direction of electron migration. It shows that during the erasure phase, electrons tunnel from the floating gate to the erase gate, thus erasing the data. Due to the effect of the sharp electric field, tunneling primarily occurs at the pointed corners of the floating gate.

[0122] The semiconductor structure and manufacturing method provided in this application, through the unique synergistic design of steps, sharp corners, and erase gates, achieve synergistic optimization and significant improvement in the core performance indicators of flash memory devices. Its unexpected technical effects are specifically reflected in: 1. During the erase operation, the strong electric field concentration effect generated by the sharp corner of the floating gate greatly improves the efficiency of electrons tunneling through the FN gate to the erase gate. This allows for a significant increase in the erase speed and enables the operation to be completed at a lower voltage, thereby reducing overall power consumption and alleviating the design pressure of high-voltage circuits.

[0123] 2. The step of the first insulating layer raises and isolates the high electric field floating gate sharp corner region, effectively suppressing the longitudinal coupling and stress impact of the erase electric field on the underlying tunneling oxide layer, and accurately guiding the unexpected electron tunneling path to the floating gate-erasure gate interface, fundamentally delaying the degradation of the tunneling oxide layer, and significantly enhancing the device's durability and data retention capability.

[0124] 3. The dual erase gate and adjustable sharp angle design further improve the uniformity of erasure, narrow the threshold voltage distribution, and increase the flexibility of the operating mode, allowing the erasure strategy to be dynamically adjusted according to the reliability status or performance requirements.

[0125] In summary, the technical solution provided in this application optimizes the charge storage and erasure path at the device physical level without significantly increasing process complexity. It can balance the inherent contradiction between improving erasure efficiency and extending service life, providing a practical and effective solution for realizing advanced non-volatile memories with high speed, high durability, and high reliability.

[0126] In some alternative embodiments, the functions / operations mentioned in the block diagrams may not occur in the order shown in the operation diagrams. For example, depending on the functions / operations involved, two consecutively shown blocks may actually be executed substantially simultaneously, or the blocks may sometimes be executed in reverse order. Furthermore, the embodiments presented and described in the flowcharts of this application are provided by way of example to provide a more comprehensive understanding of the technology. The disclosed methods are not limited to the operations and logic flows presented herein. Alternative embodiments are contemplated in which the order of various operations is changed and sub-operations described as part of a larger operation are executed independently.

[0127] In the foregoing description of this specification, the references to terms such as "one embodiment," "another embodiment," or "some embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0128] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

[0129] The above is a detailed description of the preferred embodiments of this application, but this application is not limited to the embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of this application, and these equivalent modifications or substitutions are all included within the scope defined by the claims of this application.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; A first insulating layer is disposed on the top of the substrate, and the end of the first insulating layer has a step extending away from the substrate; A floating gate is disposed on top of the first insulating layer. The end of the floating gate is raised away from the substrate by the step of the first insulating layer, and the sidewall of the raised end of the floating gate is recessed towards the center of the floating gate to form an outwardly extending sharp corner at the edge of the sidewall. An erasing grid is provided on the outside of the sharp corner; the bottom of the erasing grid extends toward the center of the floating grid to cover the lower edge sharp corner formed by the recess of the sidewall edge of the end of the floating grid; A second insulating layer is disposed between the floating gate and the erasure gate.

2. A semiconductor structure according to claim 1, characterized in that, The substrate includes an active region; On a first cross-section of the semiconductor structure, the main body portion of the floating gate covers the active region in a vertical direction; wherein, the first cross-section is a cross-section perpendicular to a first direction of the substrate in a top view and passing through the center point of the floating gate, and the main body portion of the floating gate is the portion other than the end that is raised by the step.

3. A semiconductor structure according to claim 2, characterized in that, The active region includes a doped region, and the doped region leads out the source and drain of the semiconductor structure; On the second cross-section of the semiconductor structure, the floating gate and the doped region do not overlap in the vertical direction; Wherein, the second cross section is a cross section that is perpendicular to the substrate in a second direction under the top view and passes through the active region.

4. A semiconductor structure according to claim 1, characterized in that, Both ends of the first insulating layer have steps extending away from the substrate, and the sidewall edges of both ends of the floating gate form sharp corners extending outward. The number of erase gates is two, and each erase gate is located outside one of the corners.

5. A semiconductor structure according to claim 4, characterized in that, The sharpness of the outward-extending angles of the two sidewalls differs.

6. A semiconductor structure according to claim 2, characterized in that, On a first cross-section of the semiconductor structure, the inner contour of the erase gate matches the sharp corner contour formed by the recessed sidewall edge of the end of the floating gate, and encloses the sharp corner contour.

7. A method for manufacturing a semiconductor structure, characterized in that, Includes the following steps: Provide a substrate; A first insulating layer is formed on top of the substrate; wherein the end of the first insulating layer has a step extending away from the substrate; Polysilicon is deposited over the first insulating layer to form a floating gate; wherein the ends of the floating gate are raised away from the substrate by the steps of the first insulating layer; The sidewall of the raised end of the floating gate is etched to make the sidewall recessed toward the center of the floating gate, and to form an outwardly extending sharp corner at the edge of the sidewall. A second insulating layer is formed on the surface of the floating gate; Polysilicon is deposited on the outer side of the sharp corner to form an erase gate; Wherein, forming a first insulating layer on top of the substrate includes: A first insulating dielectric layer is deposited on top of the substrate; The first insulating medium is etched to form the step; A second insulating medium is formed above the substrate and the step to obtain the first insulating layer.

8. The method for manufacturing a semiconductor structure according to claim 7, characterized in that, The formation of a second insulating layer on the surface of the floating gate includes: A third insulating medium is formed on the surface of the floating gate by a low-temperature oxidation process; A fourth insulating medium is deposited on the surface of the third insulating medium to obtain the second insulating layer.

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