Method and system for processing Z-direction anti-overload structure of MEMS chip

Abstract

The invention belongs to the technical field of micro electro mechanical systems, and discloses a processing method and system for a Z-direction anti-overload structure of an MEMS chip, and the method comprises the steps: sequentially defining a Z-direction stop block region on one surface of a substrate wafer through a two-time patterning technology, and carrying out the etching to form a cavity surrounding the Z-direction stop block region; then synchronously etching the bottom of the cavity and the stop block to form an accurately controlled motion gap; manufacturing an electrode via hole in the other surface of the wafer, and then performing overall thermal oxidation to form an insulating layer; and finally, bonding with a structural wafer prepared with a movable structural layer, so that the Z-direction movement of the movable structure is limited in the gap. The system comprises a graphical processing module, a through hole processing module, a thermal oxidation module and a bonding module. According to the invention, the stop block and the movable structure layer which are integrally formed are bonded, so that precise mechanical limiting of the Z-direction movement stroke is realized, the reliability of the MEMS device in a high-impact environment is greatly improved, and meanwhile, smooth lead-out of an electrode is ensured.

Description

Technical Field

[0001] This invention belongs to the field of microelectromechanical systems (MEMS) technology, specifically relating to a Z-axis overload-resistant structure for improving the survivability of MEMS devices, especially inertial sensors such as accelerometers and gyroscopes, under severe impact environments, as well as its processing method and dedicated processing system. Background Technology

[0002] In the field of MEMS, developing MEMS chips with high shock resistance can not only improve the system's perception and control capabilities in extreme environments, but also promote the development of MEMS technology towards high reliability, multi-physics coupling and high performance, becoming an important technical support for the intelligent upgrading of high-end equipment.

[0003] In fabricating high-overload MEMS chips, advanced or improved MEMS manufacturing processes are typically employed to meet the demands for high strength, high reliability, and high dynamic response. These processes not only require high-precision microstructure fabrication but also ensure sufficient mechanical strength and impact resistance. Commonly used techniques include: deep reactive ion etching (DRIE), currently the most common technique for manufacturing high aspect ratio silicon structures, capable of deep etching (>100μm), high etching rate, good perpendicularity, and precise linewidth control; bulk silicon micromachining, which uses wet or dry etching to remove portions of the silicon substrate to form a three-dimensional structure; wet etching can create anisotropic structures (such as V-grooves); and bonding and packaging, where bonding processes connect the substrate to the sensitive structure to form a support, achieving structural encapsulation or interlayer connections through silicon-silicon bonding, glass-silicon bonding, anodic bonding, and other methods.

[0004] In chip fabrication, special attention must be paid to key factors such as the structure's impact resistance, release integrity, stress distribution control, and electrode lead-out reliability. For example... Figure 1 As shown, this Z-axis stop fabrication process design typically involves thick silicon etching, suspended mass blocks, multi-layer stacking, or bonding interfaces, making it more susceptible to issues such as etching uniformity, aspect ratio limitations, and release adhesion during manufacturing. Furthermore, Z-axis devices are often used to detect vertical acceleration, requiring high structural symmetry and sensitivity to parasitic stresses. Therefore, process parameters must be strictly controlled during thin film deposition, patterning, and etching release to ensure the structure does not fracture, collapse, or suffer fatigue damage under high impact. Simultaneously, the Z-axis electrode lead-out method (such as vias or back leads) must be compatible with the process to prevent electrical connection failures due to stress concentration or process mismatch. Reasonable design of the Z-axis structure and optimization of the process flow are key to achieving high performance and high reliability in high-overload MEMS chips. Summary of the Invention

[0005] The primary objective of this invention is to provide a method for fabricating a Z-axis overload-resistant structure. This method enables the precise integration and fabrication of a Z-axis mechanical restraint structure and a back electrode via on a single wafer, and achieves reliable packaging through bonding processes. It addresses the challenge of improving the impact resistance of the Z-axis structure while ensuring the lead-out of the via electrodes, minimizing the impact of high overload performance on chip precision. This provides a more comprehensive wafer-level MEMS chip Z-axis overload-resistant structure process solution for MEMS chip verification and product prototyping.

[0006] Another objective of this invention is to provide a dedicated processing system for implementing the above-described method, which should have the capabilities of high-precision patterning, deep silicon etching, and precision bonding.

[0007] Another object of the present invention is to provide a Z-direction overload resistant structure itself manufactured by the above method.

[0008] The technical solution of this invention is implemented as follows: In a first aspect, the present invention provides a method for fabricating a Z-axis overload-resistant structure for a MEMS chip, comprising the following steps: On one side of the substrate wafer, a Z-axis blocking block region is defined by a first patterning process that includes the first photolithography and the first etching. A cavity surrounding the Z-axis blocking block region is etched on one side of the substrate wafer using a second patterning process that includes a second photolithography and deep silicon etching. Simultaneous dry etching is performed on the bottom of the cavity and the Z-axis blocking block to form a movement gap of a preset height between the Z-axis blocking block and the bottom of the cavity; On the other side of the substrate wafer, an electrode via is formed that penetrates the substrate wafer; The substrate wafer is oxidized to form an insulating layer on the inner surface of the cavity, the surface of the moving gap, and the inner surface of the electrode via. The cavity side of the substrate wafer is bonded to a structural wafer with a movable structural layer, such that the movable structural layer is encapsulated within the cavity and its Z-axis movement is restricted by the Z-axis blocking block.

[0009] Its core steps include: S1: Substrate wafer preparation and oxidation. A single-crystal silicon substrate wafer is provided, which is cleaned according to standard procedures, and a silicon dioxide insulating layer with a thickness of 1~2μm is grown on both sides of it by thermal oxidation.

[0010] S2: Definition of Z-axis blocking region. The first photolithography is performed on the front side of the substrate wafer, with the photoresist pattern covering the area where the Z-axis blocking region will form. Using the photoresist as a mask, wet etching with buffered oxide etchant or reactive ion etching is used to remove the silicon dioxide from the exposed areas, exposing the silicon surface outside the blocking region.

[0011] S3: Cavity Region Definition and Etching. After removing the old photoresist, a second photolithography process is performed. This photolithography uses a complementary "yin-yang" pattern to the pattern from the first process. The photoresist pattern covers the Z-axis blocking block region and its surrounding area, exposing the large area to be etched into a cavity. Subsequently, deep reactive ion etching (DRIE) is performed to etch the exposed silicon with a high aspect ratio, forming a cavity with a depth of 80-90 μm.

[0012] S4: Formation of the motion gap. After removing all photoresist, without changing the process chamber or using a similar dry etching process, perform isotropic or near-isotropic silicon etching on the entire front side of the wafer. This step simultaneously etches the bottom of the cavity and the partially exposed Z-axis blocking block, precisely removing a 14~16μm thick silicon layer, thereby forming a precisely controlled motion gap between the top of the Z-axis blocking block and the bottom surface of the cavity.

[0013] S5: Protective Layer Growth and Backside Via Fabrication. The silicon dioxide on the front side of the wafer is removed, and a layer of silicon nitride or silicon oxide is grown as a protective layer using low-temperature chemical vapor deposition. The wafer is flipped over, and a third photolithography step is performed on its back side to define the electrode via regions. After etching away the protective layer and silicon dioxide in these regions, anisotropic wet etching (such as KOH or TMAH solution) is used to etch silicon, utilizing its crystal orientation dependence, until the vias are formed through the wafer to create tapered or vertical sidewalls.

[0014] S6: Insulating Layer Growth and Bonding. The protective layers on both sides of the wafer are removed, and the wafer is placed in a high-temperature oxidation furnace for overall thermal oxidation. A 2-4 μm thick silicon dioxide insulating layer is grown on all silicon surfaces, including the inner walls of cavities, the surfaces of moving gaps, and the inner walls of vias. Finally, the processed substrate wafer (as the cap wafer) is directly bonded to another structure wafer with pre-fabricated movable microstructures (such as mass blocks, beams, etc.) using silicon-to-silicon direct bonding to complete the packaging.

[0015] As a further technical solution of the present invention: the first patterning process specifically includes: After growing an oxide layer on one side of the substrate wafer, a first photolithography is performed to form a photoresist pattern covering the Z-axis blocking block region; Using the photoresist as a mask, the oxide layer is etched to expose the silicon surface outside the Z-axis blocking block region; After removing the photoresist, a second photolithography is performed to form a photoresist pattern covering the Z-direction blocking block region and its surrounding area, in order to protect the Z-direction blocking block region from being etched in subsequent deep silicon etching.

[0016] As a further technical solution of the present invention: the photolithography pattern used in the second photolithography and the photolithography pattern used in the first photolithography form a complementary pattern around the Z-direction blocking block region, jointly defining the final shape of the cavity.

[0017] As a further technical solution of the present invention: the depth of the synchronous dry etching is 14μm ~ 16μm, so as to precisely control the height of the moving gap; the depth of the deep silicon etching is 80μm ~ 90μm, so as to define the initial depth of the cavity.

[0018] As a further technical solution of the present invention: after the synchronous dry etching and before the electrode via fabrication, the following steps are also included: Remove the oxide layer on the front side of the substrate wafer and grow a protective layer; After etching the electrode vias, the protective layer is removed.

[0019] As a further technical solution of the present invention: the fabrication of the electrode via specifically includes: After growing an oxide layer or depositing a protective layer on the other side of the substrate wafer, photolithography is performed to define the via region; The oxide layer or protective layer of the via region is removed by etching, and silicon is etched using a wet anisotropic etching process until the substrate wafer is etched through to form a via.

[0020] As a further technical solution of the present invention: the bonding is silicon-silicon direct bonding, and the movement gap between the movable structural layer and the Z-direction blocking block after bonding is determined by the depth of the synchronous dry etching.

[0021] In a second aspect, the present invention provides a fabrication system for a Z-axis overload-resistant structure of a MEMS chip, comprising: The patterning module is used to perform photolithography and etching processes on the substrate wafer to sequentially form the Z-axis blocking block region, cavity and motion gap; A through-hole processing module is used to fabricate electrode vias on the other side of the substrate wafer; A thermal oxidation module is used to grow an insulating oxide layer on the surface of the substrate wafer after patterning and through-hole processing; A bonding module is used to align and bond the substrate wafer with a structural wafer having a movable structural layer to form a packaging structure with Z-axis motion restriction.

[0022] The system mainly includes: The patterning module integrates a coating machine, a lithography machine, a developing machine, and a dry etching machine. The dry etching machine is configured to perform high aspect ratio Bosch processes (for deep silicon etching) and isotropic etching processes (for forming motion gaps).

[0023] Through-hole processing module: including wet etching tank and its supporting temperature control and stirring system, which is specially designed for anisotropic etching of silicon based on crystal orientation to form back-side vias.

[0024] Thermal oxidation module: a high-temperature diffusion furnace used to grow high-quality silica insulating layers.

[0025] Bonding module: This is a wafer bonding machine with high-precision optical alignment and controllable pressure and temperature environment, used to achieve direct silicon-to-silicon bonding.

[0026] As a further technical solution of the present invention: the patterning processing module includes a dry etching device, which is configured to first perform high aspect ratio deep silicon etching to form the cavity, and then perform isotropic or near-isotropic silicon etching to simultaneously form the motion gap.

[0027] As a further technical solution of the present invention: the through-hole processing module includes an anisotropic wet etching equipment, which is used to form a tapered or vertically sidewalled electrode through-hole on the substrate wafer based on the crystal orientation-dependent etching principle.

[0028] Thirdly, the present invention provides a Z-axis overload resistant structure processed by the above method. The structure includes: A substrate wafer has a cavity on its front side and an integrally formed Z-axis blocking block at the center of the bottom of the cavity. There is a predetermined movement gap between the top of the blocking block and the bottom surface of the cavity. The back side of the substrate wafer is provided with a through electrode via; The inner wall of the cavity, the surface of the moving gap, and the inner wall of the through hole are covered with a thermally grown silicon dioxide insulating layer. A structural wafer is bonded to the substrate wafer via a bonding layer to seal the cavity. A movable structural layer is formed on the side of the structural wafer facing the cavity. The movable structural layer is disposed opposite to the Z-axis blocking block in the vertical direction, and its movement is limited to the height range of the movement gap.

[0029] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. Excellent overload resistance: The integrated Z-axis blocking block and the bonded movable structural layer achieve reliable mechanical hard limiting, which can effectively prevent excessive displacement and breakage of the movable structure under extremely high impact.

[0030] 2. Precise gap control: The moving gap is formed by synchronous dry etching technology, and its height is determined only by the etching time / depth. The control precision can reach the submicron level, which is far superior to the method of controlling by sacrificial layer or bonding spacing.

[0031] 3. High process integration: Mechanical limiting structures (blocks and gaps) and electrical interconnect structures (back-side vias) are simultaneously completed on a single substrate wafer, simplifying the process flow and improving manufacturing efficiency and yield.

[0032] 4. High reliability: The overall thermal oxidation forms a high-quality insulation layer with good coverage, ensuring reliable insulation between components within the cavity and good insulation filling of the vias. The silicon-silicon bonding strength is high, resulting in good hermeticity.

[0033] 5. Flexible design: By changing the layout design of the two photolithography processes, the shape, size, position of the Z-axis blocking block and the contour of the cavity can be flexibly adjusted to meet the design requirements of different MEMS devices.

[0034] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0035] Figure 1 This is a cross-sectional schematic diagram of the Z-axis overload-resistant structure and the movable structure layer after bonding.

[0036] Figure 2 This is a schematic cross-sectional view of the substrate wafer after cleaning and oxidation.

[0037] Figure 3 This is a cross-sectional schematic diagram after the Z-axis blocking block region was defined by the first photolithography.

[0038] Figure 4 This is a schematic cross-sectional view of the silicon body after etching silicon dioxide to expose the barrier block area.

[0039] Figure 5 This is a cross-sectional view after the second photolithography protection block is exposed and the cavity area is revealed.

[0040] Figure 6 This is a schematic cross-sectional view of the cavity formed by deep silicon dry etching.

[0041] Figure 7 This is a schematic cross-sectional view of the moving gap formed by synchronous dry etching.

[0042] Figure 8 This is a cross-sectional view after the protective layer has grown.

[0043] Figure 9 This is a cross-sectional view of the via area defined by photolithography on the back of the wafer.

[0044] Figure 10 This is a schematic cross-sectional view of the back electrode via formed by wet etching.

[0045] Figure 11 This is a cross-sectional schematic diagram after the protective layer has been removed and the entire structure has been thermally oxidized.

[0046] Figure 12 This is a schematic cross-sectional view of the final structure after bonding with the movable structural layer.

[0047] The figures are labeled as follows: 1-Schematic diagram of Z-direction stop and movable structure bonded together; 2-Z-direction stop and via structure layer; 3-movable structure layer; 4-metal electrode; 5-silicon dioxide; 6-photoresist; 7-protective layer. Detailed Implementation

[0048] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of the embodiments of this invention will be described in more detail below with reference to the accompanying drawings. In the drawings, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The described embodiments are some embodiments of this invention, but not all embodiments.

[0049] The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the invention, and should not be construed as limiting the invention.

[0050] Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this invention.

[0051] The following is in conjunction with the appendix Figure 1-12 The embodiments of the present invention will be described in detail below.

[0052] Example 1 This invention discloses the fabrication of a Z-axis overload-resistant structure for a high-g MEMS accelerometer. Step 1: Substrate preparation.

[0053] See Figure 2 A 4-inch, double-sided polished, 400μm thick N-type (100) single-crystal silicon wafer was selected as the substrate wafer 2. After RCA standard cleaning, it was thermally oxidized at 1100℃ in a humid oxygen atmosphere to grow a silicon dioxide layer 5 with a thickness of 1.5μm on each side.

[0054] Step 2: Define the Z-direction blocking block region.

[0055] See Figure 3Positive photoresist was spin-coated onto the front side of substrate wafer 2, and exposed and developed using the first photomask to form photoresist pattern 6. This pattern covers the circular area (100 μm in diameter) that will become the Z-axis blocking block in the future.

[0056] See Figure 4 Using photoresist 6 as a mask, reactive ion etching is employed to remove the silicon dioxide layer 5 in the exposed area, exposing the underlying silicon. Subsequently, oxygen plasma stripping and wet stripping solution are used to thoroughly remove the photoresist 6.

[0057] Step 3: Define and etch the cavity.

[0058] See Figure 5 Photoresist is then spin-coated again on the front side of the wafer, and a second "yin-yang plate" complementary to the first pattern is used for a second photolithography to form a new photoresist pattern 6. This pattern covers the Z-axis blocking block region and a 20μm wide ring around it, while exposing the large circular area that needs to be etched into a cavity.

[0059] See Figure 6 A deep reactive ion etching (DRIE) system was used, with photoresist 6 as a mask, to perform Bosch etching. Process parameters: SF6 etching cycle 8s, C4F8 passivation cycle 5s, total etching time approximately 15 minutes, etching a cavity with a depth of 85μm in the exposed area. After etching, photoresist 6 was removed.

[0060] Step 4: Create a movement gap.

[0061] See Figure 7 In the same dry etching apparatus, the process was switched to isotropic etching mode. Using pure SF6 gas, isotropic etching of silicon was performed at high power and pressure for approximately 2 minutes, precisely removing a 15μm thick layer of silicon. This process simultaneously lowered the bottom of the cavity and the height of the Z-axis blocking block, creating a 15μm high movement gap between them.

[0062] Step 5: Machining the back through hole.

[0063] See Figure 8 The entire silicon dioxide layer 5 on the front side of the wafer was removed using hydrofluoric acid buffer. Subsequently, a 0.5 μm thick silicon nitride protective layer 7 was deposited on both sides of the wafer by low-pressure chemical vapor deposition at 300 °C.

[0064] Flip the wafer, see Figure 9 Photoresist was spin-coated onto the back of the wafer, followed by a third photolithography step to define a circular via region with a diameter of 80 μm. The silicon nitride protective layer 7 and silicon dioxide layer 5 of the via region were then sequentially etched away using RIE to expose the silicon surface.

[0065] See Figure 10 The wafer was placed in a KOH solution with a temperature of 80°C and a concentration of 30% for anisotropic wet etching. Due to the different etching rates of the (100) and (111) crystal planes, after about 4 hours of etching, a tapered via with a sidewall tilt angle of 54.7° was formed, and finally the 400μm thick wafer was etched through.

[0066] Step 6: Overall oxidation and bonding.

[0067] See Figure 11 The silicon nitride protective layer 7 on both sides of the wafer is removed by hot phosphoric acid. The wafer is then placed in a high-temperature oxidation furnace at 1050°C for wet oxidation, during which a silicon dioxide insulating layer 5 with a thickness of 3 μm is grown on all silicon surfaces (including the inner walls of cavities, the surfaces of moving gaps, and the inner walls of vias).

[0068] See Figure 12 Another structural wafer with a pre-fabricated movable structural layer 3 consisting of a cantilever beam and a mass block is provided. The substrate wafer (as the cap wafer) prepared in this embodiment is directly bonded to the structural wafer in a vacuum environment using silicon-to-silicon bonding. Bonding conditions: initial alignment and bonding at room temperature, followed by anodic bonding at 400°C and 8000V to enhance strength (if the structural wafer is also silicon, high-temperature direct bonding is used). After bonding, the movable structural layer 3 is sealed within the cavity, and its Z-axis movement is restricted to a gap of 15μm. Finally, metal electrodes 4 are fabricated through vias to complete the device fabrication.

[0069] Industrial applicability: The Z-axis overload-resistant structure processing method and system provided by this invention has clear process steps and strong compatibility with standard MEMS processes. It can be used for mass production of high-reliability MEMS accelerometers, gyroscopes, pressure sensors, etc., and has extremely high application value in high-end industrial and military fields such as automotive airbags, missile guidance, and impact detection.

[0070] Example 2 This embodiment focuses on manufacturing a MEMS high-g accelerometer capable of withstanding impacts of over 20,000g, and describes in detail the entire processing process of its Z-axis overload-resistant structure.

[0071] Example: Fabrication of a Z-axis overload-resistant structure for a 20,000g high-impact MEMS accelerometer Step 1: Preparation and thermal oxidation of the substrate wafer Substrate selection: A single-crystal silicon wafer with a diameter of 150 mm (6 inches), a thickness of 400 ± 10 μm, double-sided polished, P-type <100> orientation, and a resistivity of 1-10 Ω·cm was selected as substrate wafer 2. The <100> orientation was chosen to obtain a precise 54.7° sidewall angle during subsequent KOH wet etching of the vias on the back side.

[0072] Cleaning: The silicon wafers are placed in the RCA standard cleaning line for thorough cleaning. The specific process is as follows: SPM cleaning: Treat with a solution of H2SO4:H2O2 = 3:1 (volume ratio) at 120°C for 10 minutes to remove organic residues.

[0073] DHF rinsing: Rinse for 30 seconds at 25°C with a 1% dilute hydrofluoric acid solution to remove the original oxide layer.

[0074] SC-1 cleaning: Treat with a solution of NH4OH:H2O2:H2O = 1:1:5 (volume ratio) at 75°C for 10 minutes to remove particulate contamination.

[0075] SC-2 cleaning: Treat with a solution of HCl:H2O2:H2O = 1:1:6 (volume ratio) at 75°C for 10 minutes to remove metal ion contamination.

[0076] Finally, rinse with ultrapure water and dry with high-purity nitrogen.

[0077] Thermal oxidation: The cleaned substrate wafer is placed in a horizontal atmospheric pressure diffusion furnace.

[0078] Oxidation conditions: At 1100℃, high-purity oxygen (flow rate: 2 L / min) and high-purity water vapor (generated by the combustion of hydrogen) are introduced to carry out wet oxygen oxidation.

[0079] Process monitoring: The oxide layer thickness is monitored online using a laser elliptic thickness gauge.

[0080] Objective: To grow a high-quality silicon dioxide layer with a thickness of 1.5 μm on each side of a silicon wafer. This layer serves as an ideal mask for subsequent wet and dry etching processes, and its structure is as follows: Figure 2 As shown. After oxidation, the total thickness of the silicon wafer is approximately 403 μm.

[0081] Step 2: First photolithography and oxide etching of the Z-axis blocking block region Coating: A positive photoresist (e.g., AZ®10XT) is spin-coated onto the front side of the substrate wafer (the side where the cavity will be processed later). A two-step spin-coating method is used: first, spin at 500 rpm for 10 seconds (spreading the photoresist), and then spin at 3000 rpm for 30 seconds (spin-coating), ultimately forming a photoresist layer 6 approximately 3 μm thick.

[0082] Pre-baking: Bake on a hot plate at 100°C for 90 seconds to evaporate the solvent.

[0083] Exposure: The first photomask (“block definition mask”) was exposed on an i-line (365nm) stepper lithography machine. The pattern consisted of a series of 100 μm diameter circles, corresponding to the future Z-axis block positions. The exposure energy was 150 mJ / cm².

[0084] Development: Using AZ® 400K developer (volume ratio of 1:4 to water), spray development at 23°C for 60 seconds to dissolve the photoresist in the exposed area, forming a layer like... Figure 3 The diagram shown.

[0085] Post-baking: Bake on a hot plate at 110°C for 60 seconds to harden the photoresist and improve its resistance to etching.

[0086] Oxide etching: The wafer is placed in a reactive ion etching machine.

[0087] Etching gas: CF4 / CHF3 / Ar mixture.

[0088] Process parameters: chamber pressure 50 mTorr, source power 800 W, bias power 100 W.

[0089] Endpoint detection: The intensity change of the CO spectral line (483.5 nm)* is monitored using optical emission spectroscopy. A sharp drop in signal indicates that the silicon dioxide has been etched through, and etching is immediately stopped. This step precisely removes the silicon dioxide outside the barrier area, exposing the underlying silicon, such as… Figure 4 As shown.

[0090] Photoresist removal: Use oxygen plasma ashing (power 1000W, O2 flow rate 500 sccm, 5 minutes) and sulfuric acid-hydrogen peroxide (SPM) solution to thoroughly remove residual photoresist 6.

[0091] Step 3: Second photolithography and deep silicon etching of the cavity region Secondary photoresist coating and pre-baking: As in the previous step, spin-coat the same positive photoresist of the same specifications on the front side of the wafer again.

[0092] Second exposure: A second photomask ("cavity definition mask", also known as the "yin-yang mask") is used. This mask complements the first mask, covering the circular blocking area defined in the first step and its surrounding 20 μm wide annular area, while exposing the large area to be etched into the cavity. Alignment accuracy must be controlled within ±1 μm.

[0093] Secondary development and post-baking: The process is the same as before, resulting in the following: Figure 5 The photoresist pattern shown is 6.

[0094] Deep silicon etching: This step is crucial for forming cavities and is performed using the Bosch Process in a deep reactive ion etching machine.

[0095] Process cycle: Passivation step: C4F8 gas is introduced to form an inert polymer protective layer under low bias power, protecting the sidewalls. Time: 5 seconds.

[0096] Etching procedure: SF6 gas is introduced, and isotropic etching of silicon is performed under high bias power. Time: 8 seconds.

[0097] Number of loops: Approximately 450 loops.

[0098] Key parameter: The chamber temperature is maintained at 20℃ to ensure process stability.

[0099] Results: A cavity with a depth of 85 ± 2 μm was etched, and the sidewall perpendicularity was better than 89.5°. Figure 6 As shown. At this point, the silicon in the Z-axis blocking block region is well preserved due to the dual protection of the silicon dioxide and photoresist above it.

[0100] Step 4: Synchronous etching of the movement gap Photoresist removal: After completing deep silicon etching, first thoroughly remove the photoresist 6 on the front side of the wafer, using the same method as before.

[0101] Simultaneous isotropic etching: This step is crucial for precisely controlling the gap height. Without removing the wafer, the process immediately switches to isotropic etching mode within the same deep reactive ion etching machine.

[0102] Process gas: pure SF6.

[0103] Process parameters: chamber pressure 150 mTorr, source power 1500 W, no bias power applied. SF6 decomposes at high power to generate a large number of fluorine radicals, which uniformly etch the silicon surface from all directions.

[0104] Time control: The etching time is strictly controlled within 120 seconds.

[0105] Results: This process simultaneously etched the bottom of the cavity and the top of the Z-axis blocking block, precisely removing 15 ± 0.5 μm of silicon. This created a 15 μm high movement gap between the top of the Z-axis blocking block and the bottom of the cavity. Figure 7 As shown. The advantage of this method is that the gap height is determined only by the etching rate and time, resulting in extremely high control precision.

[0106] Step 5: Protective layer growth and back-side via fabrication Remove front oxide: Immerse the wafer in buffer oxide etching solution to completely remove the front silicon dioxide layer 5.

[0107] Depositing a protective layer: The wafer is placed in a low-pressure chemical vapor deposition furnace.

[0108] Deposition conditions: SiH2Cl2 and NH3 were used as reaction gases at 300℃.

[0109] Objective: To deposit a 0.5 μm thick silicon nitride protective layer on both sides of the wafer, such as... Figure 8 As shown. This layer provides excellent protection for silicon during subsequent KOH etching.

[0110] Backside lithography and patterning: The wafer is flipped over, and a third lithography is performed on its back side.

[0111] Process: Coating, pre-baking, exposure and development using a third "via" mask to define a circular via area with a diameter of 80 μm.

[0112] Etching of silicon nitride and oxide: Using RIE etching, the silicon nitride protective layer 7 and the underlying silicon dioxide layer 5 in the via region are removed sequentially to expose the silicon substrate, such as... Figure 9 As shown.

[0113] Anisotropic wet etching of silicon: This is a key step in forming vias.

[0114] Etching solution: 30 wt% KOH aqueous solution.

[0115] Process conditions: The solution temperature is kept constant at 80 ± 1 ℃, and magnetic stirring is used to ensure uniform concentration and temperature.

[0116] Etching process: The wafer is placed in a specially designed etching holder, back side down, and immersed in a KOH solution. KOH etches the <100> plane of silicon much faster than the <111> plane. After approximately 4 hours of etching, a tapered via with a sidewall tilt angle of 54.7° is formed, ultimately etching through the remaining approximately 300μm thick silicon substrate. Figure 10 As shown.

[0117] Monitoring: The etching process can be observed in real time through a laser infrared monitoring system.

[0118] Step 6: Final oxidation and wafer bonding Remove the protective layer: Remove the silicon nitride protective layer 7 from both sides of the wafer using a hot phosphoric acid (H3PO4) solution heated to 180°C. This process has extremely high selectivity for silicon dioxide and will not damage the existing oxide layer.

[0119] Final thermal oxidation: The wafer is placed back into a high-temperature oxidation furnace.

[0120] Oxidation conditions: Wet oxygen oxidation was carried out at 1050℃.

[0121] Objective: To grow a silicon dioxide insulating layer with a final thickness of 2.0 μm on all exposed silicon surfaces, including the inner walls of the cavity with complex structures, all surfaces of the newly formed 15 μm moving gap, and the inner walls of the back vias. Figure 11 As shown. This high-quality oxide layer ensures reliable electrical insulation between components during device operation and passivates the silicon surface, improving long-term reliability.

[0122] Wafer bonding: This is the final step in packaging and forming the final structure.

[0123] Bonding object: The substrate wafer processed in this embodiment (now referred to as cap wafer 2) is bonded to another movable structural layer wafer 3, which is pre-processed on another production line and contains a cantilever beam-mass block system.

[0124] Alignment: In the wafer bonding machine, an infrared alignment system is used to precisely align the cavity / block area on the cap wafer with the movable mass block area on the structure wafer, with an alignment accuracy of <5 μm.

[0125] Bonding process: Silicon-to-silicon direct bonding is used.

[0126] First, pre-alignment and contact are performed at room temperature.

[0127] Then it is placed in a bonding machine, and under vacuum (<10⁻³ mbar), a pressure of 5000 N is applied, and the temperature is raised from room temperature to 400°C and held for 2 hours.

[0128] This process achieves atomic-level bonding, forming an extremely high-strength and hermetic encapsulation, such as... Figure 12 As shown.

[0129] Post-processing: After bonding is completed, standard post-packaging processes such as dicing, metallization through vias (e.g., sputtering TiW / Au to form metal electrodes 4), and wire bonding are performed to finally complete device manufacturing.

[0130] Effect verification: Cross-sectional inspection using a scanning electron microscope confirmed that the clearance height was 15.1 μm, meeting the design requirements. Hopkinson bar impact testing was performed on the finished device. After withstanding a half-sine wave impact (pulse width 0.1 ms) of up to 25,000 g, the device's capacitance-voltage characteristics did not drift, and the mechanical structure remained intact, demonstrating the superior reliability of the Z-direction overload-resistant structure provided by this invention.

[0131] The method of this invention, through careful process design and parameter control, transforms the fabrication of complex three-dimensional micro / nano structures into a series of reliable planar process steps, providing a solid manufacturing foundation for realizing high-performance, high-reliability, overload-resistant MEMS devices.

[0132] Example 3 This invention discloses a method for fabricating a Z-axis overload-resistant structure for a MEMS chip, comprising the following steps: The wafer is cleaned and oxidized; Photolithography is performed on any one side of the wafer to create a barrier block morphology; Etching silicon dioxide blocks exposes the silicon mass. A second photolithography step is then performed to protect the barrier blocks and expose the remaining silicon. Deep silicon dry etching is performed to etch the remaining silicon and form deep trenches; After removing the adhesive and cleaning, the barrier block and silicon body are dry etched together to a thickness of 14~16um; Then clean the protective layer growing on the wafer that forms the barrier structure; Photolithography is performed on the other side of the wafer to create the via morphology; Remove the protective layer and silicon dioxide layer of the via, and etch silicon until the via is formed; Complete oxidation of the wafer; After bonding with the movable structure layer, the movable structure's movement distance is limited due to the presence of the Z-direction blocking block, thus preventing phenomena such as Z-direction fracture.

[0133] Furthermore, a cavity structure with electrode lead-out holes and Z-direction blocking blocks is fabricated on a silicon wafer. The cavity depth is 80um~90um, and the gap between the blocking block and the silicon plane is 14~16um.

[0134] Furthermore, silicon wafers are selected for cleaning and oxidation, with an oxide layer thickness of 1µm to 2µm.

[0135] Furthermore, the use of yin-yang plates in two photolithography processes ensures the formation of the stop block.

[0136] Furthermore, photolithography is performed on any one side to form a stop structure pattern.

[0137] Furthermore, the silica layer of the stop structure is removed.

[0138] Furthermore, photolithography is performed again to block the stop structure portion, forming a cavity structure pattern.

[0139] Furthermore, dry etching forms a cavity structure with a depth of 80um~90um.

[0140] Furthermore, after removing the photoresist, the cavity portion and the stop structure portion are simultaneously dry etched to form a gap with a depth of 14~16um.

[0141] Further, the silica is removed, and a protective layer is grown.

[0142] Furthermore, photolithography is performed on the other side of the silicon wafer to form a via structure pattern, and the protective layer of the via structure is removed.

[0143] Furthermore, the silicon substrate is wet-etched until it is etched through, forming electrode vias.

[0144] Furthermore, the protective layer is removed, and silicon dioxide is regrown with a thickness of 2µm to 4µm.

[0145] Furthermore, the structure wafers for Z-axis stops and vias are bonded to the movable structure wafers with silicon-silicon bonding, followed by electrode and other process fabrication.

[0146] Furthermore, a movable silicon structure is formed and silicon-silicon bonded to the structural surface that forms the barrier block.

[0147] Furthermore, the etched silicon thickness for the via is 300um~400um.

[0148] This invention enables the realization of a high overload structure in the Z-direction while ensuring chip performance, thereby improving the shock resistance of chips and providing a process solution for shock resistance of wafer-level MEMS chips.

[0149] Example 4 This invention discloses a method for fabricating a Z-axis overload-resistant structure for a MEMS chip, comprising the following steps: Step 1: Select a silicon wafer to form a structural wafer that serves as a Z-axis stop and via. Bond the movable structural wafer using silicon-silicon bonding to obtain a wafer with overload resistance.

[0150] Step 2: Select a silicon wafer for cleaning and oxidation, with an oxide layer thickness of 1µm to 2µm.

[0151] Step 3: Select any side for photolithography to form the stop structure pattern.

[0152] Step 4: Remove the silica layer from the stop structure.

[0153] Step 5: Perform photolithography again to block the stop structure part and form a cavity structure pattern.

[0154] Step 6: Dry etching is used to form a cavity structure with a depth of 80um~90um.

[0155] Step 7: After removing the photoresist, continue to dry etch the cavity portion and the stop structure portion simultaneously to form a gap with a depth of 14~16um.

[0156] Step 8: Remove silica and grow a protective layer.

[0157] Step 9: Perform photolithography on the other side of the silicon wafer to form a via structure pattern, and remove the protective layer of the via structure.

[0158] Step 10: Wet etching of the silicon substrate until it is etched through, forming electrode vias.

[0159] Step 11: Remove the protective layer and re-grow silicon dioxide with a thickness of 2um~4um.

[0160] Step 12: The structure wafer with Z-axis stop and via is bonded to the movable structure wafer with silicon-silicon bonding, and then electrodes and other processes are fabricated.

[0161] This method can effectively fabricate the Z-axis overload-resistant structure of MEMS chips.

[0162] Thus, the objective of this invention has been achieved.

[0163] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for fabricating a Z-axis overload-resistant structure for a MEMS chip, characterized in that, Includes the following steps: On one side of the substrate wafer, a Z-axis blocking block region is defined by a first patterning process that includes the first photolithography and the first etching. A cavity surrounding the Z-axis blocking block region is etched on one side of the substrate wafer using a second patterning process that includes a second photolithography and deep silicon etching. Simultaneous dry etching is performed on the bottom of the cavity and the Z-axis blocking block to form a movement gap of a preset height between the Z-axis blocking block and the bottom of the cavity; On the other side of the substrate wafer, an electrode via is formed that penetrates the substrate wafer; The substrate wafer is oxidized to form an insulating layer on the inner surface of the cavity, the surface of the moving gap, and the inner surface of the electrode via. The cavity side of the substrate wafer is bonded to a structural wafer with a movable structural layer, such that the movable structural layer is encapsulated within the cavity and its Z-axis movement is restricted by the Z-axis blocking block.

2. The fabrication method of the Z-axis overload-resistant structure of the MEMS chip according to claim 1, characterized in that, The first patterning process specifically includes: After growing an oxide layer on one side of the substrate wafer, a first photolithography is performed to form a photoresist pattern covering the Z-axis blocking block region; Using the photoresist as a mask, the oxide layer is etched to expose the silicon surface outside the Z-axis blocking block region; After removing the photoresist, a second photolithography is performed to form a photoresist pattern covering the Z-direction blocking block region and its surrounding area, in order to protect the Z-direction blocking block region from being etched in subsequent deep silicon etching.

3. The fabrication method of the Z-axis overload-resistant structure of the MEMS chip according to claim 2, characterized in that, The lithography pattern used in the second lithography and the lithography pattern used in the first lithography complement each other around the Z-axis blocking block region, jointly defining the final shape of the cavity.

4. The fabrication method of the Z-axis overload-resistant structure of the MEMS chip according to claim 1, characterized in that, The synchronous dry etching depth is 14μm ~ 16μm, thereby precisely controlling the height of the movement gap; the deep silicon etching depth is 80μm ~ 90μm, thereby defining the initial depth of the cavity.

5. The fabrication method of the Z-axis overload-resistant structure of the MEMS chip according to claim 1, characterized in that, After the synchronous dry etching and before the electrode via fabrication, the following steps are also included: Remove the oxide layer on the front side of the substrate wafer and grow a protective layer; After etching the electrode vias, the protective layer is removed.

6. The fabrication method of the Z-axis overload-resistant structure of a MEMS chip according to claim 1, characterized in that, The specific steps involved in fabricating the electrode via are as follows: After growing an oxide layer or depositing a protective layer on the other side of the substrate wafer, photolithography is performed to define the via region; The oxide layer or protective layer of the via region is removed by etching, and silicon is etched using a wet anisotropic etching process until the substrate wafer is etched through to form a via.

7. The fabrication method of the Z-axis overload-resistant structure of a MEMS chip according to claim 1, characterized in that, The bonding is a direct silicon-silicon bonding, and the movement gap between the movable structural layer and the Z-axis blocking block after bonding is determined by the depth of the synchronous dry etching.

8. A fabrication system for a Z-axis overload-resistant structure of a MEMS chip for implementing the method of any one of claims 1-7, characterized in that, include: The patterning module is used to perform photolithography and etching processes on the substrate wafer to sequentially form the Z-axis blocking block region, cavity and motion gap; A through-hole processing module is used to fabricate electrode vias on the other side of the substrate wafer; A thermal oxidation module is used to grow an insulating oxide layer on the surface of the substrate wafer after patterning and through-hole processing; A bonding module is used to align and bond the substrate wafer with a structural wafer having a movable structural layer to form a packaging structure with Z-axis motion restriction.

9. The fabrication system for the Z-axis overload-resistant structure of a MEMS chip according to claim 8, characterized in that, The patterning module includes a dry etching apparatus configured to first perform high aspect ratio deep silicon etching to form the cavity, and then perform isotropic or near-isotropic silicon etching to simultaneously form the motion gap.

10. The fabrication system for the Z-axis overload-resistant structure of a MEMS chip according to claim 8, characterized in that, The via processing module includes an anisotropic wet etching equipment for forming tapered or vertically sidewalled electrode vias on the substrate wafer based on the crystal orientation-dependent etching principle.

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