Successive approximation type ripple suppression loop applied to secondary chopping amplifier

Abstract

The invention discloses a successive approximation type ripple suppression loop applied to a second-stage chopping amplifier, and the loop comprises a high-pass filtering module which is used for eliminating a DC offset component in an output signal of the second-stage chopping amplifier, and obtaining a high-frequency ripple signal; the demodulation module is used for modulating the high-frequency ripple signal into a low-frequency offset signal; the comparison module is used for quantizing the low-frequency offset signal into a digital level signal; the successive approximation logic module is used for carrying out logic judgment according to the digital level signal and generating a binary control code; and the compensation current source array module is used for performing current compensation on the first-stage chopping amplifier according to the binary control code. By means of the innovative circuit structure and working principle, the defects of an existing two-stage chopping amplifier ripple suppression technology are effectively overcome, the technical purposes of high ripple suppression ratio, low power consumption and high stability are achieved, and the two-stage chopping amplifier ripple suppression circuit is an effective means for suppressing two-stage chopping amplifier circuit ripples and has extremely high practical value and popularization prospects.

Description

A successive approximation ripple suppression loop for a two-stage chopper amplifier Technical Field

[0001] This invention belongs to the field of integrated circuit design, specifically relating to a successive approximation ripple suppression loop applied to a two-stage chopper amplifier. Background Technology

[0002] In high-precision analog circuit systems, chopper amplifiers are the core circuit structure for achieving low-offset, low-noise signal amplification due to their ability to effectively suppress DC offset and 1 / f noise. Two-stage chopper amplifiers further enhance offset suppression through two-stage chopping operations. However, in practical applications, limitations in the manufacturing process of circuit components can easily generate high-frequency ripple signals at the amplifier output. This ripple signal severely degrades the amplifier's output accuracy, especially in small-signal amplification scenarios, and may even mask the effective signal, leading to a decline in system performance.

[0003] Existing ripple suppression techniques mainly include adding RC (capacitor-resistor) filter networks, optimizing chopper switching timing, and employing multi-stage feedback compensation. However, adding RC filter networks introduces additional phase delay, reduces circuit bandwidth, and is difficult to adapt to a wide range of ripple frequencies; optimizing chopper switching timing requires complex clock synchronization circuits, increasing circuit design complexity and power consumption; multi-stage feedback compensation is susceptible to circuit parameter drift, resulting in unstable ripple suppression performance and failing to meet the application requirements of high-precision, low-power scenarios.

[0004] Therefore, developing a ripple suppression circuit for a two-stage chopper amplifier with high ripple rejection ratio, low power consumption, and stable structure has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a successive approximation ripple suppression loop for use in a two-stage chopper amplifier.

[0006] The technical problem to be solved by the present invention is achieved through the following technical solution: Firstly, the present invention provides a successive approximation ripple suppression loop applied to a two-stage chopper amplifier. The successive approximation ripple suppression loop includes: a high-pass filter module, a demodulation module, a comparison module, a successive approximation logic module, and a compensation current source array module. The input terminal of the high-pass filter module is connected to the output terminal of the second-stage chopper amplifier in the two-stage chopper amplifier, and its output terminal is connected to the input terminal of the demodulation module. The output terminal of the demodulation module is connected to the input terminal of the successive approximation logic module. The output terminal of the successive approximation logic module is connected to the input terminal of the compensation current source array module. The output of the compensation current source array module is connected to the output branch of the first-stage chopper amplifier in the two-stage chopper amplifier; the high-pass filter module is used to eliminate the DC offset component in the output signal of the second-stage chopper amplifier to obtain a high-frequency ripple signal; the demodulation module is used to modulate the high-frequency ripple signal into a low-frequency offset signal; the comparison module is used to quantize the low-frequency offset signal into a digital level signal; the successive approximation logic module is used to perform logical judgment based on the digital level signal to generate a binary control code; the compensation current source array module is used to perform current compensation on the first-stage chopper amplifier according to the binary control code.

[0007] Optionally, the successive approximation ripple suppression loop further includes: a reference DC source; the output of the reference DC source is connected to the input of the input chopper in the secondary chopper amplifier; the reference DC source is used to transmit a clean DC signal to the secondary chopper amplifier.

[0008] Optionally, the compensation current source array module is further configured to control the current source unit combination inside the compensation current source array module to output a corresponding compensation current according to the binary control code, so as to perform current compensation on the first-stage chopper amplifier and suppress the ripple signal at the output of the second-stage chopper amplifier.

[0009] Optionally, the successive approximation logic in the successive approximation logic module includes an N-terminal logic array and a P-terminal logic array.

[0010] Optionally, the successive approximation logic module is further configured to control the first digital code of the N-terminal logic array to be at a low potential and the first digital code of the P-terminal logic array to be at a high potential when the digital level signal is at a high potential; the successive approximation logic module is further configured to control the first digital code of the N-terminal logic array to be at a high potential and the first digital code of the P-terminal logic array to be at a low potential when the digital level signal is at a low potential.

[0011] Optionally, both the N-terminal logic array and the P-terminal logic array are composed of multiple current sources with a binary distribution of current ratios.

[0012] Optionally, each current source is controlled by a binary control code. When the binary control code corresponding to the current source is 1, the current source operates; when the binary control code corresponding to the current source is 0, the current source does not operate.

[0013] Optionally, the output signal of the second-stage chopper amplifier is a differential signal.

[0014] The technical solutions provided by the embodiments of the present invention can include the following beneficial effects: In the above technical solutions, the current mismatch of the first-stage chopper amplifier can be accurately offset by the coordinated work of the successive approximation logic module and the compensation current source array module; and each module of the circuit described in the present invention adopts a low-voltage and low-power design; the compensation current array module consumes dynamic power consumption only when the compensation current needs to be adjusted, and the current amplitude of the current source unit is output on demand according to the ripple suppression requirements; the compensation current source array module adopts a temperature-stable current source structure, and the successive approximation logic integrates a reset unit, so that the circuit can resist the influence of temperature changes, power fluctuations and ripple frequency mutations, and the ripple suppression effect is stable for a long time; each module of the circuit is implemented using standardized processes, without the need for complex peripheral circuits, and is easy to integrate with the second-stage chopper amplifier on the same chip, reducing the design complexity and cost of the system; In summary, the present invention effectively solves the defects of the existing second-stage chopper amplifier ripple suppression technology through innovative circuit structure and working principle, and achieves the technical goals of high ripple suppression ratio, low power consumption and high stability. It is an effective means of suppressing the ripple of the second-stage chopper amplifier circuit and has extremely high practical value and promotion prospects.

[0015] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0016] Figure 1 is a schematic diagram of a successive approximation ripple suppression loop applied to a two-stage chopper amplifier according to an embodiment of the present invention; Figure 2 is a flowchart of the operation of a successive approximation logic module according to an embodiment of the present invention; Figure 3 is a schematic diagram of a compensation current source array module according to an embodiment of the present invention; Figure 4 is a schematic diagram of the first-stage chopper amplifier in a two-stage chopper amplifier according to an embodiment of the present invention. Detailed Implementation

[0017] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0018] Figure 1 is a schematic diagram of a successive approximation ripple suppression loop applied to a two-stage chopper amplifier according to an embodiment of the present invention. This successive approximation ripple suppression loop works in conjunction with the two-stage chopper amplifier. As shown in Figure 1, the successive approximation ripple suppression loop includes: a high-pass filter module, a demodulation module, a comparison module, a successive approximation logic module, and a compensation current source array module. The input terminal of the high-pass filter module is connected to the output terminal of the second-stage chopper amplifier in the two-stage chopper amplifier, and its output terminal is connected to the input terminal of the demodulation module. The output terminal of the demodulation module is connected to the input terminal of the successive approximation logic module. The output terminal of the successive approximation logic module is connected to the input terminal of the compensation current source array module. The output terminal of the compensation current source array module is connected to the output branch of the first-stage chopper amplifier in the two-stage chopper amplifier. The high-pass filter module is used to eliminate the DC offset component in the output signal of the second-stage chopper amplifier to obtain a high-frequency ripple signal.

[0019] Understandably, the output signal of the second-stage chopper amplifier is a differential signal. The core function of this high-pass filter module is to eliminate the DC offset component in the output signal of the second-stage chopper amplifier, preventing this DC offset component from interfering with the quantization judgment of the subsequent comparator. Specifically, the output signal of the second-stage chopper amplifier includes the effective amplified signal, the low-frequency ripple signal, and the DC offset signal. If directly input to the comparator module, it will cause the comparator module to misjudge and fail to accurately identify the offset direction corresponding to the ripple signal.

[0020] The demodulation module is used to modulate the high-frequency ripple signal into a low-frequency offset signal.

[0021] Understandably, the function of the demodulation module is to modulate the high-frequency ripple signal output by the high-pass filter module into a low-frequency offset signal so that the subsequent comparison module can more accurately determine the offset direction.

[0022] The comparison module is used to quantize the low-frequency offset signal into a digital level signal.

[0023] Understandably, the function of the comparison module is to compare the low-frequency offset signal output by the demodulation module, quantize the analog low-frequency offset signal into a digital level signal, and thus determine the offset direction.

[0024] The successive approximation logic module is used to perform logical judgments based on the digital level signal and generate binary control codes.

[0025] Optionally, the successive approximation logic in the successive approximation logic module includes an N-terminal logic array and a P-terminal logic array.

[0026] It is understandable that the function of the successive approximation logic module is to receive the digital level signal output by the comparison module, perform logical judgment through the preset successive approximation algorithm, and gradually generate an n-bit binary control code (n is a positive integer, set according to the ripple suppression accuracy requirements, usually 8 bits, 10 bits or 12 bits, this invention takes 8 bits as an example) that matches the amplitude of the current ripple signal, and transmit the binary control code to the compensation current array.

[0027] Optionally, the successive approximation logic module is further configured to control the first digital code of the N-terminal logic array to be at a low potential and the first digital code of the P-terminal logic array to be at a high potential when the digital level signal is at a high potential; the successive approximation logic module is further configured to control the first digital code of the N-terminal logic array to be at a high potential and the first digital code of the P-terminal logic array to be at a low potential when the digital level signal is at a low potential.

[0028] It is understood that Figure 2 is a flowchart of the operation of a successive approximation logic module provided in an embodiment of the present invention. As shown in Figure 2, the successive approximation logic consists of an N-terminal logic array and a P-terminal logic array, which correspond to the subsequent N-terminal and P-terminal compensation current source arrays, respectively. OUT This is the digital level signal output by the comparator. When the successive ripple suppression circuit is enabled, high-frequency ripple passes through the high-pass filter module and demodulation module. T1 clock triggers the comparator module to begin its first comparison. If COM... OUT If the voltage is high (1), then the first digit of the N-terminal logic array, N1, is low (0), and the first digit of the P-terminal logic array, P1, is high (1). If COM... OUT If the voltage level is low (0), then the first digit of the N-terminal logic array, N1, is high (1), and the first digit of the P-terminal logic array, P1, is low (0). P1 and N1 control the conduction state of the current sources corresponding to the compensation current source array, thereby compensating for the ripple once. The compensated ripple then passes through the high-pass filter module and demodulation module, and is triggered by clock T2 to enter the comparison module again for comparison, obtaining a second comparison result. The ripple is then suppressed again by the above algorithm. The above algorithm is repeated 8 times, finally suppressing the ripple to a minimum value, ensuring the normal operation of the two-stage chopper amplifier and the purity of the output signal.

[0029] The compensation current source array module is used to perform current compensation on the first-stage chopper amplifier according to the binary control code.

[0030] Optionally, Figure 3 is a structural schematic diagram of a compensation current source array module provided in an embodiment of the present invention. As shown in Figure 3, the compensation current source array module includes an N array and a P array, both of which are composed of multiple current sources with a binary distribution of current ratios.

[0031] Understandably, current compensation is performed on the two output branches of the first-stage amplifier. Both arrays consist of eight current sources distributed in a binary ratio. Each current source is controlled by a digital code; when the corresponding bit of the digital code is 1, the current source operates and performs current compensation for the first-stage amplifier. When the corresponding bit of the digital code is 0, the current source does not operate and does not participate in current compensation.

[0032] Optionally, the compensation current source array module is further configured to control the current source unit combination inside the compensation current source array module to output a corresponding compensation current according to the binary control code, so as to perform current compensation on the first-stage chopper amplifier and suppress the ripple signal at the output of the second-stage chopper amplifier.

[0033] Understandably, the function of the compensation current source array module is to receive the n-bit binary control code output by the successive approximation logic module, and according to the value of the binary control code, output the corresponding compensation current through the combination of internal current source units to compensate the current of the output branch of the first-stage chopper amplifier, thereby successively eliminating the current mismatch caused by factors such as device mismatch and temperature drift in the first-stage chopper amplifier, and thus suppressing the ripple signal at the output of the second-stage chopper amplifier.

[0034] Optionally, the successive approximation ripple suppression loop further includes: a reference DC source; the output of the reference DC source is connected to the input of the input chopper in the secondary chopper amplifier; the reference DC source is used to transmit a clean DC signal to the secondary chopper amplifier.

[0035] Understandably, to ensure low power consumption of the overall circuit, the ripple suppression loop is not performed during normal operation of the second-stage chopper amplifier, but rather to suppress ripple during a calibration cycle. When ripple is calibrated, the signal input port is disconnected, and a clean DC signal is input to the second-stage chopper amplifier from the reference DC source, resulting in a clean ripple output from the second-stage chopper amplifier.

[0036] Figure 4 is a schematic diagram of the first-stage chopper amplifier in a two-stage chopper amplifier according to an embodiment of the present invention. As shown in Figure 4, the ripple signal originates from the mismatch of the first-stage amplifier, with the input transistor mismatch being the primary factor. Taking a common folded cascode amplifier as an example of the first-stage amplifier, the input transistor mismatch leads to current mismatch in two branches, namely IP1 and IN1. The sum of IP1 and IP2 is the total current IPT of the P branch, and the sum of IN1 and IN2 is the total current IPT of the N branch. This mismatch in branch currents further leads to a mismatch between the total branch currents IPT and INT, resulting in DC offset at the output. This offset is modulated to a high frequency by the output chopper and amplified by the second-stage amplifier to form ripple. Since the compensation currents formed by the compensation capacitor array at the N and P terminals compensate the N and P compensation points respectively, the mismatch between the total branch currents IPT and INT is calibrated, suppressing the generation of DC offset and thus achieving ripple suppression.

[0037] In the above technical solution, the current mismatch of the first-stage chopper amplifier can be accurately offset by the coordinated operation of the successive approximation logic module and the compensation current source array module. Furthermore, each module of the circuit described in this invention adopts a low-voltage, low-power design. The compensation current array module consumes dynamic power only when the compensation current needs adjustment, and the current amplitude of the current source unit is output on demand according to the ripple suppression requirements. The compensation current source array module adopts a temperature-stable current source structure, and the successive approximation logic integrates a reset unit, enabling the circuit to resist the effects of temperature changes, power fluctuations, and sudden changes in ripple frequency, resulting in long-term stable ripple suppression. Each module of the circuit is implemented using standardized processes, eliminating the need for complex external circuits and facilitating integration with the second-stage chopper amplifier on the same chip, reducing system design complexity and cost. In summary, this invention, through its innovative circuit structure and working principle, effectively solves the defects of existing second-stage chopper amplifier ripple suppression technologies, achieving the technical goals of high ripple suppression ratio, low power consumption, and high stability. It is an effective means of suppressing ripple in second-stage chopper amplifier circuits, possessing extremely high practical value and promising prospects for promotion.

[0038] It should be noted that the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention.

[0039] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0040] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings and the disclosure in carrying out the claimed invention. In the description of the invention, the word "comprising" does not exclude other components or steps, "a" or "an" does not exclude a plurality, and "a plurality" means two or more, unless otherwise explicitly specified. Furthermore, while different embodiments may describe certain measures, this does not mean that these measures cannot be combined to produce good results.

[0041] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A successive approximation type ripple suppression loop applied to a two-stage chopper amplifier, characterized in that, The successive approximation ripple suppression loop includes: a high-pass filter module, a demodulation module, a comparison module, a successive approximation logic module, and a compensation current source array module; the input terminal of the high-pass filter module is connected to the output terminal of the second-stage chopper amplifier in the two-stage chopper amplifier, and the output terminal is connected to the input terminal of the demodulation module; the output terminal of the demodulation module is connected to the input terminal of the successive approximation logic module; the output terminal of the successive approximation logic module is connected to the input terminal of the compensation current source array module; the output terminal of the compensation current source array module is connected to the first stage chopper amplifier in the two-stage chopper amplifier. The output branch of the first-stage chopper amplifier is connected; the high-pass filter module is used to eliminate the DC offset component in the output signal of the second-stage chopper amplifier to obtain a high-frequency ripple signal; the demodulation module is used to modulate the high-frequency ripple signal into a low-frequency offset signal; the comparison module is used to quantize the low-frequency offset signal into a digital level signal; the successive approximation logic module is used to perform logical judgment based on the digital level signal to generate a binary control code; the compensation current source array module is used to perform current compensation on the first-stage chopper amplifier according to the binary control code.

2. The successive approximation ripple suppression loop applied to a two-stage chopper amplifier according to claim 1, characterized in that, The successive approximation ripple suppression loop further includes: a reference DC source; the output terminal of the reference DC source is connected to the input terminal of the input chopper in the secondary chopper amplifier; the reference DC source is used to transmit a clean DC signal to the secondary chopper amplifier.

3. The successive approximation ripple suppression loop applied to a two-stage chopper amplifier according to claim 1, characterized in that, The compensation current source array module is also used to control the current source unit combination inside the compensation current source array module to output the corresponding compensation current according to the binary control code, so as to perform current compensation on the first-stage chopper amplifier and suppress the ripple signal at the output of the second-stage chopper amplifier.

4. The successive approximation ripple suppression loop applied to a two-stage chopper amplifier according to claim 1, characterized in that, The successive approximation logic in the successive approximation logic module includes an N-terminal logic array and a P-terminal logic array.

5. The successive approximation ripple suppression loop applied to a two-stage chopper amplifier according to claim 4, characterized in that, The successive approximation logic module is further configured to control the first digital code of the N-terminal logic array to be at a low potential and the first digital code of the P-terminal logic array to be at a high potential when the digital level signal is at a high potential; the successive approximation logic module is further configured to control the first digital code of the N-terminal logic array to be at a high potential and the first digital code of the P-terminal logic array to be at a low potential when the digital level signal is at a low potential.

6. The successive approximation ripple suppression loop applied to a two-stage chopper amplifier according to claim 4, characterized in that, The compensation current source array module includes an N array and a P array, both of which are composed of multiple current sources with a binary distribution of current ratios.

7. The successive approximation ripple suppression loop applied to a two-stage chopper amplifier according to claim 6, characterized in that, Each current source is controlled by a binary control code. When the binary control code corresponding to the current source is 1, the current source works; when the binary control code corresponding to the current source is 0, the current source does not work.

8. The successive approximation ripple suppression loop applied to a two-stage chopper amplifier according to claim 1, characterized in that, The output signal of the second-stage chopper amplifier is a differential signal.

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