Time sequence alignment method and device, medium and equipment

Abstract

The invention discloses a time sequence alignment method and device, a medium and equipment. The time sequence alignment method comprises the steps of determining cache parallel data corresponding to a target clock period from parallel data streams corresponding to a current receiving round; performing shift selection on the cached parallel data based on a plurality of delimited reference data segments obtained by splitting a preset delimiter to obtain a plurality of to-be-retrieved data segments of each delimited reference data segment; retrieving a plurality of to-be-retrieved data segments of each delimited reference data segment based on each delimited reference data segment to obtain first delimited indication information of each delimited reference data segment; determining second delimiting indication information of the cached parallel data based on the first delimiting indication information of each delimiting reference data segment and a decision window corresponding to the target clock period; and extracting the cached parallel data according to the second delimiting indication information to obtain aligned parallel data of the target clock period. According to the method and the device, the time sequence alignment of clock cycles can be carried out on the data stream, and the recovery and alignment of the data time sequence can be ensured when disturbance occurs.

Description

A timing alignment method, apparatus, medium, and device Technical Field

[0001] This application relates to the field of communication technology, specifically to a timing alignment method, apparatus, medium, and device. Background Technology

[0002] Next-generation Passive Optical Network (PON) broadband access networks utilize passive optical network technology to achieve the last mile of fiber optic deployment to homes and offices. Standardized passive optical networks provide bidirectional operation from multiple optical network units (ONUs) located at or near the user to the optical line terminal (OLT) at the network provider.

[0003] In passive optical network systems, optical network units and optical line terminals are the most important components. When testing the function and performance of optical line terminals, it is necessary to restore the normal timing after receiving the parallel data stream obtained by serialization according to a certain encoding order. Furthermore, as the optical power changes, bit jumps or offsets may occur in the received parallel data stream, which increases the difficulty of timing recovery and alignment. Summary of the Invention

[0004] To accurately align parallel data in a parallel data stream, this application provides a timing alignment method, apparatus, medium, and device. The technical solution is as follows: Firstly, this application provides a timing alignment method, comprising: determining buffered parallel data corresponding to a target clock cycle from the parallel data stream corresponding to the current receiving round; the target clock cycle being any clock cycle in the parallel data stream; splitting a preset delimiter to obtain multiple delimiting reference data segments; shifting and selecting the buffered parallel data corresponding to the target clock cycle based on each of the multiple delimiting reference data segments to obtain multiple data segments to be retrieved corresponding to each delimiting reference data segment; and retrieving the multiple data segments to be retrieved corresponding to each delimiting reference data segment based on each delimiting reference data segment to obtain the data segments to be retrieved corresponding to each delimiting reference data segment. The system obtains the first delimiting indication information; based on the first delimiting indication information corresponding to each delimiting reference data segment and the adjudication window corresponding to the target clock cycle, it determines the second delimiting indication information corresponding to the cached parallel data; the current duration of the adjudication window corresponding to the target clock cycle is determined based on the second delimiting indication information corresponding to the target clock cycle in the previous reception round; if the second delimiting indication information corresponding to the cached parallel data indicates that there is a target data segment in the cached parallel data corresponding to the target clock cycle that is the same as or similar to the preset delimiter, the cached parallel data is extracted according to the second delimiting indication information corresponding to the cached parallel data to obtain the aligned parallel data corresponding to the target clock cycle.

[0005] Optionally, determining the cached parallel data corresponding to the target clock cycle from the parallel data stream corresponding to the current receiving round includes: determining the parallel data corresponding to the target clock cycle and the parallel data corresponding to the adjacent clock cycle based on the selection window corresponding to the current receiving round and the parallel data stream corresponding to the current receiving round; merging the parallel data corresponding to the target clock cycle and the parallel data corresponding to the adjacent clock cycle to obtain the cached parallel data corresponding to the target clock cycle.

[0006] Optionally, the step of splitting the preset delimiter to obtain multiple delimiting reference data segments includes: equally dividing the preset delimiter to obtain the multiple delimiting reference data segments, wherein the multiple delimiting reference data segments do not overlap with each other, and the multiple delimiting reference data segments constitute the complete preset delimiter.

[0007] Optionally, the method further includes: determining the number of delimiting reference data segments based on the length of the parallel data and the length of the preset delimiter.

[0008] Optionally, the step of shifting and selecting the cached parallel data corresponding to the target clock cycle based on each of the plurality of delimited reference data segments to obtain a plurality of data segments to be retrieved corresponding to each delimited reference data segment includes: determining the starting selection position corresponding to each delimited reference data segment in the cached parallel data; based on the starting selection position, extracting a continuous data segment of a preset length from the cached parallel data, and moving the starting selection position bit by bit to perform multiple extractions to obtain a plurality of data segments to be retrieved corresponding to each delimited reference data segment; the preset length is the same as the length of the corresponding delimited reference data segment.

[0009] Optionally, the step of searching multiple data segments corresponding to each delimited reference data segment to obtain first delimiting indication information corresponding to each delimited reference data segment includes: performing bit matching between each data segment to be searched in the multiple data segments to be searched corresponding to each delimited reference data segment and the corresponding delimited reference data segment to obtain multiple matching results corresponding to each delimited reference data segment; determining the first delimiting indication information corresponding to each delimited reference data segment based on the multiple matching results corresponding to each delimited reference data segment; the first delimiting indication information corresponding to each delimited reference data segment includes indication identification information and delimiting position information; the indication identification information indicates whether there is a data segment to be searched that is the same as the corresponding delimited reference data segment in the multiple data segments to be searched corresponding to the corresponding delimited reference data segment; the delimiting position information indicates the position of the data segment to be searched that is the same as the corresponding delimited reference data segment in the cached parallel data when the indication identification information indicates that there is a data segment to be searched that is the same as the corresponding delimited reference data segment in the multiple data segments to be searched corresponding to the corresponding delimited reference data segment.

[0010] Optionally, the method further includes: in the first receiving round, if the indication identifier information in the first delimitation indication information corresponding to each delimitation reference data segment indicates that there is a searchable data segment identical to the corresponding delimitation reference data segment among the multiple searchable data segments corresponding to the corresponding delimitation reference data segment, then based on the delimitation position information in the first delimitation indication information corresponding to each delimitation reference data segment, determining the second delimitation indication information corresponding to the cached parallel data; the second delimitation indication information corresponding to the cached parallel data indicates that there is a target data segment identical to the preset delimiter in the cached parallel data, and indicates the position of the target data segment in the cached parallel data.

[0011] Optionally, determining the second delimiting indication information corresponding to the cached parallel data based on the first delimiting indication information corresponding to each delimiting reference data segment and the adjudication window corresponding to the target clock cycle includes: within the current duration of the adjudication window corresponding to the target clock cycle, if the indication information in the first delimiting indication information corresponding to each delimiting reference data segment indicates that there is no data segment to be retrieved that is the same as the corresponding delimiting reference data segment among the multiple data segments to be retrieved corresponding to the corresponding delimiting reference data segment, then the timing alignment for the target clock cycle is skipped.

[0012] Optionally, determining the second delimiting indication information corresponding to the cached parallel data based on the first delimiting indication information corresponding to each delimiting reference data segment and the adjudication window corresponding to the target clock cycle includes: within the current duration of the adjudication window corresponding to the target clock cycle, if the indication identifier information in the first delimiting indication information corresponding to each delimiting reference data segment does not completely indicate that there is a searchable data segment identical to the corresponding delimiting reference data segment among the multiple searchable data segments corresponding to the corresponding delimiting reference data segment, then the indication identifier information in the first delimiting indication information corresponding to each delimiting reference data segment is statistically analyzed to obtain identifier statistical data; based on the adjudication strategy corresponding to the identifier statistical data and the delimiting position information in the first delimiting indication information corresponding to each delimiting reference data segment, the second delimiting indication information corresponding to the cached parallel data is obtained; the second delimiting indication information corresponding to the cached parallel data indicates that there is a target data segment similar to the preset delimiter in the cached parallel data, and indicates the position of the target data segment in the cached parallel data.

[0013] Optionally, the method further includes: determining a first duration of the decision window when the second delimitation indication information corresponding to the cached parallel data indicates that the target data segment is located at the boundary position of the parallel data corresponding to the target clock cycle; and determining a second duration of the decision window when the second delimitation indication information corresponding to the cached parallel data indicates that the target data segment is located at the non-boundary position of the parallel data corresponding to the target clock cycle; wherein the first duration or the second duration is the next duration of the decision window corresponding to the target clock cycle in the next reception round.

[0014] Optionally, the method further includes: after determining the second delimiting indication information corresponding to the target clock cycle in the previous receiving round, starting a target counter corresponding to the target clock cycle; the initial value of the target counter is the same as the length of the clock cycle of the parallel data stream; the value of the target counter is decremented by 1 every clock cycle; when the value of the target counter decreases to a preset threshold corresponding to the current duration, opening an adjudication window corresponding to the target clock cycle, until the adjudication window corresponding to the target clock cycle is closed after the target counter finishes counting, so as to determine the second delimiting indication information corresponding to the buffered parallel data in the current receiving round within the current duration of the adjudication window corresponding to the target clock cycle.

[0015] Optionally, determining the second delimiting indication information corresponding to the cached parallel data based on the delimiting position information in the first delimiting indication information corresponding to each delimiting reference data segment includes: performing a consistency check on the delimiting position information in the first delimiting indication information corresponding to each delimiting reference data segment to obtain a position consistency check result; and if the position consistency check result indicates that each of the delimiting position information is the same, using each of the delimiting position information as the second delimiting indication information corresponding to the cached parallel data.

[0016] Secondly, this application provides a timing alignment device, the device comprising: a data acquisition module, configured to determine cached parallel data corresponding to a target clock cycle from the parallel data stream corresponding to the current receiving round; the target clock cycle being any clock cycle in the parallel data stream; a delimiter splitting module, configured to split a preset delimiter to obtain multiple delimiting reference data segments; a shift selection module, configured to shift and select the cached parallel data corresponding to the target clock cycle based on each of the multiple delimiting reference data segments to obtain multiple data segments to be retrieved corresponding to each delimiting reference data segment; and a retrieval module, configured to retrieve the multiple data segments to be retrieved corresponding to each delimiting reference data segment based on each delimiting reference data segment to obtain each delimiting reference data segment. The data includes: a first delimiting indication information corresponding to each delimited reference data segment; a delimiting module, used to determine a second delimiting indication information corresponding to the cached parallel data based on the first delimiting indication information corresponding to each delimited reference data segment and the adjudication window corresponding to the target clock cycle; the current duration of the adjudication window corresponding to the target clock cycle is determined based on the second delimiting indication information corresponding to the target clock cycle in the previous reception round; and a data extraction module, used to extract the cached parallel data according to the second delimiting indication information corresponding to the cached parallel data when the second delimiting indication information indicates that there is a target data segment in the cached parallel data corresponding to the target clock cycle that is the same as or similar to the preset delimiter, to obtain aligned parallel data corresponding to the target clock cycle.

[0017] Thirdly, this application provides a computer-readable storage medium storing at least one instruction or at least one program, which is loaded and executed by a processor to implement the timing alignment method as described in the first aspect.

[0018] Fourthly, this application provides a computer device including a processor and a memory, wherein the memory stores at least one instruction or at least one program, the at least one instruction or the at least one program being loaded and executed by the processor to implement the timing alignment method as described in the first aspect.

[0019] Fifthly, this application provides a computer program product comprising computer instructions that, when executed by a processor, implement the timing alignment method as described in the first aspect.

[0020] This application provides a timing alignment method, apparatus, medium, and device, which have the following technical advantages: The scheme provides that it determines the buffered parallel data corresponding to the target clock cycle from the parallel data stream corresponding to the current receiving round, wherein the target clock cycle is any clock cycle in the parallel data stream; the scheme provides that it splits a preset delimiter to obtain multiple delimiting reference data segments, and based on each delimiting reference data segment, it shifts and selects the buffered parallel data corresponding to the target clock cycle to obtain multiple data segments to be retrieved corresponding to each delimiting reference data segment, which serve as the objects of delimiting retrieval; the scheme provides that it retrieves the multiple data segments to be retrieved corresponding to each delimiting reference data segment based on each delimiting reference data segment, obtaining the data segments to be retrieved corresponding to each delimiting reference data segment. The first delimiting indication information; then, based on the first delimiting indication information corresponding to each delimiting reference data segment and the adjudication window corresponding to the target clock cycle, the second delimiting indication information corresponding to the buffered parallel data of the target clock cycle can be determined, wherein the current duration of the adjudication window corresponding to the target clock cycle is determined based on the second delimiting indication information corresponding to the target clock cycle in the previous receiving round; if the second delimiting indication information corresponding to the buffered parallel data indicates that there is a target data segment in the buffered parallel data corresponding to the target clock cycle that is the same as or similar to the preset delimiter, the buffered parallel data can be extracted according to the second delimiting indication information corresponding to the buffered parallel data to obtain the aligned parallel data corresponding to the target clock cycle, and accurate deserialization processing can be performed. The scheme provided by this application can accurately perform clock cycle-by-clock-cycle timing alignment of parallel data streams, and through the dual splitting and retrieval of preset delimiters and buffered parallel data, it can more stably and precisely ensure the recovery and alignment of data timing when disturbances occur.

[0021] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0022] To more clearly illustrate the technical solutions and advantages in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 is a schematic diagram of the implementation environment of a timing alignment method provided in an embodiment of this application; Figure 2 is a flowchart of a timing alignment method provided in an embodiment of this application; Figure 3 is a flowchart of determining first delimitation indication information provided in an embodiment of this application; Figure 4 is a structural schematic diagram of a hardware implementation module provided in an embodiment of this application; Figure 5 is a schematic diagram of a timing alignment device provided in an embodiment of this application; Figure 6 is a hardware structure schematic diagram of a device for implementing a timing alignment method provided in an embodiment of this application. Detailed Implementation

[0024] To accurately align parallel data in a parallel data stream, this application provides a timing alignment method, apparatus, medium, and device. The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0025] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or server that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0026] Please refer to Figure 1, which is a schematic diagram of the implementation environment of a timing alignment method provided in this application embodiment. As shown in Figure 1, the implementation environment may include at least an optical network unit (ONU), an optical fiber link, an optical line terminal (OLT), and a serializer / deserializer (Serdes). The ONU acts as the transmitter, and the OLT acts as the receiver, receiving the serialized parallel data stream transmitted through the optical fiber link, and deserializing the parallel data stream using the serializer / deserializer. In order to test the function and performance of the OLT, such as its error reception capability, it is necessary to restore the normal timing after receiving the parallel data stream obtained by serialization processing according to a certain encoding order. Only on the basis of timing alignment can effective and accurate testing be carried out. However, when the optical power changes or is very low, or due to the delay in the transmission of serial radio frequency signals, the serialized parallel data stream output by the optical line terminal or received by the serializer / deserializer may experience bit offset. The delimiters used for data stream alignment may have bit errors. When the serializer / deserializer receives the data stream and converts it into parallel data, the position of the delimiters may be misidentified or difficult to identify, resulting in a change in the position of the deserialized data structure in the parallel data compared to before transmission.

[0027] In a timing alignment method provided in this application, buffered parallel data corresponding to a target clock cycle is determined from the parallel data stream corresponding to the current reception round received from the optical line terminal. The target clock cycle is any clock cycle in the parallel data stream. The timing alignment method provides that this application splits a preset delimiter to obtain multiple delimiting reference data segments. Based on each delimiting reference data segment, the buffered parallel data corresponding to the target clock cycle is shifted and selected to obtain multiple data segments to be retrieved corresponding to each delimiting reference data segment, which serve as the objects of delimiting retrieval. The scheme provided in this application, based on each delimiting reference data segment, retrieves the multiple data segments to be retrieved corresponding to each delimiting reference data segment to obtain a first delimiting index corresponding to each delimiting reference data segment. The method provides information on timing alignment. Based on the first delimiting indication information corresponding to each delimiting reference data segment and the adjudication window corresponding to the target clock cycle, the second delimiting indication information corresponding to the buffered parallel data for the target clock cycle can be determined. The current duration of the adjudication window corresponding to the target clock cycle is determined based on the second delimiting indication information corresponding to the target clock cycle in the previous reception round. If the second delimiting indication information indicates the presence of a target data segment with the same or similar preset delimiter in the buffered parallel data for the target clock cycle, the buffered parallel data can be extracted according to the second delimiting indication information to obtain the aligned parallel data for the target clock cycle, and then accurately deserialized. This application provides a timing alignment method that can accurately perform clock-cycle-by-clock-cycle timing alignment of parallel data streams. Furthermore, through dual decomposition and retrieval of preset delimiters and buffered parallel data, it can more stably and precisely guarantee the recovery and alignment of data timing when disturbances occur.

[0028] Please refer to Figure 2, which is a flowchart of a timing alignment method provided in an embodiment of this application. This application provides the operation steps of the method as described in the embodiment or flowchart, but based on conventional or non-inventive labor, more or fewer operation steps may be included. The order of steps listed in the embodiment is only one of many possible execution orders and does not represent the only execution order. In actual system or server products, the method can be executed sequentially or in parallel (e.g., in a parallel processor or multi-threaded processing environment) according to the embodiment or the accompanying drawings. As shown in Figure 2, a timing alignment method provided in an embodiment of this application may include the following steps: S210: Determine the cached parallel data corresponding to the target clock cycle from the parallel data stream corresponding to the current receiving round.

[0029] In this embodiment, the parallel data stream is a serialized signal. Under conditions such as changes in optical power, very low optical power, or the influence of uncertain transmission delay of serial radio frequency signals, bit offsets or bit jumps may occur in the parallel data stream, which may easily cause the position of the deserialized data structure in the parallel data to change compared to before transmission.

[0030] In the embodiments of this application, the target clock period is any clock period in the parallel data stream.

[0031] In one embodiment of this application, the aforementioned parallel data stream may employ a fixed-length encoding method.

[0032] In one embodiment of this application, step S210 can be implemented as follows: S211: Based on the selection window corresponding to the current receiving round and the parallel data stream corresponding to the current receiving round, determine the parallel data corresponding to the target clock cycle and the parallel data corresponding to the adjacent clock cycle relative to the target clock cycle.

[0033] For example, if the selection window corresponding to the current receiving round indicates that the duration is two clock cycles, the aforementioned adjacent clock cycle can be the next clock cycle after the target clock cycle.

[0034] For example, when the selection window corresponding to the current receiving round indicates that the duration is three clock cycles, the aforementioned adjacent clock cycles can be the previous clock cycle and the next clock cycle of the target clock cycle, or the aforementioned adjacent clock cycles can be the next clock cycle and the next two clock cycles of the target clock cycle.

[0035] S212: Merge the parallel data corresponding to the target clock cycle and the parallel data corresponding to the adjacent clock cycle to obtain the cached parallel data corresponding to the target clock cycle.

[0036] The parallel data corresponding to multiple clock cycles are concatenated to obtain the cached parallel data corresponding to the target clock cycle, which serves as the data range for delimiting the search of the target clock cycle.

[0037] When the adjacent clock cycle is the next clock cycle after the target clock cycle, the above step S212 can be implemented as follows: the parallel data corresponding to the target clock cycle is used as the high-order data in the cached parallel data; the parallel data corresponding to the next clock cycle is used as the low-order data in the cached parallel data.

[0038] For example, the parallel data corresponding to the i-th clock cycle can be denoted as... The parallel data corresponding to the next clock cycle can be denoted as That is, the parallel data corresponding to each clock cycle is M bits wide. The parallel data corresponding to the i-th clock cycle and the parallel data corresponding to the (i+1)-th clock cycle are merged into a 2*M-bit wide data set, which is used as the cached parallel data corresponding to the i-th clock cycle, and can be denoted as... ,in: It can be used as high-order data, that is In ; It can be used as low-order data, that is In .

[0039] It is understandable that, due to the transmission delay, the W-bit delimiter has a certain probability of being separated into parallel data corresponding to two clock cycles (the parallel data corresponding to each clock cycle is M bits wide). Therefore, the M-bit parallel data corresponding to two consecutive clock cycles can be merged into 2*M-bit wide data as cached parallel data so that the delimiter in the parallel data corresponding to each clock cycle can be accurately retrieved.

[0040] In the above embodiments, by flexibly setting the selection window in different receiving rounds, the data retrieval range for the target clock cycle during timing alignment can be dynamically adjusted, and problems such as bit offset or bit transition can be dealt with, thereby improving the accuracy of timing alignment.

[0041] S220: Split the preset delimiter to obtain multiple delimited reference data segments.

[0042] In this embodiment, a predefined delimiter with complete semantic information is split into multiple delimiting reference data segments. Each delimiting reference data segment is a local, continuous bit data segment within the predefined delimiter. Each delimiting reference data segment serves as a reference and basis for subsequent delimiting retrieval.

[0043] Among them, the default delimiter is a symbol used to delimit characters, and its main function is to identify the start or end position of data.

[0044] In one embodiment of this application, the number of delimiting reference data segments can be determined based on the length (bit width) of the parallel data corresponding to each clock cycle and the length (bit width) of the preset delimiter. Optionally, the number of delimiting reference data segments can be four.

[0045] In one embodiment of this application, a preset delimiter can be equally divided to obtain multiple delimiting reference data segments. The multiple delimiting reference data segments do not overlap with each other, and the multiple delimiting reference data segments form a complete preset delimiter.

[0046] For example, a W-bit wide predefined delimiter D can be divided into four delimited reference data segments, namely... W-bit width SynCode <0> SynCode <1> SynCode <2> SynCode <3> , where: SynCode <0> = D[W-1: *W], that is, the bit data of the first delimiting reference data segment is the (W-1)th bit to the (W-1)th bit of the preset delimiter. *W bits of data; SynCode <1> = D[ *W-1: *W], that is, the bit data of the second delimiting reference data segment is the bit data of the preset delimiter. *W-1 to the 1st position *W bits of data; SynCode <2> = D[ *W-1: *W], that is, the bit data of the third delimiting reference data segment is the bit data of the preset delimiter. *W position to the 1st *W bits of data; SynCode <3> = D[ *W-1:0], that is, the bit data of the fourth delimiting reference data segment is the bit data of the preset delimiter. *W bits to bit 0.

[0047] In another embodiment of this application, the preset delimiters can also be split in an overlapping manner or in an unequal manner.

[0048] S230: Based on each of the multiple delimited reference data segments, shift and select the cached parallel data corresponding to the target clock cycle to obtain multiple data segments to be retrieved corresponding to each delimited reference data segment.

[0049] In this embodiment, based on the bit width of each delimiting reference data segment, the cached parallel data corresponding to the target clock cycle is shifted and selected to form multiple arrays. Each array includes multiple data segments to be retrieved corresponding to a delimiting reference data segment, and each data segment to be retrieved is the smallest data object for delimiting retrieval. The bit width of each data segment to be retrieved can be the same as the bit width of the corresponding delimiting reference data segment.

[0050] In another embodiment of this application, there may be overlapping data bits between multiple data segments to be retrieved corresponding to the same delimited reference data segment; there may also be overlapping data bits or duplicate data segments to be retrieved between multiple data segments to be retrieved corresponding to different delimited reference data segments.

[0051] In one embodiment of this application, step S230 can be implemented as follows: S231: Determine the starting selection position corresponding to each delimited reference data segment in the cached parallel data.

[0052] S232: Based on the initial selection position, extract a continuous data segment of a preset length from the cached parallel data, and move the initial selection position bit by bit to extract multiple times to obtain multiple data segments to be retrieved corresponding to each delimited reference data segment.

[0053] The preset length is the same as the length of the corresponding delimited reference data segment.

[0054] For example, the cached parallel data corresponding to the target clock cycle can be denoted as data_in_buffer<2*M-1:0>, and the parallel data corresponding to the target clock cycle is located in the high-order bits of the cached parallel data. The preset delimiter can be denoted as Delimiter. <w-1:0>The default delimiter has a bit width of W, which is the same as the aforementioned delimiter reference data segment SynCode. <0> = D[W-1: The multiple data segments to be retrieved corresponding to *W] can be represented as search_data <0> <j>< *W-1:0>, where 0≤j<M, j is an integer, meaning the bit width of each data segment to be retrieved is also . *W, the highest bit of the cached parallel data data_in_buffer<2*M-1:0> corresponding to the target clock cycle can be used as the delimiting reference data segment SynCode. <0> The initial starting position is selected, and a W-bit wide data segment is extracted as the delimiting reference data segment SynCode. <0> The first corresponding data segment to be retrieved, search_data <0> <0> <= data_in_buffer<2*M-1:2*M- *W>; Then, offset the starting selection position by one bit, and extract another W-bit wide data segment as the delimiting reference data segment SynCode. <0> The corresponding second data segment to be retrieved, search_data <0> <1> <= data_in_buffer<2*M-2:2*M- *W-1>......until the delimited reference data segment SynCode is extracted. <0> The corresponding Mth data segment to be retrieved, search_data <0> <m-1><= data_in_buffer <M: M- *W+1>; and the above-mentioned delimited reference data segment SynCode <1> = D[ *W-1: The multiple data segments to be retrieved corresponding to *W] can be represented as search_data <1> <j>< *W-1:0>, where 0≤j<M, j is an integer, and the bit width of each data segment to be retrieved is also . *W can be obtained from the 2nd*M-th of the cached parallel data data_in_buffer<2*M-1:0> corresponding to the target clock cycle. Starting with bit W-1, extract a data segment of width W, shifting by one bit each time, until M data segments to be retrieved are obtained; this is related to the aforementioned delimited reference data segment SynCode. <2> = D[ *W-1: The multiple data segments to be retrieved corresponding to *W] can be represented as search_data <2> <j>< *W-1:0>, where 0≤j<M, j is an integer, and the bit width of each data segment to be retrieved is also . *W can be obtained from the 2nd*M-th of the cached parallel data data_in_buffer<2*M-1:0> corresponding to the target clock cycle. *Starting with bit W-1, extract a data segment of width W, shifting by one bit each time, until M data segments to be retrieved are obtained; this is related to the aforementioned delimited reference data segment SynCode. <3> = D[ The multiple data segments to be retrieved corresponding to *W-1:0] can be represented as search_data <3> <j>< *W-1:0>, where 0≤j<M, j is an integer, and the bit width of each data segment to be retrieved is also . *W can be obtained from the 2*M- of the cached parallel data data_in_buffer<2*M-1:0> corresponding to the target clock cycle. *Starting with bit W-1, extract a data segment of width W, and offset by one bit each time, until M data segments to be retrieved are obtained.

[0055] With search_data <0> <0> For example, search_data <0> <0> <= data_in_buffer<2*M-1:2*M- *W> indicates that the data from the 2*M-1th bit to the 2*M-th bit in data_in_buffer<2*M-1:0> will be stored in the buffer. *W bits represent data_in_buffer<2*M-1:2*M- *W> is assigned the value search_data <0> <0> .

[0056] Based on the above splitting and shifting selection methods, if a searchable data segment that is the same as its respective delimiting reference data segment can be found, then the searchable data segments that are the same as their respective delimiting reference data segments are in the same position, that is, the values ​​of j are the same.

[0057] In the above embodiments, by splitting the preset delimiter and performing a certain width shift selection on the cached parallel data, the local cached parallel data obtained by the shift selection is delimited based on the data segment of the split part of the preset delimiter. This provides more decision criteria for subsequently determining the position of the preset delimiter in the cached parallel data, and improves the accuracy and effectiveness of the delimitation retrieval.

[0058] S240: Based on each delimitation reference data segment, search for multiple data segments to be searched corresponding to each delimitation reference data segment to obtain the first delimitation indication information corresponding to each delimitation reference data segment.

[0059] In this embodiment, each delimited reference data segment is used to search multiple data segments corresponding to each delimited reference data segment. The search determines whether any data segment identical to the corresponding delimited reference data segment exists among these multiple data segments, thus determining the position of each delimited reference data segment in the cached parallel data corresponding to the target clock cycle. That is, the first delimitation indication information corresponding to each delimited reference data segment can indicate whether a data segment identical to the corresponding delimited reference data segment exists in the cached parallel data corresponding to the target clock cycle or among the multiple data segments corresponding to each delimited reference data segment. It also indicates the position of this data segment within the multiple data segments corresponding to the corresponding delimited reference data segment or within the cached parallel data corresponding to the target clock cycle.

[0060] In the embodiments of this application, the first delimitation indication information corresponding to each of the multiple delimitation reference data segments provides more decision-making basis for subsequently determining the position of the complete preset delimiter in the cached parallel data, thereby improving the accuracy and effectiveness of delimitation retrieval.

[0061] In one embodiment of this application, as shown in FIG3, step S240 can be implemented as follows: S241: perform bit matching between each data segment to be retrieved in the plurality of data segments to be retrieved corresponding to each delimited reference data segment and the corresponding delimited reference data segment to obtain a plurality of matching results corresponding to each delimited reference data segment.

[0062] Based on the fact that the bit width or / length of each data segment to be retrieved in the multiple data segments corresponding to each delimiting reference data segment is the same as the bit width / length of the corresponding delimiting reference data segment, each data segment to be retrieved in the multiple data segments corresponding to each delimiting reference data segment can be compared and matched bit by bit with the corresponding delimiting reference data segment to obtain multiple matching results corresponding to each delimiting reference data segment. Each matching result indicates whether a data segment to be retrieved is the same as the corresponding delimiting reference data segment. Here, "same" means that the data on each bit is the same, that is, completely identical.

[0063] Optionally, the matching results can also indicate the degree of similarity between a data segment to be retrieved and the corresponding delimited reference data segment. The degree of similarity can be characterized by the proportion of identical bits in the data.

[0064] S242: Based on multiple matching results corresponding to each delimitation reference data segment, determine the first delimitation indication information corresponding to each delimitation reference data segment.

[0065] Feasibly, the first delimiting indication information corresponding to each delimiting reference data segment may include indication identification information and delimiting position information; the indication identification information indicates whether there is a searchable data segment identical to the corresponding delimiting reference data segment among the multiple searchable data segments corresponding to the corresponding delimiting reference data segment; the delimiting position information indicates the position of the searchable data segment identical to the corresponding delimiting reference data segment in the cached parallel data when the indication identification information indicates that there is a searchable data segment identical to the corresponding delimiting reference data segment among the multiple searchable data segments corresponding to the corresponding delimiting reference data segment.

[0066] For example, based on the aforementioned exemplary embodiment, in the delimitation reference data segment SynCode <0> The corresponding multiple search data segments search_data <0> <j>If the search_data segment to be retrieved exists in the search_data segment... <0> <32> With SynCode <0> If they are the same, it indicates that the delimited reference data segment SynCode is being defined. <0> It exists in the cached parallel data data_in_buffer<2*M-1:0> corresponding to the target clock cycle, and its position in the cached parallel data data_in_buffer<2*M-1:0> is 32, which can be used to define the delimited reference data segment SynCode. <0> The corresponding indicator flag information Match_flag0 = 1, and the delimiting reference data segment SynCode is set. <0> The corresponding delimiting location information is Match_ID0 = 32; in the delimiting reference data segment SynCode... <1> The corresponding multiple data segments to be inspected, search_data <1> <j>If it exists in the array when search_data <1> <32> = SynCode <1> This indicates that the delimited reference data segment is SynCode. <1> It exists in the cached parallel data data_in_buffer<2*M-1:0> corresponding to the target clock cycle, and its position in the cached parallel data data_in_buffer<2*M-1:0> is 32, which can be used to define the delimited reference data segment SynCode. <1> The corresponding indicator flag information Match_flag1 = 1, and the delimiting reference data segment SynCode is set. <1> The corresponding delimiting location information is Match_ID1=32; similarly, if the delimiting reference data segment SynCode<0~3> is located in its respective multiple search data segments search_data<0~3>... <j>If a matching data segment can be found in each delimiting reference data segment, then the first delimiting indication information corresponding to each delimiting reference data segment includes a set of indication flag information Match_flag and delimiting position information Match_ID. If no matching data segment can be found, the indication flag information Match_flag can be set to 0.

[0067] S250: Based on the first delimitation indication information corresponding to each delimitation reference data segment and the decision window corresponding to the target clock cycle, determine the second delimitation indication information corresponding to the cached parallel data.

[0068] The current duration of the decision window corresponding to the target clock cycle is determined based on the second delimitation indication information corresponding to the target clock cycle in the previous receiving round.

[0069] In this embodiment, the first delimiting indication information corresponding to each of the multiple delimiting reference data segments provides more decision-making basis for determining the position of the complete preset delimiter in the cached parallel data. This embodiment can, within the current duration of the decision window corresponding to the target clock cycle (i.e., the effective duration of the decision window corresponding to the target clock cycle in the current reception round), comprehensively decide and evaluate whether there exists a data segment (hereinafter referred to as the target data segment) in the cached parallel data corresponding to the target clock cycle that is the same as or similar to the entire preset delimiter, based on the first delimiting indication information corresponding to each delimiting reference data segment. If such a data segment exists, the position of the target data segment in the cached parallel data corresponding to the target clock cycle can also be indicated. That is, the second delimiting indication information corresponding to the aforementioned cached parallel data can indicate whether there is a target data segment in the cached parallel data corresponding to the target clock cycle that is the same as or similar to the preset delimiter, and can also indicate the position of the target data segment in the cached parallel data corresponding to the target clock cycle.

[0070] In this embodiment, by comprehensively adjudicating and evaluating whether a target data segment identical or similar to the entire preset delimiter exists in the cached parallel data corresponding to the target clock cycle based on the first delimiting indication information corresponding to each delimiting reference data segment, the preset delimiter in the cached parallel data corresponding to the target clock cycle can be retrieved and located even if the preset delimiter is disturbed or shifted to a certain extent, thereby enabling stable and accurate timing alignment. The bit width of the delimiting reference data segment and the specific adjudication strategy reflect the fault tolerance capability provided by this embodiment.

[0071] In another embodiment of this application, the above method may further include: S251: In the first receiving round, if the indication identifier information in the first delimitation indication information corresponding to each delimitation reference data segment indicates that there is a searchable data segment with the same name as the corresponding delimitation reference data segment among the multiple searchable data segments corresponding to the corresponding delimitation reference data segment, then based on the delimitation position information in the first delimitation indication information corresponding to each delimitation reference data segment, a second delimitation indication information corresponding to the cached parallel data is determined; the second delimitation indication information corresponding to the cached parallel data indicates that there is a target data segment with the same name as the preset delimiter in the cached parallel data, and indicates the position of the target data segment in the cached parallel data.

[0072] In other words, if a data segment identical to the corresponding delimiting reference data segment is found among multiple data segments to be retrieved corresponding to each delimiting reference data segment (at this time, the indicator flag information Match_flag corresponding to each delimiting reference data segment can all be 1), then it can be directly determined that a pre-delimited symbol exists in the cached parallel data corresponding to the target clock cycle. Then, the position of the pre-delimited symbol (which is also the target data segment) in the cached parallel data corresponding to the target clock cycle can be determined according to the delimiting position information Match_ID corresponding to each delimiting reference data segment, and it can be recorded as Select_ID.

[0073] In an optional implementation, if the indication information in the first delimitation indication information corresponding to each delimitation reference data segment indicates that there is a searchable data segment with the same name as the corresponding delimitation reference data segment among the multiple searchable data segments corresponding to the corresponding delimitation reference data segment, step S251 may further include: S2511: performing a consistency check on the delimitation position information in the first delimitation indication information corresponding to each delimitation reference data segment to obtain the position consistency check result.

[0074] In other words, the position consistency test result indicates whether the delimitation position information in the first delimitation indication information corresponding to each delimitation reference data segment is the same.

[0075] S2512: If the position consistency test result indicates that all delimited position information is the same, then each delimited position information shall be used as the second delimited indication information corresponding to the cached parallel data.

[0076] The accuracy of the Select_ID data can be improved by checking the location consistency.

[0077] In one embodiment of this application, specifically, the first delimitation indication information corresponding to each delimitation reference data segment includes indication identification information and delimitation location information. Step S250 may include: S252: within the current duration of the adjudication window corresponding to the target clock cycle, if the indication identification information in the first delimitation indication information corresponding to each delimitation reference data segment does not completely indicate that there is a searchable data segment identical to the corresponding delimitation reference data segment among the multiple searchable data segments corresponding to the corresponding delimitation reference data segment, then the indication identification information in the first delimitation indication information corresponding to each delimitation reference data segment is statistically analyzed to obtain identification statistics data.

[0078] It is feasible that when the Match_flag in the first delimitation indication information is 1, it indicates that among the multiple data segments to be retrieved corresponding to the corresponding delimitation reference data segment, there exists a data segment to be retrieved that is identical to the corresponding delimitation reference data segment; when the Match_flag in the first delimitation indication information is 0, it indicates that among the multiple data segments to be retrieved corresponding to the corresponding delimitation reference data segment, there is no data segment to be retrieved that is identical to the corresponding delimitation reference data segment. Since the indication flags in the first delimitation indication information corresponding to each delimitation reference data segment do not completely indicate the existence of a data segment to be retrieved that is identical to the corresponding delimitation reference data segment among the multiple data segments to be retrieved corresponding to the corresponding delimitation reference data segment, some indication flags in the first delimitation indication information corresponding to each delimitation reference data segment may have a Match_flag of 1, while others may have a Match_flag of 0.

[0079] It is feasible to identify the statistical data, which can indicate the number of indication flags with Match_flag set to 1 in the first delimitation indication information corresponding to each delimitation reference data segment, as well as the delimitation reference data segment corresponding to Match_flag set to 1.

[0080] S253: Based on the adjudication strategy corresponding to the identifier statistics and the delimitation position information in the first delimitation indication information corresponding to each delimitation reference data segment, the second delimitation indication information corresponding to the cached parallel data is obtained; the second delimitation indication information corresponding to the cached parallel data indicates that there is a target data segment in the cached parallel data that is similar to the preset delimiter, and indicates the position of the target data segment in the cached parallel data.

[0081] The adjudication strategy corresponding to the identification statistics can be designed according to specific business needs. In this way, even if the indicator information in the first delimitation indication information corresponding to each delimitation reference data segment does not completely indicate that there is a searchable data segment with the same name as the corresponding delimitation reference data segment among multiple searchable data segments corresponding to the corresponding delimitation reference data segment, the preset delimitation symbol can be retrieved and located, thereby dealing with a certain degree of disturbance or offset.

[0082] For example, based on the aforementioned exemplary embodiment, the number of times the four Match_flags are 1 is counted and denoted as the identifier statistics Match_flag_num; when Match_flag_num = 3, if Match_flag0 = 1, Match_flag1 = 1, Match_ID0 = Match_ID1, then Select_ID <= Match_ID0, that is, Match_ID0 is assigned to Select_ID; if Match_flag0 = 1, Match_flag2 = 1, Match_ID0 = Match_ID2, then Select_ID <= Match_ID0; if Match_flag0 = 1, Match_flag3 = 1, Match_ID0 = Match_ID3, then Select_ID <= Match_ID0; if Match_flag0 = 1, Match_flag2 = 1, Match_ID1 = Match_ID2, then Select_ID <= Match_ID1; if Match_flag1 = 1, Match_flag3 = 1, Match_ID1 = Match_ID3, then Select_ID<=Match_ID1; if Match_flag2 = 1, Match_flag3 = 1, Match_ID2 = Match_ID3, then Select_ID<=Match_ID2.

[0083] When Match_flag_num = 2, the corresponding decision strategy can be executed to determine Select_ID. Alternatively, when Match_flag_num ≤ 2, it can be considered that the error in determining Select_ID is large, so timing alignment of the target clock cycle can be skipped.

[0084] In one embodiment of this application, step S250 may optionally include: S254: within the current duration of the adjudication window corresponding to the target clock cycle, if the indication information in the first delimitation indication information corresponding to each delimitation reference data segment indicates that there is no data segment to be retrieved that is the same as the corresponding delimitation reference data segment among the multiple data segments to be retrieved corresponding to the corresponding delimitation reference data segment, then the timing alignment of the target clock cycle is skipped.

[0085] Alternatively, the cached parallel data corresponding to the target clock cycle can be redefined by expanding the cached data range, and the above delimitation retrieval process can be re-executed.

[0086] S260: When the second delimiting indication information corresponding to the cached parallel data indicates that there is a target data segment in the cached parallel data corresponding to the target clock cycle that is the same as or similar to the preset delimiter, the cached parallel data is extracted according to the second delimiting indication information corresponding to the cached parallel data to obtain the aligned parallel data corresponding to the target clock cycle.

[0087] In this embodiment of the application, the cached parallel data is extracted into continuous data segments according to the second delimiting indication information corresponding to the cached parallel data. The bit width of the aligned parallel data corresponding to the target clock cycle is the same as the bit width of the parallel data corresponding to the target clock cycle. The aligned parallel data corresponding to the target clock cycle is a data segment with a bit width starting from the target data segment (or it can be considered as starting from the preset delimiter).

[0088] In one embodiment of this application, if the second delimiting indication information Select_ID corresponding to the cached parallel data is k (0≤k<M), it indicates that there is a target data segment in the cached parallel data corresponding to the target clock cycle that is the same as or similar to the preset delimiter, and the position of the target data segment in the cached parallel data corresponding to the target clock cycle is data_in_buffer<2*Mk-1: 2*MWk>. Then, starting from the 2*Mk-1th bit of the cached parallel data data_in_buffer<2*M-1:0> corresponding to the target clock cycle, M bits of data can be extracted to obtain the M-bit wide aligned parallel data data_out corresponding to the target clock cycle. <m-1:0>When the target clock cycle is the i-th clock cycle, the aligned parallel data corresponding to the i-th clock cycle. , that is yes The data segment from bit 2*Mk-1 to bit Mk.

[0089] In one embodiment of this application, the above method may further include: S310: when the second delimitation indication information corresponding to the cached parallel data indicates that the target data segment is located at the boundary position of the parallel data corresponding to the target clock cycle, determine the first duration of the decision window.

[0090] Here, the boundary position refers to the highest T bits or the lowest T bits of the above parallel data. T can be 1 or 2, etc., and there is no restriction here.

[0091] For example, if the parallel data bit width corresponding to the target clock cycle is M, and the second delimiting indication information Select_ID = M-1 or Select_ID = 0 corresponding to the buffered parallel data, then the determined target data segment can be considered to be located at the boundary position of the parallel data corresponding to the current clock. In subsequent receiving rounds, due to external environmental disturbances or errors in the data stream, the parallel data corresponding to a certain clock cycle may experience a bit offset or error, which may affect the retrieval result of the preset delimiter in the buffered parallel data corresponding to that clock cycle. For example, the preset delimiter may not be retrieved, or the aligned parallel data of the specified bit width may not be extracted.

[0092] For example, when the second delimiting indication information Select_ID = 0 corresponding to the cached parallel data, it means that the target data segment is in the high bit of the parallel data corresponding to the target clock cycle. In subsequent reception rounds, the problem of left offset may easily occur. Therefore, the first duration of the decision window can be set to three clock cycles.

[0093] For example, when the second delimiting indication information Select_ID = M-1 corresponding to the cached parallel data, it indicates that the target data segment is in the low bit of the parallel data corresponding to the target clock cycle. In subsequent reception rounds, the problem of right offset is likely to occur. Therefore, the first duration of the decision window can be set to three clock cycles.

[0094] S310: When the second delimitation indication information corresponding to the cached parallel data indicates that the target data segment is located at the non-boundary position of the parallel data corresponding to the target clock cycle, determine the second duration of the decision window.

[0095] Non-boundary locations refer to the portion of the parallel data other than the boundary locations mentioned above.

[0096] For example, if the parallel data bit width corresponding to the target clock cycle is M, and the second delimiting indication information corresponding to the buffered parallel data is 0 < Select_ID < M-1, even if a bit offset or error occurs, the preset delimiter will still appear in the buffered parallel data corresponding to the target clock cycle in subsequent receiving rounds. And according to the determined position of the target data segment, M-bit width aligned parallel data can be extracted. Therefore, the second duration of the adjudication window corresponding to the target clock cycle in subsequent receiving rounds can be set to one clock cycle.

[0097] The aforementioned first or second duration is the next duration of the decision window corresponding to the target clock cycle in the next reception round. In subsequent reception rounds, by dynamically adjusting the duration of the decision window corresponding to the target clock cycle in the subsequent reception rounds, sufficient opportunity is provided to determine or update the second delimitation indication information based on the cached parallel data corresponding to the target clock cycle in the subsequent reception rounds, thereby ensuring the effectiveness and accuracy of delimitation retrieval.

[0098] In one embodiment of this application, taking the current reception round as an example, the control of the current duration of the adjudication window corresponding to the target clock cycle can be achieved by the following steps: S410: After determining the second delimitation indication information corresponding to the target clock cycle in the previous reception round, start the target counter corresponding to the target clock cycle.

[0099] The initial value of the target counter is the same as the length of the clock cycle of the parallel data stream; the value of the target counter is decremented by 1 every clock cycle.

[0100] S420: When the value of the target counter decreases to a preset threshold corresponding to the current duration, the adjudication window corresponding to the target clock cycle is opened until the target counter finishes counting and the adjudication window corresponding to the target clock cycle is closed, so as to determine the second delimitation indication information corresponding to the buffered parallel data in the current receiving round within the current duration of the adjudication window corresponding to the target clock cycle.

[0101] For example, when the current duration is one clock cycle, the preset threshold is 0; when the current duration is three clock cycles, the preset threshold is 2. It is feasible to trigger a pulse signal (Loadtimer_flag) after determining the second delimitation indication information corresponding to the target clock cycle in the previous reception round. When Loadtimer_flag=1, the target counter corresponding to the target clock cycle is started. The target counter can be a decrementing counter, with its initial value being the same as the length of the clock cycle of the parallel data stream. When the pulse signal arrives, the target counter begins to decrement, and its value automatically decreases by 1 every clock cycle. If the second delimiting indication information Select_ID corresponding to the target clock cycle in the previous reception round indicates that the preset delimiter is not at the boundary position, then when the value of the target counter decreases to 0, a decision window of one clock cycle will be generated. If the second delimiting indication information Select_ID corresponding to the target clock cycle in the previous reception round indicates that the preset delimiter is at the boundary position, then when the value of the target counter is 2, 1, or 0, a decision window of one clock cycle will be generated respectively, thus forming a decision window with a current duration of three clock cycles. Furthermore, in the current reception round, after determining the second delimiting indication information corresponding to the buffered parallel data, a target counter corresponding to the target clock cycle will also be generated to control the duration of the decision window corresponding to the target clock cycle in the next reception round as the next duration.

[0102] In one embodiment of this application, in order to identify and remove pseudo-random codes in the parallel data stream to achieve time alignment of valid data, a timer or clock cycle counter l can be set. When the parallel data stream is received, a pulse signal is generated synchronously. The pulse signal is used to trigger the timer and set an initial value timer_count = L, which corresponds to the length of the pseudo-random code (L M bits wide, occupying L clock cycles). After each clock cycle, timer_count is decremented by 1. When timer_count is 0, delimitation search and data alignment processing are performed clock cycle by clock cycle.

[0103] Figure 4 is a schematic diagram of a hardware implementation module provided in an embodiment of this application. As shown in Figure 4, the parallel data buffer pool is used for parallel data data_in of M bits width for each clock cycle based on the selection window corresponding to the current receiving round. <m-1:0>Cache merging is performed, such as merging the parallel data corresponding to the target clock cycle and the next clock cycle to obtain the cached parallel data data_in_buffer<2*M-1:0> corresponding to the target clock cycle; the feature position retrieval module is used to search for the delimiter D in the cached parallel data. First, the delimiter D is split to obtain multiple delimiting reference data segments SynCode<0~3>. Then, multiple searchable data segments search_data<0~3> corresponding to each of the multiple delimiting reference data segments are selected from the cached parallel data, and the first delimiting indication information corresponding to each delimiting reference data segment is retrieved and output. The first delimiting indication information corresponding to each delimiting reference data segment includes a set of Match_flag and Match_ID. Figure 4 shows four sets of Match_flag and Match_ID; the alignment adjudication module is used to determine the second delimiting indication information Select_ID corresponding to the cached parallel data within the current duration of the adjudication window corresponding to the target clock cycle based on the multiple sets of output Match_flag and Match_ID. For example, it can be in Match_flag_num In cases where ≥3, the second delimiting indication information Select_ID is determined, and the next duration of the adjudication window Window_D corresponding to the next reception round is re-determined by triggering a pulse signal (Loadtimer_flag). The sorting module is used to extract data from the buffered parallel data according to the second delimiting indication information Select_ID corresponding to the buffered parallel data to obtain the aligned parallel data Data_out corresponding to the target clock cycle. <m-1:0>The above process can be referred to the foregoing embodiments, and will not be repeated here.

[0104] As can be seen from the above embodiments, the timing alignment method provided in this application determines the buffered parallel data corresponding to the target clock cycle from the parallel data stream corresponding to the current receiving round, wherein the target clock cycle is any clock cycle in the parallel data stream; the scheme provided in this application splits a preset delimiter to obtain multiple delimiting reference data segments, and based on each delimiting reference data segment, shifts and selects the buffered parallel data corresponding to the target clock cycle to obtain multiple data segments to be retrieved corresponding to each delimiting reference data segment, which serve as the objects of delimiting retrieval; the scheme provided in this application, based on each delimiting reference data segment, retrieves the multiple data segments to be retrieved corresponding to each delimiting reference data segment to obtain the first delimiting indication information corresponding to each delimiting reference data segment. Furthermore, based on the first delimiting indication information corresponding to each delimiting reference data segment and the adjudication window corresponding to the target clock cycle, the second delimiting indication information corresponding to the buffered parallel data of the target clock cycle can be determined. The current duration of the adjudication window corresponding to the target clock cycle is determined based on the second delimiting indication information corresponding to the target clock cycle in the previous reception round. If the second delimiting indication information corresponding to the buffered parallel data indicates the presence of a target data segment in the buffered parallel data corresponding to the target clock cycle that is identical or similar to the preset delimiter, the buffered parallel data can be extracted according to the second delimiting indication information to obtain the aligned parallel data corresponding to the target clock cycle, and then accurately deserialized. The scheme provided in this application can accurately perform clock-cycle-by-clock-cycle timing alignment of parallel data streams, and through the dual decomposition and retrieval of the preset delimiter and the buffered parallel data, it can more stably and precisely guarantee the recovery and alignment of data timing when disturbances occur.

[0105] This application embodiment also provides a timing alignment device 500, as shown in FIG5. The device may include: a data acquisition module 510, used to determine the cached parallel data corresponding to a target clock cycle from the parallel data stream corresponding to the current receiving round; the target clock cycle is any clock cycle in the parallel data stream; a delimiter splitting module 520, used to split a preset delimiter to obtain multiple delimiter reference data segments; a shift selection module 530, used to shift and select the cached parallel data corresponding to the target clock cycle based on each of the multiple delimiter reference data segments to obtain multiple data segments to be retrieved corresponding to each delimiter reference data segment; and a retrieval module 540, used to retrieve the multiple data segments to be retrieved corresponding to each delimiter reference data segment based on each delimiter reference data segment. The first delimiting indication information corresponding to each delimiting reference data segment is obtained; the delimiting module 550 is used to determine the second delimiting indication information corresponding to the cached parallel data based on the first delimiting indication information corresponding to each delimiting reference data segment and the adjudication window corresponding to the target clock cycle; the current duration of the adjudication window corresponding to the target clock cycle is determined based on the second delimiting indication information corresponding to the target clock cycle in the previous reception round; the data extraction module 560 is used to extract the cached parallel data according to the second delimiting indication information corresponding to the cached parallel data when the second delimiting indication information corresponding to the cached parallel data indicates that there is a target data segment in the cached parallel data corresponding to the target clock cycle that is the same as or similar to the preset delimiter, to obtain the aligned parallel data corresponding to the target clock cycle.

[0106] In one embodiment of this application, the data acquisition module 510 includes: a data caching unit, configured to determine parallel data corresponding to the target clock cycle and parallel data corresponding to an adjacent clock cycle relative to the target clock cycle based on the selection window corresponding to the current receiving round and the parallel data stream corresponding to the current receiving round; and a data merging unit, configured to merge the parallel data corresponding to the target clock cycle and the parallel data corresponding to the adjacent clock cycle to obtain cached parallel data corresponding to the target clock cycle.

[0107] In one embodiment of this application, the delimiter splitting module 520 includes: an equal division unit, used to equally divide the preset delimiter to obtain the plurality of delimiter reference data segments, wherein the plurality of delimiter reference data segments do not overlap with each other, and the plurality of delimiter reference data segments constitute the complete preset delimiter.

[0108] In one embodiment of this application, the delimiter splitting module 520 further includes: a quantity determination unit, used to determine the quantity of the delimiting reference data segment based on the length of the parallel data and the length of the preset delimiter.

[0109] In one embodiment of this application, the shift selection module 530 includes: a starting selection position determination unit, configured to determine the starting selection position corresponding to each delimited reference data segment in the cached parallel data; and a shift extraction unit, configured to extract a continuous data segment of a preset length from the cached parallel data based on the starting selection position, and perform multiple extractions by shifting the starting selection position bit by bit to obtain multiple data segments to be retrieved corresponding to each delimited reference data segment; wherein the preset length is the same as the length of the corresponding delimited reference data segment.

[0110] In one embodiment of this application, the retrieval module 540 includes: a bit matching unit, configured to perform bit matching between each of the plurality of data segments to be retrieved corresponding to each delimited reference data segment and the corresponding delimited reference data segment to obtain a plurality of matching results corresponding to each delimited reference data segment; and a first indication determination unit, configured to determine first delimited indication information corresponding to each delimited reference data segment based on the plurality of matching results corresponding to each delimited reference data segment; the first delimited indication information corresponding to each delimited reference data segment includes indication identification information and delimited position information; the indication identification information indicates whether there is a data segment to be retrieved that is the same as the corresponding delimited reference data segment among the plurality of data segments to be retrieved corresponding to the corresponding delimited reference data segment; and the delimited position information indicates the position of the data segment to be retrieved that is the same as the corresponding delimited reference data segment in the cached parallel data when the indication identification information indicates that there is a data segment to be retrieved that is the same as the corresponding delimited reference data segment among the plurality of data segments to be retrieved corresponding to the corresponding delimited reference data segment.

[0111] In one embodiment of this application, the apparatus 500 further includes: a second indication determination unit, configured to, in a first receiving round, if the indication identifier information in the first delimitation indication information corresponding to each delimitation reference data segment indicates that there is a searchable data segment identical to the corresponding delimitation reference data segment among the plurality of searchable data segments corresponding to the corresponding delimitation reference data segment, then determine the second delimitation indication information corresponding to the cached parallel data based on the delimitation position information in the first delimitation indication information corresponding to each delimitation reference data segment; the second delimitation indication information corresponding to the cached parallel data indicates that there is a target data segment identical to the preset delimiter in the cached parallel data, and indicates the position of the target data segment in the cached parallel data.

[0112] In one embodiment of this application, the delimiting module 550 is further configured to skip timing alignment of the target clock cycle if, within the current duration of the adjudication window corresponding to the target clock cycle, the indication information in the first delimiting indication information corresponding to each delimiting reference data segment indicates that there is no searchable data segment identical to the corresponding delimiting reference data segment among the multiple searchable data segments corresponding to the corresponding delimiting reference data segment.

[0113] In one embodiment of this application, the delimiting module 550 includes: a statistics unit, configured to, within the current duration of the adjudication window corresponding to the target clock cycle, if the indication identifier information in the first delimiting indication information corresponding to each delimiting reference data segment does not completely indicate that there is a searchable data segment identical to the corresponding delimiting reference data segment among the multiple searchable data segments corresponding to the corresponding delimiting reference data segment, then perform statistics on the indication identifier information in the first delimiting indication information corresponding to each delimiting reference data segment to obtain an identifier statistics data set; a third indication determination unit, configured to, based on the adjudication strategy corresponding to the identifier statistics data set and the delimiting position information in the first delimiting indication information corresponding to each delimiting reference data segment, obtain second delimiting indication information corresponding to the cached parallel data; the second delimiting indication information corresponding to the cached parallel data indicates that there is a target data segment in the cached parallel data that is similar to the preset delimiter, and indicates the position of the target data segment in the cached parallel data.

[0114] In one embodiment of this application, the apparatus 500 further includes: a first window unit, configured to determine a first duration of the adjudication window when the second delimitation indication information corresponding to the cached parallel data indicates that the target data segment is located at the boundary position of the parallel data corresponding to the target clock cycle; and a second window unit, configured to determine a second duration of the adjudication window when the second delimitation indication information corresponding to the cached parallel data indicates that the target data segment is located at the non-boundary position of the parallel data corresponding to the target clock cycle; wherein the first duration or the second duration is the next duration of the adjudication window corresponding to the target clock cycle in the next reception round.

[0115] In one embodiment of this application, the device 500 further includes: a timing start unit, configured to start a target counter corresponding to the target clock cycle after determining the second delimiting indication information corresponding to the target clock cycle in the previous receiving round; the initial value of the target counter is the same as the length of the clock cycle of the parallel data stream; the value of the target counter is decremented by 1 every clock cycle; and a window persistence unit, configured to open an adjudication window corresponding to the target clock cycle when the value of the target counter decreases to a preset threshold corresponding to the current persistence duration, until the adjudication window corresponding to the target clock cycle is closed after the target counter finishes counting, so as to determine the second delimiting indication information corresponding to the buffered parallel data in the current receiving round within the current persistence duration of the adjudication window corresponding to the target clock cycle.

[0116] In one embodiment of this application, the delimiting module 550 includes: a consistency verification unit, configured to perform a consistency verification on the delimiting position information in the first delimiting indication information corresponding to each delimiting reference data segment, and obtain a position consistency verification result; and a fourth indication determination unit, configured to, when the position consistency verification result indicates that each of the delimiting position information is the same, use each of the delimiting position information as the second delimiting indication information corresponding to the cached parallel data.

[0117] In the embodiments of this application, the terms "module" or "unit" refer to a computer program or part of a computer program that has a predetermined function and works with other related parts to achieve a predetermined goal, and can be implemented wholly or partially using software, hardware (such as processing circuitry or memory), or a combination thereof. Similarly, a processor (or multiple processors or memory) can be used to implement one or more modules or units. Furthermore, each module or unit can be part of an overall module or unit that includes the functionality of that module or unit.

[0118] It should be noted that the apparatus provided in the above embodiments is only illustrated by the division of the above functional modules when implementing its functions. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the apparatus and method embodiments provided in the above embodiments belong to the same concept, and the specific implementation process can be found in the method embodiments, which will not be repeated here.

[0119] This application provides a computer device including a processor and a memory. The memory stores at least one instruction or at least one program, which is loaded and executed by the processor to implement a timing alignment method as provided in the above method embodiments.

[0120] Figure 6 illustrates a hardware structure diagram of a device for implementing a timing alignment method provided in an embodiment of this application. The device may constitute or include the apparatus or system provided in the embodiment of this application. As shown in Figure 6, device 10 may include one or more processors (represented in Figure 6 as processors 1002a, 1002b, ..., 1002n, which may include, but are not limited to, microprocessors (MCUs) or programmable logic devices (FPGAs), a memory 1004 for storing data, and a transmission device 1006 for communication functions. In addition, it may include: a display, an input / output interface (I / O interface), a universal serial bus (USB) port (which may be included as one of the ports of the I / O interface), a network interface, a power supply, and / or a camera. Those skilled in the art will understand that the structure shown in Figure 6 is merely illustrative and does not limit the structure of the aforementioned electronic device. For example, device 10 may also include more or fewer components than shown in Figure 6, or have a different configuration than shown in Figure 6.

[0121] It should be noted that the aforementioned one or more processors and / or other data processing circuits are generally referred to herein as "data processing circuits". These data processing circuits may be wholly or partially embodied in software, hardware, firmware, or any other combination thereof. Furthermore, the data processing circuits may be a single, independent processing module, or wholly or partially integrated into any other element within device 10 (or the mobile device). As involved in the embodiments of this application, the data processing circuits serve as a processor control mechanism (e.g., selection of a variable resistor termination path connected to an interface).

[0122] The memory 1004 can be used to store software programs and modules of application software, such as the program instructions / data storage device corresponding to the method described in the embodiments of this application. The processor executes various functional applications and data processing by running the software programs and modules stored in the memory 1004, thereby implementing the timing alignment method described above. The memory 1004 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 1004 may further include memory remotely located relative to the processor, and these remote memories can be connected to the device 10 via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0123] The transmission device 1006 is used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by the communication provider of device 10. In one example, the transmission device 1006 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 1006 may be a Radio Frequency (RF) module, used for wireless communication with the Internet.

[0124] The display may be, for example, a touchscreen liquid crystal display (LCD) that allows the user to interact with the user interface of device 10 (or mobile device).

[0125] This application embodiment also provides a computer-readable storage medium, which can be disposed in a server to store at least one instruction or at least one program related to implementing a timing alignment method in the method embodiment. The at least one instruction or the at least one program is loaded and executed by the processor to implement the timing alignment method provided in the above method embodiment.

[0126] Optionally, in this embodiment, the storage medium may be located at at least one of the multiple network servers in a computer network. Optionally, in this embodiment, the storage medium may include, but is not limited to, various media capable of storing program code, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0127] This invention also provides a computer program product or computer program, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform a timing alignment method provided in the various optional embodiments described above.

[0128] As can be seen from the embodiments of the timing alignment method, apparatus, medium, and device provided in this application, the scheme provided in this application determines the buffered parallel data corresponding to the target clock cycle from the parallel data stream corresponding to the current receiving round, wherein the target clock cycle is any clock cycle in the parallel data stream; the scheme provided in this application splits a preset delimiter to obtain multiple delimiting reference data segments, and based on each delimiting reference data segment, shifts and selects the buffered parallel data corresponding to the target clock cycle to obtain multiple data segments to be retrieved corresponding to each delimiting reference data segment, which serve as the objects of delimiting retrieval; the scheme provided in this application retrieves the multiple data segments to be retrieved corresponding to each delimiting reference data segment based on each delimiting reference data segment, to obtain the data segments to be retrieved corresponding to each delimiting reference data segment. The first delimiting indication information; then, based on the first delimiting indication information corresponding to each delimiting reference data segment and the adjudication window corresponding to the target clock cycle, the second delimiting indication information corresponding to the buffered parallel data of the target clock cycle can be determined, wherein the current duration of the adjudication window corresponding to the target clock cycle is determined based on the second delimiting indication information corresponding to the target clock cycle in the previous receiving round; if the second delimiting indication information corresponding to the buffered parallel data indicates that there is a target data segment in the buffered parallel data corresponding to the target clock cycle that is the same as or similar to the preset delimiter, the buffered parallel data can be extracted according to the second delimiting indication information corresponding to the buffered parallel data to obtain the aligned parallel data corresponding to the target clock cycle, and accurate deserialization processing can be performed. The scheme provided by this application can accurately perform clock cycle-by-clock-cycle timing alignment of parallel data streams, and through the dual splitting and retrieval of preset delimiters and buffered parallel data, it can more stably and precisely ensure the recovery and alignment of data timing when disturbances occur.

[0129] It should be noted that the order of the embodiments described above is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. Furthermore, the above description focuses on specific embodiments of this application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps described in the claims can be performed in a different order than that shown in the embodiments and still achieve the desired results. Additionally, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired results. In some implementations, multitasking and parallel processing are also possible or may be advantageous.

[0130] The various embodiments in this application are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the device, equipment, and storage medium embodiments are basically similar to the method embodiments, so the descriptions are relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0131] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0132] The above description is only a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application. < / j> < / j> < / j> < / j> < / j> < / j> < / j>

Claims

1. A timing alignment method, characterized in that, The method includes: determining buffered parallel data corresponding to a target clock cycle from the parallel data stream corresponding to the current receiving round; the target clock cycle being any clock cycle in the parallel data stream; splitting a preset delimiter to obtain multiple delimiting reference data segments; shifting and selecting the buffered parallel data corresponding to the target clock cycle based on each of the multiple delimiting reference data segments to obtain multiple data segments to be retrieved corresponding to each delimiting reference data segment; retrieving the multiple data segments to be retrieved corresponding to each delimiting reference data segment based on each delimiting reference data segment to obtain first delimiting indication information corresponding to each delimiting reference data segment; based on the... The first delimiting indication information corresponding to each delimiting reference data segment and the adjudication window corresponding to the target clock cycle are used to determine the second delimiting indication information corresponding to the cached parallel data. The current duration of the adjudication window corresponding to the target clock cycle is determined based on the second delimiting indication information corresponding to the target clock cycle in the previous reception round. If the second delimiting indication information corresponding to the cached parallel data indicates that there is a target data segment in the cached parallel data corresponding to the target clock cycle that is the same as or similar to the preset delimiter, the cached parallel data is extracted according to the second delimiting indication information corresponding to the cached parallel data to obtain the aligned parallel data corresponding to the target clock cycle.

2. The method according to claim 1, characterized in that, The step of determining the cached parallel data corresponding to the target clock cycle from the parallel data stream corresponding to the current receiving round includes: determining the parallel data corresponding to the target clock cycle and the parallel data corresponding to the adjacent clock cycle based on the selection window corresponding to the current receiving round and the parallel data stream corresponding to the current receiving round; merging the parallel data corresponding to the target clock cycle and the parallel data corresponding to the adjacent clock cycle to obtain the cached parallel data corresponding to the target clock cycle.

3. The method according to claim 1, characterized in that, The step of splitting the preset delimiter to obtain multiple delimiting reference data segments includes: equally dividing the preset delimiter to obtain the multiple delimiting reference data segments, wherein the multiple delimiting reference data segments do not overlap with each other, and the multiple delimiting reference data segments constitute the complete preset delimiter.

4. The method according to claim 3, characterized in that, The method further includes: determining the number of delimiting reference data segments based on the length of the parallel data and the length of the preset delimiter.

5. The method according to claim 1, characterized in that, The step of shifting and selecting the cached parallel data corresponding to the target clock cycle based on each of the plurality of delimited reference data segments to obtain a plurality of data segments to be retrieved corresponding to each delimited reference data segment includes: determining the starting selection position corresponding to each delimited reference data segment in the cached parallel data; based on the starting selection position, extracting a continuous data segment of a preset length from the cached parallel data, and moving the starting selection position bit by bit to perform multiple extractions to obtain a plurality of data segments to be retrieved corresponding to each delimited reference data segment; the preset length is the same as the length of the corresponding delimited reference data segment.

6. The method according to claim 1, characterized in that, The step of retrieving multiple data segments corresponding to each delimited reference data segment to obtain first delimiting indication information corresponding to each delimited reference data segment includes: performing bit matching between each data segment to be retrieved in the multiple data segments to be retrieved corresponding to each delimited reference data segment and the corresponding delimited reference data segment to obtain multiple matching results corresponding to each delimited reference data segment; determining the first delimiting indication information corresponding to each delimited reference data segment based on the multiple matching results corresponding to each delimited reference data segment; the first delimiting indication information corresponding to each delimited reference data segment includes indication identification information and delimiting position information; the indication identification information indicates whether there is a data segment to be retrieved that is the same as the corresponding delimited reference data segment in the multiple data segments to be retrieved corresponding to the corresponding delimited reference data segment; the delimiting position information indicates the position of the data segment to be retrieved that is the same as the corresponding delimited reference data segment in the cached parallel data when the indication identification information indicates that there is a data segment to be retrieved that is the same as the corresponding delimited reference data segment in the multiple data segments to be retrieved corresponding to the corresponding delimited reference data segment.

7. The method according to claim 6, characterized in that, The method further includes: in the first receiving round, if the indication identifier information in the first delimiting indication information corresponding to each delimiting reference data segment indicates that there is a searchable data segment identical to the corresponding delimiting reference data segment among the multiple searchable data segments corresponding to the corresponding delimiting reference data segment, then based on the delimiting position information in the first delimiting indication information corresponding to each delimiting reference data segment, determining the second delimiting indication information corresponding to the cached parallel data; the second delimiting indication information corresponding to the cached parallel data indicates that there is a target data segment identical to the preset delimiter in the cached parallel data, and indicates the position of the target data segment in the cached parallel data.

8. The method according to claim 6, characterized in that, The step of determining the second delimiting indication information corresponding to the cached parallel data based on the first delimiting indication information corresponding to each delimiting reference data segment and the adjudication window corresponding to the target clock cycle includes: within the current duration of the adjudication window corresponding to the target clock cycle, if the indication information in the first delimiting indication information corresponding to each delimiting reference data segment indicates that there is no data segment to be retrieved that is the same as the corresponding delimiting reference data segment among the multiple data segments to be retrieved corresponding to the corresponding delimiting reference data segment, then the timing alignment of the target clock cycle is skipped.

9. The method according to claim 6, characterized in that, The step of determining the second delimiting indication information corresponding to the cached parallel data based on the first delimiting indication information corresponding to each delimiting reference data segment and the adjudication window corresponding to the target clock cycle includes: within the current duration of the adjudication window corresponding to the target clock cycle, if the indication identifier information in the first delimiting indication information corresponding to each delimiting reference data segment does not completely indicate that there is a searchable data segment identical to the corresponding delimiting reference data segment among the multiple searchable data segments corresponding to the corresponding delimiting reference data segment, then the indication identifier information in the first delimiting indication information corresponding to each delimiting reference data segment is statistically analyzed to obtain identifier statistical data; based on the adjudication strategy corresponding to the identifier statistical data and the delimiting position information in the first delimiting indication information corresponding to each delimiting reference data segment, the second delimiting indication information corresponding to the cached parallel data is obtained; the second delimiting indication information corresponding to the cached parallel data indicates that there is a target data segment similar to the preset delimiter in the cached parallel data, and indicates the position of the target data segment in the cached parallel data.

10. The method according to any one of claims 7 or 9, characterized in that, The method further includes: determining a first duration of the decision window when the second delimitation indication information corresponding to the cached parallel data indicates that the target data segment is located at the boundary position of the parallel data corresponding to the target clock cycle; and determining a second duration of the decision window when the second delimitation indication information corresponding to the cached parallel data indicates that the target data segment is located at the non-boundary position of the parallel data corresponding to the target clock cycle; wherein the first duration or the second duration is the next duration of the decision window corresponding to the target clock cycle in the next reception round.

11. The method according to claim 1, characterized in that, The method further includes: after determining the second delimiting indication information corresponding to the target clock cycle in the previous receiving round, starting a target counter corresponding to the target clock cycle; the initial value of the target counter is the same as the length of the clock cycle of the parallel data stream; the value of the target counter is decremented by 1 every clock cycle; when the value of the target counter decreases to a preset threshold corresponding to the current duration, opening an adjudication window corresponding to the target clock cycle, until the adjudication window corresponding to the target clock cycle is closed after the target counter finishes counting, so as to determine the second delimiting indication information corresponding to the buffered parallel data in the current receiving round within the current duration of the adjudication window corresponding to the target clock cycle.

12. The method according to claim 7, characterized in that, The step of determining the second delimiting indication information corresponding to the cached parallel data based on the delimiting position information in the first delimiting indication information corresponding to each delimiting reference data segment includes: performing a consistency check on the delimiting position information in the first delimiting indication information corresponding to each delimiting reference data segment to obtain a position consistency check result; and when the position consistency check result indicates that each of the delimiting position information is the same, using the delimiting position information as the second delimiting indication information corresponding to the cached parallel data.

13. A timing alignment device, characterized in that, The apparatus includes: a data acquisition module, configured to determine cached parallel data corresponding to a target clock cycle from the parallel data stream corresponding to the current receiving round; the target clock cycle being any clock cycle in the parallel data stream; a delimiter splitting module, configured to split a preset delimiter to obtain multiple delimiting reference data segments; a shift selection module, configured to shift and select the cached parallel data corresponding to the target clock cycle based on each of the multiple delimiting reference data segments to obtain multiple data segments to be retrieved corresponding to each delimiting reference data segment; and a retrieval module, configured to retrieve the multiple data segments to be retrieved corresponding to each delimiting reference data segment based on each delimiting reference data segment to obtain a first delimiting reference data segment. Boundary indication information; a delimiting module, used to determine the second delimiting indication information corresponding to the cached parallel data based on the first delimiting indication information corresponding to each delimiting reference data segment and the adjudication window corresponding to the target clock cycle; the current duration of the adjudication window corresponding to the target clock cycle is determined based on the second delimiting indication information corresponding to the target clock cycle in the previous reception round; a data extraction module, used to extract the cached parallel data according to the second delimiting indication information corresponding to the cached parallel data when the second delimiting indication information corresponding to the cached parallel data indicates that there is a target data segment in the cached parallel data corresponding to the target clock cycle that is the same as or similar to the preset delimiter, to obtain the aligned parallel data corresponding to the target clock cycle.

14. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores at least one instruction or at least one program segment, which is loaded and executed by a processor to implement a timing alignment method as described in any one of claims 1 to 12.

15. A computer device, characterized in that, The computer device includes a processor and a memory, the memory storing at least one instruction or at least one program, the at least one instruction or the at least one program being loaded and executed by the processor to implement a timing alignment method as described in any one of claims 1 to 12.

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