Multi-system wireless test method and system based on FPGA reconstruction

Abstract

The invention belongs to the technical field of communication testing, and particularly relates to a multi-system wireless testing method and system based on FPGA reconstruction, which are applied to a testing system consisting of backplane interconnection, eight-channel signal processing, a radio frequency channel, a clock, a master control and a power supply module through power-on self-test, power supply, clock distribution and bus establishment. Matching and uploading FPGA reconstruction firmware of a to-be-tested system, and dynamically loading the firmware based on an FPP * 32 mode to complete FPGA reconstruction; analyzing a test instruction of the upper computer, issuing parameters by sub-buses, and completing radio frequency link establishment and time sequence calibration; multi-system radio frequency signal receiving and transmitting and baseband processing are completed in a transmitting / receiving mode, and test data are generated; the working states of all the modules are integrated; power failure is not needed, and the steps S2-S5 are repeated to realize multi-system test seamless switching; and finishing test ending and system resetting. Flexible adaptation of multi-system testing is achieved through FPGA dynamic reconstruction, the testing efficiency is greatly improved, and the testing cost is reduced.

Description

A Multi-Standard Wireless Testing Method and System Based on FPGA Reconstruction Technical Field

[0001] This invention belongs to the field of communication testing technology, and in particular relates to a multi-standard wireless testing method and system based on FPGA reconstruction. Background Technology

[0002] In modern electronic technology fields such as wireless communication and radar detection, testing equipment is a core support for ensuring product development, production debugging, performance verification, and operation and maintenance. Its performance, flexibility, and integration directly determine the R&D efficiency, testing accuracy, and industrialization cost of related electronic systems. Currently, for different testing needs, the industry generally adopts a model of independently developed and deployed dedicated testing equipment, such as wireless communication integrated testers, multi-channel acquisition and playback equipment, channel simulators, and multi-channel radar echo simulators. Most of these dedicated testing equipment uses independent hardware architecture designs, with low sharing and reuse of core hardware units, making it difficult to achieve flexible adaptation for multi-standard testing. Firstly, hardware resources are wasted, and testing costs remain high: each type of dedicated testing equipment requires a separate dedicated hardware architecture design. The core hardware units of different devices cannot be shared and reused, resulting in repeated investment in hardware resources, significantly increasing the R&D, procurement, and deployment costs of testing equipment. At the same time, multiple sets of hardware equipment also occupy a lot of physical space, which is not conducive to the application of miniaturized and integrated testing scenarios.

[0003] Secondly, the equipment has poor compatibility and is difficult to conduct collaborative testing: the hardware architecture, communication protocols and software interfaces of various test equipment are all independently designed and lack unified standards and specifications. When testing multiple devices collaboratively, the linkage and debugging between various devices is extremely difficult. It is necessary to develop special interface adaptation modules and collaborative control software, which not only increases the complexity of the test process, but also makes it easy for collaborative failures to occur, affecting test efficiency and test accuracy.

[0004] Third, it lacks flexibility and scalability: the functions of existing dedicated testing equipment are fixed. Once the hardware architecture is designed, it is difficult to flexibly adjust and expand the functions according to changes in testing requirements. When testing requirements are switched, the entire set of dedicated testing equipment must be replaced. It is impossible to achieve functional adaptation through simple software upgrades or hardware reconstruction. It has extremely poor versatility, making it difficult to meet the testing needs of multiple scenarios and types, and it is also unable to adapt to future upgrades and iterations of testing technologies.

[0005] Fourth, the switching efficiency for multi-standard testing is low and the operation is complex. For testing requirements of different wireless communication standards, existing equipment requires power-off to replace hardware modules or re-flash firmware. The switching process is time-consuming and prone to configuration errors due to manual operation. It cannot achieve seamless and fast switching for multi-standard testing, and it is difficult to meet the comprehensive testing requirements of batch and multi-standard testing.

[0006] Therefore, existing technologies suffer from problems such as independent deployment of various test devices, inability to share hardware resources, poor compatibility, insufficient flexibility, and low efficiency in switching between multiple standards. These issues result in high testing costs, low efficiency, and poor scalability, failing to meet the diverse, multi-scenario, high-efficiency, and low-cost testing needs of modern electronic technology. This invention aims to provide a testing method and system that integrates multiple types of test devices onto a unified hardware platform, enabling flexible and seamless switching of testing functions for different wireless communication standards through dynamic FPGA reconfiguration. Summary of the Invention

[0007] The purpose of this invention is to provide a multi-standard wireless testing method and system based on FPGA reconstruction, in order to solve the technical problems of independent deployment, inability to share hardware resources, poor compatibility, insufficient flexibility, and low efficiency of multi-standard switching in various testing devices in the prior art.

[0008] To solve the above-mentioned technical problems, the present invention adopts the following technical solution: Firstly, it provides a multi-standard wireless testing method based on FPGA reconstruction, applied to a test system composed of a backplane interconnect module, an eight-channel signal processing module, an RF channel module, a clock module, a main control module, and a power supply module, comprising the following steps: S1: The main control module starts and completes power-on self-tests of all other modules; the power supply module supplies power to each module; the clock module generates a synchronous clock and distributes it to each module via a clock distribution link; the backplane interconnect module establishes a three-level data interaction channel; each module completes a communication handshake with the main control module and reports its initial working status; S2: The main control module obtains the wireless communication standard type to be tested. S3: The main control module receives the test instructions from the host computer and parses out the RF frequency, transmit power, sampling rate, channel simulation parameters and test mode. It sends baseband processing parameters to the eight-channel signal processing module and sampling rate and conversion mode configuration parameters to the AD / DA module. It sends frequency matching, power attenuation and channel link switching instructions to the RF channel module. The RF channel module builds the corresponding transmit link or receive link according to the instructions. S4: Multi-standard RF signal transmission and reception and baseband processing are performed in transmit test mode and receive test mode respectively to obtain test data. In the transmit test mode, the main control module configures the channel simulation parameters of the eight-channel signal processing module through the backplane interconnect module. The eight-channel signal processing module processes the transmit baseband data to simulate the transmission signal passing through the wireless channel. S5: The eight-channel signal processing module transmits the baseband-processed test data to the backplane interconnect module, and then uploads it to the main control module at high speed via the Ethernet switching bus. The main control module parses and stores the test data, and collects the power status of the RF channel module, the lock status of the clock module, the power supply status of the power supply module, and the operation status of the eight-channel signal processing module in real time. After integrating the test data with the working status of each module, it feeds back the results. S6: When switching to other wireless communication standards for testing, the main control module does not need to power off the system. It directly repeats steps S2-S5 according to the new test standard. The system management FPGA dynamically reconfigures the dual high-performance FPGAs to complete the test configuration and signal processing of the new standard until all multi-standard test tasks are completed. S7: After receiving the test end command from the host computer, the main control module sends a stop working command to each module. The eight-channel signal processing module stops signal generation and processing, the RF channel module closes the signal transceiver link, the main control module saves all test data and status logs and generates a test report, and each module sends a reset command.

[0009] Preferably, the specific process of the main control module obtaining the wireless communication standard type to be tested and matching the corresponding FPGA reconfiguration firmware file in step S2 is as follows: S211: The main control module receives the test task instruction issued by the host computer through the Ethernet bus. The test task instruction includes the wireless communication standard identifier to be tested; S212: The main control module retrieves the locally preset standard-FPGA reconfiguration firmware mapping table. This table stores the unique association identifier between different wireless standards and the corresponding FPGA reconfiguration firmware files; S213: The main control module matches the corresponding reconfiguration firmware file according to the standard identifier: the integrity of the locally stored firmware file is verified by MD5. If the verification fails, the backup file is automatically retrieved from the platform's backup storage area. If the backup file is also invalid, the firmware matching failure is reported to the host computer and this step is terminated; if the verification is successful, the main control module parses the basic attributes of the firmware file, including the FPGA model to which the firmware is adapted, the loading timing parameters, and the algorithm version number, and confirms that it is compatible with the dual high-performance FPGA hardware version of the eight-channel signal processing module.

[0010] Preferably, the specific process of uploading the FPGA reconfiguration firmware file and dynamically loading the FPGA in step S2 is as follows: FPGA reconfiguration firmware file upload: S221: Based on the asynchronous RS485 bus of the backplane interconnect module, the main control module establishes an FTP communication link with the eight-channel signal processing module, sends a firmware upload command to the system management FPGA, and carries the firmware file name, size, and transmission check code; S222: After receiving the command, the system management FPGA initializes the specified partition of the EMMC storage unit, clears the historical firmware files in the partition, and sends feedback to the main control module that the storage partition is ready; S22 3: The main control module uploads the reconstructed firmware file to the EMMC storage partition using a segmented transmission method. After each segment is transmitted, the system management FPGA verifies the transmission checksum of the segment. If the verification passes, it reports successful segment reception; otherwise, it requests the main control module to retransmit the segment. S224: After all segments are transmitted, the system management FPGA performs an MD5 checksum on the entire firmware file. If the checksum passes, it reports firmware upload completion to the main control module and renames the firmware file to a fixed identifier name. If the checksum fails, it reports upload failure, and the main control module re-executes this stage of the process, retrying a maximum of 3 times. If it still fails, it terminates and reports the failure. PGA Dynamic Loading: S225: After receiving confirmation of firmware upload completion, the system management FPGA calls the pre-integrated dynamic configuration driver; S226: The dynamic configuration driver initializes the hardware interface of the FPP×32 configuration mode, sets the loading timing parameters, and sends a configuration reset command to the dual high-performance FPGAs, causing the dual high-performance FPGAs to enter the firmware loading ready state; S227: The system management FPGA reads the reconstructed firmware file from the EMMC storage unit, configures the loading timing according to the FPP program (frame header synchronization → continuous transmission of configuration data → frame tail verification), and writes the firmware data stream to the dual high-performance FPGAs. Configuration register of A; S228: Dual high-performance FPGAs receive configuration data in real time. After completing firmware loading, they automatically perform internal self-tests. If the self-test passes, they send a reconstruction success level signal to the system management FPGA. If the self-test fails, they send a reconstruction failure level signal and feedback a failure code; S229: After receiving the reconstruction success signal, the system management FPGA uploads an FPGA reconstruction completion status message to the main control module via an asynchronous RS485 bus. The message includes the reconstruction mode, firmware version, and loading time. If a reconstruction failure signal is received, a failure code is fed back to the host computer, and the firmware reloading process is triggered, with a maximum of 2 retries.

[0011] Preferably, the specific process of step S3 is as follows: S31: Receiving test commands and parsing parameters: S311: The main control module receives standardized test command frames issued by the host computer through the Ethernet switching bus. The frame format is: frame header + command type + parameter segment + checksum + frame trailer; S312: The main control module first checks the CRC32 checksum of the command frame. If the check fails, it reports the invalid command to the host computer and requests a retransmission. If the check succeeds, it parses the parameter segment, extracts the specified core parameters, and stores them in categories; S313: The main control module performs a legality check on the parsed parameters: the RF frequency matches the frequency band capability of the RF channel module. If it exceeds the range, it automatically corrects it to the most recent legal value and makes a note; the transmit power meets the output capability of the RF channel module. If it exceeds the range, it reports the power parameter exceeding the limit and terminates this stage; the sampling rate matches the hardware specifications of the AD / DA module. If they do not match, it automatically adapts to the optimal sampling rate and reports it to the host computer. Step 1; S32: Perform precise distribution of sub-bus parameters, including high-speed serial bus distribution, asynchronous RS485 bus distribution, and clock allocation link distribution; S33: Perform link configuration verification and status feedback: S331: The main control module sends a link detection command to the RF channel module. The RF channel module collects the signal power at the link input or output end through its built-in power detection circuit to verify whether the transmit or receive link is conducting and whether the power attenuation meets the configuration value; S332: The main control module sends a sampling test command to the AD / DA module. The AD / DA module outputs a reference sine wave signal to verify whether the sampling rate and conversion mode configuration are correct; S333: The main control module summarizes the configuration status of all modules, generates a configuration completion status message, and uploads it to the host computer; S334: If any module configuration fails, the main control module locates the faulty module and fault type, reports the fault information to the host computer, and triggers the reconfiguration process.

[0012] Preferably, the specific process of step S32 is as follows: S321: High-speed serial bus transmission: The main control module initializes the communication link of the high-speed serial bus and sends a parameter transmission pre-synchronization command to the bus. After receiving the command, the eight-channel signal processing module and the AD / DA module return a ready response. The main control module encapsulates the baseband processing parameters into a binary parameter packet and transmits it to the dual high-performance FPGAs of the eight-channel signal processing module through the high-speed serial bus. After receiving the parameter packet, the dual high-performance FPGAs verify the matching of the parameter version number with the reconstructed FPGA firmware version. If the matching is successful, the parameters are written into the dedicated configuration register and feedback is given that the baseband parameters have been successfully received. If the matching is not successful, feedback is given that the parameter version is incompatible, and the main control module retransmits the parameters of the adapted version. The main control module transmits the sampling rate and conversion mode configuration parameters to the AD / DA module. The parameters include the sampling rate value, the conversion mode identifier, and the sampling clock phase offset value. After receiving the parameters, the AD / DA module configures the internal phase-locked loop to achieve sampling rate matching and adjusts the sampling clock phase. After completion, feedback is given that the AD / DA configuration is ready.

[0013] S322: Asynchronous RS485 Bus Sending: The main control module sends link configuration command frames to the RF channel module via the asynchronous RS485 bus, including frequency matching commands, power attenuation commands, and link switching commands. After receiving the commands, the RF channel module configures the frequency synthesizer to lock the target frequency, configures the digitally controlled attenuator through the SPI interface to complete the power attenuation value setting, and switches the link switch through a relay to build the transmit or receive link. After the RF channel module completes the configuration, it collects the current link frequency lock status and the actual attenuation value, encapsulates them into a link configuration response frame, and feeds it back to the main control module. If the frequency is not locked, reconfiguration is triggered.

[0014] S323: Clock Distribution Link Issuance: The main control module sends a clock division configuration command to the clock module; after receiving the command, the clock module configures its internal frequency divider to divide the main clock into the target clock frequency, and distributes the synchronization clock to the backplane clock distribution link through the clock distribution chip; the main control module issues timing calibration commands to the eight-channel signal processing module, AD / DA module, and RF channel module through the clock distribution link; after receiving the synchronization clock, each module adjusts the phase difference between its internal working clock and the synchronization clock; after completing the timing calibration, each module reports the clock synchronization completion status back to the main control module; the main control module verifies the synchronization status of all modules, and if there are any unsynchronized modules, it reissues the calibration command.

[0015] Preferably, the specific process of step S4 is as follows: S41: Transmission and reception of multi-standard RF signals and baseband processing in the transmit test mode; S42: Transmission and reception of multi-standard RF signals and baseband processing in the receive test mode; Preferably, the specific process of step S41 is as follows: S411: Generation of multi-standard digital baseband signals: Dual high-performance FPGAs read baseband processing parameters. The first high-performance FPGA is responsible for signal generation logic, and the second FPGA is responsible for parallel processing, verification, and channel simulation. Based on the reconstructed standard algorithm, the FPGA first generates the original bitstream of the standard to be tested; baseband signal processing is executed sequentially, including encoding, interleaving, modulation, and frame encapsulation; the second high-performance FPGA reads the configured channel simulation parameters, performs channel simulation, including generating multipath channel impulse response and convolution operation, and performs real-time verification of the generated digital baseband signal. If the verification passes, the signal is transmitted to the receiver. Eight parallel IQ digital signals are output to the AD / DA module; if verification fails, a baseband signal generation anomaly is reported to the main control module, terminating this stage and triggering regeneration; S412: Digital-to-Analog Conversion: The AD / DA module receives the digital baseband signal output from the FPGA and converts the digital IQ signal into an intermediate frequency analog IQ signal; S413: RF Transmit Link Conditioning and Output: The RF channel module receives the intermediate frequency analog IQ signal and selects the appropriate processing path for frequency conversion processing according to the configured frequency band type; the frequency-converted RF signal is filtered out for spurious signals by a bandpass filter and then amplified by a power amplification link; after signal amplification, the power is precisely adjusted to the target value through the configured power attenuation link; the RF signal is output to the RF interface of the device under test via an eight-channel selection switch, and the RF channel module simultaneously collects the actual power, frequency, and EVM value of the output signal and feeds it back to the main control module.

[0016] Preferably, the specific process of step S42 is as follows: S421: The RF signal output by the device under test is connected to the receiving link input of the RF channel module, and out-of-band interference signals are filtered out by a low-pass filter; according to the configured target RF frequency, the corresponding sampling path is selected for amplification; the amplified signal is controlled by an automatic gain control circuit to ensure that the signal power of each node is ≥-20dBm and the overall dynamic range of the receiving link is ≥70dB; the conditioned intermediate frequency analog IQ signal is output to the AD / DA module, and the RF channel module collects the actual frequency, power, and signal-to-noise ratio of the received signal and feeds it back to the main control module; S422: Analog-to-digital conversion is performed: the AD / DA module receives the intermediate frequency analog IQ signal, completes analog-to-digital conversion according to the configured sampling rate, and converts the analog signal into a digital IQ baseband signal; S423: Digital baseband processing and analysis: dual high-performance FPGAs receive the digital baseband signal, and based on the standard algorithm reconstructed in S2, perform quadrature demodulation, synchronization processing, equalization processing, and decoding processing in sequence.

[0017] Preferably, the specific process of step S5 is as follows: S51: The dual high-performance FPGAs encapsulate the test data into standardized data frames according to the format and channel classification; the eight-channel signal processing module sends the encapsulated test data frames to the backplane interconnect module; the backplane interconnect module converts the received high-speed serial bus data frames into Ethernet frame format and forwards them to the dedicated data receiving port of the main control module through the gigabit Ethernet switching bus; S52: Status data is collected at fixed intervals, including the status of the RF channel module, clock module, power supply module, and eight-channel signal processing module; S53: The main control module performs parsing operations on the test data and status data: splitting the data frames according to the format and channel, extracting specified key indicators, and performing cross-validation and data standardization; data integration and real-time feedback: the main control module integrates the test data and the status data of each module into a unified feedback message.

[0018] Secondly, a multi-mode wireless test system based on FPGA reconstruction is provided to implement the aforementioned multi-mode wireless test method based on FPGA reconstruction. The system includes a backplane interconnect module, an eight-channel signal processing module, a radio frequency channel module, a clock module, a main control module, and a power supply module. The backplane interconnect module constructs a three-level data interaction channel consisting of a high-speed serial bus, an Ethernet switching bus, an asynchronous RS485 bus, and a trigger I / O switching bus. The high-speed serial bus is used to transmit baseband processing parameters and test data, the Ethernet switching bus is used for high-speed uploading of test data, and the asynchronous RS485 bus is used to transmit module control commands and status feedback information. The baseband signal processing module of the eight-channel signal processing module adopts dual high-performance FPGAs + system management. The FPGA employs a three-chip architecture. The RF channel module includes a transmit link and a receive link. The clock module uses a temperature-controlled crystal oscillator as the main clock source to generate a nanosecond-level synchronous clock, which is then distributed to each module of the system via a clock distribution link. The power supply module adopts a hierarchical power supply architecture with centralized conversion and discrete voltage regulation for each module, providing suitable DC power to each module. The main control module is communicatively connected to the backplane interconnect module, the eight-channel signal processing module, the RF channel module, the clock module, and the power supply module, and is used to complete system initialization configuration, FPGA reconfiguration file matching and loading, full-domain test parameter distribution and link configuration, control of multi-standard RF signal transmission and reception and baseband processing, test data acquisition and real-time feedback, seamless switching of multi-standard tests, and test termination reset.

[0019] The beneficial effects of this invention include: 1. Seamless switching between multiple standards for testing, significantly improving testing efficiency: By dynamically loading programs onto dual high-performance FPGAs using the system management FPGA in FPP×32 configuration mode, different wireless communication standards can be reconfigured without powering down the test system. During switching, only the process of matching and loading the FPGA reconfiguration file to the test data feedback needs to be repeated, avoiding the cumbersome operations of replacing hardware and burning firmware in traditional equipment. This significantly shortens the switching time for multiple standards testing, meets the comprehensive testing needs of batch and multiple standards, and improves overall testing efficiency. At the same time, the FPGA reconfiguration process employs mechanisms such as MD5 verification, fragmented transmission, and breakpoint resumption to ensure the accuracy and reliability of firmware loading and avoid test interruptions caused by reconfiguration failures.

[0020] 2. Unified hardware platform architecture significantly reduces testing costs: Based on a unified hardware platform consisting of a backplane interconnect module, an eight-channel signal processing module, and an RF channel module, the baseband signal processing, modulation and demodulation, and channel simulation functions for different wireless communication standards are realized through FPGA reconstruction. There is no need to design a separate dedicated hardware platform for different standards, realizing the sharing and reuse of hardware resources and effectively reducing the cost of hardware R&D, procurement, and deployment. At the same time, the unified hardware platform significantly reduces the physical space occupation and adapts to the needs of miniaturized and integrated testing scenarios.

[0021] 3. Multi-bus collaborative transmission ensures the accuracy and real-time performance of parameter distribution and data transmission: The backplane interconnect module constructs a three-level data interaction channel consisting of a high-speed serial bus, an Ethernet switching bus, and an asynchronous RS485 bus. Dedicated buses are used for different types of data: the high-speed serial bus enables low-latency, high-bandwidth transmission of baseband processing parameters and test data; the Ethernet switching bus completes high-speed uploading of test data to the main control module; and the asynchronous RS485 bus enables interference-resistant transmission of module control commands and status feedback information. Simultaneously, a multi-bus precise distribution + validity verification + version matching mechanism is employed during parameter distribution to ensure the compatibility of test parameters with hardware modules and FPGA reconfigured firmware, avoiding test errors caused by incorrect parameter configuration.

[0022] 4. Precise and controllable end-to-end signal processing enhances test accuracy: The RF channel module adopts a transmit architecture combining direct RF output and single-conversion, and a receive architecture combining low-pass sampling, band-pass sampling, and IQ zero-IF demodulation. This enables high-precision transmission and reception of signals across the entire 1MHz~8GHz frequency band. The receive link provides an RF gain of no less than 40dB and a dynamic range of over 70dB. Furthermore, automatic gain control keeps the signal power at each node of the receive link at -20dBm or higher, ensuring that the signal EVM index does not deteriorate. Dual high-performance FPGAs employ a parallel processing architecture to hardware-accelerate computationally intensive tasks such as modulation / demodulation and channel simulation. This enables high-precision generation and convolution operations of multipath channel impulse responses, accurately simulating complex channel environments such as multipath fading and frequency-selective fading. The detection accuracy of test indicators is far superior to traditional test equipment. Attached Figure Description

[0023] Figure 1 is a diagram of the architecture of the multi-standard wireless test system based on FPGA reconstruction according to the present invention.

[0024] Figure 2 is a schematic diagram of the architecture of the eight-channel signal processing module of the present invention. Detailed Implementation

[0025] The present invention will be further described in detail below with reference to Figures 1 and 2: Example 1 Referring to Figure 1, a multi-mode wireless testing method based on FPGA reconstruction is applied to a test system composed of a backplane interconnect module, an eight-channel signal processing module, a radio frequency channel module, a clock module, a main control module, and a power supply module. The baseband signal processing module of the eight-channel signal processing module adopts a three-chip architecture of dual high-performance FPGA + system management FPGA, including the following steps: S1: Platform initialization configuration: The main control module starts and completes the power-on self-test of the power supply module, clock module, radio frequency channel module, and eight-channel signal processing module. The power supply module completes the adaptation power supply of each module through centralized conversion + module discrete voltage regulation. The clock module generates a nanosecond-level synchronous clock with a constant temperature crystal oscillator as the main clock source and distributes it to each module of the platform through the clock distribution link. The backplane interconnect module establishes a three-level data interaction channel of high-speed serial bus, Ethernet switching bus, asynchronous RS485 bus, and trigger IO switching bus. Each module completes the communication handshake with the main control module and feedback the initial working status.

[0026] S2: FPGA Reconstruction File Matching and Loading: The main control module obtains the wireless communication standard type to be tested, matches the corresponding FPGA reconstruction firmware file, and uploads the FPGA reconstruction firmware file and dynamically loads the FPGA: The reconstruction firmware file is uploaded to the EMMC storage unit of the eight-channel signal processing module. The system management FPGA calls the dynamic configuration driver, reads the reconstruction firmware file from the EMMC storage unit based on the FPPx32 configuration mode, and dynamically loads the dual high-performance FPGAs according to the FPP program configuration loading timing. This completes the configuration of the baseband signal processing algorithm, modulation and demodulation protocol, and channel simulation logic corresponding to the standard to be tested. After the dual high-performance FPGAs are loaded, they report the reconstruction success status to the system management FPGA. The system management FPGA uploads the reconstruction success status to the main control module via the asynchronous RS485 bus.

[0027] S3: Test Parameter Distribution and Link Configuration: The main control module receives test commands from the host computer and parses out the RF frequency, transmit power, sampling rate, channel simulation parameters, and test mode. It then distributes baseband processing parameters to the eight-channel signal processing module via a high-speed serial bus and sampling rate and conversion mode configuration parameters to the AD / DA module. It also distributes frequency matching, power attenuation, and channel link switching commands to the RF channel module via an asynchronous RS485 bus. The RF channel module builds the corresponding transmit or receive link according to these commands. Finally, it distributes clock division coefficient configuration parameters to each module via a clock distribution link to complete the timing synchronization calibration of each module.

[0028] S4: Transmission and reception of multi-standard RF signals and baseband processing: In the transmission test mode, dual high-performance FPGAs generate digital baseband signals of the standard to be tested according to the configured baseband processing parameters. At the same time, they generate multipath channel impulse responses according to the channel simulation parameters and perform convolution operations with the digital baseband signals to simulate complex channel environments. After being converted from digital to analog by the AD / DA module, the signals are sent to the transmission link of the RF channel module. The transmission link converts the intermediate frequency analog signals into RF signals of the target frequency using either direct RF output or single-conversion method according to the configuration. After power amplification and filtering, the signals are output to the device under test.

[0029] In the receiving test mode, the receiving link of the RF channel module filters, amplifies and converts the RF signal output by the device under test to obtain an intermediate frequency analog signal. After being converted from analog to digital by the AD / DA module, the signal is sent to the dual high-performance FPGAs. The dual high-performance FPGAs complete the quadrature demodulation, synchronization, equalization and decoding of the digital baseband signal based on the reconstruction algorithm.

[0030] S5: Test Data Acquisition and Real-time Feedback: The eight-channel signal processing module transmits the baseband-processed test data and channel simulation analysis results to the backplane interconnect module via a high-speed serial bus, and then uploads them to the main control module via an Ethernet switching bus. The main control module parses and stores the test data, and acquires the power status of the RF channel module, the lock status of the clock module, the power supply status of the power supply module, and the operation status of the eight-channel signal processing module in real time via an asynchronous RS485 bus. After integrating the test data with the working status of each module, it feeds the data back to the host computer.

[0031] S6: Seamless switching between multiple standards for testing: If it is necessary to switch to other wireless communication standards for testing, the main control module does not need to power off the platform. It can directly repeat steps S2-S5 according to the new test standard. The system management FPGA dynamically reconfigures the dual high-performance FPGAs again to complete the test configuration and signal processing of the new standard until all multi-standard test tasks are completed.

[0032] S7: Test Completion and Platform Reset: After receiving the test completion command from the host computer, the main control module sends a stop command to each module. The eight-channel signal processing module stops signal generation and processing, the RF channel module shuts down the signal transmission and reception link, the main control module saves all test data and status logs and generates a test report, and then sends a reset command to each module. The power supply module switches to standby power supply mode, the clock module keeps the main clock source locked at low power, and the platform returns to the initial standby state.

[0033] In step S2, the main control module obtains the wireless communication standard type to be tested and matches the corresponding FPGA reconstructed firmware file. The specific process is as follows: S211: The main control module receives the test task instruction issued by the host computer through the Ethernet bus. The test task instruction includes the wireless communication standard identifier to be tested, including 5GNR, 4GLTE, WiFi6, Bluetooth 5.3, etc.

[0034] S212: The main control module retrieves the locally preset standard-FPGA reconfiguration firmware mapping table. This table stores the unique association identifier between different wireless standards and the corresponding .rbf format FPGA reconfiguration firmware files. The unique association identifier is in the form of: MD5 value + file name.

[0035] S213: The main control module matches the corresponding reconstructed firmware file according to the standard identifier: First, it verifies the integrity of the locally stored firmware file through MD5. If the verification fails, it automatically retrieves the backup file from the platform's backup storage area. If the backup file is also invalid, it reports the firmware matching failure to the host computer and terminates this step.

[0036] If the verification is successful, the main control module parses the basic attributes of the firmware file, including the FPGA model to which the firmware is adapted, the loading timing parameters, and the algorithm version number, to confirm compatibility with the dual high-performance FPGA hardware versions of the eight-channel signal processing module.

[0037] The specific process of uploading the FPGA reconfiguration firmware file and dynamically loading the FPGA in step S2 is as follows: Uploading the FPGA reconfiguration firmware file: S221: Based on the asynchronous RS485 bus of the backplane interconnect module, the main control module and the eight-channel signal processing module establish an FTP communication link, send a firmware upload command to the system management FPGA, and carry the firmware file name, size, and transmission check code.

[0038] S222: After receiving the instruction, the system management FPGA initializes the specified partition of the EMMC storage unit, which can be / mnt / fpga_config / , clears the historical firmware files in the partition, and sends a message to the main control module that the storage partition is ready.

[0039] S223: The main control module uses a segmented transmission method (128KB per segment) to upload the reconstructed firmware file to the EMMC storage partition. After each segment is transmitted, the system management FPGA verifies the transmission check code of the segment. If the verification is successful, it will report that the segment has been successfully received. If the verification fails, it will require the main control module to retransmit the segment.

[0040] S224: After all fragments are transmitted, the system management FPGA performs MD5 verification on the overall firmware file. If the verification is successful, it sends a message to the main control module that the firmware upload is complete and renames the firmware file to a fixed identifier name, such as gsrd.core.rbf. If the verification fails, it sends a message that the upload failed and the main control module re-executes this stage of the process, retrying a maximum of 3 times. If it still fails, it terminates and reports the failure.

[0041] FPGA Dynamic Loading: S225: After receiving the "Firmware upload complete" confirmation, the system management FPGA calls the pre-integrated dynamic configuration driver, which provides the application layer with a standardized call channel to access the FPGAManager kernel interface.

[0042] S226: The dynamic configuration driver initializes the hardware interface of the FPP×32 configuration mode, sets the loading timing parameters, including clock frequency of 100MHz, data width of 32bit, loading start delay of 200μs, and sends a configuration reset command to the dual high-performance FPGAs, so that the dual high-performance FPGAs enter the firmware loading ready state.

[0043] S227: The system management FPGA reads the .rbf format reconstructed firmware file from the EMMC storage unit, loads the firmware data stream according to the FPP program configuration timing, and writes it into the configuration registers of the dual high-performance FPGAs in parallel 32-bit mode: frame header synchronization → continuous transmission of configuration data → frame tail verification.

[0044] S228: Dual high-performance FPGAs receive configuration data in real time. After firmware loading is completed, they automatically perform internal self-tests, including verifying firmware integrity and algorithm logic validity. If the self-test passes, a "reconstruction successful" level signal is sent to the system management FPGA. The high level lasts for 10ms. If the self-test fails, a "reconstruction failed" level signal is sent, and a failure code is fed back, which can be 0x01 = firmware corruption or 0x02 = timing mismatch.

[0045] S229: After receiving the "Reconstruction Successful" signal, the system management FPGA uploads the "FPGA Reconstruction Complete" status message to the main control module via the asynchronous RS485 bus. The message includes the reconstruction mode, firmware version, and loading time. If the "Reconstruction Failed" signal is received, the failure code is sent back to the host computer, and the firmware reloading process is triggered. The process can be retried up to 2 times.

[0046] In the above process, the core parameters of the FPP×32 configuration mode are as follows: data transmission rate: 3.2Gbps (100MHz clock × 32bit width), which is twice as efficient as the traditional FPPx16 mode.

[0047] Loading fault tolerance mechanism: Supports "breakpoint resume". If data transmission is interrupted during loading, the system management FPGA can record the interruption position and resume loading from the breakpoint after communication is restored, without having to retransmit the complete firmware.

[0048] Dynamic configuration driver: The driver encapsulates the Linux kernel's FPGAManager interface and provides standardized APIs, such as fpga_config_load() and fpga_config_verify(), to automate the entire process of loading command issuance, real-time status feedback, and exception interrupt handling, without requiring manual intervention in the underlying FPGA configuration.

[0049] Reliability assurance of status feedback: When the system management FPGA uploads status to the main control module, it adopts a dual mechanism of message + heartbeat, that is, a heartbeat message is sent every 50ms to confirm that the communication link is normal. The core status of successful or failed reconstruction is transmitted with message with CRC check to avoid loss or tampering of status information.

[0050] The specific process of step S3 is as follows: S31: Test command reception and parameter parsing: S311: The main control module receives the standardized test command frame issued by the host computer through the Ethernet switching bus. The frame format is: frame header + command type + parameter segment + check code + frame tail. The parameter segment is encapsulated in TLV (Type-Length-Value) format to ensure that the parameter parsing is unambiguous.

[0051] S312: The main control module first checks the CRC32 checksum of the command frame. If the check fails, it sends a "command invalid" message to the host computer and requests a retransmission. If the check succeeds, it parses the parameter segment, extracts the core parameters, and stores them in categories: basic test parameters: radio frequency (1MHz~8GHz), transmit power (-120dBm~+20dBm), sampling rate (100kSps~2GSps, in 100kSps increments).

[0052] Advanced configuration parameters: Channel simulation parameters (multipath number 1~16, path delay 0~100μs, power attenuation 0~80dB), test mode (0=transmit test, 1=receive test, 2=transmit-receive coordination test).

[0053] Timing synchronization parameters: clock division factor (1, 2, 4, or 8), AD / DA conversion mode (0 = single-ended sampling, 1 = differential sampling).

[0054] S313: The main control module performs a legality check on the parsed parameters: the radio frequency must match the frequency band capability of the radio channel module, 1MHz~5800MHz is the direct output frequency band, 4800MHz~8000MHz is the frequency conversion band, and if it exceeds the range, it will be automatically corrected to the most recent legal value and noted.

[0055] The transmit power must meet the output capability of the RF channel module, i.e. -120dBm to +20dBm. If it exceeds this range, a "power parameter over limit" message will be fed back and the current stage will be terminated. The sampling rate must match the hardware specifications of the AD / DA module, with a maximum of 2GSps. If they do not match, the optimal sampling rate will be automatically adapted and synchronized with the host computer.

[0056] S32: Precise distribution of bus parameters (main control module → each hardware module), including high-speed serial bus distribution, asynchronous RS485 bus distribution, and clock distribution link distribution.

[0057] S33: Link configuration verification and status feedback: S331: The main control module sends a link detection command to the RF channel module. The RF channel module collects the signal power at the link input or output end through the built-in power detection circuit to verify whether the transmit / receive link is conducting and whether the power attenuation meets the configuration value.

[0058] S332: The main control module sends a sampling test command to the AD / DA module. The AD / DA module outputs a 1kHz reference sine wave signal to verify whether the sampling rate and conversion mode configuration are correct.

[0059] S333: The main control module summarizes the configuration status of all modules, including baseband parameters, AD / DA configuration, RF link, and clock synchronization, and generates a configuration completion status message to upload to the host computer. The message includes the actual values ​​of the configuration parameters of each module, the synchronization accuracy, and the link conduction status.

[0060] S334: If any module configuration fails, the main control module locates the faulty module and fault type, such as RF frequency not locked or AD / DA sampling rate not supported, reports the fault information to the host computer and triggers the reconfiguration process.

[0061] The specific process of step S32 is as follows: S321: High-speed serial bus transmission: The main control module initializes the communication link of the high-speed serial bus, sends parameters to the bus and sends a pre-synchronization command. After receiving the command, the eight-channel signal processing module and the AD / DA module return a "ready response" to ensure the synchronization of the communication link.

[0062] The main control module encapsulates baseband processing parameters, including channel simulation parameters, modulation and demodulation algorithm parameters, and 8-channel parallel processing enable parameters, into a binary parameter packet. This packet is then sent to the dual high-performance FPGAs of the eight-channel signal processing module via a high-speed serial bus. The parameter packet carries the module address and parameter version number.

[0063] After receiving the parameter packet, the dual high-performance FPGAs verify the matching of the parameter version number with the reconstructed firmware version of the FPGA. If the match is successful, the parameters are written to a dedicated configuration register and "baseband parameter received successfully" is returned. If the match is not successful, "parameter version incompatible" is returned and the main control module reissues the parameters of the adapted version.

[0064] The main control module sends sampling rate and conversion mode configuration parameters to the AD / DA module. The parameters include the sampling rate value, conversion mode identifier, and sampling clock phase offset value (-90°~+90°). After receiving the parameters, the AD / DA module configures its internal PLL (phase-locked loop) to achieve sampling rate matching and adjusts the sampling clock phase. After completion, it sends a "AD / DA configuration ready" message.

[0065] S322: Asynchronous RS485 Bus Sending: The main control module sends a "link configuration command frame" to the RF channel module via the asynchronous RS485 bus (baud rate 115200, 8N1 format), which contains three core commands: Frequency Matching Command: Target RF frequency + frequency band type + local oscillator frequency; the frequency band type includes direct output or frequency conversion, and the local oscillator frequency needs to be configured for frequency conversion bands, such as the local oscillator fixed at 3800MHz for the 4800~8000MHz frequency band; Power Attenuation Command: Total attenuation value + attenuation level configuration, including 2-stage digitally controlled attenuators: 0~31dB, 1dB step; 2-stage switching attenuation amplifier group: 0 / 10 / 20 / 30dB.

[0066] Link switching command: Test mode + channel number + link enable flag; channel number is 1~8.

[0067] After receiving the command, the RF channel module first configures the frequency synthesizer (ADF4368) to lock the target frequency, then configures the digitally controlled attenuator through the SPI interface to complete the power attenuation value setting, and finally sets the transmit / receive link by switching the link switch through a relay.

[0068] After the RF channel module completes its configuration, it collects the current link's frequency lock status and actual attenuation value, encapsulates them into a "link configuration response frame," and feeds them back to the main control module. If the frequency is not locked, it triggers reconfiguration, and can retry a maximum of 3 times.

[0069] S323: Clock distribution link issuance, full module timing calibration: The main control module sends a "clock division configuration command" to the clock module, which includes the target division coefficient and synchronization accuracy requirements. The target division coefficient can be 1, 2, 4, or 8, and the synchronization accuracy requirement is in the nanosecond range. After receiving the command, the clock module configures its internal frequency divider to divide the 500MHz main clock (temperature-controlled crystal oscillator) into the target clock frequency. For example, if the division coefficient is 2, the output is 250MHz. The synchronization clock is then distributed to the backplane clock distribution link through the clock distribution chip. The main control module issues a "timing calibration command" to the eight-channel signal processing module, AD / DA module, and RF channel module through the clock distribution link. After receiving the synchronization clock, each module adjusts the phase difference between its internal working clock and the synchronization clock to ≤1ns.

[0070] After each module completes timing calibration, it sends a "clock synchronization complete" status message to the main control module. The main control module then verifies the synchronization status of all modules. If any modules are not synchronized, the calibration command is reissued.

[0071] The specific process of step S4 is as follows: S41: Transmission and reception of multi-standard RF signals and baseband processing in the transmission test mode. The specific process is as follows: S411: Generate multi-standard digital baseband signals on the dual high-performance FPGA side: The dual high-performance FPGA reads the baseband processing parameters issued in step S3, including standard identifier, modulation method, code rate, frame structure, and channel simulation parameters. The first high-performance FPGA is responsible for the signal generation logic, and the second FPGA is responsible for parallel processing and verification.

[0072] Based on the reconstructed standard algorithms, including LDPC encoding and OFDM modulation for 5G NR and 1024-QAM modulation for WiFi 6, the FPGA first generates the original bitstream of the standard to be tested, which can be a random bitstream or a customized test bitstream.

[0073] The baseband signal processing flow is executed sequentially: Encoding: Channel coding is completed according to the standard protocol, which can be convolutional coding, Turbo coding, or LDPC coding; Interleaving: The encoded data is interleaved to improve anti-fading capability; Modulation: Digital modulation is completed according to the configured modulation method, such as BPSK, QPSK, 16QAM, 64QAM, or 256QAM, to generate IQ baseband digital signals; Frame encapsulation: According to the standard frame structure, which can be the time slot structure of 5G NR or the subframe structure of LTE, it is encapsulated into a digital baseband frame that conforms to the protocol; The second high-performance FPGA reads the channel simulation parameters configured by S3, including the number of multipaths, the delay of each path, and the power attenuation value, and performs channel simulation analysis.

[0074] Generate multipath channel impulse response: Generate a corresponding number of time delay taps based on the number of multipaths, and configure the corresponding time delay and power attenuation values ​​for each tap; Convolution operation: Perform real-time convolution operation between the demodulated digital baseband signal and the multipath channel impulse response to simulate complex channel environments such as multipath fading and frequency selective fading. Where x(t) is the input signal at time t, y(t) is the output signal of the fading channel at time t, and h(t) is the channel impulse response at time t. It is the delay due to multipath propagation.

[0075] The generated digital baseband signal is verified in real time, such as EVM prediction value detection. If the verification passes, the 8-channel parallel IQ digital signal is output to the AD / DA module; if the verification fails, "baseband signal generation abnormal" is fed back to the main control module, terminating this stage and triggering regeneration.

[0076] S412: Digital-to-Analog Conversion on the AD / DA Module Side: The AD / DA module receives the digital baseband signal output from the FPGA and converts the digital IQ signal into an intermediate frequency (IF) analog IQ signal according to the configured sampling rate (100kSps~2GSps) and conversion mode (single-ended or differential). The IF frequency is 1MHz~5800MHz, or fixed at 350MHz / 800MHz, matching the RF link frequency band. After conversion, the AD / DA module sends the IF analog IQ signal to the transmit link input of the RF channel module and feeds back the digital-to-analog conversion completion status to the main control module. S413: RF Transmit Link Conditioning and Output on the RF Channel Module Side: The RF channel module receives the IF analog IQ signal and first selects the processing path according to the configured frequency band type: 1MHz~5800MHz direct output band: The IF analog signal is already the target RF frequency; only filtering and power adjustment are performed on the IF analog signal, with a maximum instantaneous bandwidth of 1GHz; 4800MHz~8000MHz frequency conversion band: The IF signal is converted... The frequency is converted to the target RF frequency (through mixer + local oscillator signal), with a maximum instantaneous bandwidth of 1GHz. The RF signal after frequency conversion is filtered by a custom LTCC bandpass filter to remove spurious signals, and then amplified through a power amplifier link: if the transmit power configuration value is ≤-10dBm: it is amplified only through the front-end low noise amplifier (LNA); if the transmit power configuration value is >-10dBm: the back-end two-stage power amplifier is enabled to amplify the signal to the target power; finally, the RF signal is output to the RF interface of the device under test through an 8-channel selection switch. The RF channel module simultaneously collects the actual power, frequency, and EVM value of the output signal and feeds it back to the main control module.

[0077] S42: Transmission and reception of multi-standard RF signals and baseband processing in the receive test mode. The specific process is as follows: S421: RF receive link conditioning on the RF channel module side: The RF signal output by the device under test is connected to the receive link input of the RF channel module. First, it passes through an 8GHz low-pass filter to filter out out-of-band interference signals. According to the configured target RF frequency, the corresponding sampling path is selected: 1MHz~1.4GHz: RF direct sampling, directly amplifying the RF signal with low noise, gain ≥40dB; 1.4GHz~3GHz: RF signal downconverted to 350MHz intermediate frequency, and then amplified; 3GHz~8GHz: RF signal downconverted to 800MHz intermediate frequency, and then amplified; The amplified signal is controlled by an automatic gain control (AGC) circuit to keep the signal power of each node at -20dBm and above, and the overall dynamic range of the receive link is ≥70dB; The conditioned intermediate frequency analog IQ signal is output to the AD / DA module. The RF channel module collects the actual frequency, power, and signal-to-noise ratio of the received signal and feeds it back to the main control module.

[0078] S422: Analog-to-digital conversion is performed on the AD / DA module side: The AD / DA module receives the intermediate frequency analog IQ signal, completes the analog-to-digital conversion according to the configured sampling rate of 100kSps~2GSps, and converts the analog signal into a digital IQ baseband signal; after the conversion is completed, the 8-channel parallel digital baseband signal is output to the dual high-performance FPGAs, and the "analog-to-digital conversion completed" status is fed back to the main control module.

[0079] S423: Digital baseband processing analysis on the dual high-performance FPGA side: The dual high-performance FPGAs receive digital baseband signals and perform the following processing sequentially: Quadrature demodulation: Quadrature demodulation of the digital IQ signal is performed to compensate for carrier frequency offset and phase shift, restoring the baseband digital signal; Synchronization processing: Based on the synchronization sequence of the standard protocol, such as the PSS / SSS synchronization signal of 5G NR, frame synchronization, symbol synchronization, and time synchronization are completed; Decoding: Channel decoding is completed according to the standard protocol to restore the original bit stream; Performance analysis: Key test indicators such as EVM, BER, and BLER of the signal are calculated; EVM calculation is as follows: ; where r i For the reference signal, i=1,2,…,N, that is, the signal transmitted by the transmitting end; y i For the receiving end to receive signals, i=1,2,…,N.

[0080] The bit error rate (BER) and block bit error rate (BLER) are calculated as follows: ; The first FPGA is responsible for baseband processing, and the second is responsible for performance analysis. After processing, the raw bit stream and test indicators are summarized and output to the high-speed serial bus of the backplane interconnect module. At the same time, the "baseband processing completed" status is fed back to the main control module.

[0081] In the above process, adaptive matching of the transmit or receive link: when the FPGA generates the digital baseband signal, it will automatically read the link parameters of the RF channel module, including bandwidth and frequency, and adjust the bandwidth and center frequency of the signal to ensure the matching between the baseband signal and the RF link.

[0082] Parallel processing and low latency guarantee: Dual high-performance FPGAs adopt a "ping-pong operation" architecture to process 8-channel signals, with a baseband processing latency of ≤10μs per channel, meeting real-time testing requirements; High-precision implementation of channel simulation: The generation accuracy of multipath channel impulse response reaches 0.1μs (latency) and 0.1dB (power attenuation), and the convolution operation adopts hardware acceleration logic; The specific process of step S5 is as follows: S51: Data encapsulation on the eight-channel signal processing module side: Dual high-performance FPGAs encapsulate the core test data output from S4 into standardized data frames according to "format classification + channel classification", and the frame structure is as follows: |4Byte frame header|2Byte format identifier|1Byte channel number|1Byte data type|variable length test data segment|4Byte CRC check code|2Byte frame tail|; Wherein: the test data segment includes: transmit / receive mode identifier, EVM value, BER / BLER value, multipath channel simulation results (measured values ​​of latency / power attenuation of each path), and baseband signal frame structure analysis results. Data is encapsulated in parallel across 8 channels, with each channel generating an independent data frame to avoid crosstalk between channels; high-speed serial bus transmission: the eight-channel signal processing module sends the encapsulated test data frames to the backplane interconnect module via a 12.5Gbps high-speed serial bus; Ethernet switching bus forwarding: the backplane interconnect module converts the received high-speed serial bus data frames into Ethernet frame format and forwards them to the dedicated data receiving port of the main control module via a gigabit Ethernet switching bus.

[0083] S52: Real-time acquisition of multi-module status data: While receiving core test data, the main control module sends status acquisition commands to each module via an asynchronous RS485 bus with a baud rate of 115200 and 8N1 format, acquiring the following status data at a fixed period of 100ms / time: RF channel module status acquisition: Acquisition content includes actual power of the transmit or receive link, frequency lock status, filter working status, AGC gain value, and measured EVM value; Clock module status acquisition: Acquisition of main clock source frequency, internal and external reference clock switching status, clock lock status, and clock phase difference of each module; Power supply module status acquisition: Acquisition of power supply voltage or current (12V, 5V, 3.3V), power supply, protection circuit status (overvoltage, overcurrent, overheating, or short circuit), and standby / working mode of each module.

[0084] Eight-channel signal processing module status acquisition: Acquires FPGA computing load rate, reconstructed firmware version, AD / DA conversion error, and 8-channel parallel processing status; S53: Data parsing and integration feedback: After receiving core test data and status data, the main control module splits the data frames by standard and channel, extracts key indicators, including the EVM value and BER value of 5GNR standard-channel 1; converts all data into a format recognizable by the host computer (JSON or CSV), with unified units: power: dBm, latency: μs, EVM:%.

[0085] The main control module integrates core test data and status data of each module into a unified feedback message. The message structure includes test task ID, standard identifier, channel number, core test indicators, and status codes of each module, which facilitates visualization and subsequent analysis by the host computer.

[0086] A multi-standard wireless test system based on FPGA reconstruction includes a backplane interconnect module, an eight-channel signal processing module, an RF channel module, a clock module, a main control module, and a power supply module. The backplane interconnect module constructs a three-level data interaction channel consisting of a high-speed serial bus, an Ethernet switching bus, an asynchronous RS485 bus, and a trigger I / O switching bus. The high-speed serial bus has a transmission line rate of 12.5Gbps and is used to transmit baseband processing parameters and test data. The Ethernet switching bus is used for high-speed uploading of test data, and the asynchronous RS485 bus is used to transmit module control commands and status feedback information.

[0087] Referring to Figure 2, the eight-channel signal processing module includes: a radio frequency transceiver module: including 8 independent receiving channels (RX1~RX8) and 8 independent transmitting channels (TX1~TX8), each channel having a complete radio frequency signal transceiver link, supporting multi-channel parallel operation.

[0088] Receive Channel (RX): After the external RF signal is selected by the receive channel switch, it enters the low noise amplifier (LNA) for signal amplification, then passes through the bandpass filter to filter out spurious signals, and is then sent to the downconverter to mix with the local oscillator signal, and outputs the intermediate frequency signal to the AD / DA module.

[0089] Transmit channel (TX): The intermediate frequency signal from the AD / DA module is mixed with the local oscillator signal by the upconverter to generate an RF signal. After being amplified to the target power by the power amplifier (PA), it is filtered by the bandpass filter and then output to the external device by the transmit channel switch.

[0090] Transceiver Local Oscillator: Provides quadrature local oscillator signals for 8 transceiver channels to ensure frequency consistency and phase synchronization of multi-channel mixing.

[0091] AD / DA Module: The AD / DA module acts as a "digital-to-analog bridge" between the RF transceiver module and the baseband signal processing module, containing four ADC / DAC chips. Each chip supports multi-channel AD / DA conversion, ultimately achieving parallel digital-to-analog / analog-to-digital conversion of eight RF signals. Each chip integrates multiple AD converters to convert the intermediate frequency analog signal output from the RF receiving channel into a digital signal for transmission to the baseband signal processing module. Similarly, each chip integrates multiple DA converters to convert the digital baseband signal generated by the baseband signal processing module into an analog intermediate frequency signal for input to the RF transmitting channel.

[0092] Baseband signal processing module: Based on a three-chip architecture (FPGA1, FPGA2, FPGA3) of dual high-performance FPGAs and a system management FPGA, it implements complex algorithm processing for digital signals, including demodulation, encoding, filtering, and channel simulation, and serves as the signal processing hub of the module. Dual high-performance FPGA1 and FPGA2: Primarily responsible for parallel baseband processing of 8 signals, including algorithms for quadrature demodulation, synchronization, equalization, and decoding, supporting real-time processing of multiple signal standards; simultaneously, they interconnect with external trigger modules via a high-speed serial bus (25Gbps×8) to achieve synchronous triggering and event linkage of multi-channel signals. FPGA3: Responsible for the module's system control and peripheral management, communicating with the main control module via an RS485 bus, receiving configuration commands and providing feedback on the module's operating status; it integrates GPIO interfaces to control RF switches and local oscillator sources. The baseband signal processing module achieves high-speed interconnection with the backplane of the comprehensive test instrument via a backplane connector, transmitting baseband data, control commands, and synchronization clocks. The connection method uses a high-speed backplane connector, which supports differential signal transmission and features low crosstalk and high reliability, ensuring signal integrity of multi-channel data during backplane transmission.

[0093] The RF channel module includes a transmit link and a receive link. The transmit link supports signal output in the 1MHz~8GHz frequency band, with the 1MHz~5800MHz band using a direct RF output scheme and a maximum instantaneous bandwidth of 1GHz, and the 4800MHz~8000MHz band using a single-conversion scheme and a maximum instantaneous bandwidth of 1GHz. The transmit link integrates a two-stage digitally controlled attenuator and a two-stage switching attenuation amplifier group, enabling precise adjustment of transmit power within the range of -120dBm~+20dBm. The receive link uses a combination of low-pass sampling, band-pass sampling, and IQ zero-IF demodulation to achieve full-band reception from 1MHz to 8GHz, providing an RF gain of no less than 40dB and a dynamic range of over 70dB, with the signal power of each node in the receive link controlled at -20dBm and above.

[0094] The clock module uses a temperature-controlled crystal oscillator as the main clock source, generating a nanosecond-level synchronous clock. This synchronous clock is distributed to all modules in the system via a clock distribution link, supporting clock division factors of 1, 2, 4, and 8. The power supply module adopts a hierarchical power supply architecture with centralized conversion and discrete voltage regulation for each module, providing suitable DC power and integrating overvoltage, overcurrent, overheat, and short-circuit protection circuits. The main control module communicates with the backplane interconnect module, the eight-channel signal processing module, the RF channel module, the clock module, and the power supply module, respectively, and is used to complete system initialization configuration, FPGA reconfiguration file matching and loading, full-domain test parameter distribution and link configuration, control of multi-standard RF signal transmission and reception and baseband processing, test data acquisition and real-time feedback, seamless switching between multi-standard tests, and test termination reset.

Claims

1. A multi-standard wireless testing method based on FPGA reconstruction, characterized in that, This test system, composed of a backplane interconnect module, an eight-channel signal processing module, an RF channel module, a clock module, a main control module, and a power supply module, includes the following steps: S1: The main control module starts up and completes power-on self-tests for all other modules; the power supply module supplies power to all modules; the clock module generates a synchronous clock and distributes it to all modules; the backplane interconnect module establishes a three-level data interaction channel; S2: The main control module obtains the wireless communication standard type to be tested, matches the corresponding FPGA reconfiguration firmware file, and uploads the FPGA reconfiguration firmware file and dynamically loads the FPGA; S3: The main control module receives and parses test commands, sends baseband processing parameters to the eight-channel signal processing module, sends sampling rate and conversion mode configuration parameters to the AD / DA module, and sends frequency matching, power attenuation, and channel link switching commands to the RF channel module. The RF channel module builds the corresponding transmit or receive link according to the commands; S4: The transmission and reception of multi-standard RF signals and baseband processing are performed in both transmit and receive test modes. In the transmission test mode, the main control module configures the channel simulation parameters of the eight-channel signal processing module through the backplane interconnect module. The eight-channel signal processing module processes the transmission baseband data to simulate the transmission signal passing through the wireless channel. S5: The eight-channel signal processing module transmits the baseband processed test data to the backplane interconnect module. The main control module parses the test data and collects the working status of each module in real time. S6: When it is necessary to switch to other wireless communication standards for testing, the main control module does not need to power off the system. It directly repeats steps S2-S5 according to the new test standard. The system management FPGA dynamically reconfigures the dual high-performance FPGAs to complete the test configuration and signal processing of the new standard. S7: After receiving the test end command, the main control module sends a stop working command to each module. The eight-channel signal processing module stops signal generation and processing, the RF channel module closes the signal transceiver link, the main control module saves all test data and status logs and generates a test report, and each module sends a reset command.

2. The multi-standard wireless testing method based on FPGA reconstruction according to claim 1, characterized in that, In step S2, the main control module obtains the wireless communication standard type to be tested and matches the corresponding FPGA reconfiguration firmware file. The specific process is as follows: S211: The main control module receives the test task instruction issued by the host computer through the Ethernet bus. The test task instruction includes the wireless communication standard identifier to be tested; S212: The main control module retrieves the locally preset standard-FPGA reconfiguration firmware mapping table. This table stores the unique association identifier between different wireless standards and the corresponding FPGA reconfiguration firmware files; S213: The main control module matches the corresponding reconfiguration firmware file according to the standard identifier: the integrity of the locally stored firmware file is verified by MD5. If the verification fails, the backup file is automatically retrieved from the platform's spare storage area. If the verification is successful, the main control module parses the basic attributes of the firmware file to confirm compatibility with the dual high-performance FPGA hardware versions of the eight-channel signal processing module.

3. The multi-standard wireless testing method based on FPGA reconstruction according to claim 2, characterized in that, The specific process of FPGA reconfiguration firmware file upload and FPGA dynamic loading in step S2 is as follows: FPGA reconfiguration firmware file upload: S221: The main control module establishes an FTP communication link with the eight-channel signal processing module, sends a firmware upload command to the system management FPGA, and carries the firmware file name, size, and transmission checksum; S222: After receiving the command, the system management FPGA initializes the specified partition of the EMMC storage unit, clears the historical firmware files in the partition, and reports to the main control module that the storage partition is ready; S223: The main control module uploads the reconfigured firmware file to the EMMC storage partition using a segmented transmission method. After each segment is transmitted, the system management FPGA verifies the transmission checksum of the segment. If the verification passes, it reports successful segment reception; if the verification fails, it requests the main control module to retransmit the segment; S224: After all segments are transmitted, the system management FPGA performs an MD5 checksum on the entire firmware file. If the verification passes, it reports firmware upload completion to the main control module and renames the firmware file to a fixed identifier name; if the verification fails, it reports upload failure, and the main control module re-executes this stage of the process; GA Dynamic Loading: S225: After receiving confirmation of firmware upload completion, the system management FPGA calls the pre-integrated dynamic configuration driver; S226: The dynamic configuration driver initializes the hardware interface of the FPP×32 configuration mode, sets the loading timing parameters, and sends a configuration reset command to the dual high-performance FPGAs, enabling the dual high-performance FPGAs to enter the firmware loading ready state; S227: The system management FPGA reads the reconstructed firmware file from the EMMC storage unit, configures the loading timing according to the FPP program (frame header synchronization → continuous transmission of configuration data → frame tail verification), and writes the firmware data stream into the configuration registers of the dual high-performance FPGAs; S228: The dual high-performance FPGAs receive configuration data in real time, and automatically perform internal self-tests after firmware loading is completed. If the self-test passes, a reconstruction success level signal is sent to the system management FPGA; if the self-test fails, a reconstruction failure level signal is sent, along with a failure code; S229: After receiving the reconstruction success signal, the system management FPGA uploads an FPGA reconstruction completion status message to the main control module; if a reconstruction failure signal is received, a failure code is sent to the host computer, and the firmware reloading process is triggered.

4. The multi-standard wireless testing method based on FPGA reconstruction according to claim 1, characterized in that, The specific process of step S3 is as follows: S31: Test command reception and parameter parsing: S311: The main control module receives the standardized test command frame sent by the host computer through the Ethernet switching bus; S312: The main control module first verifies the CRC32 checksum of the command frame. If the verification fails, it reports the invalid command to the host computer and requests a retransmission. If the verification succeeds, it parses the parameter segment, extracts the specified core parameters, and stores them in categories; S313: The main control module performs a validity check on the parsed parameters; S32: Bus parameter sending is performed, including high-speed serial bus sending, asynchronous RS485 bus sending, and clock distribution link sending; S33: Link configuration verification and status feedback are performed: S33 1. The main control module sends a link detection command to the RF channel module. The RF channel module collects the signal power at the link input or output end through its built-in power detection circuit to verify whether the transmit or receive link is conducting and whether the power attenuation meets the configuration value.

2. The main control module sends a sampling test command to the AD / DA module. The AD / DA module outputs a reference sine wave signal to verify whether the sampling rate and conversion mode configuration are correct.

3. The main control module summarizes the configuration status of all modules, generates a configuration completion status message, and uploads it to the host computer.

4. If any module fails to configure, the main control module locates the faulty module and fault type, reports the fault information to the host computer, and triggers the reconfiguration process.

5. The multi-standard wireless testing method based on FPGA reconstruction according to claim 4, characterized in that, The specific process of step S32 is as follows: S321: High-speed serial bus transmission: The main control module initializes the communication link of the high-speed serial bus, sends parameters to the bus and sends a pre-synchronization command. After receiving the command, the eight-channel signal processing module and the AD / DA module return a ready response. The main control module encapsulates the baseband processing parameters into binary parameter packets and sends them to the dual high-performance FPGAs of the eight-channel signal processing module. After receiving the parameter packets, the dual high-performance FPGAs verify the matching of the parameter version number with the reconstructed FPGA firmware version. If the match is successful, the parameters are written to a dedicated configuration register and feedback is given that the baseband parameters have been successfully received. If the match is unsuccessful, feedback is given that the parameter versions are incompatible, and the main control module resends the parameters with the appropriate version. The main control module sends the sampling rate and conversion mode configuration parameters to the AD / DA module. After receiving the parameters, the AD / DA module configures its internal phase-locked loop to achieve sampling rate matching and adjusts the sampling clock phase. S322: Asynchronous RS485 bus transmission: The main control module sends link configuration command frames to the RF channel module through the asynchronous RS485 bus. The RF channel module is configured with a frequency synthesizer to lock the target frequency, sets the power attenuation value, and establishes a transmit or receive link by switching the link switch via a relay. After the RF channel module completes its configuration, it collects the current link's frequency lock status and actual attenuation value, encapsulates them into a link configuration response frame, and feeds it back to the main control module; S323: Clock distribution link issuance: The main control module sends a clock division configuration command to the clock module; The clock module configures its internal frequency divider to divide the main clock into the target clock frequency, and distributes the synchronization clock to the backplane clock distribution link through the clock distribution chip; The main control module issues timing calibration commands to the eight-channel signal processing module, AD / DA module, and RF channel module through the clock distribution link, and each module adjusts the phase difference between its internal working clock and the synchronization clock; After each module completes timing calibration, it sends a feedback message to the main control module indicating that clock synchronization is complete.

6. The multi-standard wireless testing method based on FPGA reconstruction according to claim 1, characterized in that, The specific process of step S4 is as follows: S41: Transmission and reception of multi-standard RF signals and baseband processing in the transmit test mode; S42: Transmission and reception of multi-standard RF signals and baseband processing in the receive test mode.

7. The multi-standard wireless testing method based on FPGA reconstruction according to claim 6, characterized in that, The specific process of step S41 is as follows: S411: Multi-standard digital baseband signal generation and channel simulation: Dual high-performance FPGAs read baseband processing parameters. The first high-performance FPGA is responsible for signal generation logic, and the second FPGA is responsible for parallel processing and verification. Based on the reconstructed standard algorithm, the FPGA first generates the original bit stream of the standard to be tested. The baseband signal processing is executed sequentially, including encoding, interleaving, modulation, and frame encapsulation. The second high-performance FPGA reads the configured channel simulation parameters, performs channel simulation, including generating multipath channel impulse response and convolution operation, and performs real-time verification on the generated digital baseband signal. If the verification passes, the 8-channel parallel IQ digital signal is output to the AD / DA module. If the verification fails, a baseband signal generation anomaly is reported to the main control module, terminating this stage and triggering regeneration; S412: Digital-to-Analog Conversion: The AD / DA module receives the digital baseband signal output from the FPGA and converts the digital IQ signal into an intermediate frequency analog IQ signal; S413: RF Transmit Link Conditioning and Output: The RF channel module receives the intermediate frequency analog IQ signal and selects the appropriate processing path for frequency conversion processing according to the configured frequency band type; the frequency-converted RF signal is filtered out for spurious signals by a bandpass filter and then amplified by a power amplifier link; the power is precisely adjusted to the target value through the configured power attenuation link; the RF signal is output to the RF interface of the device under test through an 8-channel selection switch, and the RF channel module simultaneously collects the actual power, frequency, and EVM value of the output signal and feeds it back to the main control module.

8. The multi-standard wireless testing method based on FPGA reconstruction according to claim 6, characterized in that, The specific process of step S42 is as follows: S421: The RF signal output by the device under test is connected to the receiving link input of the RF channel module, and out-of-band interference signals are filtered out by a low-pass filter; according to the configured target RF frequency, the corresponding sampling path is selected for amplification; the amplified signal is controlled by an automatic gain control circuit to ensure that the signal power of each node is ≥-20dBm and the overall dynamic range of the receiving link is ≥70dB; the conditioned intermediate frequency analog IQ signal is output to the AD / DA module, and the RF channel module collects the actual frequency, power, and signal-to-noise ratio of the received signal and feeds it back to the main control module; S422: Analog-to-digital conversion is performed: the AD / DA module receives the intermediate frequency analog IQ signal, completes analog-to-digital conversion according to the configured sampling rate, and converts the analog signal into a digital IQ baseband signal; S423: Digital Baseband Processing Analysis: The dual high-performance FPGAs receive digital baseband signals and, based on the S2 reconstruction standard algorithm, sequentially perform quadrature demodulation, synchronization processing, equalization processing, and decoding processing.

9. The multi-standard wireless testing method based on FPGA reconstruction according to claim 1, characterized in that, The specific process of step S5 is as follows: S51: The dual high-performance FPGAs encapsulate the test data into standardized data frames; the eight-channel signal processing module sends the encapsulated test data frames to the backplane interconnect module; the backplane interconnect module converts the received high-speed serial bus data frames into Ethernet frame format and forwards them to the dedicated data receiving port of the main control module; S52: Status data is collected at fixed intervals, including the status of the RF channel module, clock module, power supply module, and eight-channel signal processing module; S53: The main control module performs parsing operations on the test data and status data: splits the data frames according to the format and channel, extracts the specified key indicators, and performs cross-verification and data standardization. The main control module integrates the test data and the status data of each module into a unified feedback message.

10. A multi-standard wireless test system based on FPGA reconstruction, used to implement the multi-standard wireless test method based on FPGA reconstruction described in any one of 1-9, characterized in that, The system includes a backplane interconnect module, an eight-channel signal processing module, an RF channel module, a clock module, a main control module, and a power supply module. The backplane interconnect module constructs a three-level data interaction channel consisting of a high-speed serial bus, an Ethernet switching bus, an asynchronous RS485 bus, and a trigger I / O switching bus. The high-speed serial bus is used to transmit baseband processing parameters and test data, the Ethernet switching bus is used for high-speed uploading of test data, and the asynchronous RS485 bus is used to transmit module control commands and status feedback information. The baseband signal processing module of the eight-channel signal processing module adopts a three-chip architecture of dual high-performance FPGAs + a system management FPGA. The RF channel module includes a transmit link and a receive link; the clock module uses a temperature-controlled crystal oscillator as the main clock source to generate a nanosecond-level synchronous clock, and distributes the synchronous clock to each module of the system through a clock distribution link; the power supply module adopts a hierarchical power supply architecture of centralized conversion + module discrete voltage regulation to provide suitable DC power supply for each module; the main control module is communicatively connected to the backplane interconnect module, the eight-channel signal processing module, the RF channel module, the clock module, and the power supply module, and is used to complete system initialization configuration, FPGA reconstruction file matching and loading, full-domain test parameter distribution and link configuration, control of multi-standard RF signal transmission and reception and baseband processing, test data acquisition and real-time feedback, seamless switching of multi-standard tests, and test termination reset.

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