Semiconductor device including active portion and bit line

Abstract

There is provided a semiconductor device including: a first active portion; an isolation region on a side surface of the first active portion; and a bit line connected to the first active portion, where the first active portion includes a first region in contact with the isolation region and a second region extending upward from the first region, where the second region is spaced apart from the isolation region, and where the bit line includes: a line portion extending in a first horizontal direction; and a contact portion below the line portion, where the contact portion is connected to the second region of the first active portion.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0152823, filed on October 31, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference for all purposes. Technical Field

[0003] This disclosure relates to a semiconductor device including an active portion and a bit line, and a method for forming the semiconductor device. Background Technology

[0004] This disclosure relates to a semiconductor device including an active portion and a bit line, and a method for forming the semiconductor device.

[0005] Research is underway to reduce the size of the components that make up semiconductor devices and improve their performance. For example, in DRAM, research is being conducted on reliably and stably fabricating smaller components. Summary of the Invention

[0006] A semiconductor device for increasing integration is provided.

[0007] A semiconductor device for improving reliability is also provided.

[0008] A method for manufacturing semiconductor devices is also provided, which can increase integration and improve reliability.

[0009] According to one aspect of this disclosure, a semiconductor device includes: a first active portion; an isolation region on a side surface of the first active portion; and a bit line connected to the first active portion, wherein the first active portion includes a first region in contact with the isolation region and a second region extending upward from the first region, wherein the second region is spaced apart from the isolation region, and wherein the bit line includes: a line portion extending in a first horizontal direction; and a contact portion below the line portion, wherein the contact portion is connected to the second region of the first active portion.

[0010] According to one aspect of this disclosure, a semiconductor device includes: a first active portion; a second active portion adjacent to the first active portion; an isolation region between the first active portion and the second active portion; a bit line connected to the first active portion; a contact structure connected to the second active portion; and a data storage structure connected to the contact structure, wherein the first active portion includes an upper surface that protrudes upward, and wherein the bit line includes: a contact portion that contacts the upper surface of the first active portion; and a line portion on the contact portion that extends in a first horizontal direction.

[0011] According to one aspect of this disclosure, a semiconductor device includes: active regions; isolation regions between the active regions; a gate structure extending across the active regions and into the isolation regions; and bit lines connected to the active regions, wherein each active region includes a first active portion and a second active portion, wherein the first active portion and the second active portion of each corresponding active region in the active regions are spaced apart from each other by a gate structure in the gate structure intersecting the corresponding active regions, wherein the active regions include the first active regions, wherein the bit lines include a first bit line connected to the first active portion of the first active regions, wherein the first active portion of the first active regions includes: a first region including a side surface contacting the isolation regions; and a second region extending upward from the first region, the second region being spaced apart from the isolation regions, and wherein the first bit line includes: a line portion extending in a first horizontal direction; and a contact portion located below the line portion and connected to the second region of the first active portion. Attached Figure Description

[0012] The above and other aspects and features of certain embodiments of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0013] Figure 1A This is a plan view illustrating a semiconductor device according to one or more embodiments of the present disclosure;

[0014] Figure 1B It is shown Figure 1A A plan view of some components;

[0015] Figure 2A This is a cross-sectional view showing the region intercepted along line I-I' in Figure 1;

[0016] Figure 2B It is shown Figure 2A A magnified view of the area indicated by "A" in the middle;

[0017] Figure 3 It shows along Figure 1A A cross-sectional view of the area intercepted by line II-II';

[0018] Figure 4A and Figure 4B This is a diagram illustrating a semiconductor device according to one or more embodiments of the present disclosure;

[0019] Figure 5A and Figure 5B This is a diagram illustrating a semiconductor device according to one or more embodiments of the present disclosure;

[0020] Figure 6A and Figure 6B A diagram illustrating a semiconductor device according to one or more embodiments of the present disclosure; and

[0021] Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 and Figure 16 This is a diagram illustrating an example of a method for forming a semiconductor device according to one or more embodiments of the present disclosure. Detailed Implementation

[0022] In the following text, terms such as “upper,” “middle,” and “lower” may be replaced by other terms such as “first,” “second,” and “third” to describe the elements in the specification. Although the terms “first,” “second,” and “third” can be used to describe a variety of elements, the elements are not limited by the terms, and a “first element” may be referred to as a “second element.” The reference numerals BL (BL1) and BL (BL2) shown in the accompanying drawings can be described as indicating that the element referred to as “BL” includes the element referred to as “BL1” and the element referred to as “BL2.” Even without a separate explanation, the size ratios, width ratios, length ratios, etc., between the elements depicted in the accompanying drawings can be understood from the elements depicted in the drawings.

[0023] In the following description, the same reference numerals refer to the same elements throughout the specification.

[0024] It should be understood that when a component is referred to as being “connected” to or connected to another component, it can be directly or indirectly connected to the other component.

[0025] Furthermore, when a component "comprises" or "includes" an element, the component may also include other elements without excluding them, unless there is a specific description to the contrary.

[0026] Throughout the specification, when one component is “on” another component, this includes not only when the component is in contact with the other component, but also when there is another component between the two components.

[0027] As used herein, the expressions “at least one of a, b, or c” and “at least one of a, b, and c” indicate “only a”, “only b”, “only c”, “both a and b”, “both a and c”, “both b and c”, and “all a, b, and c”.

[0028] As used herein, the singular forms “a,” “one,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0029] Identification codes may be used for the purposes of description of any method or process described herein, but are not intended to indicate the order of each step or operation. Each step or operation may be performed in a different order than that shown, unless the context clearly indicates otherwise. One or more steps or operations may be omitted unless the context of this disclosure clearly indicates otherwise.

[0030] The various actions, behaviors, blocks, steps, etc. in the flowchart can be executed in the presented order, in different orders, or simultaneously. Furthermore, in one or more embodiments, some of the actions, behaviors, blocks, steps, etc., may be omitted, added, modified, or skipped without departing from the scope of this disclosure.

[0031] Reference Figure 1A , Figure 1B , Figure 2A , Figure 2B and Figure 3 Exemplary examples of semiconductor devices according to one or more embodiments of this disclosure are described. Figure 1A This is a plan view illustrating a semiconductor device according to one or more embodiments of the present disclosure, and Figure 1B It is shown Figure 1A A plan view of some of the components. Figure 2A This is a cross-sectional view showing the region intercepted along line I-I' in Figure 1, and Figure 2B It is shown Figure 2A A magnified view of the area indicated by "A". Figure 3 It shows along Figure 1A A cross-sectional view of the area intercepted by line II-II'.

[0032] refer to Figure 1A , Figure 1B , Figure 2A , Figure 2B and Figure 3 The semiconductor device 1 according to one or more embodiments may include a substrate SUB, an active region ACT, an isolation region STI, a bit line BL, and an insulating spacer structure SP.

[0033] The substrate SUB can be a semiconductor substrate. The substrate SUB can be provided as a bulk silicon wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, or a semiconductor-on-insulator (SeOI) layer. The substrate SUB can include group IV semiconductors, group III-V compound semiconductors, or group II-VI compound semiconductors. For example, the substrate SUB can be a substrate comprising at least one of silicon, silicon carbide, germanium, and silicon-germanium. For example, the substrate SUB can be a single-crystal silicon substrate comprising a silicon material (e.g., single-crystal silicon material).

[0034] An active region ACT can be disposed on a substrate SUB. The active region ACT can have a shape protruding from the substrate SUB in the vertical direction Z. The active region ACT can be formed of the same semiconductor material as the substrate SUB, for example, single-crystal silicon. Each active region ACT can have a strip shape extending in the D direction. An isolation region STI can define the active region ACT on the substrate SUB. The isolation region STI can be disposed on the side surface of the active region ACT. The isolation region STI can be disposed between the active regions ACT. The isolation region STI can be formed of an insulating material including at least one of silicon oxide and silicon nitride.

[0035] The semiconductor device 1 may further include a gate structure GS that extends across the active region ACT and into the isolation region STI. The gate structure GS may be disposed in a gate trench GT that extends across the active region ACT and into the isolation region STI. Each of the gate structures GS may have a linear shape extending in the X direction.

[0036] Each of the gate structures GS may include a gate pattern GP and a gate capping layer GC.

[0037] Each of the gate patterns GP may include a gate dielectric layer Gox and a gate electrode GE. In each gate structure GS, the gate dielectric layer Gox may be disposed on the inner wall of a gate trench GT, and the gate electrode GE may partially fill the gate trench GT on the gate dielectric layer Gox. A gate capping layer GC may fill the remaining portion of the gate trench GT on the gate electrode GE. The gate electrode GE and the gate capping layer GC may be stacked sequentially. The gate dielectric layer Gox may be disposed between the bottom surface of the gate electrode GE and the bottom surface of the gate trench GT, between the side surface of the gate electrode GE and the sidewall of the gate trench GT, and between the side surface of the gate capping layer GC and the sidewall of the gate trench GT.

[0038] Each of the active regions ACT may include active portions AF1 and AF2 spaced apart from each other by the gate structure GS.

[0039] In a gate structure GS, a pair of adjacent gate structures GS can span an active region ACT. Therefore, an active region ACT can include active portions AF1 and AF2 spaced apart from each other by a pair of gate structures GS. In an active region ACT, active portions AF1 and AF2 can include a first active portion AF1 disposed between a pair of gate structures GS, and a second active portion AF2 disposed outside the pair of gate structures GS. For example, in the gate structures GS, the first gate structure GS1 and the second gate structure GS2, which are adjacent to each other, can intersect with the first active region ACT1 in the active region ACT, and the first active region ACT1 can include a first active portion AF1 and a second active portion AF2 spaced apart from each other by the first gate structure GS1 and the second gate structure GS2. Therefore, each of the active regions ACT can include a second active portion AF2 spaced apart from each other in the D direction, and a first active portion AF1 between the second active portions AF2.

[0040] The active region ACT can include the first active region ACT1, the second active region ACT2, and the third active region ACT3.

[0041] The first active region ACT1 and the second active region ACT2 can be adjacent to each other in the X direction (separated by the isolation region STI). The first active region ACT1 and the third active region ACT3 can be adjacent to each other in the Y direction (again separated by the isolation region STI).

[0042] The X and Y directions can be horizontal directions parallel to the upper surface of the substrate SUB and perpendicular to each other. The D direction can be a diagonal direction parallel to the upper surface of the substrate SUB. The Y direction can be referred to as the first horizontal direction, the X direction as the second horizontal direction, and the D direction as the diagonal direction. As noted above, the Z direction can also be referred to as the vertical direction in this paper.

[0043] In such Figure 1B On the plane, the first active portion AF1 of the first active region ACT1 can be adjacent in the X direction to the second active portion AF2 of the second active region ACT2, which is positioned at a lower position. In, for example... Figure 1B On the plane, the second active portion AF2 of the second active portion AF2 of the first active region ACT1, which is set higher in the X direction, can be set between the second active portion AF2 of the second active portion AF2 of the second active region ACT2 and the second active portion AF2 of the third active region ACT3, which is set lower.

[0044] The upper surface AF2_U of the second active portion ACT2 (AF2) can be set at a higher level than the upper surface AF1_U of the first active portion ACT1 (AF1) (i.e., farther from the substrate SUB).

[0045] In one or more embodiments, the upper surface AF1_U of the first active portion ACT1 (AF1) may have an upwardly convex shape (i.e., it is convex on the side opposite to the substrate SUB).

[0046] In one or more embodiments, the upper surface AF2_U of the second active portion ACT2 (AF2) may have a substantially flat shape.

[0047] In each active region ACT, the first active portion AF1 may include a first region AP1 that contacts the isolation region STI and a second region AP2 that extends upward from the first region AP1 in the Z direction and is spaced apart from the isolation region STI.

[0048] In one or more embodiments, the vertical thickness of the second region AP2 may be greater than the width of the second region AP2.

[0049] In each active region ACT, the side surface of the first active portion AF1 may include a first side surface AP1S of the first region AP1, a second side surface AP2S of the second region AP2, and a curved portion APB between the first side surface AP1S and the second side surface AP2S. The curved portion APB may be a region that bends from the first side surface AP1S and the second side surface AP2S.

[0050] The curved portion APB can be set at the first level L1, the upper surface AF1_U of the first active portion ACT1 (AF1) can be set at the second level L2, and the upper surface AF2_U of the second active portion ACT2 (AF2) can be set at the third level L3.

[0051] In one or more embodiments, the height difference H1 between the first level L1 and the second level L2 may be greater than the height difference H2 between the second level L2 and the third level L3.

[0052] Each active region ACT may include a first source / drain region SD1 disposed in the upper region of the first active portion AF1, a second source / drain region SD2 disposed in the upper region of the second active portion AF2, and a channel region CH disposed in the lower regions of the first active portion AF1 and the second active portion AF2 and in the active region ACT below the gate structure GS. Each channel region CH may be disposed below the lower surface of a gate structure GS and within the first active portion AF1 and the second active portion AF2 disposed on both sides of the gate electrode GE of a gate structure GS.

[0053] The gate dielectric layer Gox, the gate electrode GE, the first source / drain region SD1, the channel region CH, and the second source / drain region SD2 can form a transistor TR.

[0054] The semiconductor device 1 may further include bit lines BL and insulating spacer structures SP.

[0055] Each bit line BL may include a line portion LP extending in the Y direction and a contact portion CP disposed below the line portion LP and connected to the first active portion AF1.

[0056] The contact portion CP can be electrically connected to the upper surface AF1_U of the first active portion AF1. The contact portion CP can contact the upper surface AF1_U of the first active portion AF1. The vertical length of the contact portion CP can be equal to or less than the vertical length of the second region AP2. Here, the vertical length can be the thickness in the vertical direction Z.

[0057] The width of the contact portion CP in the X direction can be substantially the same as the width of the second region AP2 of the first active portion AF1 in the X direction. For example... Figure 2B As shown, the side surface of the contact portion CP in the X direction can be aligned with the side surface AP2S of the second region AP2 of the first active portion AF1 in the X direction.

[0058] The width of the contact portion CP in the X direction can be smaller than the width of the first region AP1 of the first active portion AF1 in the X direction.

[0059] The width of the contact portion CP in the Y direction can be greater than the width of the second region AP2 of the first active portion AF1 in the Y direction. The width of the contact portion CP in the Y direction can be greater than the width of the first region AP1 of the first active portion AF1 in the Y direction.

[0060] The line portion LP may include at least one conductive layer. For example, the line portion LP may include a first conductive layer 12a, a second conductive layer 12b, and a third conductive layer 12c stacked sequentially. The first to third conductive layers (12a, 12b, and 12c) may include different materials. The first conductive layer 12a may include doped silicon. For example, the first conductive layer 12a may include at least one of doped polycrystalline silicon and doped epitaxial silicon. The second conductive layer 12b may include at least one of TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, and CoSi. The third conductive layer 12c may include at least one of Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, and Co.

[0061] Each contact portion CP can extend from the line portion LP. For example, each contact portion CP can extend from the first conductive layer 12a of the line portion LP. Therefore, the contact portion CP can be formed from the first conductive layer 12a.

[0062] The isolation region STI may include an isolation region STIa disposed between a first active portion AF1 of a first active region ACT1 and a second active portion AF2 of a second active region ACT2. The isolation region STIa may further include a portion between a contact spacer SP_C and the second active portion AF2. The isolation region STIa may be disposed between the first active portion AF1 of the first active region ACT1 and the second active portion AF2 of the second active region ACT2, and may extend between the contact spacer SP_C and the second active portion AF2.

[0063] The semiconductor device 1 may further include a buffer insulating structure 6 on the active region ACT, the isolation region STI, and the gate structure GS. The buffer insulating structure 6 may include at least one insulating material. For example, the buffer insulating structure 6 may include a first insulating layer 6a, a second insulating layer 6b, and a third insulating layer 6c stacked sequentially. The first insulating layer 6a and the third insulating layer 6c may include silicon oxide, and the second insulating layer 6b may include silicon nitride.

[0064] The line portion LP of bit line BL can be set on buffer insulation structure 6.

[0065] Semiconductor device 1 may also include a bit line capping pattern BC on bit line BL.

[0066] Each bitline capping pattern BC may include an insulating material such as silicon nitride. Each bitline capping pattern BC may include at least one insulating material layer. For example, each bitline capping pattern BC may include a first insulating material layer 15, a second insulating material layer 21 on the first insulating material layer 15, and a third insulating material layer 27 on the second insulating material layer 21. In each bitline capping pattern BC, the thickness of the second insulating material layer 21 may be less than the thickness of each of the first insulating material layer 15 and the third insulating layer 27.

[0067] The semiconductor device 1 may further include insulating spacer structures SP. Each insulating spacer structure SP may include a contact spacer SP_C and a line spacer SP_L.

[0068] The contact spacer SP_C can be disposed on the side surface of the second region AP2 of the first active portion AF1 and the side surface of the contact portion CP of the bit line BL. The contact spacer SP_C can contact the side surface of the second region AP2 of the first active portion AF1 and the side surface of the contact portion CP of the bit line BL.

[0069] Line spacer SP_L can be disposed on the side surface of the line portion LP of bit line BL and the side surface of bit line capping pattern BC. Line spacer SP_L can contact the side surface of the line portion LP of bit line BL and the side surface of bit line capping pattern BC. The width of line spacer SP_L can be smaller than the width of contact spacer SP_C.

[0070] Each insulating spacer structure SP may include an inner spacer 30, an intermediate spacer 42, an outer spacer 45, and a plug spacer 36.

[0071] Intermediate spacer 42 and outer spacer 45 can be disposed on the side surface of the line portion LP of bit line BL and the side surface of bit line cover pattern BC.

[0072] The insert spacer 36 may be disposed on the side surface of the contact portion CP of the bit line BL. The insert spacer 36 may include a spacer pattern 36b and a spacer liner 36a covering the side and bottom surfaces of the spacer pattern 36b.

[0073] The inner spacer 30 can be disposed between the side surface of the position line cover pattern BC and the intermediate spacer 42, between the side surface of the line portion LP of the position line BL and the intermediate spacer 42, and between the side surface of the contact portion CP of the position line BL and the plug spacer 36, and can extend to cover the lower surface and outer surface of the plug spacer 36.

[0074] The inner spacer 30 may include at least one of SiN and SiCN. The intermediate spacer 42 may include at least one of silicon oxide and a low-k dielectric. Here, the low-k dielectric may be a dielectric with a dielectric constant less than that of silicon oxide. According to one or more embodiments, the intermediate spacer 42 may be an air gap. The outer spacer 45 may include at least one of SiN and SiCN.

[0075] The semiconductor device 1 may also include a contact structure CNT. The contact structure CNT may be formed of a conductive material. The contact structure CNT may be electrically connected to the second source / drain region SD2 of the second active portion AF2.

[0076] Each contact structure CNT may include a lower conductive layer 55, an upper conductive layer 64 on the lower conductive layer 55, an intermediate conductive layer 61 between the lower conductive layer 55 and the upper conductive layer 64, and a pad pattern 75p on the upper conductive layer 64. The lower conductive layer 55 may contact the second source / drain region SD2.

[0077] The lower conductive layer 55 may include doped polysilicon, such as polysilicon with N-type conductivity. The intermediate conductive layer 61 may include a metal-semiconductor compound layer. The upper conductive layer 64 may include a conductive layer 64b and a barrier layer 64a covering the side and bottom surfaces of the conductive layer 64b. The barrier layer 64a may include at least one of TiN, TaN, WN, TiSiN, TaSiN, and RuTiN, and the conductive layer 64b may include a metallic material such as W. The pad pattern 75p may include at least one of Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, and NiSi. The pad pattern 75p may be positioned at a higher level than the bit line cap pattern BC (i.e., farther from the substrate SUB) and cover a portion of the upper surface of the adjacent bit line cap pattern BC.

[0078] In one example, the pad pattern 75p and the upper conductive layer 64 can be formed by different processes, such that a boundary surface can be formed between the lower surface of the pad pattern 75p and the upper surface of the upper conductive layer 64.

[0079] The semiconductor device 1 may also include upper spacers 58 surrounding the side surfaces of the upper conductive layer 64. The upper spacers 58 may include an insulating material such as silicon oxide or silicon nitride.

[0080] Semiconductor device 1 may also include insulating gates IF parallel to each other. Each insulating gate IF may have a linear shape extending in the X direction. The insulating gate IF may be perpendicularly overlapped with the gate structure GS. The insulating gate IF may be formed of an insulating material such as silicon nitride or silicon oxide. The insulating gate IF may separate the contact structure CNT from the bit line capping pattern BC. Within the insulating gate IF, a portion of the insulating gate IF that is perpendicularly overlapped with the bit line BL may be positioned at a higher level than the bit line BL (i.e., farther from the substrate SUB) and may penetrate a portion of the bit line capping pattern BC.

[0081] The semiconductor device 1 may also include an insulating isolation pattern 78, an etch stop layer 85, and a data storage structure DS.

[0082] An insulating isolation pattern 78 may be disposed on the side surface of the pad pattern 75p and may extend downward. The insulating isolation pattern 78 may be disposed at a higher level than the bit line BL (i.e., farther from the substrate SUB). An etch stop layer 85 may be disposed on the insulating isolation pattern 78 and the pad pattern 75p and may be formed of an insulating material.

[0083] In one or more embodiments, the data storage structure DS can be a capacitor storing information in DRAM. For example, the data storage structure DS can be a capacitor for DRAM, including a first electrode 88 penetrating an etch stop layer 85 and electrically connected to a contact structure CNT, a dielectric layer 90 covering the first electrode 88 and the etch stop layer 85, and a second electrode 92 on the dielectric layer 90. The dielectric layer 90 can include a high dielectric, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The high dielectric can be a dielectric having a dielectric constant higher than that of silicon oxide.

[0084] In one or more embodiments, the data storage structure DS can be a structure that stores information of a memory other than DRAM. For example, in the data storage structure DS, the dielectric layer 90 may include a ferroelectric layer that can record data using polarization states.

[0085] In one or more embodiments, by forming the upper surface of the first active portion AF1 to be upwardly convex, the contact area between the first source / drain region SD1 of the first active portion AF1 and the contact portion CP of the bit line BL can be increased. Accordingly, the contact resistance between the first source / drain region SD1 of the first active portion AF1 and the contact portion CP of the bit line BL can be reduced, thereby improving the performance of the semiconductor device.

[0086] In one or more embodiments, the first active portion AF1 may include a second region AP2 protruding upward from the first region AP1. Since the second region AP2 can minimize the vertical thickness of the contact portion CP of the bit line BL, the bit line BL including the contact portion CP can be formed without defects.

[0087] In the following, various examples of modifications to the elements of the above-described exemplary embodiments will be described. The various examples of modifications to the elements of the above-described embodiments described below will focus on the modified or replaced elements. Here, elements described above may be directly referenced without separate detailed description, or descriptions may be omitted. Furthermore, elements that can be modified or replaced as described below are described with reference to the accompanying drawings; however, elements that can be modified or replaced may be combined with each other or with the elements described above to form a semiconductor device according to one or more embodiments of this disclosure.

[0088] refer to Figure 4A and Figure 4B This document will describe exemplary examples of semiconductor devices according to one or more embodiments of the present disclosure. Figure 4A This is a cross-sectional view showing the region intercepted along line I-I' in Figure 1, and Figure 4B It is shown Figure 4A A magnified view of the area indicated by "Aa".

[0089] In one or more embodiments, reference Figure 4A and Figure 4B The contact parts mentioned above can be modified. Figure 2A and Figure 2B The CP) is used to form a contact portion CPa with an increased vertical length, and the second region described above can be modified. Figure 2A and Figure 2B AP2) to form a second region AP2a with a reduced vertical length. Here, the vertical length can be the thickness in the vertical direction Z.

[0090] In one example, the vertical length of the contact portion CPa can be greater than the vertical length of the second region AP2a.

[0091] As described above, the curved portion APB can be located at the first level L1, and the upper surface AF2_U of the second active portion AF2 can be located at the third level L3.

[0092] The upper surface AF1a_U of the second vertical portion AP2a of the first active portion AF1 can be set at the middle horizontal L2a.

[0093] In one example, the height difference H1a between the first level L1 and the intermediate level L2a can be equal to or less than the height difference H2a between the intermediate level L2a and the third level L3. For example, in Figure 4B The diagram shows that the height difference H1a between the first level L1 and the intermediate level L2a is less than the height difference H2a between the intermediate level L2a and the third level L3. However, in one or more embodiments, the height difference H1a between the first level L1 and the intermediate level L2a may be substantially equal to the height difference H2a between the intermediate level L2a and the third level L3.

[0094] refer to Figure 5A and 5B This document will describe exemplary examples of semiconductor devices according to one or more embodiments of the present disclosure. Figure 5A This is a cross-sectional view showing the region intercepted along line I-I' in Figure 1, and Figure 5B It is shown Figure 5A A magnified view of the area indicated by "Ab".

[0095] In one or more embodiments, reference Figure 5A and Figure 5B It is possible to modify the second region, which has a width substantially the same as the contact portion CP described above. Figure 2A and Figure 2BThe second region AP2b, which is upwardly protruding, is formed to have a width greater than that of the contact portion CP. The upper surface of the second region AP2b can contact the contact portion CP. In the X direction, the width of the second region AP2b can be greater than the width of the contact portion CP. For example, the maximum width of the second region AP2b in the X direction can be greater than the maximum width of the contact portion CP in the X direction.

[0096] The width of the lower region of the second region AP2b can be greater than the width of the upper region of the second region AP2b. In the X direction, the width of the lower region of the second region AP2b can be greater than the width of the contact portion CP. Accordingly, the electrical characteristics of the first source / drain region SD1 formed within the second region AP2b can be improved.

[0097] refer to Figure 6A and Figure 6B This document will describe exemplary examples of semiconductor devices according to one or more embodiments of the present disclosure. Figure 6A This is a cross-sectional view showing the region intercepted along line I-I' in Figure 1, and Figure 6B It is shown Figure 6A A magnified view of the area indicated by "Ac".

[0098] In one or more embodiments, reference Figure 6A and Figure 6B The first conductive layer of the aforementioned bit line BL ( Figure 2A and Figure 2B 12a) can be transformed into a first conductive layer 12aa with a narrow width. For example, the width of the first conductive layer 12aa of the bit line BL can be smaller than the width of each of the second conductive layer 12b and the third conductive layer 12c of the bit line BL.

[0099] The above contact parts ( Figure 2A and Figure 2B The CP can be transformed into a contact portion CPb with a narrow width. Therefore, in the X direction, the width of the contact portion CPb can be smaller than the width of the second region AP2.

[0100] Next, refer to Figure 1A , Figure 2B and Figures 7 to 16 The present disclosure will describe exemplary methods for forming a semiconductor device according to one or more embodiments. Figure 7 This is a process flow diagram illustrating an exemplary example of a method for forming a semiconductor device according to one or more embodiments of the present disclosure, and Figures 8 to 16 This is a cross-sectional view used to illustrate an exemplary example of a method for forming a semiconductor device according to one or more embodiments of the present disclosure. Figures 7 to 16 middle, Figure 8, Figure 10 , Figure 12 , Figure 14 , Figure 15 and Figure 16 It is along Figure 1A The cross-sectional view taken by line I-I', and Figure 9 , Figure 11 and Figure 13 It is along Figure 1A The cross-sectional view taken from line II-II'.

[0101] refer to Figure 1A , Figure 1B , Figure 7 , Figure 8 and Figure 9 An isolation region STI (S10) can be formed to define the active region ACT. The active region ACT and the isolation region STI can be formed on the substrate SUB. The isolation region STI can be formed on the side surface of the active region ACT. The active region ACT can be as follows: Figure 1A and Figure 1B The arrangement is as shown in the image. For example, each active region ACT can have a strip shape extending in the D direction. The active regions ACT can be formed of a semiconductor material such as single-crystal silicon. The isolation regions (STI) can be formed of an insulating material. The isolation regions (STI) can be shallow trench isolation.

[0102] A unit transistor TR (S20) can be formed. Forming the unit transistor TR may include forming a gate trench GT that intersects with the isolation region STI and the active region ACT, and forming a gate structure GS within the gate trench GT. Each gate structure GS may have a linear shape extending in the X direction.

[0103] Each gate structure GS may include a gate pattern GP and a gate capping layer GC on the gate pattern GP. Each gate pattern GP may include a gate dielectric layer Gox and a gate electrode GE. In each gate pattern GP, ​​the gate dielectric layer Gox may be formed on the inner wall of a gate trench GT, and the gate electrode GE may partially fill the gate trench GT on the gate dielectric layer Gox. The gate capping layer GC may fill the remaining portion of the gate trench GT on the gate electrode GE. The gate capping layer GC may be formed of an insulating material such as silicon nitride. The gate dielectric layer Gox may extend from a portion disposed between the inner walls of the gate electrode GE and the gate trench GT to a point between the inner walls of the gate capping layer GC and the gate trench GT.

[0104] The forming unit transistor TR may further include forming a channel region CH and a first source / drain region SD1 and a second source / drain region SD2. The channel region CH and the first source / drain region SD1 and the second source / drain region SD2 may be formed within each active region ACT. Therefore, each active region ACT may include a channel region CH and the first source / drain region SD1 and the second source / drain region SD2. In one of the active regions ACT, the first source / drain region SD1 and the second source / drain region SD2 may be formed in the upper region of the active region ACT, and the channel region CH may be formed in the active region ACT below the first source / drain region SD1 and the second source / drain region SD2 and in the active region ACT below the gate structure GS.

[0105] Each unit transistor TR may include a gate electrode GE, a gate dielectric layer Gox, a channel region CH, a first source / drain region SD1, and a second source / drain region SD2.

[0106] In the gate structure GS, a pair of adjacent gate structures GS can extend across each active region ACT and into the isolation region STI. For example, each active region ACT may include active portions AF1 and AF2, which are spaced apart from each other by a pair of adjacent gate structures GS.

[0107] In each active region ACT, the active portions AF1 and AF2 may include a second active portion AF2 spaced apart from each other in the D direction and a first active portion AF1 disposed between the second active portions AF2.

[0108] A buffer insulation structure 6 can be formed. The buffer insulation structure 6 may include a first insulating layer 6a, a second insulating layer 6b, and a third insulating layer 6c stacked sequentially. The first insulating layer 6a and the third insulating layer 6c may be formed of silicon oxide, and the second insulating layer 6b may be formed of silicon nitride.

[0109] The buffer insulating structure 6 can cover the active region ACT, the isolation region STI, and the gate structure GS, but can leave the first source / drain region SD1 of the first active portion AF1 uncovered. Therefore, the first source / drain region SD1 of the first active portion AF1 can be exposed. The buffer insulating structure 6 can expose the first source / drain region SD1, a portion of the upper surface of the isolation region STI adjacent to the first source / drain region SD1, and a portion of the upper surface of each gate structure GS adjacent to the first source / drain region SD1.

[0110] refer to Figure 1A , Figure 1B , Figure 7 , Figure 10 and Figure 11The exposed isolation region STI and gate structure GS, which are not covered by the buffer insulation structure 6, can be partially etched to form a recessed region 7. Simultaneously, a portion of the first active portion AF1 can be etched to reduce its height, and the edge of the upper surface of the first active portion AF1 can be etched to form an upwardly convex upper surface of the first active portion AF1. Therefore, the upper surface of the first active portion AF1 can be formed at a lower level than the upper surface of the second active portion AF2, and the upper surface of the first active portion AF1 can have an upwardly convex curved shape. The upper surface of the second active portion AF2 can have a generally flat shape.

[0111] An insulating pattern 8 can be formed to partially fill the recessed region 7, wherein the insulating pattern 8 exposes the upper surface of the first active portion AF1. The insulating pattern 8 can be formed of an insulating material such as silicon oxide or silicon nitride.

[0112] refer to Figure 1A , Figure 1B , Figure 7 , Figure 12 and Figure 13 It can form at least one conductive layer (12a, 12b, 12c) and at least one insulating layer (15, 21, 27).

[0113] At least one conductive layer (12a, 12b, 12c) may comprise a first conductive layer 12a, a second conductive layer 12b, and a third conductive layer 12c stacked sequentially. The first conductive layer 12a may be formed on the buffer insulating structure 6, the insulating pattern 8, and the first active portion AF1. The first conductive layer 12a may contact the first active portion AF1 when filling the recessed region 7. At least one insulating layer (15, 21, 27) may comprise a first insulating material layer 15, a second insulating material layer 21, and a third insulating material layer 27 stacked sequentially.

[0114] refer to Figure 1A , Figure 1B , Figure 7 and Figure 14 Bit lines BL can be formed (S30). Forming bit lines BL may include patterning at least one conductive layer (12a, 12b, 12c) and at least one insulating layer (15, 21, 27).

[0115] At least one conductive layer (12a, 12b, 12c) can be patterned and formed into bit lines BL. At least one insulating layer (15, 21, 27) can be patterned and formed into bit line capping pattern BC. Each bit line BL can have the shape of a line extending in the Y direction. Bit lines BL can be formed to contact the upper surface of the first active portion AF1.

[0116] In one or more embodiments, the first active portion AF1 may be formed in a shape protruding from the bottom surface of the recessed region 7, and the insulating pattern 8 may be formed to cover the side surface of the protruding portion of the first active portion AF1 from the bottom surface of the recessed region 7. Due to the protruding portion of the first active portion AF1 from the bottom surface of the recessed region 7, and the insulating pattern 8, the process of patterning at least one conductive layer (12a, 12b, 12c) for forming the bit line BL can be performed defect-free. For example, since at least one conductive layer (12a, 12b, 12c) does not completely fill the recessed region 7 but only partially fills it, at least one conductive layer (12a, 12b, 12c) located in the recessed region 7 can be patterned defect-free. Because the first active portion AF1 may be formed in a shape protruding from the bottom surface of the recessed region 7, the bit line BL can be formed defect-free.

[0117] refer to Figure 1A , Figure 1B , Figure 7 and Figure 15 The insulating pattern not covered by the bit line BL can be removed by etching. Figure 14 The insulating pattern 8). Therefore, the insulating pattern can be removed ( Figure 14 The insulation pattern 8), and the insulation pattern covered by the bit line BL can be retained ( Figure 13 Insulation pattern 8).

[0118] In order to remove the insulating pattern ( Figure 14 While increasing the separation distance between the second source / drain region SD2 in the second active portion AF2 and the first source / drain region SD1 in the first active portion AF1 by increasing the insulating pattern 8), a portion of the first active portion AF1 can be etched. Therefore, the first active portion AF1 may include a protruding region P1 that protrudes from the isolation region STI and has a lower region with a width greater than the upper region.

[0119] refer to Figure 1A , Figure 1B , Figure 7 and Figure 16 To further increase the separation distance between the second source / drain region SD2 in the second active portion AF2 and the first source / drain region SD1 in the first active portion AF1 while removing the first conductive layer 12a that is not located below the bit line BL and remains in the recessed region 7, a portion of the first active portion AF1 can be etched. Therefore, it is possible to form a structure as described above. Figure 2A and Figure 2B The first area (like the one in the middle) Figure 2B First region AP1) and second region ( Figure 2BThe first active part AF1 of the second region AP2).

[0120] In one or more embodiments, to prevent the first conductive layer 12a from remaining in the region where the bit line BL is not formed while the first active portion AF1 is being formed, it can be done as follows: Figure 6A and Figure 6B The first conductive layer 12a is thus over-etched to form the first conductive layer. Figure 6A and Figure 6B Layer 12aa).

[0121] In one or more embodiments, by controlling the etching process that etches a portion of the first active portion AF1, it is also possible to... Figure 5A and Figure 5B Similarly, a second region is formed, the width of which is greater than the width of the upper region. Figure 5B The first active part AF1 of the second region AP2b in the middle.

[0122] refer to Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 3 and Figure 7An insulating spacer structure SP can be formed (S40). Forming the insulating spacer structure SP may include forming an inner spacer 30, forming a plug spacer 36, forming an intermediate spacer 42, and forming an outer spacer 45. The inner spacer 30 may conformally cover the inner wall of the recessed region 7, and conformally cover the buffer insulating structure 6 not covered by the bit line BL, the side surface of the bit line BL, and the side surface of the bit line capping pattern BC. The plug spacer 36 may be formed to fill the recessed region 7 on the inner spacer 30. The plug spacer 36 may include a spacer pattern 36b and a spacer liner 36a covering the side and lower surfaces of the spacer pattern 36b. The intermediate spacer 42 and the outer spacer 45 may be sequentially formed on the line portion LP of the bit line BL and the side surface of the bit line capping pattern BC. An insulating barrier IF may be formed. The insulating barrier IF may be formed to partially penetrate the bit line capping pattern BC and extend between the bit lines BL. A contact structure CNT (S50) may be formed. A first material layer is formed between bit line structures BL and BC, including bit line BL and bit line capping pattern BC. An insulating barrier IF is formed to separate the first material layers from each other in the X direction. The separated first material layers are partially etched to form a lower conductive layer 55. An upper spacer 58 is formed on the side surface of the empty space above the lower conductive layer 55. A siliconization process is performed to form an intermediate conductive layer 61 on the lower conductive layer 55, an upper conductive layer 64 on the intermediate conductive layer 61, and a pad pattern 75p on the upper conductive layer 64. An insulating isolation pattern 78 can be formed between the pad patterns 75p of the contact structure CNT, and an etch stop layer 85 can be formed on the pad patterns 75p and the insulating isolation pattern 78. A data storage structure DS (S60) can be formed. The data storage structure DS may include a first electrode 88 that penetrates the etch stop layer 85 and is electrically connected to the pad patterns 75p of the contact structure CNT, a dielectric layer 90 covering the first electrode 88 and the etch stop layer 85, and a second electrode 92 on the dielectric layer 90.

[0123] In one or more embodiments, since the first active portion AF1 can be formed to protrude from the bottom surface of the recessed region 7, for example, a second region can be formed ( Figure 2B The first active portion AF1 of the second region AP2 can form the bit line BL without defects.

[0124] In one or more embodiments, although as Figure 15 and Figure 16 The process is performed in the same manner to increase the separation distance between the second source / drain region SD2 in the second active portion AF2 and the first source / drain region SD1 in the first active portion AF1, but at least one conductive layer in the region where the bit line BL is not formed can be completely removed. Figure 12Layers 12a, 12b, and 12c in the middle ensure that no portion is retained. Therefore, after the bit line BL is formed, it is possible to prevent at least one conductive layer (retained in the region where the bit line BL is not formed) from being retained. Figure 12 Defects caused by the conductive material of layers 12a, 12b, and 12c.

[0125] In one or more embodiments, by increasing the separation distance between the second source / drain region SD2 in the second active portion AF2 and the first source / drain region SD1 in the first active portion AF1, leakage current between the second source / drain region SD2 in the second active portion AF2 and the first source / drain region SD1 in the first active portion AF1 can be prevented, and parasitic capacitance between the second source / drain region SD2 in the second active portion AF2 and the first source / drain region SD1 in the first active portion AF1 can be reduced, thereby improving the performance of the semiconductor device.

[0126] As described above, according to one or more embodiments, a semiconductor device may be provided, including an active portion and a bit line. The active portion includes a first region having a side surface in contact with an isolation region and a second region extending upward from the first region and spaced apart from the isolation region. The bit line includes a contact portion connected to the second region of the active portion.

[0127] In one or more embodiments, by forming an active portion including a second region protruding from the isolation region, defects that occur during the patterning process used to form bit lines can be prevented.

[0128] In one or more embodiments, by forming the upper surface of the active portion into an upwardly convex shape, the contact area between the active portion and the bit line contact portion can be increased. Therefore, since the resistance between the source / drain region formed in the active portion and the bit line can be reduced, the performance of the semiconductor device can be improved.

[0129] Even by reducing the size of the active portion and bit lines, the integration density of semiconductor devices can be improved because active portions and bit lines can be provided to prevent defects and improve performance, as described above.

[0130] The various aspects and features of this disclosure are not limited to those described above, and can be more readily understood through the description of specific embodiments thereof.

[0131] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A semiconductor device, comprising: First active part; The isolation region on the side surface of the first active portion; and Bit lines connected to the first active portion The first active portion includes a first region in contact with the isolation region and a second region extending upward from the first region, wherein the second region is spaced apart from the isolation region. The bit lines include: The line portion extends in the first horizontal direction; and A contact portion located below the line portion, wherein the contact portion is connected to the second region of the first active portion.

2. The semiconductor device according to claim 1, further comprising: Insulating spacer structures including contact spacers and line spacers, The contact spacer is located on the side surface of the second region of the first active portion and on the side surface of the contact portion. The line spacers are located on the side surface of the line portion.

3. The semiconductor device according to claim 2, wherein, The width of the contact spacer is greater than the width of the line spacer.

4. The semiconductor device according to claim 2, in, The isolation region contacts the side surface of the first region of the first active portion, and The contact spacer is in contact with the side surface of the second region of the first active portion and the side surface of the contact portion.

5. The semiconductor device according to claim 1, wherein, The contact portion extends from the line portion.

6. The semiconductor device according to claim 1, in, The line portion includes a first conductive layer, a second conductive layer, and a third conductive layer. The first conductive layer, the second conductive layer, and the third conductive layer are stacked sequentially. Wherein, the contact portion extends from the first conductive layer of the line portion, and The first conductive layer comprises doped polycrystalline silicon.

7. The semiconductor device according to claim 1, wherein, The side surface of the first active portion has a curved portion between the side surface of the first region and the side surface of the second region.

8. The semiconductor device according to claim 2, further comprising: The second active portion is adjacent to the first active portion and spaced apart from the first active portion by the isolation region. Wherein, the upper surface of the second active portion is at a first height level. Wherein, the upper surface of the second region of the first active portion is at the second height level. Wherein, the region between the side surface of the first region of the first active portion and the side surface of the second region of the first active portion is at a third height level, and The second height level is at a lower level than the first height level.

9. The semiconductor device according to claim 8, in, The isolation region is located between the first region of the first active portion and the second active portion, and The isolation area extends from the portion between the first region of the first active portion and the second active portion to the point between the contact spacer and the second active portion.

10. The semiconductor device according to claim 8, wherein, In the first active portion, the vertical thickness of the second region is greater than the width of the second region.

11. The semiconductor device according to claim 8, further comprising: Contact structure on the second active portion; and The data storage structure on the contact structure, The lower surface of the contact structure is at a higher level than the upper surface of the first active portion.

12. A semiconductor device, comprising: First active part; A second active portion adjacent to the first active portion; The isolation region between the first active portion and the second active portion; Bit lines connected to the first active portion; A contact structure connected to the second active portion; and Data storage structure connected to the contact structure. The first active portion includes an upper surface. Wherein, the upper surface of the first active portion bulges upward, and The bit lines include: The contact portion that contacts the upper surface of the first active portion; and The line portion on the contact portion extends along a first horizontal direction.

13. The semiconductor device according to claim 12, wherein, The contact portion extends from the line portion.

14. The semiconductor device according to claim 12, further comprising: Insulating spacers The first active portion includes a first region that contacts the isolation region and a second region that is spaced apart from the isolation region and contacts the insulating spacer. The insulating spacer includes: A contact spacer located on the side surface of the second region of the first active portion and on the side surface of the contact portion; and Line spacers located on the side surface of the line portion. Wherein, the upper surface of the second active portion is at a higher level than the upper surface of the first active portion, and The isolation area also includes the portion between the contact spacer and the second active portion.

15. A semiconductor device, comprising: Active region; The isolation area between the active areas; A gate structure extending across the active region and into the isolation region; and Bit lines connected to the active region Each of the active regions includes a first active portion and a second active portion. In this context, the first active portion and the second active portion of each corresponding active region in the active region are spaced apart from each other by gate structures that intersect with the corresponding active regions in the gate structure. The active region includes a first active region. The bit line includes a first bit line connected to the first active portion of the first active region. The first active portion of the first active region includes: A first region, comprising a side surface in contact with the isolated region; and A second region extending upward from the first region, the second region being spaced apart from the isolation region, and The first bit line includes: The line portion extending in the first horizontal direction; and The contact portion is located below the line portion and is connected to the second region of the first active portion.

16. The semiconductor device according to claim 15, wherein, Each of the gate structures includes: Gate electrode; The gate capping pattern on the gate electrode; and Gate dielectric layers on the side and bottom surfaces of the gate electrode.

17. The semiconductor device of claim 16, further comprising: Insulating pattern, The gate structure includes a first gate structure. The first gate structure intersects with the first active region and is adjacent to the first active portion of the first active region. Wherein, the insulating pattern is located between the gate capping pattern of the first gate structure and the second region of the first active portion of the first active region, and The contact portion of the first bit line includes a portion that contacts the upper surface of the second region of the first active portion of the first active region and a portion that contacts the upper surface of the insulating pattern.

18. The semiconductor device according to claim 15, wherein, The contact portion extends from the line portion.

19. The semiconductor device of claim 15, further comprising: Insulating spacer, the insulating spacer comprising: Contact spacers on the side surface of the second region of the first active portion of the first active region and on the side surface of the contact portion; and Line spacers on the side surface of the line portion.

20. The semiconductor device according to claim 15, wherein, The side surface of the first active portion of the first active region has a curved portion between the side surface of the first region of the first active portion of the first active region and the side surface of the second region of the first active portion of the first active region.

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