Preparation method of semiconductor device and semiconductor process equipment

Abstract

The invention provides a preparation method of a semiconductor device and semiconductor process equipment, and belongs to the technical field of semiconductors, the preparation method of the semiconductor device comprises the steps that a stacking structure is formed, and the stacking structure comprises at least one functional layer and at least one sacrificial layer which are alternately stacked; transversely etching the sacrificial layer along the side wall of the stacked structure so as to expose a part of width of the functional layer; an oxidation step, a first etching step and a second etching step are circularly executed to thin the exposed width part of the functional layer, the oxidation step comprises oxidizing the exposed surface of the functional layer to generate an oxidation layer, the first etching step comprises removing the oxidation layer and stopping on the surface of the functional layer, and the second etching step comprises etching the exposed width part of the functional layer. According to the invention, the thinning efficiency of the functional layer can be improved, the surface state of the thinned functional layer is better, the thickness of the thinned exposed width part of each functional layer is relatively consistent, the parameter drift of the device is reduced, and the stability and yield of the device are improved.

Description

Semiconductor device fabrication methods and semiconductor process equipment Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a method for fabricating a semiconductor device and semiconductor process equipment. Background Technology

[0002] With the rapid development of applications in the field of Artificial Intelligence (AI), the demand for high-performance memory continues to rise. Dynamic Random Access Memory (DRAM) technology has gradually entered a bottleneck period. How to improve the storage capacity per unit area of ​​DRAM has become a key development direction for the next generation of DRAM.

[0003] Three-dimensional dynamic random access memory (3D DRAM) is an advanced DRAM technology with a novel memory cell structure that allows for the stacking of multiple memory layers and the use of vertical interconnect technology to increase memory density and performance. Unlike traditional DRAM with horizontally placed memory cells, the fabrication process of 3D DRAM requires the formation of a stacked structure. After selective lateral etching of the sacrificial layer in the stacked structure, a portion of the width of the functional layers in the stacked structure is exposed. Subsequently, the exposed width of the functional layers needs to be thinned to provide more processing space for the wordline process.

[0004] The prior art CN118969619A describes a method of alternating surface modification and modified layer etching to thin the channel layer. During the modified layer etching, one or more of the following mixed gases are selected from NF3, NH3, CF4, F2, ClF3 and He under remote plasma source ionization. However, this thinning method cannot simultaneously consider efficiency, process simplification, and the surface condition of the channel layer after thinning. For example, when etching the modified layer, a mixed gas of NF3, NH3, and He under remote plasma source ionization is used. This process first utilizes NF3 and NH3 to react and generate fluorides (ammonium fluoride and ammonium difluoride), which are then condensed on the surface of the modified layer. The modified layer then reacts with the fluorides to generate easily sublimable ammonium hexafluorosilicate, which is then sublimated by radiation heating. This process is very complex and requires heating and cooling, resulting in low etching efficiency. Furthermore, it relies solely on surface modification to thin the channel layer, leading to low thinning efficiency. Another example is when etching the modified layer using a mixed gas of CF4, F2, and He under remote plasma source ionization. This process cannot stop at the surface of the channel layer during etching of the modified layer, resulting in a poor surface condition and high roughness after the channel layer is thinned. Summary of the Invention

[0005] In view of this, the embodiments of this application aim to provide a method for fabricating a semiconductor device and semiconductor process equipment to solve the problem in the prior art that thinning the functional layer cannot simultaneously achieve efficiency, process simplification, and surface state after thinning the functional layer.

[0006] This application provides a method for fabricating a semiconductor device, comprising: forming a stacked structure, the stacked structure including at least one functional layer and at least one sacrificial layer alternately stacked; laterally etching the sacrificial layer along the sidewall of the stacked structure to expose a portion of the width of the functional layer; and cyclically performing an oxidation step, a first etching step, and a second etching step to thin the exposed width of the functional layer, the oxidation step including oxidizing the exposed surface of the functional layer to form an oxide layer, the first etching step including removing the oxide layer and stopping at the surface of the functional layer, and the second etching step including etching the exposed width of the functional layer.

[0007] In some embodiments, the time of the oxidation step is greater than or equal to the time of the second etching step within each cycle.

[0008] In some embodiments, the first etching step further includes etching away byproducts on the surface of the functional layer.

[0009] In some embodiments, the process gas for the first etching step includes hydrogen fluoride gas.

[0010] In some embodiments, after each of at least one of the first etching steps, the inner wall of the process chamber is treated with hydrogen-containing gas and oxygen-containing gas.

[0011] In some embodiments, the process gas for the second etching step includes an oxygen-containing gas and a fluorine-containing gas, wherein the flow rate ratio of the oxygen-containing gas to the fluorine-containing gas is 2 to 20.

[0012] In some embodiments, when performing the oxidation step, the vacuum level of the process chamber is 0.5 Torr to 2 Torr, the total flow rate of the process gas is 200 sccm to 2000 sccm, the radio frequency source is a microwave source with a power of 200W to 900W, the temperature of the wafer carrier module is 40℃ to 300℃, and the process time is 30s to 100s.

[0013] In some embodiments, when performing the second etching step, the vacuum level of the process chamber is 0 Torr to 20 Torr, the total flow rate of the process gas is 100 sccm to 500 sccm, the radio frequency source is a microwave source with a power of 200W to 1500W, the temperature of the wafer carrier module is 150°C to 250°C, and the process time is less than 30s.

[0014] In some embodiments, when performing the first etching step, the pressure in the process chamber is 10 Torr to 50 Torr, and the temperature of the wafer carrier module is 10°C to 300°C.

[0015] This application also provides a semiconductor process apparatus, including: a process chamber, an air intake assembly, an air extraction assembly, and a controller. The controller includes at least one processor and at least one memory, the memory storing a computer program. When the computer program is executed by the processor, it implements the method for fabricating the semiconductor device.

[0016] This application provides a method for fabricating a semiconductor device and a semiconductor process apparatus. The method for fabricating the semiconductor device includes forming a stacked structure, the stacked structure including at least one functional layer and at least one sacrificial layer alternately stacked; laterally etching the sacrificial layer along the sidewall of the stacked structure to expose a portion of the width of the functional layer; cyclically performing an oxidation step, a first etching step, and a second etching step to thin the exposed width of the functional layer, the oxidation step including oxidizing the exposed surface of the functional layer to form an oxide layer, the first etching step including removing the oxide layer and stopping at the surface of the functional layer, and the second etching step including etching the exposed width of the functional layer. The oxidation step described in this application can oxidize the exposed surface of the functional layer, thereby reducing the surface roughness of the functional layer and uniformly consuming the thickness of the functional layer. The first etching step can remove the oxide layer generated on the exposed surface of the functional layer, thereby making the exposed surface of the functional layer smoother. Then, the second etching step is used to etch the functional layer, improving the thinning efficiency. At the same time, since the exposed surface of the functional layer is smoother, the etching can be more uniform and flat. After thinning the width portion of the exposed functional layer, the surface condition of the exposed functional layer is better, and the thickness of each exposed width portion of the functional layer after thinning is also more consistent, thereby reducing the parameter drift of the device and improving the stability and yield of the device. Attached Figure Description

[0017] Figure 1 is a flowchart of the method for fabricating a semiconductor device provided in an embodiment of this application.

[0018] Figure 2 is a schematic diagram of a structure in which at least one functional layer and at least one sacrificial layer are formed on a substrate according to an embodiment of this application.

[0019] Figure 3 is a schematic diagram of a stacked structure formed by an etched sacrificial layer and a functional layer according to an embodiment of this application.

[0020] Figure 4 is a schematic diagram of a structure in which a sacrificial layer is etched laterally along the sidewall of a stacked structure according to an embodiment of this application.

[0021] Figure 5 is an electron microscope image of a local area in Figure 4.

[0022] Figure 6 is a schematic diagram of the structure of generating an oxide layer by oxidizing the exposed surface of the functional layer according to an embodiment of this application.

[0023] Figure 7 is an electron microscope image of a local area in Figure 6.

[0024] Figure 8 is an electron microscope image of a local area in Figure 6 when the total flow rate of the process gas is too small during the oxidation step in an embodiment of this application.

[0025] Figure 9 is a schematic diagram of the structure for etching to remove the oxide layer according to an embodiment of this application.

[0026] Figure 10 is an electron microscope image of a local area in Figure 9.

[0027] Figure 11 is an electron microscope image of a local area in Figure 9 when the proportion of oxygen-containing gas in the process gas is too low during the second etching step provided in an embodiment of this application.

[0028] Figure 12 is an electron microscope image of a local area in Figure 9 when the temperature of the wafer carrier module is too low during the execution of the second etching step according to an embodiment of this application.

[0029] Figure 13 is a schematic diagram of the structure after thinning the exposed width portion of the functional layer according to an embodiment of this application.

[0030] Figure 14 is an electron microscope image of a local area in Figure 9.

[0031] Figure 15 is a schematic diagram of the structure of a semiconductor process equipment provided in an embodiment of this application.

[0032] The reference numerals in the attached figures are as follows: 100-substrate; 200-stacked structure; 201-sacrificial layer; 202-functional layer; 300-mask layer; 400-isolation trench; 500-extension trench; 600-oxide layer; 20-process chamber; 20A-inlet assembly; 20B-remote plasma source; 20C-vacuum assembly; 21-uniform disk; 22-wafer carrier module. Detailed Implementation

[0033] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0034] This application provides a method for fabricating a semiconductor device, which can be a DRAM, 3DDRAM, or a capacitor structure, a GAA (gate-all-around) device, etc. Figure 1 is a flowchart of a method for fabricating a semiconductor device according to an embodiment of this application. As shown in Figure 1, the method for fabricating a semiconductor device includes: step S100: forming a stacked structure, the stacked structure including at least one functional layer and at least one sacrificial layer alternately stacked; step S200: laterally etching the sacrificial layer along the sidewall of the stacked structure to expose a portion of the width of the functional layer; and step S200: cyclically performing an oxidation step, a first etching step, and a second etching step to thin the exposed width of the functional layer, wherein the oxidation step includes oxidizing the exposed surface of the functional layer to generate an oxide layer, the first etching step includes removing the oxide layer and stopping at the surface of the functional layer, and the second etching step includes etching the exposed width of the functional layer.

[0035] Figures 2 to 14 are schematic diagrams of the corresponding steps of the semiconductor device fabrication method provided in one embodiment of this application. Next, the semiconductor device fabrication method provided in this application will be described in detail with reference to Figures 2 to 14.

[0036] As shown in Figure 2, in step S100, a substrate 100 is provided. The material of the substrate 100 can be silicon (Si), germanium (Ge), silicon-germanium (GeSi), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide (GaAs), silicon carbide (SiC), gallium nitride (GaN), indium phosphide (InP), zinc sulfide (ZnS), cadmium sulfide (CdS), or cadmium telluride (CdTe), etc., or it can be an organic semiconductor material or other semiconductor materials known in the art. Device structures such as doped regions, trench isolation structures, and embedded epitaxial layers can also be formed on and / or within the substrate 100, which will not be explained in detail here.

[0037] Referring to Figure 2, at least one functional layer 202 and at least one sacrificial layer 201 are formed on the substrate 100. The sacrificial layer 201 and the functional layer 202 can be stacked alternately from bottom to top. Figure 2 exemplarily shows 8 sacrificial layers 201 and 8 functional layers 202, but this is not a limitation. The sacrificial layer 201 and the functional layer 202 can also be less than 8 layers or more than 8 layers, for example, 1 layer, 5 layers, 10 layers, 20 layers, 50 layers, and 100 layers. In some embodiments, to meet thickness requirements, the sacrificial layer 201 and the functional layer 202 can be greater than or equal to 20 layers. The formation process of the sacrificial layer 201 and the functional layer 202 includes, but is not limited to, epitaxial growth processes, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0038] In some embodiments, the thicknesses of the sacrificial layer 201 and the functional layer 202 may be equal or unequal, which does not affect the implementation of this application. The thicknesses of the sacrificial layer 201 and the functional layer 202 can be designed according to actual needs.

[0039] In some embodiments, the sacrificial layer 201 and the functional layer 202 are made of different materials, and both are preferably made of materials with a high etch selectivity, thereby enabling selective lateral etching processes. For example, one of the sacrificial layer 201 and the functional layer 202 can be made of silicon, and the other can be made of germanium-silicon, but this is not a limitation; other materials with a high etch selectivity can also be used for the sacrificial layer 201 and the functional layer 202. In Figure 2, the sacrificial layer 201 is made of silicon, and the functional layer 202 is made of germanium-silicon. In this way, the functional layer 202 can be selectively and directionally grown epitaxially on the surface of the sacrificial layer 201, and the process flow is simple and controllable.

[0040] Please continue referring to Figure 2. A mask layer 300 is formed on the topmost functional layer 202. The mask layer 300 can act as a mask in subsequent etching processes to protect the areas of the sacrificial layer 201 and the functional layer 202 that do not need to be etched. In some embodiments, the mask layer 300 can be a single-layer or stacked structure made of materials such as silicon nitride, silicon oxide, silicon oxynitride, and silicon oxycarbide.

[0041] As shown in Figure 3, a pattern is first formed on the mask layer 300 using photolithography and etching processes. Then, the patterned mask layer 300 is used as a sacrificial layer 201 and a functional layer 202 formed by alternating mask etching to form at least one isolation trench 400. The isolation trench 400 can penetrate all sacrificial layers 201 and all functional layers 202, thereby forming multiple stacked structures 200. Adjacent stacked structures 200 are separated by the isolation trench 400.

[0042] In some embodiments, when etching the functional layer 202 and the sacrificial layer 201, a portion of the depth of the substrate 100 may also be etched, so that the isolation trench 400 extends into the substrate 100. Subsequently, the portion of the isolation trench 400 located in the substrate 100 may be filled with isolation material to form a trench isolation structure.

[0043] Furthermore, as mentioned above, the number of sacrificial layers 201 and functional layers 202 may be relatively large, resulting in a large aspect ratio of the isolation trench 400. For example, the aspect ratio of the isolation trench 400 may be greater than or equal to 50, which drastically increases the etching difficulty. In order to achieve a better morphology for the sidewalls of the isolation trench 400, in some embodiments, the Bosch process can be used to etch alternating sacrificial layers 201 and functional layers 202. The core of the Bosch process is to achieve etching and edge passivation by alternating the etching gas and passivation gas. The passivation gas deposits a polymer on the sidewalls to suppress lateral etching, while ion bombardment maintains continuous vertical etching, thereby achieving a high aspect ratio vertical etching structure. After etching, an isolation trench 400 with nearly vertical sidewalls can be formed.

[0044] Furthermore, during the etching of the alternating sacrificial layer 201 and functional layer 202 using the Bosch process, polymers form on the inner walls of the isolation trench 400. These polymers can adversely affect subsequent lateral etching processes. Therefore, after forming the stacked structure 200, the semiconductor structure in Figure 3 is typically wet-cleaned using a cleaning agent to remove the polymers from the sidewalls of the stacked structure 200. However, the acidic components in the cleaning agent may break the chemical bonds on the sidewalls of the stacked structure 200 while removing the polymers, leading to bond breakage. Simultaneously, the polymers are difficult to remove completely, potentially leaving impurity particles on the sidewalls of the stacked structure 200, which can affect subsequent lateral etching processes. These impurity particles typically contain carbon, nitrogen, and oxygen.

[0045] Based on this, after etching the stacked structure 200 to form the isolation trench 400, the sidewalls of the stacked structure 200 can be surface-treated using the free radicals of the processing gas. The free radicals of the processing gas can generate gas by breaking bonds on the sidewalls of the stacked structure 200, thereby removing the broken bonds on the sidewalls of the stacked structure 200. At the same time, the free radicals of the processing gas can also react with impurity particles on the sidewalls of the stacked structure 200 to generate gas, thereby removing the impurity particles on the sidewalls of the stacked structure 200.

[0046] Furthermore, the processing gas can be an inert gas or a gas that does not react with the sacrificial layer 201 and the functional layer 202, thereby avoiding damage to the sacrificial layer 201 and the functional layer 202 by surface treatment of the sidewalls of the stacked structure 200. In some embodiments, the processing gas includes at least one of hydrogen, nitrogen, and oxygen. For example, the processing gas may include at least one of hydrogen, nitrogen, oxygen, argon, helium, neon, ammonia, nitric oxide, and water vapor. The processing gas may also carry free radicals of the processing gas. Taking hydrogen as an example, the reaction energy of hydrogen free radicals (hydrogen free radical H·) is about 2.26 eV, which is much greater than the bond energy of various Si-Ge bonds (about 0.61 eV). When hydrogen free radicals come into contact with the sidewalls of the stacked structure 200, their unpaired electrons attract the broken bonds or impurity particles on the sidewalls of the stacked structure 200, causing a layer of hydrogen free radicals to be adsorbed on the sidewalls of the stacked structure 200. Then, relying on the reaction energy, covalent bonds are generated, forming a gas that is carried away.

[0047] It should be noted that free radicals mainly participate in the reaction through the activity of unpaired electrons, and their energy comes from the activity energy. Free radicals themselves have a high energy state, making them prone to adsorbing broken bonds or impurity particles on the sidewalls of the stacked structure 200. Furthermore, the energy adsorption is relatively strong and not easily dissociated. Utilizing their high reactivity, they can effectively remove broken bonds or impurity particles from the sidewalls of the stacked structure 200, ensuring that the sidewalls of the stacked structure 200 are in a relatively clean state. Compared to directly using the processing gas to surface-treat the sidewalls of the stacked structure 200, using the free radicals of the processing gas to surface-treat the sidewalls of the stacked structure 200 is more effective.

[0048] As shown in Figures 4 and 5, in step S200, the sacrificial layer 201 is etched laterally along the sidewall of the stacked structure 200 to form at least one extension groove 500. The extension groove 500 connects to the isolation trench 400 and extends laterally. The extension groove 500 is generated by etching the sacrificial layer 201. Therefore, from a planar perspective, the extension groove 500 surrounds the isolation trench 400. Each sacrificial layer 201 corresponds to a row of extension grooves 500. In Figure 4, the eight rows of extension grooves 500 are arranged at intervals in the thickness direction of the stacked structure 200. A functional layer 202 is spaced between two adjacent rows of extension grooves 500. Therefore, the extension trench 500 exposes part of the width of the functional layer 202. As can be seen from Figure 4, the depth of the extension trench 500 is D, and the width of the exposed part at the end of the functional layer 202 is also D. When the semiconductor device is a 3D DRAM, the exposed width of the functional layer 202 will serve as the channel of the transistor. The length of the capacitor and the transistor in the memory cell can be precisely defined by laterally etching the sacrificial layer 201.

[0049] It should be noted that if there are two or more isolation trenches 400, when the sacrificial layer 201 is etched laterally along the sidewall of the stacked structure 200, the sacrificial layer 201 between two adjacent isolation trenches 400 is not completely removed. After the lateral etching is completed, the two adjacent isolation trenches 400 are not connected and remain isolated from each other.

[0050] In some embodiments, a fluorine-containing gas can be used to laterally etch the sacrificial layer 201 along the sidewalls of the stacked structure 200. Taking the sacrificial layer 201 as a germanium-silicon material and the functional layer 202 as a silicon material as an example, the etching rate of the fluorine-containing gas on germanium-silicon can reach 4000 nm / min, while the etching rate on silicon is only 40 nm / min, resulting in a selectivity ratio as high as 100:1. It can be considered that during the etching of the sacrificial layer 201, the functional layer 202 is basically not etched, thereby achieving the purpose of selective etching of the sacrificial layer 201 on the sidewalls of the stacked structure 200. The fluorine-containing gas can be CF4, NF3, SF6, XeF2, F2, C4F8, C3F6, CHF3, CH2F2, CH3F, etc., which will not be listed here.

[0051] As shown in Figures 6-11, step S300 is executed by cyclically performing the oxidation step, the first etching step, and the second etching step to thin the exposed width of the functional layer 202. When the semiconductor device is a 3D DRAM, subsequent processes will form part of the word lines within the extension trench 500. By thinning the exposed width of the functional layer 202, the longitudinal width H1 of the extension trench 500 can be increased, thereby increasing the space for forming word lines and helping to reduce the coupling between adjacent word lines.

[0052] Specifically, as shown in Figures 6 and 7, the oxidation step includes oxidizing the exposed surface of the functional layer 202 to generate an oxide layer 600. An oxidizing process gas can be introduced into the process chamber. The process gas enters the isolation trench 400 and the extension trench 500, contacting the exposed surface of the functional layer 202, thereby oxidizing the exposed surface of the functional layer 202 and generating an oxide layer 600 on the exposed surface of the functional layer 202. While oxidizing the exposed surface of the functional layer 202, the thickness of the exposed width portion of the functional layer 202 is reduced, thus achieving a preliminary uniform thinning of the exposed width portion of the functional layer 202. Simultaneously, oxidizing the surface of the functional layer 202 can also reduce the roughness and particle count of the exposed surface, resulting in a smoother and cleaner surface after the subsequent removal of the oxide layer 600, with a better surface condition, which is beneficial to the etching uniformity and smoothness of the subsequent first and second etching steps.

[0053] For example, the functional layer 202 can be made of silicon. An oxidizing process gas is used to oxidize the exposed surface of the silicon, thereby generating silicon oxide, which is the oxide layer 600. It is understood that when the sacrificial layer 201 is also made of an easily oxidizable material (such as germanium-silicon), the oxidation step will also oxidize the exposed surface of the sacrificial layer 201, resulting in the oxide layer 600 also being located on the exposed surface of the sacrificial layer 201. That is, the oxide layer 600 is formed conformally on the inner walls of the isolation trench 400 and the extension trench 500, but this does not affect the implementation of this application.

[0054] In some embodiments, the process gas for the oxidation step may include oxygen (O2), helium-oxygen (HeO2), H2O, N2O, NO2, NO, etc., with a wider range of applications. Of course, the process gas for the oxidation step may also include inert gases such as nitrogen (N2) and argon (Ar). Preferably, the process gas for the oxidation step may be a combination of oxygen, helium-oxygen, and nitrogen.

[0055] In some embodiments, the process gas in the oxidation step carries free radicals of the corresponding process gas. For example, when the process gas in the oxidation step is oxygen, oxygen also carries oxygen free radicals. As explained above, free radicals mainly participate in the reaction by relying on the activity of unpaired electrons, and the energy comes from the activity energy. The free radicals themselves have a high energy state, are easy to adsorb on the exposed surface of the functional layer 202, and the energy adsorption is relatively strong and not easy to dissociate. Taking advantage of the high reactivity, the exposed surface of the functional layer 202 can be oxidized well, ensuring that an oxide layer 600 of relatively uniform thickness is generated on the exposed surface of each functional layer 202. Compared with directly using the process gas to oxidize the exposed surface of the functional layer 202, using the free radicals carried in the process gas to oxidize the exposed surface of the functional layer 202 can more uniformly thin the width portion of the exposed functional layer 202, thereby ensuring that the thinning thickness of the width portion of the exposed functional layer 202 is uniform, and at the same time, it can also increase the deposition efficiency.

[0056] As shown in Figure 8, if the total flow rate of the process gas is too low during the oxidation step, resulting in insufficient process gas volume in the process chamber, the sacrificial layer 201 is easily etched laterally (as shown by the blue dashed box in Figure 8). Simultaneously, the exposed width of the functional layer 202 is also easily thinned unevenly (as shown by the red dashed box in Figure 8). Therefore, in some embodiments, the total flow rate of the process gas during the oxidation step can be 200 sccm to 2000 sccm, thereby avoiding the lateral etching of the sacrificial layer 201 while also increasing the uniformity of the thinned width of the exposed functional layer 202.

[0057] In some embodiments, when performing the oxidation step, the vacuum level of the process chamber can be 0.5 Torr to 2 Torr, the RF power supply can be a microwave source, the power of the RF power supply can be 200W to 900W, the temperature of the wafer carrier module can be 40°C to 300°C, and the process time can be 30s to 100s, but should not be limited thereto.

[0058] Specifically, as shown in Figures 9 and 10, the first etching step includes removing the oxide layer 600 and stopping at the surface of the functional layer 202. Process gas can be introduced into the process chamber, and the process gas enters the isolation trench 400 and the extension trench 500, contacts the oxide layer 600, thereby etching and removing the oxide layer 600 and stopping at the surface of the functional layer 202.

[0059] It should be noted that the process gas in the first etching step needs to consider the etching selectivity ratio between the functional layer 202 and the sacrificial layer 201, so that the etching stops on the surface of the functional layer 202 after etching the oxide layer 600. Simultaneously, the simplification and efficiency of the process must be considered, aiming to remove the oxide layer 600 as simply and quickly as possible. Furthermore, during the cyclic execution of the oxidation step, the first etching step, and the second etching step, some byproducts are usually generated. These byproducts can be polymers containing elements such as silicon, oxygen, and fluorine, with complex compositions. These byproducts may adhere to the surface of the oxide layer 600 or be mixed within it, creating self-limiting effects and hindering the second etching step. Therefore, the first etching step also needs to be able to remove the byproducts on the surface of the functional layer 202 to ensure that the second etching step can continue, avoiding limitations on the thinning thickness of the exposed width of the functional layer 202.

[0060] For example, the oxide layer 600 can be made of silicon oxide, and the process gas for the first etching step can be hydrogen fluoride (HF). The oxide layer 600 and byproducts are removed under high pressure using hydrogen fluoride. Firstly, hydrogen fluoride has a high etching selectivity for both silicon oxide and silicon, allowing it to stop at the surface of the functional layer 202 after removing the oxide layer 600. Furthermore, the process of removing the oxide layer 600 using hydrogen fluoride is relatively simple, requiring no heating or cooling, resulting in higher efficiency. Secondly, hydrogen fluoride can effectively remove byproducts without adversely affecting process continuity or material selectivity, and it does not produce particulate contamination. It also allows for precise control of the etching amount. Of course, the process gas for the first etching step can also include hydrogen, nitrogen, and argon, in addition to hydrogen fluoride; these will not be listed here.

[0061] In some embodiments, when performing the first etching step, the vacuum level of the process chamber can be 10 Torr to 50 Torr (to maintain a high-pressure environment), and the temperature of the wafer carrier module can be 10°C to 300°C, but should not be limited thereto.

[0062] Furthermore, since hydrogen fluoride gas adheres to the inner wall of the process chamber under high pressure, long-term accumulation of hydrogen fluoride gas can significantly impact the normal process. Therefore, every m times (m ≥ 1) of the first etching step, the inner wall of the process chamber can be treated with hydrogen-containing gas (such as hydrogen) and oxygen-containing gas (such as oxygen or helium-oxygen) to remove the adhering hydrogen fluoride, thus maintaining stability and cleanliness within the process chamber.

[0063] The value of m can be designed as needed. For example, m can be set to 1 so that the inner wall of the process chamber is processed after each first etching step, which can keep the process chamber stable and clean to the greatest extent. Of course, the inner wall of the process chamber can also be processed after the thinning process of a wafer is completed, which will not be elaborated on here.

[0064] Furthermore, the second etching step includes etching the exposed width portion of the functional layer 202. In some embodiments, the duration of the second etching step can be controlled to minimize the etching of an excessively thick functional layer 202 in each second etching step, thereby avoiding uneven etching. In some embodiments, the oxidation step time can be longer than the second etching step time within each cycle, allowing the oxidation step to effectively remove particles generated in the second etching step of the previous cycle and smooth the surface of the functional layer 202 again, ensuring that each second etching step is performed on a relatively smooth and clean surface, thus improving the uniformity and smoothness of the second etching step.

[0065] For example, the material of the functional layer 202 can be silicon, and the process gas of the second etching step can include fluorine-containing gases (such as CF4, NF3, SF6, XeF2, F2) and oxygen-containing gases (such as O2, NO or N2O), and can also include hydrogen-containing gases (such as H2) or inert gases such as nitrogen (N2) and argon (Ar).

[0066] In some embodiments, the process gas in the second etching step carries free radicals of the corresponding process gas. For example, when the process gas in the second etching step is a fluorine-containing gas, an oxygen-containing gas, or a hydrogen-containing gas, the process gas also carries free radicals of the fluorine-containing gas, the oxygen-containing gas, and the hydrogen-containing gas. As explained above, free radicals mainly participate in the reaction through the activity of unpaired electrons, and their energy comes from the activity energy. The free radicals themselves have a high energy state, making them easy to adsorb on the exposed surface of the functional layer 202. Moreover, the energy adsorption is relatively strong and not easily dissociated. Utilizing the advantage of high reactivity, the functional layer 202 can be etched better, ensuring the etching uniformity of the functional layer 202, while also increasing the etching efficiency.

[0067] As shown in Figure 11, during the second etching step, if the proportion of oxygen-containing gas in the process gas is too high, it will inhibit the etching reaction. If the proportion of oxygen-containing gas in the process gas is too low, it will easily lead to the sacrificial layer 201 being etched laterally (as shown by the blue dashed box in Figure 11), and it will also easily lead to uneven thinning of the exposed width portion of the functional layer 202 (as shown by the red dashed box in Figure 11). Therefore, in some embodiments, during the second etching step, the flow rate ratio of oxygen-containing gas to fluorine-containing gas can be 2~20, thereby ensuring the normal progress of the etching reaction while avoiding the lateral etching of the sacrificial layer 201, and also increasing the uniformity of the thinned width portion of the exposed width portion of the functional layer 202.

[0068] As shown in Figure 12, during the second etching step, if the temperature of the wafer carrier module is too low, the end region of the exposed width portion of the functional layer 202 may thin too quickly, leading to breakage of the end region of the exposed width portion of the functional layer 202 (as shown by the red dashed box in Figure 12). If the temperature of the wafer carrier module is too high, etching may be difficult to occur. Therefore, in some embodiments, the temperature of the wafer carrier module can be 150℃~250℃ during the second etching step, thereby ensuring the normal progress of the etching reaction and preventing the end region of the exposed width portion of the functional layer 202 from breaking due to excessive thinning.

[0069] In some embodiments, when performing the second etching step, the vacuum level of the process chamber can be 0 Torr to 20 Torr, the total flow rate of the process gas can be 100 sccm to 500 sccm, the RF power supply can be a microwave source, the power of the RF power supply can be 200W to 1500W, and the process time can be less than 30s, but should not be limited thereto.

[0070] As shown in Figures 13 and 14, each time the oxidation step, the first etching step, and the second etching step are executed, the exposed width portion of the functional layer 202 is thinned by a certain amount. The number of cycles is determined based on the required thinning thickness of the exposed width portion of the functional layer 202, thus completing the thinning of the exposed width portion of the functional layer 202. As can be seen from Figure 13, after the exposed width portion of the functional layer 202 is thinned, the thickness of the exposed width portion of the functional layer 202 is less than the thickness of the portion of the functional layer 202 enclosed by the sacrificial layer 201, and the longitudinal width of the extension groove 500 becomes wider (H2>H1). Furthermore, as shown in Figure 14, after thinning the exposed width portion of functional layer 202, the thickness of each exposed width portion of functional layer 202 is relatively consistent, indicating that this application can improve the thickness consistency of each exposed width portion of functional layer 202 after thinning. At the same time, since the exposed surface of functional layer 202 is relatively smooth, the etching can be more uniform and flat. After thinning the exposed width portion of functional layer 202, the exposed surface of functional layer 202 is smoother and in better condition, thereby reducing the parameter drift of the device and improving the stability and yield of the device. In addition, both the oxidation step and the second etching step can reduce the thickness of functional layer 202, with higher thinning efficiency.

[0071] In some embodiments, the exposed width of the functional layer 202 needs to be thinned by 20nm to 30nm. Assuming that performing one oxidation step, one first etching step and one second etching step can thin the functional layer 202 by 2nm to 3nm, then it is only necessary to cycle through the oxidation step, the first etching step and the second etching step 10 times to complete the thinning of the exposed width of the functional layer 202.

[0072] It should be noted that different processes will be carried out in this application when different semiconductor devices need to be manufactured, which will not be listed here.

[0073] Based on this, an embodiment of this application also provides a semiconductor process apparatus. Figure 15 is a schematic diagram of the structure of the semiconductor process apparatus provided in an embodiment of this application. As shown in Figure 15, the semiconductor process apparatus may include a process chamber 20, an inlet assembly 20A, an exhaust assembly 20C, a remote plasma source (RPS) 20B, and a controller (not shown in Figure 15). The inlet assembly 20A may include a gas channel that connects the remote plasma source 20B and the process chamber 20. An inlet valve (the black rectangular block on the gas channel in Figure 15) is provided on the gas channel. Exemplarily, the controller may be a host computer or a slave computer. The controller can introduce and evacuate gas into the process chamber 20 by controlling the opening and closing of the inlet valve of the inlet assembly 20A and the evacuation valve of the evacuation assembly 20C (the black rectangular block between the evacuation assembly 20C and the process chamber 20 in Figure 15). The controller can also control the inlet flow rate by controlling the opening degree of the inlet valve of the inlet assembly 20A and the exhaust flow rate by controlling the opening degree of the evacuation valve of the evacuation assembly 20C. Furthermore, the controller can control the evacuation of the process chamber 20 by controlling the evacuation assembly 20C, for example, by controlling the opening degree of the evacuation valve or the speed of the evacuation pump, thereby controlling the pressure inside the process chamber 20 and removing reaction byproducts.

[0074] Furthermore, the semiconductor process equipment may also include structures such as a flow equalization disk 21 and a wafer carrier module 22. A flow equalization space is formed between the flow equalization disk 21 and the top of the process chamber 20, which is used to uniformly flow the process gas into the process chamber 20. The wafer carrier module 22 is used to carry the wafer. The wafer carrier module 22 may be, for example, an electrostatic chuck, a mechanical chuck, or a vacuum adsorption chuck.

[0075] When process gas is introduced into the process chamber 20, including continuously introducing process gas into the process chamber 20 via a remote plasma source 20B, some of the process gas is ionized to generate free radicals. Compared to simply introducing process gas directly, the free radicals of the process gas have higher reactivity. Utilizing the free radicals of the process gas for deposition or etching can improve efficiency and uniformity. Of course, when process gas is introduced into the process chamber 20, the process gas may not be ionized, thus no free radicals are generated, and deposition or etching can be performed using a purely chemical etching process.

[0076] Furthermore, the controller includes at least one processor and at least one memory, the memory storing a computer program that, when executed by the processor, implements the above-described method for fabricating the semiconductor device.

[0077] In summary, this embodiment provides a method for fabricating a semiconductor device and a semiconductor process apparatus. The method for fabricating the semiconductor device includes forming a stacked structure 200, the stacked structure 200 including at least one functional layer 202 and at least one sacrificial layer 201 stacked alternately; laterally etching the sacrificial layer 201 along the sidewall of the stacked structure 200 to expose a portion of the width of the functional layer 202; and cyclically performing an oxidation step, a first etching step, and a second etching step to thin the exposed width of the functional layer 202. The oxidation step includes oxidizing the exposed surface of the functional layer 202 to generate an oxide layer 600, the first etching step includes removing the oxide layer 600 and stopping at the surface of the functional layer 202, and the second etching step includes etching the exposed width of the functional layer 202. The oxidation step in this application can oxidize the exposed surface of the functional layer 202 to reduce the surface roughness of the functional layer 202 and uniformly consume the thickness of the functional layer 202. The first etching step can remove the oxide layer 600 generated on the exposed surface of the functional layer 202, thereby making the exposed surface of the functional layer 202 smoother. Then, the second etching step is used to etch the functional layer 202 to improve the thinning efficiency. At the same time, since the exposed surface of the functional layer 202 is relatively smooth, the etching can be more uniform and flat. After thinning the width of the exposed portion of the functional layer 202, the surface condition of the exposed functional layer 202 is better, and the thickness of each exposed width portion of the functional layer 202 after thinning is also more consistent, thereby reducing the parameter drift of the device and improving the stability and yield of the device.

[0078] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section.

[0079] It should also be noted that although preferred embodiments have been disclosed above, these embodiments are not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application, or modify them into equivalent embodiments, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application, without departing from the content of the technical solutions of this application, shall still fall within the scope of protection of the technical solutions of this application.

[0080] It should also be understood that, unless otherwise specified or indicated, the terms “first,” “second,” “third,” etc., in the specification are used only to distinguish the various components, elements, and steps in the specification, and not to indicate the logical or sequential relationships between the various components, elements, and steps.

[0081] Furthermore, it should be recognized that the terminology described herein is used only to describe particular embodiments and is not intended to limit the scope of this application. It must be noted that the singular forms “a” and “an” as used herein include plural bases unless the context clearly indicates the opposite. For example, a reference to “a step” or “an apparatus” means a reference to one or more steps or apparatuses, and may include secondary steps and secondary apparatuses. All conjunctions used should be understood in the broadest sense. Also, the word “or” should be understood as having the definition of logical “or”, not logical “exclusive OR”, unless the context clearly indicates the opposite. Furthermore, implementations of the methods and / or devices in the embodiments of this application may include performing selected tasks manually, automatically, or in combination.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A stacked structure is formed, the stacked structure comprising at least one functional layer and at least one sacrificial layer stacked alternately; The sacrificial layer is etched laterally along the sidewall of the stacked structure to expose a portion of the width of the functional layer. In addition, an oxidation step, a first etching step, and a second etching step are performed cyclically to thin the exposed width portion of the functional layer. The oxidation step includes oxidizing the exposed surface of the functional layer to form an oxide layer. The first etching step includes removing the oxide layer and stopping on the surface of the functional layer. The second etching step includes etching the exposed width portion of the functional layer.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, Within each cycle, the time of the oxidation step is greater than or equal to the time of the second etching step.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that, The first etching step also includes etching away byproducts on the surface of the functional layer.

4. The method for fabricating a semiconductor device according to claim 1 or 3, characterized in that, The process gas for the first etching step includes hydrogen fluoride gas.

5. The method for fabricating a semiconductor device according to claim 4, characterized in that, After each of the first etching steps is performed at least once, the inner wall of the process chamber is treated with hydrogen-containing gas and oxygen-containing gas.

6. The method for fabricating a semiconductor device according to claim 1, characterized in that, The process gas for the second etching step includes an oxygen-containing gas and a fluorine-containing gas, wherein the flow rate ratio of the oxygen-containing gas to the fluorine-containing gas is 2 to 20.

7. The method for fabricating a semiconductor device according to claim 1, characterized in that, During the oxidation step, the vacuum level of the process chamber is 0.5 Torr to 2 Torr, the total flow rate of the process gas is 200 sccm to 2000 sccm, the radio frequency source is a microwave source with a power of 200W to 900W, the temperature of the wafer carrier module is 40℃ to 300℃, and the process time is 30s to 100s.

8. The method for fabricating a semiconductor device according to claim 1, characterized in that, When performing the second etching step, the vacuum level of the process chamber is 0 Torr~20 Torr, the total flow rate of the process gas is 100 sccm~500 sccm, the radio frequency source is a microwave source, and the power of the radio frequency source is 200W~1500W, the temperature of the wafer carrier module is 150℃~250℃, and the process time is less than 30s.

9. The method for fabricating a semiconductor device according to claim 1, characterized in that, When performing the first etching step, the pressure in the process chamber is 10 Torr~50 Torr, and the temperature of the wafer carrier module is 10℃~300℃.

10. A semiconductor process apparatus, characterized in that, include: The device includes a process chamber, an air intake assembly, an air extraction assembly, and a controller, wherein the controller includes at least one processor and at least one memory, the memory storing a computer program that, when executed by the processor, implements the method for fabricating a semiconductor device as described in any one of claims 1 to 9.

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