Low-loss IGBT (Insulated Gate Bipolar Translator) chip with compensation type floating P region and preparation method of low-loss IGBT chip

Abstract

The invention belongs to the field of power semiconductor devices, and particularly discloses a low-loss IGBT chip with a compensation type floating P region and a preparation method of the low-loss IGBT chip. According to the invention, the N-CS layer is formed in the floating P region, the N-CS layer forms a hole barrier when the device is conducted, the hole concentration of the emitter side is increased by the floating P region, electron injection of the emitter side is enhanced in order to maintain electric neutrality, and the on-state voltage drop can be effectively reduced. In the switching process, the N-CS layer and the floating P region are mutually depleted, the expansion time of a depletion layer is shortened, and the switching time of the device is shortened. The switching loss can be reduced while the low on-state voltage drop of the device is maintained, and the on-state voltage drop and the switching loss are effectively balanced. An N-type layer is introduced into a floating P region, and the original maximum electric field is reduced due to positive charges provided by N-CS, so that the reduction of the electric flux of the traditional floating P region, the reduction of a concentrated high electric field near a groove, the protection of a gate oxide layer at the bottom of the groove and the improvement of the blocking voltage of the device are facilitated.

Description

Low-loss IGBT chip with compensated floating P-region and its fabrication method Technical Field

[0001] This application belongs to the field of power semiconductor devices, and more specifically, relates to a low-loss IGBT chip with a compensated floating P-region and a method for fabricating the same. Background Technology

[0002] IGBTs are high-voltage, high-power devices widely used in new energy vehicles, photovoltaics, energy storage, rail transportation, and other fields. They combine the advantages of high frequency of MOSFETs and low on-state voltage drop of BJTs, and occupy a major market share in the power device field.

[0003] Existing IGBT chips struggle to balance high voltage withstand capability, low loss, and process feasibility. Specifically, this manifests in the following ways: (1) Low blocking voltage: Existing technologies introduce an N-CS layer between P-base and N-drift, which enhances the electric field concentration effect at the bottom of the CSTBT trench, leading to gate oxide breakdown or a decrease in breakdown voltage. Increased N-CS layer doping concentration also leads to a further decrease in blocking voltage. (2) High switching losses: Floating P-region structures and N-CS layer structures can effectively reduce the on-state voltage drop of the device. However, excessive carriers during the on-state cause a decrease in the device's switching speed, increasing the device's switching losses. (3) Complex manufacturing process: In order to solve the problem of reduced device voltage withstand capability caused by the N-CS layer and to balance the relationship between IGBT on-state voltage drop and turn-off losses, many new IGBT cell structures have shown good results, but their processes are complex and difficult to manufacture. Summary of the Invention

[0004] In view of the shortcomings of the prior art, the purpose of this application is to provide a low-loss IGBT chip with a compensated floating P-region and its fabrication method, aiming to solve the problem of the difficulty in balancing high voltage resistance, low loss and process feasibility in existing IGBT chips.

[0005] To achieve the above objectives, in a first aspect, this application provides a low-loss IGBT chip with a compensated floating P-region, the cell structure of which includes: a collector structure, a drift region structure, a trench gate structure, and an emitter structure. The emitter structure is located above the drift region structure and is composed of an emitter metal, an N+ emitter region, a P-type base region, a first N-type carrier storage layer, a floating P-region, a second N-type carrier storage layer, and a third N-type carrier storage layer. The emitter metal is located at the top of the emitter structure, the N+ emitter region is located above the P-type base region, the P-type base region is located above the first N-type carrier storage layer, and the first N-type carrier storage layer is located between the P-type base region and the drift region structure, forming a hole barrier. The floating P-region is located on the left and right sides of the trench gate structure and is symmetrically distributed. It is divided into upper and lower parts by the second and third N-type carrier storage layers, forming a three-layer structure of "upper floating P-region / N-CS layer / lower floating P-region".

[0006] Preferably, both the upper floating P-region and the lower floating P-region are doped with boron ions, and the N-CS layer is doped with phosphorus ions, and the doping concentration of the three-layer structure of "upper floating P-region / N-CS layer / lower floating P-region" decreases sequentially.

[0007] Preferably, the second N-type carrier storage layer and the third N-type carrier storage layer are located in the middle of the floating P region, with a depth not exceeding the depth of the trench gate structure and not extending to the bottom corner of the trench gate structure.

[0008] Preferably, the second N-type carrier storage layer and the third N-type carrier storage layer have the same depth and are symmetrically positioned.

[0009] Preferably, the depth of the floating P region is greater than the depth of the first N-type carrier storage layer.

[0010] Preferably, the depth of the floating P region is greater than the depth of the gate in the trench gate structure.

[0011] To achieve the above objectives, in a second aspect, this application provides a method for fabricating a low-loss IGBT chip with a compensated floating P-region as described in the first aspect, comprising: using an N-type substrate as the N-type drift region of the IGBT chip; implanting boron ions on the left and right sides of the trench location to form a floating P-region structure; implanting phosphorus ions in the upper region within the floating P-region structure to form an N-type carrier storage layer structure; globally implanting boron ions in the upper region within the N-type carrier storage layer structure to form a P-type base region structure; activating impurities through high-temperature annealing to form an embedded PN junction structure; fabricating a trench gate structure, wherein the trench gate structure divides the N-type carrier storage layer structure and the P-type base region structure into three parts respectively, resulting in two symmetrically distributed three-layer structures of "upper floating P-region / N-CS layer / lower floating P-region"; fabricating an emitter structure; and fabricating a collector structure.

[0012] Preferably, in the upper region within the floating P-region structure, two phosphorus ion implantations form a flat N-type carrier storage layer structure, wherein the first implantation is a local phosphorus ion implantation and the second is a global phosphorus ion implantation.

[0013] Overall, the above-described technical solutions conceived in this application have the following beneficial effects compared with the prior art: (1) This application proposes a low-loss IGBT chip with a compensated floating P-region. Unlike the traditional carrier storage trench gate bipolar transistor (CSTBT) where the N-CS layer is formed only under the P-type base region, this application forms an N-CS layer inside the floating P-region. Since the N-CS layer forms a hole barrier when the device is turned on, the floating P-region increases the hole concentration on the emitter side. In order to maintain electrical neutrality, the electron injection on the emitter side is enhanced, which can effectively reduce the on-state voltage drop. During the switching process, the N-CS layer and the floating P-region deplete each other, shortening the expansion time of the depletion layer and reducing the switching time of the device. While maintaining the low on-state voltage drop of the device, the switching loss can also be reduced, effectively balancing the on-state voltage drop and the switching loss.

[0014] (2) This application proposes a low-loss IGBT chip with a compensated floating P region. An N-type layer is introduced inside the floating P region. Since the positive charge provided by N-CS reduces the original maximum electric field, it is beneficial to reduce the current flux of the traditional floating P region, reduce the high electric field concentrated near the trench, protect the gate oxide layer at the bottom of the trench, and improve the blocking voltage of the device. Attached Figure Description

[0015] Figure 1 is a cross-sectional schematic diagram of the CSTBT cell structure provided by the prior art.

[0016] Figure 2 is a 3D schematic diagram of a low-loss IGBT chip with a compensated floating P-region provided in an embodiment of this application.

[0017] Figure 3 is a cross-sectional schematic diagram of a low-loss IGBT chip structure with a compensated floating P-region provided in an embodiment of this application.

[0018] Figure 4 is a schematic diagram of the fabrication process of the IGBT chip provided in the embodiment of this application. In Figure 4a, the substrate is N-type, the floating P region is formed by boron ion implantation, the N-CS layer is formed by phosphorus ion implantation, the P-base layer is formed by boron ion implantation, the trench etching, oxide growth and polysilicon filling are shown in Figure 4e, the N+ emitter region is formed by arsenic ion implantation, the front metallization is shown in Figure 4g, and the back process is shown in Figure 4h.

[0019] Figure 5 is a comparison chart of the output characteristics of the three structures provided in the embodiments of this application.

[0020] Figure 6 shows the electric field distribution diagrams when the three structures provided in the embodiments of this application are blocked. The left side corresponds to FD-IGBT (IGBT with floating P-region structure), the middle side corresponds to CSTBT (Carrier Stored Trench Bipolar Transistor), and the right side corresponds to the improved structure of this application.

[0021] Figure 7 is a comparison chart of the three structural turn-off characteristics provided in the application embodiments.

[0022] Figure 8 shows the hole current distribution when the three structures provided in the embodiments of this application are turned off. The left side corresponds to FD-IGBT, the middle side corresponds to CSTBT, and the right side corresponds to the improved structure of this application.

[0023] Figure 9 is a comparison chart of the three structural commissioning characteristics provided in the application embodiments. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0025] The embodiments of this application are described below with reference to the accompanying drawings.

[0026] As shown in Figure 1, the existing CSTBT cell structure includes: collector structure, drift region structure, trench gate structure and emitter structure.

[0027] The collector structure is located at the bottom and consists of a collector metal and a P-type collector region. The P-type collector region is located above the collector metal and is connected to the collector metal.

[0028] The drift region structure is located above the collector structure and consists of an N-type field cutoff layer (N-FS) and an N-type drift region (N-drift). The N-type field cutoff layer (N-FS) is located between the P-type collector region (P-collector) and the N-type drift region (N-drift) and is used to prevent the electric field from passing through, thus playing a protective role. The N-type drift region (N-drift) is located above the N-type field cutoff layer (N-FS) and is the main current transmission channel.

[0029] The emitter structure is located above the drift region structure and consists of an emitter metal, an N+ emitter region, a P-base region, an N-type carrier storage layer (N-CS), and a floating P region. The emitter metal is located at the top of the emitter structure and is used to collect current. The N+ emitter region is located above the P-base region and is used to emit electrons. The P-base region is located above the N-CS region and is used to form a conductive channel. The N-CS region is located between the P-base region and the N-drift region and is used to form a hole barrier to enhance the conductivity modulation effect of the device. The floating P regions are located on the left and right sides of the gate (G) and are symmetrically distributed.

[0030] The trench gate structure runs through the drift region structure and the emitter structure, and includes two gates (G). The gates (G) are located below the emitter metal and above the N-type drift region, and are used to control the switching of the device.

[0031] As shown in Figures 2 and 3, this application proposes a low-loss IGBT chip with a compensated floating P-region, whose cell structure also includes: a collector structure, a drift region structure, a trench gate structure, and an emitter structure. The improvement of this application lies in the floating P-region of the emitter structure.

[0032] The emitter structure is located above the drift region structure and consists of an emitter metal, an N+ emitter region, a P-base region, a first N-type carrier storage layer (N-CS), a floating P region, a second N-type carrier storage layer (N-CS), and a third N-type carrier storage layer (N-CS). The emitter metal is located at the top of the emitter structure and is used to collect current. The N+ emitter region is located above the P-base region and is used to emit electrons. The P-base region is located above the first N-type carrier storage layer (N-CS) and is used to form a conductive channel. The first N-type carrier storage layer (N-CS) is located between the P-base region and the N-drift region and forms a hole barrier to enhance the conductivity modulation effect of the device. The floating P region is located on the left and right sides of the gate (G) and is symmetrically distributed. It is divided into upper and lower parts by the second and third N-type carrier storage layers (N-CS) respectively, forming a three-layer structure of "upper floating P region / N-CS layer / lower floating P region".

[0033] On the one hand, in the on state, the floating P-region structure increases the hole concentration on the emitter side due to the hole barrier formed by the N-CS layer. To maintain electrical neutrality, the electron injection on the emitter side is enhanced, effectively reducing the on-state voltage drop. On the other hand, in the off state, the negative charge portion of the floating P-region is compensated by the positive charge provided by the embedded N-CS layer, reducing the current flux of the traditional floating P-region, reducing the electric field strength near the trench, protecting the gate oxide layer at the bottom of the trench, and improving the device's blocking voltage. At the same time, since the N-CS layer reduces the hole concentration in the floating P-region and reduces the overlap area between the gate and the high-potential region, this structure reduces the device's Miller capacitance, improves the device's switching speed, and significantly reduces the device's switching losses.

[0034] Preferably, both the upper and lower floating P-regions are doped with boron ions, and the N-CS layer is doped with phosphorus ions. The doping concentration of the three-layer structure of the upper floating P-region / N-CS layer / lower floating P-region decreases sequentially, ensuring that the N-CS layer can play a role in local charge compensation during blocking and can be quickly depleted during switching.

[0035] Preferably, the N-CS layer is located in the middle of the floating P region, with a depth not exceeding the depth of the trench gate structure and not extending to the bottom corner of the trench gate structure, to ensure that the electric field at the bottom of the trench is borne by the N-drift / upper floating P region LP, and to prevent the electric field near the gate oxide layer from concentrating under high voltage due to the N-CS layer.

[0036] Preferably, the second N-type carrier storage layer and the third N-type carrier storage layer have the same depth and are symmetrically positioned.

[0037] Preferably, the depth of the floating P-region is greater than the depth of the first N-type carrier storage layer, which increases the hole concentration on the emitter side, enhances electron injection on the emitter side, and reduces the on-state voltage drop.

[0038] Preferably, the depth of the floating P region is greater than the depth of the gate (G), thereby reducing the number of carriers in the branch region and increasing the number of carriers in the main region during the turn-on phase, thus reducing the on-state voltage drop. Figure 4 is a schematic diagram of the IGBT chip fabrication process. The method includes the following steps: Step 1. Epitaxial layer preparation. Specifically, an N-type substrate is used as the drift region of the IGBT chip, as shown in Figure 4a.

[0039] Step 2. Formation of the N-CS layer and the upper and lower floating P regions.

[0040] 2.1. Forming a floating P-region: Specifically, boron ions are injected on both sides of the trench gate to form a floating P-region structure, as shown in Figure 4b.

[0041] 2.2. Formation of the N-CS layer. Specifically, the N-CS layer is formed by two phosphorus ion implantations, as shown in Figure 4c. The first implantation involves localized phosphorus ion implantation above the floating P-region, and the second implantation involves global implantation to form a relatively flat N-CS layer.

[0042] 2.3. Formation of floating P-regions and P-base regions. Specifically, global implantation of boron ions forms floating P-regions and P-base regions, as shown in Figure 4d.

[0043] 2.4. High-temperature annealing, specifically, long-term dejunction annealing is carried out in a high-temperature furnace tube at a temperature of 1100℃~1150℃ to activate impurities and form a stable embedded PN junction structure.

[0044] Step 3. Fabrication of the trench gate.

[0045] 3.1. Trench etching: Specifically, a hard mask is deposited, the trench location is defined by photolithography, and a dry etching method is used to form deep trenches.

[0046] 3.2. Gate oxide growth, specifically, sacrificial oxidation is performed to remove the damaged layer, followed by the growth of a high-quality gate oxide layer.

[0047] 3.3 Gate electrode filling: Specifically, heavily doped polysilicon is deposited to fill the trench, and then etched back to make the polysilicon surface flush, as shown in Figure 4e.

[0048] Step 4. Emitter fabrication. Specifically, an N+ emitter region is defined using a photomask, and arsenic or phosphorus ions are implanted, as shown in Figure 4f.

[0049] Step 5. Front-side dielectric layer and metallization. Specifically, deposit the interlayer dielectric layer, photolithographically create contact holes, and etch until the silicon surface is exposed. Sputter the barrier metal and thick aluminum alloy, and photolithographically etch to form the emitter, as shown in Figure 4g.

[0050] Step 6. Backside process.

[0051] 6.1. Thinning, specifically, grinding the back side of the wafer to the designed thickness.

[0052] 6.2. Forming a field cutoff layer, specifically, phosphorus ions are implanted on the back side to form an N-FS layer.

[0053] 6.3. Forming a P-type collector region, specifically, boron ions are implanted on the back side to form a P-type collector region.

[0054] 6.4. Laser annealing, specifically, uses laser annealing to activate impurities on the back side, avoiding heating the metal on the front side.

[0055] 6.5. Backside metallization, specifically, evaporation or sputtering of backside metal to form a collector contact, as shown in Figure 4h.

[0056] It should be noted that this application employs a two-step process to prepare the N-CS layer. The first implantation of phosphorus ions partially compensates for the boron ions in the floating P-regions on both sides, while the second implantation of phosphorus ions forms a relatively flat N-CS layer. A single implantation to form the N-CS layer results in a thicker N-CS layer below the P-type base region, with the N-CS layers on both sides submerged by the floating P-regions above and below, leading to a decrease in device breakdown voltage and an increase in losses. By performing two implantations, a uniformly thick N-CS layer can be formed, effectively reducing device losses and improving breakdown voltage.

[0057] Example: This example simulates FD-IGBT, CSTBT, and improved IGBT under the same conditions.

[0058] The output characteristics of the three structures are shown in Figure 5, where the horizontal axis... Represents collector-emitter voltage, ordinate This represents the collector current density. Under the same conditions (same gate voltage and temperature), the on-state voltage drop of the FD-IGBT is 1.68V, while the on-state voltage drop of the CSTBT and the improved structure is 1.55V.

[0059] Figure 6 shows the electric field distribution of the three structures during blocking. The horizontal axis x-direction represents the horizontal dimension, the vertical axis y-direction represents the vertical dimension, and the electric field represents the electric field strength. It can be seen that the electric field of FD-IGBT and CSTBT is concentrated near the bottom of the trench. The electric field near the bottom of the trench is alleviated in the improved IGBT chip structure, which protects the gate oxide layer at the bottom of the trench and improves the blocking voltage of the device.

[0060] The turn-off characteristics of the three structures are shown in Figure 7, where the horizontal axis represents time and the vertical axis represents the time interval. Represents collector-emitter voltage, ordinate The parameters in the table represent the collector current density. Indicates the shutdown time. This represents the turn-off loss. Under the same conditions (same temperature, same gate resistance), the turn-off time and turn-off loss of the FD-IGBT are 2.767 μs and 42.8 mJ / cm, respectively. 2 The turn-off time and turn-off loss of the CSTBT are 2.831 μs and 43.5 mJ / cm, respectively. 2 The turn-off time and turn-off loss of the improved structure are 2.463 μs and 29.2 mJ / cm, respectively. 2 .

[0061] Figure 8 shows the hole current during turn-off for the three structures. The horizontal axis x-direction represents the lateral dimension, the vertical axis y-direction represents the longitudinal dimension, and hCurrentDensity represents the hole current density. The hole current of FD-IGBT and CSTBT is concentrated below the P-type base region, while the hole current of the improved IGBT chip structure is distributed throughout the drift region, which can extract holes more effectively and reduce turn-off time and turn-off loss.

[0062] The activation characteristics of the three structures are shown in Figure 9, where the horizontal axis represents Time and the vertical axis represents... Represents gate voltage, ordinate The collector current density is represented. Under the same conditions (same temperature and gate resistance), the turn-on time of FD-IGBT and CSTBT is similar. Compared with the two, the turn-on time of the improved structure is reduced by 36%.

[0063] This application proposes a low-loss IGBT chip with a compensated floating P-region and its fabrication method. The method involves introducing deep floating P-regions on both sides of the trench gate and embedding an N-CS layer inside the floating P-region, while the N-CS layer is also formed below the P-type base region. This design effectively balances on-state voltage drop and switching losses, improves the device's breakdown voltage reliability, and is compatible with existing IGBT chip manufacturing processes.

[0064] In this application, the terms "first" and "second," etc., are used to distinguish different objects, not to describe a specific order of objects. For example, "first response message" and "second response message," etc., are used to distinguish different response messages, not to describe a specific order of response messages.

[0065] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0066] In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more, for example, multiple processing units means two or more processing units, multiple elements means two or more elements, etc.

[0067] It should be understood that expressions such as “comprising” and “may include” used in this application indicate the existence of the disclosed functions, operations, or constituent elements, and do not limit one or more additional functions, operations, and constituent elements. In this application, terms such as “comprising” and / or “having” are to be interpreted as indicating a particular characteristic, number, operation, constituent element, component, or combination thereof, but not to exclude the existence or possibility of adding one or more other characteristics, numbers, operations, constituent elements, components, or combinations thereof.

[0068] Furthermore, in this application, the expression "and / or" includes any and all combinations of the associated listed words. For example, the expression "A and / or B" may include A, may include B, or may include both A and B.

[0069] In the description of the embodiments of this application, it should be noted that, unless otherwise explicitly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a detachable connection or a non-detachable connection; it can be a direct connection or an indirect connection through an intermediate medium. "Fixed connection" refers to a connection where the relative positional relationship remains unchanged after connection. "Rotary connection" refers to a connection where the components can rotate relative to each other after connection. "Sliding connection" refers to a connection where the components can slide relative to each other after connection. The directional terms mentioned in the embodiments of this application, such as "top," "bottom," "inner," "outer," "left," and "right," are only for reference to the directions in the accompanying drawings. Therefore, the directional terms used are for better and clearer explanation and understanding of the embodiments of this application, and are not intended to indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.

[0070] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A low-loss IGBT chip with a compensated floating P-region, the cell structure of which includes: The present invention comprises a collector structure, a drift region structure, a trench gate structure, and an emitter structure, characterized in that the emitter structure is located above the drift region structure and is composed of an emitter metal, an N+ emitter region, a P-type base region, a first N-type carrier storage layer, a floating P-region, a second N-type carrier storage layer, and a third N-type carrier storage layer. The emitter metal is located at the top of the emitter structure, the N+ emitter region is located above the P-type base region, the P-type base region is located above the first N-type carrier storage layer, and the first N-type carrier storage layer is located between the P-type base region and the drift region structure, forming a hole barrier. The floating P-region is located on the left and right sides of the trench gate structure and is symmetrically distributed, divided into upper and lower parts by the second and third N-type carrier storage layers, forming a three-layer structure of "upper floating P-region / N-CS layer / lower floating P-region".

2. The IGBT chip as described in claim 1, characterized in that, Both the upper and lower floating P-regions are doped with boron ions, and the N-CS layer is doped with phosphorus ions. The doping concentration of the three-layer structure of "upper floating P-region / N-CS layer / lower floating P-region" decreases sequentially.

3. The IGBT chip as described in claim 1, characterized in that, The second N-type carrier storage layer and the third N-type carrier storage layer are located in the middle of the floating P region, with a depth not exceeding the depth of the trench gate structure and not extending to the bottom corner of the trench gate structure.

4. The IGBT chip as described in claim 3, characterized in that, The second N-type carrier storage layer and the third N-type carrier storage layer have the same depth and are symmetrically positioned.

5. The IGBT chip as described in claim 1, characterized in that, The depth of the floating P region is greater than the depth of the first N-type carrier storage layer.

6. The IGBT chip as described in claim 1, characterized in that, The depth of the floating P-region is greater than the depth of the gate in the trench gate structure.

7. A method for fabricating a low-loss IGBT chip with a compensated floating P-region as described in any one of claims 1 to 6, characterized in that, include: An N-type substrate is used as the N-type drift region of the IGBT chip; Boron ions are injected on the left and right sides of the trench location to form a floating P-region structure; phosphorus ions are injected in the upper region of the floating P-region structure to form an N-type carrier storage layer structure; and boron ions are injected globally in the upper region of the N-type carrier storage layer structure to form a P-type base region structure. High-temperature annealing activates impurities to form an embedded PN junction structure; a trench gate structure is fabricated, which divides the N-type carrier storage layer structure and the P-type base region structure into three parts, resulting in two symmetrically distributed three-layer structures of "upper floating P region / N-CS layer / lower floating P region"; an emitter structure is fabricated; and a collector structure is fabricated.

8. The preparation method according to claim 7, characterized in that, In the upper region within the floating P-region structure, two phosphorus ion implantations form a flat N-type carrier storage layer structure, wherein the first implantation is a local phosphorus ion implantation and the second is a global phosphorus ion implantation.

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