Photoelectric co-packaging structure with integrated three-dimensional heat dissipation function and manufacturing method thereof

Abstract

The invention provides a photoelectric co-packaging structure with an integrated three-dimensional heat dissipation function and a manufacturing method of the photoelectric co-packaging structure. The photoelectric co-packaging structure comprises a silicon optical chip; the high-heating-power electric chip is bonded with the diamond substrate through hybrid bonding, and a vertical via hole penetrating through the thickness of the diamond substrate is formed in the diamond substrate; the low-heating-power electric chip is inversely arranged on the silicon optical chip through thermocompression bonding; wherein the high-heating-power electric chip and the silicon optical chip are stacked and integrated in a three-dimensional mode, and the vertical via hole forms a main heat dissipation path of the high-heating-power electric chip. According to the invention, no matter which optical port coupling mode is adopted, the photoelectric co-packaging structure with the integrated three-dimensional heat dissipation function, which is low in cost and flexible in arrangement, can be realized.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and in particular relates to an optoelectronic co-packaging structure with integrated three-dimensional heat dissipation function and its manufacturing method. Background Technology

[0002] Optoelectronic co-packaging refers to integrating silicon photonics (PIC), driver / TIA electrical chip (EIC), and computing / switching (XPU / Switch) chip together using advanced packaging. This improves signal transmission speed and bandwidth, and achieves low latency, low power consumption, and high performance. The core issues to be addressed are improving performance and integration, enhancing thermal management and reliability, and facilitating fiber optic interconnection.

[0003] Currently, various optoelectronic co-packaging technologies are basically developed around the above-mentioned issues. These three aspects are interdependent and restrictive. In general, avoiding contamination of the PIC optical port is very difficult when using molding processes to process the PIC, making it hard to achieve efficient edge coupling output of the optical port. Different placement positions of the EIC and PIC lead to different heat dissipation efficiencies and also affect the signal output methods, which involves the question of whether to use processes such as TGV, TSV, and TMV. Different optical port coupling methods also affect the overall packaging solution. At present, various solutions are being developed and verified around the above difficulties, each with its own advantages and disadvantages. There is still no clear process route that can be mass-produced, and various solutions are in a stage of flourishing development. Summary of the Invention

[0004] The purpose of this invention is to solve the thermal management problem in CPO products by combining two solutions to achieve low-cost and flexible layout.

[0005] To this end, the present invention provides an optoelectronic co-packaging structure with integrated three-dimensional heat dissipation function, comprising: a silicon photonic chip; a high-heat-generating power chip bonded to a diamond substrate by hybrid bonding, wherein a vertical via is formed in the diamond substrate through its thickness; and a low-heat-generating power chip flip-chip bonded to the silicon photonic chip by thermo-press bonding; wherein the high-heat-generating power chip and the silicon photonic chip are three-dimensionally stacked and integrated, and the vertical via constitutes the main heat dissipation path of the high-heat-generating power chip.

[0006] Furthermore, preferably, in the optoelectronic co-packaging structure of the present invention, the active surface of the high-heat-generating power chip is bonded to the diamond substrate, the vertical via is located outside the projection area of ​​the active surface of the high-heat-generating power chip, and the chip heat is laterally diffused and conducted to the vertical via through the diamond substrate.

[0007] Furthermore, preferably, in the optoelectronic co-packaging structure of the present invention, a malleable metal layer is provided at the end of the vertical via that is away from the diamond substrate.

[0008] Furthermore, preferably, in the optoelectronic co-packaging structure of the present invention, the malleable metal layer is an indium sheet, which is disposed between the vertical via and the heat sink to increase the contact area and reduce the interface thermal resistance.

[0009] Furthermore, preferably, in the optoelectronic co-packaging structure of the present invention, the high-heat-generating power chip is bonded to the silicon photonic chip via the diamond substrate in a flip-chip manner, and the vertical via is directly thermally connected to the heat sink.

[0010] Furthermore, preferably, in the optoelectronic co-packaging structure of the present invention, the high-heat-generating power chip is disposed in a positive mounting manner, with its active surface facing away from the silicon photonic chip, and is electrically interconnected with the packaging substrate or the silicon photonic chip through wire bonding, and the vertical via is thermally connected to the heat sink.

[0011] Furthermore, preferably, the present invention also provides a method for manufacturing a photoelectric co-packaging structure with integrated three-dimensional heat dissipation function, comprising the following steps: providing a silicon photonic chip wafer; flip-chipping a low-heat-generating power chip onto the silicon photonic chip wafer via thermo-press bonding; providing a high-heat-generating power chip and forming a first hybrid bonding interface on one of its surfaces; providing a diamond substrate, forming vertical vias therein, and forming a second hybrid bonding interface on one of its surfaces corresponding to the first hybrid bonding interface; bonding the high-heat-generating power chip to the diamond substrate via a thermo-press hybrid bonding process; and three-dimensionally stacking and integrating the high-heat-generating power chip bonded to the diamond substrate with the silicon photonic chip wafer.

[0012] Furthermore, preferably, in the manufacturing method of the optoelectronic co-packaging structure with integrated three-dimensional heat dissipation function of the present invention, when integrating the high-heat-generating power chip bonded to the diamond substrate with the silicon photonic chip wafer, the high-heat-generating power chip is electrically and mechanically connected to the silicon photonic chip through the diamond substrate using a flip-chip bonding process.

[0013] Furthermore, preferably, in the manufacturing method of the optoelectronic co-packaging structure with integrated three-dimensional heat dissipation function of the present invention, when integrating the high-heat-generating power electrical chip bonded to the diamond substrate with the silicon photonic chip wafer, a front mounting and wire bonding process is adopted so that the active surface of the high-heat-generating power electrical chip faces away from the silicon photonic chip, and electrical interconnection is achieved through wires.

[0014] Using this invention, regardless of the optical port coupling method used, a low-cost and flexibly arranged optoelectronic co-packaging structure with integrated three-dimensional heat dissipation function can be realized. Attached Figure Description

[0015] Figure 1This is a schematic diagram illustrating a 3D stacking method for achieving heat dissipation in optoelectronic co-packaging structures that were the mainstream in the field before the completion of this invention.

[0016] Figure 2 This is a schematic diagram illustrating the CPO process based on the EIC Fanout technology.

[0017] Figure 3 This is a schematic diagram showing the CPO process of the TSMC process route.

[0018] Figure 4 This is a schematic diagram illustrating the three-dimensional structure of an EIC chip and a PIC chip with TDV heat dissipation according to a preferred embodiment of the present invention.

[0019] Figure 5 This is a schematic diagram illustrating the three-dimensional structure of an EIC chip and a PIC chip with TDV heat dissipation according to a preferred embodiment of the present invention.

[0020] Figure 6 This is a schematic diagram illustrating the stage process of hybrid bonding of EIC-H and TDV in a preferred embodiment of the present invention.

[0021] Figure 7 This is a schematic diagram illustrating the integration method of EIC-H in a preferred embodiment of the present invention. Detailed Implementation

[0022] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Other embodiments or modifications obtained by those skilled in the art based on the embodiments of this application without creative effort are all within the scope of protection of this application.

[0023] Advantages of this solution To address thermal management issues in CPO products, a hybrid approach is used to achieve low-cost, flexible deployment: The high-heat-generating EIC (EIC-H) chip is bonded with diamond vias (TDV). Since the thermal conductivity of diamond is 2000-2200 W / m·K, which is about five times that of copper, the overall structure is conducive to heat dissipation. For low-heat-generating electrical chips (EIC-L), flip-chip bonding is used to achieve three-dimensional integration of EIC-L with PIC. This enables low-cost and flexible placement.

[0024] With the development of high-speed data communication, artificial intelligence, and cloud computing technologies, photonic integrated circuits (PIC) have become one of the key technologies for improving data transmission speed and bandwidth. Co-packaged photonic circuits (CPO) technology integrates silicon photonic chips (PIC), driver / TIA circuit chips (EIC), and computing / switching chips (XPU / Switch) to significantly improve system transmission speed and bandwidth, while reducing power consumption, achieving low latency and high performance.

[0025] However, optoelectronic co-packaging technology faces many challenges, especially in the following aspects: 3D Stacking and Signal Outtake of EICs and PICs: Effectively outtaking signals and connecting them to compute / switch chips (XPU / Switch) in the 3D stacking structure of EICs and PICs remains a technical challenge. Different stacking methods and heat dissipation approaches will affect the final performance.

[0026] Thermal Management and Warpage Control: With co-packaging of optoelectronic chips, thermal management becomes a critical issue due to high power consumption. How to effectively control heat, prevent heat buildup, and simultaneously improve the reliability of the packaging structure to ensure the long-term stability of the chip remains a significant challenge for current technology.

[0027] Current optoelectronic co-packaging technologies are still in the exploration and verification stage when addressing these issues, and a large-scale mass production process has not yet been established. In particular, technical bottlenecks remain in optical port coupling and heat dissipation design.

[0028] For 2.5D optoelectronic co-packaging, the EIC and PIC are integrated side-by-side on an interposer, which connects the ASIC / switch, EIC, and PIC via micro-bumps. The interposer also supports fiber optic assemblies with PIC fiber blocks, which requires very high alignment accuracy (1μm) to achieve good optical coupling efficiency. For 3D optoelectronic co-packaging, EIC and PIC are stacked vertically, which can further reduce the area, further reduce the distance between the optical engine and the computing chip, and further reduce latency and loss.

[0029] Currently, the mainstream approach in the industry is 3D stacking, with solutions such as... Figure 1 As shown.

[0030] like Figure 2As shown, Broadcom's CPO process is based on EIC Fanout technology; the PIC is on top, and the EIC is below, stacked vertically; TMV process; the EIC is interconnected with the switch chip via RDL and TMV, substrate traces. The PIC does not require TSV process; the EIC needs to be thinned to 100um; similar to the CoWoS-L process; RDL traces are flexible and can be densely arranged; capacitors are easy to add; heat dissipation of EIC is relatively difficult.

[0031] like Figure 3 As shown, the TSMC process route places the PIC at the bottom and the EIC at the top, with hybrid bonding and vertical stacking. The PIC has a TSV and uses its own special silicon photonics process, with vertical optical coupling and no EMC filling. Advanced packaging processes and other circuits can be used to achieve electrical connections. The EIC connects to the computing chip via the TSV and switch, supporting interposer processes. The number of RDL layers is determined by the inetpsoer process, and the L / S ratio can be less than 1µm, resulting in better SI performance compared to substrate routing. Placing the EIC on top facilitates heat dissipation; however, the high integration of the EIC presents significant challenges for design companies, and hybrid bonding shifts the design process forward. Adding decoupling capacitors is also difficult. Using front-end processes results in high packaging costs.

[0032] Marvell's process route embeds the PIC chip within a molding compound, which incorporates a vertically connected metal VIA (Through Molding Via). The TMV, 300µm high, connects to the RDL metal layers on the front and back of the PIC. The front layer has two RDL metal layers, while the back layer has one. The back RDL is connected to the substrate via a C4 bump, while the front RDL is connected to the EIC chip via a micro-bump. The EIC is positioned on top for better heat dissipation.

[0033] Currently, various solutions are under development and verification, each with its own advantages and disadvantages. No clear process route for large-scale mass production has yet been formed, and various solutions are in a stage of flourishing.

[0034] This paper proposes an optoelectronic packaging method that allows for 3D stacking of EIC chips and PIC chips with TDV (Digital Transmission Device), supports side-mounted optical output, and enables wafer reconfiguration, thus solving thermal management issues. Specifically, two solutions are presented, such as... Figure 4 and Figure 5 As shown.

[0035] A 3D stacking method and structure for EIC and PIC chips with TDV heat dissipation are proposed, characterized by the following features: 1. Based on a differentiated thermal management strategy, high thermal power EIC-H is selected. Cu / SiO2 interfaces are made by EIC-H and diamond surface damascus process. High thermal power EIC-H and diamond bonding are achieved through a hybrid bonding process. Finally, the overall layout temperature is uniform through a standard heat sink.

[0036] 2. An indium sheet with good ductility is added between the TDV and the heat sink to ensure maximum thermal contact area.

[0037] 3. TDV can be adapted to wire bonding processes. By mounting the EIC-H in the correct orientation, the heat peak concentration area on the active surface of the EIC-H can be moved away from the PIC, improving the thermal impact on the PIC. At the same time, the overall package structure dissipates heat through convection.

[0038] The key steps include: 1. Differentiated thermal management and chip sorting This step forms the basis for all subsequent targeted thermal designs. Through testing, high-heat-generating EIC chips (EIC-H) are separated from ordinary EICs. This allows valuable advanced thermal resources (such as diamond bonding and TDV) to be precisely applied to the parts that need them most, thereby achieving an optimal balance between thermal performance and manufacturing cost.

[0039] 2. Hybrid bonding of EIC-H and diamond This is the core solution to the "heat generation" problem inside the EIC-H chip. A Cu / SiO2 hybrid bonding interface is fabricated on the active surface of the chip (which is usually the hot spot area where the transistors are located) using a damascus process, and then bonded to a diamond substrate that has been treated in the same way.

[0040] Utilizing diamond's extremely high thermal conductivity (more than five times that of copper), it serves as a highly efficient lateral heat diffusion layer, rapidly "spreading out" the hot spots generated by the chip. The Cu / SiO2 interface: Cu pillars provide a highly efficient vertical heat conduction path, while the SiO2 insulating layer provides electrical isolation. This hybrid bonding achieves a unified solution for mechanical connection, electrical interconnection, and thermal management.

[0041] 3. TDV heat dissipation path and process scalability The TDV (Dielectric Transmission Device) fabricated on the back side of the wafer efficiently conducts heat collected by the diamond layer bonded to the active surface of the EIC-H (Electronic Integrated Circuit-H) chip to the back of the chip. TDV not only serves as a thermal path but also offers additional wiring flexibility, potentially adaptable to wire bonding processes. Most importantly, TDV significantly improves upon the problem of insufficient contact area between pure diamond and the heatsink caused by the high hardness of pure diamond.

[0042] 4. Indium plate interface and overall convection heat dissipation Application of indium sheet: A highly ductile indium sheet is added between the top of the TDV and the macroscopic metal heat sink. It can undergo plastic deformation under relatively low pressure, filling any microscopic unevenness that may exist between the top of the TDV and the heat sink, thereby maximizing the contact area and further reducing the interfacial thermal resistance.

[0043] 5. Option 2: EIC-H upright mounting and system-level convection cooling Mount the EIC-H with its active side (high heat source) facing away from the PIC chip below. This physically increases the distance between the heat source and the PIC, effectively reducing the heat directly conducted to the PIC.

[0044] Ultimately, the heat is dissipated into the surrounding environment through a standard heat sink. This method typically employs forced convection (such as air cooling or liquid cooling) to continuously remove the total heat generated by the chip, ensuring the entire system operates within a stable temperature field. The proposed method incorporates microchannels that run through each layer and connect to an external cooling system, forming a highly efficient convection heat dissipation system.

[0045] Phase 1: Hybrid bonding of EIC-H and TDV.

[0046] The first stage is to achieve hybrid bonding of EIC-H and TDV. For example... Figure 6 As shown, firstly, a TDV is fabricated on a diamond substrate, and a Cu / SiO2 hybrid bonding interface is prepared on the bonding surface between EIC-H and diamond. Subsequently, a permanent bonding connection between EIC-H and diamond TDV is achieved through a hot-pressing hybrid bonding process.

[0047] Phase 2, Optoelectronic Integration Technology The task at this stage is to integrate EIC-L and EIC-H on the PIC. The choice of solution directly depends on the trade-offs between system performance, size, cost, and heat dissipation. The specific process and solution are as follows: First, guided by the EIC layout design, bumps are fabricated on the PIC wafer. Chip mounting is then performed. EIC-L typically uses standard processes; the key lies in the integration method of EIC-H, for which... Figure 7 As shown, two paths are proposed: Option 1, flip-chip bonding, aims for extreme performance. This option is ideal when the system design prioritizes high performance, high density, and optimal heat dissipation, and can withstand the corresponding process complexity and cost. It achieves the shortest electrical interconnects and efficient heat dissipation based on thermal conduction (such as through TDV to the heat sink) through EIC-H flip-chip bonding, but at the cost of a higher process threshold.

[0048] Option 2, choosing a combination of standard mounting and wire bonding, prioritizes economy and feasibility. This option is more suitable when project priorities include rapid verification, cost control, and high yield. It utilizes widely available and mature wire bonding technology, significantly reducing manufacturing difficulty and cost, and achieves heat dissipation through system-level thermal convection. Although compromises are required in integration density and signal delay, the technical risk is low.

[0049] Phase 3: Layout of Packaging Substrate and Heat Dissipation Structure First, flip-chip technology is used to interconnect the chip and the packaging substrate. Then, the heat dissipation paths are arranged differently: in Scheme 1, indium wafer packaging technology is used to connect the TDV and the heat sink, taking advantage of indium's excellent ductility to maximize the thermal contact area between the interfaces; Scheme 2 is different, using wire bonding technology to achieve electrical interconnection and mechanical fixation between the TDV and the packaging substrate.

[0050] It should be noted that the application of this patent solution is not limited to optoelectronic co-packaging. Whether it is traditional 2D packaging, or various heterogeneous integrated structures based on interposers (2.1D, 2.3D, 2.5D) or direct chip stacking (3D), as long as the proposed core heat dissipation and bonding method is used, it falls within the protection scope of this patent.

[0051] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0052] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0053] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

[0054] The above embodiments of the present invention are merely examples for clearly illustrating the present invention and are not intended to limit the implementation of the present invention. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively describe all possible implementations here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A photoelectric co-packaging structure with integrated three-dimensional heat dissipation function, characterized in that, include: Silicon photonics chip; A high-heat-generating power chip is bonded to a diamond substrate by hybrid bonding, wherein vertical vias penetrating the thickness of the diamond substrate are formed. A low-heat-generating power electrical chip is flip-chip bonded onto the silicon photonics chip via thermo-press bonding. The high-heat-generating power chip and the silicon photonics chip are stacked and integrated in three dimensions, and the vertical vias constitute the main heat dissipation path of the high-heat-generating power chip.

2. The optoelectronic co-packaging structure according to claim 1, characterized in that, The active surface of the high-heat-generating power chip is bonded to the diamond substrate. The vertical via is located outside the projection area of ​​the active surface of the high-heat-generating power chip and conducts the chip heat laterally through the diamond substrate to the vertical via.

3. The optoelectronic co-packaging structure according to claim 1, characterized in that, A ductile metal layer is provided at the end of the vertical via that is away from the diamond substrate.

4. The optoelectronic co-packaging structure according to claim 3, characterized in that, The ductile metal layer is an indium sheet, which is disposed between the vertical via and the heat sink to increase the contact area and reduce the interface thermal resistance.

5. The optoelectronic co-packaging structure according to claim 1, characterized in that, The high-heat-generating power chip is bonded to the silicon photonic chip via the diamond substrate in a flip-chip manner, and the vertical via is directly thermally connected to the heat sink.

6. The optoelectronic co-packaging structure according to claim 1, characterized in that, The high-heat-generating power electrical chip is mounted upright, with its active surface facing away from the silicon photonics chip. It is electrically interconnected with the packaging substrate or the silicon photonics chip via wire bonding. The vertical via is thermally connected to the heat sink.

7. A method for manufacturing a photoelectric co-packaging structure with integrated three-dimensional heat dissipation function, characterized in that, Including the following steps: Provide silicon photonics chip wafers; Low-heat-generating power electrical chips are flip-chip bonded onto the silicon photonic chip wafer via thermo-press bonding; A high-heat-generating power electrical chip is provided, and a first hybrid bonding interface is formed on one of its surfaces; A diamond substrate is provided in which vertical vias are formed and a second hybrid bonding interface corresponding to the first hybrid bonding interface is formed on one of its surfaces; The high-heat-generating power chip is bonded to the diamond substrate using a hot-press hybrid bonding process; The high-heat-generating power chip bonded to the diamond substrate is three-dimensionally stacked and integrated with the silicon photonic chip wafer.

8. The manufacturing method according to claim 7, characterized in that, When integrating the high-heat-generating power chip bonded to the diamond substrate with the silicon photonic chip wafer, a flip-chip bonding process is used to electrically and mechanically connect the high-heat-generating power chip to the silicon photonic chip through the diamond substrate.

9. The manufacturing method according to claim 7, characterized in that, When integrating the high-heat-generating power electrical chip bonded to the diamond substrate with the silicon photonic chip wafer, a front-mounted and wire bonding process is used so that the active side of the high-heat-generating power electrical chip faces away from the silicon photonic chip, and electrical interconnection is achieved through wires.

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