Carrier wafer removal method for temporary bonding structure and semiconductor device

Abstract

The invention provides a carrier wafer removing method for a temporary bonding structure and a semiconductor device. The problems that in the prior art, etching uniformity is poor, devices are prone to being damaged, and the yield is low are solved. The removing method comprises the following steps: mechanically grinding a silicon carrier wafer temporarily bonded with a device wafer, and thinning the silicon carrier wafer to a first thickness; forming a patterned masking layer on the surface of the thinned silicon carrier wafer; performing dry etching on the exposed silicon by taking the masking layer as a barrier layer until etching to an interface between the silicon and the dielectric layer below; in the dry etching process, lateral etching is carried out on the silicon bottom of the area which is not covered by the masking layer; and performing a chemical mechanical polishing process to polish the surface of the dielectric layer. By utilizing the method, low-stress stripping and surface planarization are realized, the problems of corrosion and uniformity are avoided, the process efficiency and the yield are remarkably improved, and the method is suitable for a 3D integrated manufacturing process with extremely high requirements on surface quality and process control.

Description

Method for removing carrier wafers for temporary bonding structures and semiconductor devices Technical Field

[0001] This invention relates to the field of advanced semiconductor packaging technology, and in particular to a method for removing carrier wafers for temporary bonding structures and a semiconductor device. Background Technology

[0002] As semiconductor process nodes continue to advance, the critical dimensions of integrated circuits (ICs) continue to shrink, and Moore's Law, which traditionally relies on transistor size reduction to improve performance and reduce costs, is gradually facing bottlenecks. On the one hand, the technical difficulty and manufacturing cost of front-end processes such as photolithography, etching, and deposition have increased dramatically after entering the nanometer or even sub-nanometer scale; on the other hand, physical limitations such as power consumption, heat dissipation, and interconnect delays also hinder the improvement of single-chip integration density. Against this backdrop, the industry has begun to seek new technological paths to continue the trend of performance growth and functional integration. Among them, advanced packaging technology, due to its ability to achieve multi-chip integration at the packaging level, effectively improves system performance and functional density, and has become an important means to break through the limitations of Moore's Law.

[0003] Compared to 2.5D packaging, 3D packaging is a more advanced packaging solution. It achieves higher integration and superior performance by vertically stacking chips, representing the future direction of advanced packaging technology. Its core idea is to increase the transistor density per unit volume by vertically stacking chips. However, simply stacking chips vertically, while reducing the area occupied in a two-dimensional plane, does not reduce the overall volume. Therefore, chip thinning is necessary to reduce the vertical height after stacking, thereby truly achieving an increase in transistor density per unit volume. Summary of the Invention

[0004] Therefore, the purpose of this invention is to solve the problems of poor etching uniformity, easy damage to devices, and low yield in the prior art.

[0005] This invention provides a method for removing a carrier wafer for a temporary bonding structure, comprising the following steps: mechanically grinding a silicon carrier wafer temporarily bonded to a device wafer to thin it to a first thickness; forming a patterned masking layer on the surface of the thinned silicon carrier wafer, wherein the masking layer exposes a portion of the silicon surface; using the masking layer as a barrier layer, dry etching is performed on the exposed silicon until the interface between the silicon and the underlying dielectric layer is etched; during the dry etching process, the charge accumulation effect of plasma at the interface is utilized to laterally etch the bottom of the silicon in the area not covered by the masking layer, thereby forming a gap between the silicon and the dielectric layer and weakening the bonding force between them; performing a chemical mechanical polishing process, using polishing stress to peel the silicon layer with weakened bonding force from the dielectric layer, and polishing the surface of the dielectric layer.

[0006] Furthermore, preferably, in the carrier wafer removal method of the present invention, the etching rate of silicon by the process gas used in the dry etching is much higher than the etching rate of the underlying dielectric layer.

[0007] Furthermore, preferably, in the carrier wafer removal method of the present invention, the sum of the size of the patterned feature on the patterned masking layer and the length of the gap formed by unilateral etch is greater than 25% of the total bonding area.

[0008] Furthermore, preferably, in the carrier wafer removal method of the present invention, the pattern is circular or square with a radius of R, and the gap length formed by lateral etching on one side is R to 2R.

[0009] Furthermore, preferably, in the carrier wafer removal method of the present invention, the masking layer is formed by a standard photolithography process, or by covering the surface of the silicon carrier wafer with a mold having a preset pattern.

[0010] Furthermore, preferably, in the carrier wafer removal method of the present invention, the dry etching reduces the area of ​​the plasma emission source and sequentially forms an etching pattern on the surface of the silicon carrier wafer in a local scanning manner, thereby inducing bottom lateral etching.

[0011] Furthermore, preferably, in the carrier wafer removal method of the present invention, in the dry etching step, by controlling the etching conditions, the lateral voids formed at the bottom of different etching areas are interconnected, thereby causing the silicon carrier wafer to undergo large-area peeling before chemical mechanical polishing.

[0012] Furthermore, preferably, in the carrier wafer removal method of the present invention, the lateral voids formed in the dry etching step are not completely connected, and the silicon carrier wafer and the dielectric layer still retain some bonding force, and finally the peeling is achieved by the mechanical stress of the chemical mechanical polishing step.

[0013] Furthermore, preferably, in the carrier wafer removal method of the present invention, the chemical mechanical polishing process adopts an endpoint control mode based on the endpoint detection mode of the dielectric layer material.

[0014] Furthermore, preferably, the present invention also provides a semiconductor device in which the carrier wafer removal method as described in any one of claims 1 to 9 is used during the manufacturing process to remove the temporarily bonded silicon carrier wafer.

[0015] This invention enables low-stress peeling and surface planarization, avoiding corrosion and uniformity issues, significantly improving process efficiency and yield, and is suitable for 3D integrated manufacturing processes with extremely high requirements for surface quality and process control. Attached Figure Description

[0016] Figure 1 is a schematic diagram illustrating the sacrificial carrier silicon wafer debonding process according to a preferred embodiment of the present invention.

[0017] Figure 2 is a schematic diagram illustrating the carrier silicon wafer debonding process of grinding + dry etching + CMP according to a preferred embodiment of the present invention.

[0018] Figure 3 is a schematic diagram illustrating the side etching of the silicon bottom according to a preferred embodiment of the present invention.

[0019] Figure 4 is a schematic diagram illustrating the unbonding of the silicon bottom side-etched gap connection according to a preferred embodiment of the present invention.

[0020] Figure 5 is a schematic diagram illustrating the non-connected debonding of the silicon bottom lateral etched gaps according to a preferred embodiment of the present invention.

[0021] Figure 6 is a schematic diagram showing a comparison between ETCH etching according to a preferred embodiment of the present invention and conventional blank mask etching.

[0022] Figure 7 is a schematic diagram showing the photomask structure according to a preferred embodiment of the present invention.

[0023] Figure 8 is a schematic diagram illustrating the carrier silicon wafer debonding process flow of grinding + dry etching (patterned bottom side etching) + CMP according to a preferred embodiment of the present invention. Detailed Implementation

[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Other embodiments or modifications obtained by those skilled in the art based on the embodiments of this application without creative effort are all within the scope of protection of this application.

[0025] In 3D packaging, wafer thinning is a crucial step. Once the wafer thickness is reduced to a certain level, it becomes insufficient to maintain adequate mechanical strength on its own, necessitating the use of a carrier wafer for support to facilitate subsequent processing. This process begins with temporary bonding between the wafer to be thinned and the carrier wafer. After thinning is complete and sufficient mechanical strength is achieved, the wafer is then bonded to other wafers or substrates. Finally, ensuring structural stability, the wafer is debonded from the carrier wafer, completing the temporary support system.

[0026] There are many technical solutions for temporary bonding and debonding. One common method is temporary bonding adhesive bonding and debonding. Specifically, the wafer to be thinned is adhered to a mechanically strong carrier wafer using a temporary bonding adhesive, thus providing sufficient support during the thinning process. This bonding process requires the bonding adhesive to have good thermal stability, chemical compatibility, and mechanical strength to ensure structural integrity is maintained during subsequent thinning, etching, and cleaning processes.

[0027] Once the thinned wafer has completed the key processing steps and has sufficient self-supporting capacity, it needs to be debonded from the carrier wafer through specific methods (such as thermal peeling, ultraviolet debonding, laser peeling, or solvent cleaning) to remove the temporary bonding adhesive, restore the wafer body, and proceed with subsequent processing.

[0028] The reasons why this process is not widely used in fabs are as follows: High contamination risk: Temporary bonding adhesive is an organic material. After the device wafer and the carrier wafer are temporarily bonded, the wafer still needs to undergo several subsequent process steps. Since organic materials are easily decomposed in high-temperature or plasma environments, the residues released may introduce particulate or chemical contamination, which is difficult to control effectively and affects yield.

[0029] Bonding thickness control is challenging: Temporary bonding adhesive is typically applied to the wafer surface via spin coating, but due to its soft nature, the coating thickness fluctuates. Furthermore, during bonding, the compression between the device wafer and the carrier wafer causes adhesive layer deformation, resulting in uneven overall bonding thickness. This thickness error severely impacts the alignment accuracy and stability of subsequent thinning and precision patterning processes.

[0030] Poor material compatibility: Processes using temporary bonding adhesives typically employ glass as the carrier wafer to support debonding methods such as UV debonding and laser lift-off. However, glass differs from silicon, a material commonly used in wafer fabs, in terms of thermal expansion coefficients and electrical properties, leading to poor process compatibility. Furthermore, glass is more fragile than silicon, increasing the risk of wafer breakage and equipment damage during the manufacturing process.

[0031] Given the above issues, in the standard process flow of actual wafer fabs, we prefer to use silicon wafers as carrier wafers and temporarily bond them to device wafers through fusion bonding. This method avoids organic contamination, and the stacked wafers bonded in this way have high thickness uniformity, which can meet the high-precision processing requirements of subsequent processes.

[0032] After temporary bonding is completed, the device wafer will undergo thinning and subsequent critical processing steps such as patterning and metallization. Once the device wafer is finally bonded to the target wafer or substrate and has sufficient mechanical strength, the silicon carrier wafer is removed through destructive methods to unbond the temporary bond, thus completing the entire processing flow.

[0033] In the aforementioned temporary bonding and debonding processes, temporary fusion bonding is a common and mature process in fabs. Similar to hybrid bonding, this process involves CMP planarization before bonding, thus achieving high thickness uniformity after bonding. Given the maturity of this process, temporary bonding technology itself does not present significant problems.

[0034] The key is the temporary debonding process. Currently, the commonly used process involves completely removing the carrier wafer through destructive methods. A 12-inch wafer is 775µm thick. First, mechanical grinding is used to remove most of the silicon as quickly as possible. Its advantage is its high grinding speed. Its disadvantage is that it's a purely mechanical method of silicon removal, which puts significant stress on the wafer. To avoid affecting the device wafer, we use mechanical grinding to thin it to 30µm-70µm (the thinnest possible is 30µm). Next, wet etching is used to remove almost all the remaining silicon. Its advantage is that it removes silicon without stress, avoiding mechanical damage to the device wafer. Its disadvantage is that wet etching has lower etching precision, resulting in incomplete silicon removal in certain areas and over-etching of the underlying dielectric layer. Furthermore, wet etching involves immersion in a corrosive solution, which inevitably damages the wafer's coating. Finally, there's the CMP process, whose main function is to remove the silicon that wasn't completely removed by the wet etching process. It also smooths out any unevenness caused by damage to the bottom dielectric layer resulting from the wet etching. This ensures that the thickness uniformity of the device wafer after removing the carrier wafer meets the requirements. The advantages of CMP are its good uniformity of the final film thickness and its moderate stress, which doesn't adversely affect the device wafer. Its disadvantages are its slow polishing rate and low wheat powder level (WPH). In summary, the current method combines polishing, wet etching, and CMP to achieve the debonding process of sacrificial silicon carrier wafers. A schematic diagram of the process is shown in Figure 1.

[0035] The problem with the above process lies in the wet etching step. Its advantage, as mentioned above, is that it's a stress-free process and won't cause stress damage to the device wafer. Its main disadvantages are detailed below: In actual manufacturing processes, the etching rate varies across different areas during wet etching. When the target etched film layer is thick, this non-uniformity is further amplified, leading to increased inconsistency in the final residual film thickness. During wet etching, silicon in some areas may be completely etched, while residual silicon remains in other areas. In this case, the wet etching time is usually extended to ensure that the silicon layer in all areas is completely removed. However, extending the etching time can cause a series of problems.

[0036] First, silicon in areas with higher etching rates will be removed earlier, exposing the underlying dielectric layer. This dielectric layer will then be continuously subjected to chemical etching for the remaining etching time, leading to decreased thickness uniformity and increased surface roughness, thus increasing the difficulty of subsequent chemical mechanical polishing (CMP) processes. Second, the extended exposure time of the entire device wafer in the etching solution may also pose a potential risk of structural damage or performance degradation.

[0037] On the other hand, while extending the wet etching time can prevent excessive etching of the dielectric layer, the selectivity of the etchant for silicon is much higher than its selectivity for the dielectric layer. This leads to a significant increase in the difference in residual silicon thickness across different locations on the wafer. Simultaneously, surface silicon residue will also increase significantly. This will severely impact the uniformity and control precision of subsequent CMP processes.

[0038] In summary, the wet etching process suffers from insufficient uniformity in etching rate, leading to variations in silicon layer thickness and residual issues. Furthermore, the potential adverse effects of the etching solvent on the device wafer are the root causes of these problems.

[0039] If we skip the wet etching step and remove the carrier wafer using a combination of grinding and CMP, the problem lies in the excessive stress grinding exerts on the wafer. If we grind a thicker layer, the stress from grinding can affect the device wafer, especially when the carrier wafer is relatively thin. If we grind a thinner layer, leaving a relatively thicker silicon, we can then use CMP to remove the silicon. CMP exerts less stress on the device wafer compared to grinding, avoiding negative impacts. However, this method suffers from slow CMP grinding rates, resulting in very low wet silicon penetration (WPH) when removing relatively thick silicon. In conclusion, while the grinding + CMP method is technically feasible, it is difficult to implement in actual production.

[0040] In view of the problems existing in the above-mentioned sacrificial carrier silicon wafer debonding process, the present invention provides an innovative improvement solution.

[0041] Existing technologies optimize the final removal of the silicon carrier wafer by adjusting the process parameters of grinding, wet etching, and CMP. Alternatively, the wet etching step can be eliminated, and grinding and CMP can be used to remove the silicon carrier wafer; this method also primarily optimizes the process through process parameter formulation. The purpose of this invention is to optimize the removal process of the silicon carrier wafer by adding a dry etching step and employing a novel photomask design.

[0042] To address the disadvantages of wet etching in the removal process of carrier silicon wafers, and the problems that would arise if wet etching were to be used, we replaced wet etching with a dry etching process. Using a formulation with a high selectivity ratio for Si relative to the dielectric film, the carrier silicon wafer is removed in a stress-free manner. Subsequently, CMP is used to remove some of the dielectric film, thereby ensuring the uniformity of the substrate wafer thickness and improving the surface roughness of the dielectric film, which is beneficial for subsequent processes such as CVD, PVD, and Litho. A schematic diagram of the optimized process flow is shown in Figure 2.

[0043] The previous grinding process thins the carrier wafer to 30-70µm, with a minimum of 30µm. Dry etching, however, requires almost complete removal of silicon. Therefore, if only dry etching is used to remove Si from the silicon wafer, the overall WPH (wafer thickness) is very low. This invention employs a special photomask design, combined with subsequent CMP (Continuous Metal Processing) to remove all silicon and a portion of the dielectric film (with some loss), ultimately ensuring the uniformity of the device wafer thickness.

[0044] The design of this invention replaces blank etching with pattern etching, i.e., designing a photomask with a pattern on it. It can be circular or square. We spin-coat a layer of photoresist onto the wafer, and then form a pattern on the surface through exposure and development (the above is the photolithography process). Then, a dry etching process is performed. During this process, areas blocked by the photoresist cannot be etched; only the exposed silicon is etched away. After the silicon in these areas is etched, it encounters the dielectric film layer, which is usually SiO2 directly connected to the silicon. SiO2 is an electrically insulating material. Because the bottom is an insulator, a large amount of plasma charge accumulates at the bottom. Since the silicon on the sides is a semiconductor, the charge diffuses to the surrounding silicon, reacting with it. This results in the bottom lateral etching of silicon, as shown in Figure 3.

[0045] When silicon undergoes lateral etching, creating gaps, the silicon separates from the dielectric film. As the gaps created by the lateral etching of different patterns connect, the silicon wafer naturally peels off. We can then use a CMP process to polish the dielectric film to optimize its flatness and roughness. A schematic diagram is shown in Figure 4.

[0046] In practical applications of this invention, the bottom etching of silicon in the patterned areas does not need to be completely continuous; only localized bottom etching is required to significantly weaken the interfacial adhesion between the silicon layer and the underlying dielectric film layer. During the subsequent chemical mechanical polishing (CMP) process, the mechanical stress introduced by the polishing process itself causes the silicon layer with reduced adhesion to preferentially peel off from the dielectric film layer, thereby achieving effective removal of the carrier silicon wafer. Furthermore, CMP can further remove some dielectric film material to improve the surface smoothness and optimize the interface roughness after removing the carrier wafer. The entire CMP process employs an endpoint-based control mode, that is, the process termination point is determined by monitoring the signal changes in the dielectric film layer, rather than using a fixed-time control method. Therefore, even if a large-area instantaneous peeling of the silicon layer occurs during polishing, it will not substantially affect the stability of the CMP process or the endpoint determination. A schematic diagram is shown in Figure 5.

[0047] Here's an example: When the pattern is circular, the radius of the hole is R, and the etched seams around it are also R, then the radius of the bottom of the silicon in the final top view is 2R. The area for unbonding is thus 4πR. 2 The actual etched volume is πR. 2 T (where T represents the thickness of silicon), meaning that originally 4πR needed to be etched. 2 T's silicon now only requires etching πR 2 With a higher silicon content (T), the wafer penetration rate (WPH) increases by about three times. If the etching time is appropriately increased to allow for more lateral etching, the WPH can be improved even further. This assumes the lateral etching gaps are completely connected. If they are not completely connected, and the area of ​​the conventional etching plus the gap area only occupies half of the total wafer area, then the actual etched hole radius is R, and the etched area is πR. 2 Including the area of ​​the gap, the actual area of ​​unbonding is 4πR. 2 Since the area of ​​unbonding is only half of the total area, the total area is 8πR. 2 Multiplying this by the thickness T, it means that compared to the original blank mask dry etching, the etching volume of this method is 1 / 8 of the original, which is an 8-fold increase in WPH. In summary, this method can significantly improve the overall WPH of the carrier wafer silicon removal process. If the dry etching formula is further optimized to increase the gap extension length and reduce the proportion of the lateral etching plus pattern area to the total area of ​​the bonding wafer, the WPH can be improved even more.

[0048] The preferred scope of this invention is as follows: the feature size radius of the pattern is R, the side etch gap is R-2R on one side, and the side etch plus the feature size of the pattern accounts for more than 25% of the entire wafer (i.e., the bonding area). Thus, the patterned dry etching of this invention has a dry etching rate 4-36 times that of the original blank mask dry etching.

[0049] The specific calculation etching diagram is shown in Figure 6.

[0050] The photomask structure used in this invention only needs to have a certain number of patterns on it. The shapes of the patterns can be square, circular, etc., as shown in Figure 7. Since this invention does not have strict requirements on the dimensional accuracy of the patterns, and only needs to achieve lateral etching between the silicon layer and the underlying dielectric film layer, there are no special requirements for the fabrication accuracy of the photomask. In practical applications, even standard lithography processes can be omitted. Instead, a mold made of a dielectric material or other insulating material with a patterned structure is placed on the silicon wafer surface and then subjected to dry etching plasma etching to form the corresponding patterns on the silicon surface. Subsequently, during the etching process, lateral etching occurs at the bottom of the silicon, thereby forming void connections, which promotes the peeling of the silicon wafer, or significantly weakens the adhesion between it and the dielectric film layer through the lateral etching gaps.

[0051] Alternatively, a simpler approach can be adopted: by reducing the area of ​​the plasma emission source, localized etching can be performed on the wafer, thereby forming a patterned structure on the surface of the silicon wafer and achieving lateral etching on its bottom, thus achieving the same desorption effect as the method described above.

[0052] In summary, this invention replaces the conventional wet cleaning process with a patterned dry etching process, while requiring a certain amount of over-etching to create gaps through lateral etching at the bottom of the pattern. The optimized process flow is as follows: grinding, dry etching, and CMP. A detailed process flow diagram of this invention is shown in Figure 8.

[0053] The actual area to be etched in this invention: πR 2 Actual unbonding area: π(R+L) 2 The debonding area as a percentage of the total wafer area is: 1 / X. The etching rate of this invention: Blank mask etching rate: (R+L)²X / R 2 This invention uses a combination of grinding, dry etching, and CMP to remove the silicon wafer from the carrier. Compared with the original process, dry etching replaces wet etching.

[0054] The dry etching of this invention is not blank mask etching, but patterned etching. It utilizes the difference in charge accumulation in the dielectric film layer on the bottom of the silicon, i.e., the difference in etching rate selectivity. The dry etching formulation has a higher etching rate for silicon compared to the dielectric film layer, meaning it has higher selectivity for silicon. Lateral etching on the bottom creates gaps. These gaps between patterns are interconnected, allowing the silicon wafer to detach and separate. Even if the gaps on the bottom are not interconnected, as long as gaps are created, the bonding force at the interface will decrease. The stress applied to the wafer by CMP can then directly peel off the silicon. Thus, the CMP process directly removes a portion of the dielectric film layer, improving overall thickness uniformity and roughness. The preferred range of this invention is: the feature size radius of the pattern is R, the side of the lateral etching gap is R-2R, and the lateral etching plus the feature size of the pattern occupies more than 25% of the entire wafer (i.e., the bonding area). Therefore, the patterned dry etching of this invention has a rate 4-36 times higher than the original blank mask dry etching.

[0055] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0056] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0057] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

[0058] The above embodiments of the present invention are merely examples for clearly illustrating the present invention and are not intended to limit the implementation of the present invention. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively describe all possible implementations here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A method for removing a carrier wafer used in temporary bonding structures, characterized in that, Includes the following steps: The silicon carrier wafer temporarily bonded to the device wafer is mechanically ground to reduce it to a first thickness. A patterned masking layer is formed on the surface of the thinned silicon carrier wafer, the masking layer exposing a portion of the silicon surface; Using the masking layer as a barrier layer, the exposed silicon is dry etched until the interface between the silicon and the underlying dielectric layer is reached. During the dry etching process, the charge accumulation effect of plasma at the interface is used to laterally etch the bottom of the silicon in the area not covered by the masking layer, thereby forming a gap between the silicon and the dielectric layer and weakening the bonding force between them. Then, a chemical mechanical polishing process is performed to use polishing stress to peel the silicon layer with weakened bonding force from the dielectric layer and polish the surface of the dielectric layer.

2. The carrier wafer removal method according to claim 1, characterized in that, The dry etching process uses a process gas that etches silicon at a much higher rate than it etches the underlying dielectric layer.

3. The carrier wafer removal method according to claim 1, characterized in that, The sum of the size of the patterned features on the patterned masking layer and the length of the voids formed by lateral etching on one side accounts for more than 25% of the total bonding area.

4. The carrier wafer removal method according to claim 3, characterized in that, The pattern is circular or square with a radius of R, and the gap length formed by lateral etching on one side is from R to 2R.

5. The carrier wafer removal method according to claim 1, characterized in that, The masking layer is formed by standard photolithography or by covering the surface of a silicon carrier wafer with a mold having a preset pattern.

6. The carrier wafer removal method according to claim 1, characterized in that, The dry etching process reduces the area of ​​the plasma emission source and sequentially forms etching patterns on the surface of the silicon carrier wafer in a local scanning manner, thereby inducing bottom lateral etching.

7. The carrier wafer removal method according to claim 1, characterized in that, In the dry etching process, by controlling the etching conditions, the lateral voids formed at the bottom of different etching areas are interconnected, thereby causing the silicon carrier wafer to undergo large-area peeling before chemical mechanical polishing.

8. The carrier wafer removal method according to claim 1, characterized in that, In the dry etching step, the lateral voids formed are not completely connected, and some bonding force is still maintained between the silicon carrier wafer and the dielectric layer. Finally, the mechanical stress of the chemical mechanical polishing step is used to achieve the peeling.

9. The carrier wafer removal method according to claim 1, characterized in that, The chemical mechanical polishing process uses an endpoint detection mode based on the dielectric layer material to control the process endpoint.

10. A semiconductor device, characterized in that, The temporary bonded silicon carrier wafer was removed during the manufacturing process using the carrier wafer removal method as described in any one of claims 1 to 9.

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