Light emitting diode screening method

Abstract

The invention provides a light-emitting diode screening method, which comprises the following steps of: providing a wafer which is provided with a plurality of light-emitting diode structures; testing each light emitting diode structure on the wafer through wafer-level electrostatic discharge; testing each light emitting diode structure on the wafer by wafer-level collapse voltage; testing the light emitting diode structures on the wafer according to wafer-level photoelectric characteristics; splitting the light emitting diode structures on the wafer to form a plurality of light emitting diode crystal grains; and excluding a part of the light emitting diode crystal grains with abnormity, wherein the abnormity comprises one of electrostatic discharge test abnormity, collapse voltage test abnormity, photoelectric characteristic test abnormity and appearance abnormity.

Description

LED screening method Technical Field

[0001] This invention relates to a method for screening light-emitting diodes (LEDs), and more particularly to a method for screening LEDs that reduces the probability of missing abnormal chips. Background Technology

[0002] Light-emitting diodes (LEDs) possess advantages such as high optical efficiency, long lifespan, small size, and specific spectral distribution, and are widely used in optical fields such as lighting and displays. Therefore, for LED chip manufacturers, improving production efficiency, reducing product defect rates, and ensuring that the final products supplied to downstream module manufacturers meet relevant acceptance standards are currently urgent goals that the industry needs to strive to achieve.

[0003] Figure 1 shows a flowchart of an existing LED chip screening method. In this manufacturing process, the photoelectric characteristics of each LED structure, which has not yet been cleaved but has been pre-formed, are fully inspected on the wafer. This includes tests for VF (Forward Voltage), IF (Forward Current), VR (Reverse Voltage), IR (Reverse Current), WLD (Wavelength of Dominant Emission), and LOP (Light Output Power). These tests are the main quality control methods for evaluating the photoelectric performance of LEDs. After the photoelectric characteristic tests are completed, a dicing and cleaving process is performed to form individual individual chips, followed by electrostatic discharge (ESD) testing.

[0004] Current ESD testing methods involve packaging LED chips into TO CAN (Transistor Outline Package) packages and then performing sampling tests. Due to the limitations of the TO CAN packaging method, the ESD testing process is lengthy. Therefore, existing manufacturing processes cannot perform full inspection of all produced LED chips and can only perform sampling. This results in a high probability that defective LED chips will enter the downstream supply chain. Therefore, reducing the defect rate of LED products supplied to the downstream supply chain is a pressing issue that needs to be addressed. Summary of the Invention

[0005] The main objective of this invention is to provide an innovative method for screening light-emitting diodes. Through an improved screening process, this invention can perform full inspection of all LED structures or LED chips before and after splitting by electrostatic discharge testing and breakdown voltage testing, thereby reducing the flow of defective LED chips into subsequent processes and improving production efficiency.

[0006] To achieve the above objectives, the present invention provides a method for screening light-emitting diodes (LEDs), comprising the following steps: First, a wafer is provided, on which multiple LED structures are disposed. Second, a wafer-level electrostatic discharge (ESD) test is performed on each LED structure on the wafer. Next, a wafer-level breakdown voltage (LDV) test is performed on each LED structure on the wafer. Then, a wafer-level photoelectric property test is performed on each LED structure on the wafer, and each LED structure on the wafer is split to form multiple LED chips. Finally, LED chips with abnormalities are excluded, wherein the abnormality includes one of the following: ESD test abnormality, breakdown voltage test abnormality, photoelectric property test abnormality, and appearance abnormality.

[0007] In one embodiment of the present invention, the light-emitting diode screening method further includes a step of half-cutting the wafer before the step of performing wafer-level electrostatic discharge testing, so that multiple dicing channels are formed between adjacent light-emitting diode structures.

[0008] In one embodiment of the present invention, the light-emitting diode screening method further includes a step of electrostatic discharge capability testing before the step of performing wafer-level electrostatic discharge testing, wherein a portion of the light-emitting diode structure is subjected to an electrostatic discharge capability test to confirm an electrostatic discharge capability level of that portion of the light-emitting diode structure.

[0009] In one embodiment of the present invention, the step of performing wafer-level electrostatic discharge (ESD) testing in the LED screening method is to perform wafer-level ESD testing on each LED structure according to its ESD capability level.

[0010] In one embodiment of the present invention, the light-emitting diode screening method further includes a step of breakdown voltage capability testing before the step of performing wafer-level breakdown voltage testing, wherein a breakdown voltage capability test is performed on a portion of the light-emitting diode structure to confirm a breakdown voltage capability level of that portion of the light-emitting diode structure.

[0011] In one embodiment of the present invention, the step of performing wafer-level breakdown voltage testing in the light-emitting diode screening method is to perform wafer-level breakdown voltage testing on each light-emitting diode structure according to the breakdown voltage capability level.

[0012] To achieve the above objectives, the present invention provides a method for screening light-emitting diodes (LEDs), comprising the following steps: First, a wafer is provided, wherein the wafer has a plurality of LED structures. Second, the LED structures on the wafer are split to form a plurality of LED chips. Next, each LED chip is subjected to a chip-level electrostatic discharge (ESD) test, a chip-level breakdown voltage (DBV) test, and a chip-level photoelectric property (PIP) test. Finally, LED chips with abnormalities are excluded, wherein the abnormality includes one of the following: ESD test abnormality, DBV test abnormality, PIP test abnormality, and appearance abnormality.

[0013] In one embodiment of the present invention, the light-emitting diode screening method further includes a step of half-cutting the wafer before the step of splitting the light-emitting diode structures on the wafer, so that multiple cleaving channels are formed between adjacent light-emitting diode structures.

[0014] In one embodiment of the present invention, the light-emitting diode screening method further includes a step of electrostatic discharge capability testing before the step of performing grain-level electrostatic discharge testing, wherein a portion of the light-emitting diode grains is subjected to an electrostatic discharge capability test to confirm the electrostatic discharge capability level of that portion of the light-emitting diode grains.

[0015] In one embodiment of the present invention, the step of performing a grain-level electrostatic discharge test in the LED screening method is to perform a grain-level electrostatic discharge test on each LED chip according to its electrostatic discharge capability level.

[0016] In one embodiment of the present invention, the light-emitting diode screening method further includes a step of breakdown voltage capability testing before the step of performing a die-level breakdown voltage test, wherein a breakdown voltage capability test is performed on a portion of the light-emitting diode dies to confirm a breakdown voltage capability level of that portion of the light-emitting diode dies.

[0017] In one embodiment of the present invention, the step of performing a grain-level breakdown voltage test in the light-emitting diode screening method is to perform a grain-level breakdown voltage test on each light-emitting diode die according to its breakdown voltage capability level.

[0018] Other objects of the present invention, as well as the technical means and implementation methods of the present invention, will be understood by those skilled in the art upon referring to the accompanying drawings and the embodiments described below. Attached Figure Description

[0019] Figure 1 shows a flowchart of a traditional LED chip screening method;

[0020] Figure 2 shows a flowchart of a light-emitting diode screening method according to an embodiment of the present invention;

[0021] Figure 3 shows a detailed flowchart of step S03 in the flowchart shown in Figure 2 in one embodiment of the present invention;

[0022] Figure 4A shows a top-view image of a qualified LED chip;

[0023] Figure 4B shows a scanning electron microscope image of a cross-section of the outer periphery of a qualified LED chip.

[0024] Figure 4C shows a top-view image of the LED die used in the test NG;

[0025] Figure 4D shows a scanning electron microscope image of a cross-section of the outer periphery of the LED die in the test NG.

[0026] Figure 5A shows a top-view image of a qualified LED chip;

[0027] Figure 5B shows a scanning electron microscope image of a cross-section of the center of a qualified LED grain.

[0028] Figure 5C shows a top-view image of the LED die used in the test NG;

[0029] Figure 5D shows a scanning electron microscope image of a cross-section of the center of a light-emitting diode in test NG;

[0030] Figure 6 shows a flowchart of a light-emitting diode screening method according to another embodiment of the present invention; and

[0031] Figure 7 shows a detailed flowchart of step S14 in the flowchart shown in Figure 6 in another embodiment of the present invention.

[0032] Explanation of reference numerals in the attached figures:

[0033] Step S01

[0034] Step S02

[0035] Step S03

[0036] Step S03-1

[0037] Step S03-2

[0038] Step S03-3

[0039] Step S03-4

[0040] Step S04

[0041] Step S05

[0042] Step S06

[0043] Step S07

[0044] Step S11

[0045] Step S12

[0046] Step S13

[0047] Step S14

[0048] Step S14-1

[0049] Step S14-2

[0050] Step S14-3

[0051] Step S14-4

[0052] Step S15

[0053] Step S16

[0054] Step S17. Detailed Implementation

[0055] The following embodiments will explain the content of this invention. These embodiments are not intended to limit the implementation of this invention to any specific environment, application, or special method described in the embodiments. Therefore, the descriptions of the embodiments are merely illustrative of the invention and not intended to limit it. It should be noted that in the following embodiments and accompanying drawings, elements not directly related to this invention have been omitted and are not shown, and the dimensional relationships between the elements in the drawings are for ease of understanding only and are not intended to limit the actual scale.

[0056] Please refer to Figure 2, which shows a flowchart of a light-emitting diode (LED) screening method according to an embodiment of the present invention. As shown in the figure, in step S01, a wafer is provided. This wafer has undergone epitaxial processing of compound semiconductors such as gallium nitride (GaN), gallium arsenide (GaAs), or indium phosphide (InP), as well as subsequent patterning and metallization processes, so that the wafer already has multiple uncut LED structures. In step S02, the wafer is half-cut, forming multiple dicing channels between adjacent LED structures on the wafer. Next, in step S03, wafer-level electrostatic discharge (ESD) testing and wafer-level Zener Breakdown Voltage (Vz) testing are performed on all uncut LED structures between the dicing channels on the wafer. After these two tests are completed, wafer-level photoelectric characteristic tests, including VF, IF, VR, IR, WLD, and LOP, are also performed on all uncut LED structures. It should be noted that the term "wafer level" here refers to the structure of the light-emitting diode on the wafer before it has been cut and split into grains.

[0057] Please refer to Figure 3, which further divides step S03 into four sub-steps, as explained below. In step S03-1, a wafer-level electrostatic discharge (ESD) capability test is performed. This ESD capability test is not performed on all LED structures on the wafer, but only on a portion of the LED structures on the wafer. Based on the test results, the specific ESD capability level that these tested LED structures can withstand without being damaged by electrostatic discharge is determined. After the ESD capability test is completed, the ESD capability level of the LED structures on this wafer can be confirmed, serving as the ESD test standard for subsequent full inspection.

[0058] In step S03-2, a wafer-level breakdown voltage capability test is performed. Similarly, this step only tests the Vz capability of the light-emitting diode structure on the upper part of the wafer. Based on the test results, the specific breakdown voltage capability level that the tested light-emitting diode structure can withstand is determined so that it will not be damaged by reverse voltage breakdown. A breakdown voltage capability level is then confirmed as the test standard for Vz during subsequent full inspection.

[0059] In step S03-3, wafer-level electrostatic discharge (ESD) testing and wafer-level breakdown voltage testing are performed on all LED structures on the wafer. That is, the ESD capability level and breakdown voltage capability level confirmed in the previous two steps are used to perform ESD full inspection and Vz full inspection on all LED structures.

[0060] In steps S03-4, a full wafer-level optoelectronic characteristic test is performed on all light-emitting diode structures on the wafer, including VF, IF, VR, IR, WLD, LOP and other tests, to understand the electrical performance and optoelectronic characteristics of the light-emitting diodes and to identify the location of defective light-emitting diode structures on the wafer.

[0061] As shown in Figure 2, in step S04, after multiple LED structures complete ESD, Vz, and photoelectric characteristic tests, the wafers are cleaved along the dicing line to form multiple LED chips. Next, in step S05, based on the photoelectric characteristic test results from the previous steps, LED chips are sorted and automated optical inspection (AOI) is performed. It is worth noting that after the ESD and Vz tests in step S03, NG (No Good) defective products will exhibit abnormal appearance characteristics. These defective products can then be eliminated through automated optical inspection or manual visual inspection, as shown in step S06. The abnormalities referred to here include one or a combination of abnormal electrostatic discharge tests, abnormal breakdown voltage tests, abnormal photoelectric characteristic tests, and abnormal appearance. Finally, in step S07, after eliminating NG defective products, qualified LED chips can be screened out.

[0062] Please refer to Figures 4A, 4B, 4C, and 4D together. Figure 4A shows a top-view image of a qualified LED chip, and Figure 4B shows a scanning electron microscope (SEM) image of the outer cross-section of the qualified chip within the box in Figure 4A. Conversely, Figure 4C shows a top-view image of a failed (NG) LED chip, and Figure 4D shows a scanning electron microscope (SEM) image of the outer cross-section of the failed chip. Clearly, the boxes in Figures 4C and 4D clearly show defects caused by electrostatic discharge (ESD) breakdown around the chip. Furthermore, please refer to Figures 5A, 5B, 5C, and 5D together. Figure 5A shows a top-view image of a qualified LED chip, and Figure 5B shows a scanning electron microscope (SEM) image of the central cross-section of the qualified chip within the box in Figure 5A. In contrast, Figure 5C shows a top-view image of the tested NG LED chip, while Figure 5D shows a scanning electron microscope image of a cross-section of the NG chip's center. Clearly, the boxes in Figures 5C and 5D clearly show the defect of electrostatic discharge breakdown at the chip's center. This defect facilitates identification by AOI or visual inspection in steps S05 and S06, allowing for the screening and rejection of NG chips.

[0063] Please refer to Figure 6, which shows a flowchart of a light-emitting diode (LED) screening method according to another embodiment of the present invention. This embodiment is largely the same as the embodiment shown in Figure 2, except that the target for ESD, Vz, and photoelectric characteristic tests in the embodiment shown in Figure 2 is a wafer-level LED structure. In contrast, in the embodiment shown in Figure 6, the target for ESD, Vz, and photoelectric characteristic tests is a die-level LED die, as detailed below.

[0064] As shown in the figure, in step S11, a wafer is provided. This wafer has undergone epitaxial growth processes for compound semiconductors such as gallium nitride (GaN), gallium arsenide (GaAs), or indium phosphide (InP), as well as subsequent patterning and metallization processes, resulting in multiple uncut and unsplit light-emitting diode (LED) structures on the wafer. In step S12, the wafer is half-cut, forming multiple cleavage paths between adjacent LED structures. In step S13, the wafer is split along the cleavage paths to form multiple LED chips.

[0065] Next, in step S14, die-level electrostatic discharge (ESD) testing and die-level breakdown voltage (LDV) testing are performed on all LED chips. After these two tests are completed, die-level photoelectric characteristic tests, including VF, IF, VR, IR, WLD, and LOP, are also performed on all LED chips. It should be noted that "die-level" here refers to LED chips that have been cut and split into chip structures.

[0066] Please refer to Figure 7, which further divides step S14 into four sub-steps, as explained below. In step S14-1, a grain-level electrostatic discharge (ESD) capability test is performed. Similarly, this ESD capability test is not performed on all LED chips, but only on a portion of them. Based on the test results, the specific ESD capability level that these tested LED chips can withstand without being damaged by electrostatic discharge is determined. After the ESD capability test is completed, an ESD capability level of the LED chip can be confirmed, which serves as the ESD test standard for subsequent full inspection.

[0067] In step S14-2, a chip-level breakdown voltage capability test is performed. Similarly, this step only tests the Vz capability of a portion of the LED chips, and determines the specific breakdown voltage capability level that the tested LED chips can withstand without being damaged by reverse voltage breakdown based on the test results. A breakdown voltage capability level is then confirmed as the test standard for Vz when all chips are inspected in the future.

[0068] In step S14-3, all LED chips undergo grain-level electrostatic discharge (ESD) testing and grain-level breakdown voltage (DVT) testing. That is, the ESD capability level and DVT capability level confirmed in the previous two steps are used to perform a full ESD inspection and a full Vz inspection on all LED chips.

[0069] In step S14-4, all light-emitting diode (LED) chips undergo a full inspection of their photoelectric characteristics at the chip level, including tests for VF, IF, VR, IR, WLD, and LOP, to understand the electrical performance and photoelectric characteristics of the LEDs.

[0070] Subsequent steps S15, S16, and S17 are substantially the same as those described above in steps S05, S06, and S07, and will not be repeated here. It should be noted that if, during the manufacturing process of a mature LED product, the electrostatic discharge capability level and breakdown voltage capability level of the product can be confirmed due to familiarity with its photoelectric characteristics, then the confirmation process for ESD capability level and Vz capability level in steps S03-1 and S03-2 in Figure 3 or steps S14-1 and S14-2 in Figure 7 can be omitted during the screening process. A full inspection of ESD, Vz, and photoelectric characteristics can be performed directly. On the other hand, if after executing steps S05 and S06 in Figure 2 or steps S14-1 and S14-2 in Figure 6, it is found that the overall defect rate of the products has increased, then steps S03-1 and S03-2 in Figure 3 or steps S14-1 and S14-2 in Figure 7 need to be repeated to re-execute the confirmation process of ESD capability level and Vz capability level, confirm the better ESD capability level and Vz capability level, and re-screen the products to prevent NG defective products from flowing into the downstream supply chain.

[0071] Please refer to Table 1 below, which shows a specific embodiment of the LED screening method of the present invention. As shown in Table 1, approximately 72,000 LED chips were subjected to different ESD capability level tests at 2100–2600V, with a reverse current of 100μA and 25V applied. Based on the test results, the NG defect rate after full screening based on ESD, Vz capability level, and photoelectric characteristics ranged from 1.329% to 1.552%, with 959 to 1121 NG defects. In contrast, using a screening method that only assesses general photoelectric characteristics without applying ESD or Vz screening conditions resulted in an NG defect rate of only 0.263% and only 57 NG defects. More specifically, if the products that pass the initial screening are further subjected to three rounds of ESD testing at 2000V to confirm the effectiveness of the initial screening results, Table 1 shows that the defect rate after ESD testing drops significantly to 0.006% to 0.015%, with only 4 to 11 NG defects. In other words, only a very small number of NG defects exist among the products that pass the initial screening. In contrast, the control group without this invention, after further confirmation of the effectiveness of the initial screening results, still shows a defect rate of 1.423% and more than 300 NG defects. Clearly, this invention can effectively screen out NG defects compared to traditional methods, preventing them from entering the downstream supply chain and thus improving the yield of shipped products.

[0072] Table 1

[0073]

[0074] In summary, the LED screening method of this invention can perform rigorous electrostatic discharge and breakdown voltage tests on all LED structures or LED chips before and after splitting. This stringent full inspection procedure comprehensively screens out defective products, reducing the influx of NG chips into subsequent processes and substantially improving production efficiency. It overcomes the problems of traditional screening methods, which are limited to sampling inspection in LED packaging, leading to high missed defect rates and impacting the yield of subsequent supply chain products.

[0075] The above embodiments are merely illustrative of implementation schemes of the present invention and to explain the technical features of the present invention, and are not intended to limit the scope of protection of the present invention. Any changes or equivalent arrangements that can be easily made by those skilled in the art are within the scope of the present invention, and the scope of protection of the present invention should be determined by the claims.

Claims

1. A method for screening light-emitting diodes (LEDs), comprising: providing a wafer having a plurality of LED structures; performing a wafer-level electrostatic discharge (ESD) test on each of the LED structures on the wafer; performing a wafer-level breakdown voltage (LDV) test on each of the LED structures on the wafer; performing a wafer-level photoelectric property (PIP) test on each of the LED structures on the wafer; splitting each of the LED structures on the wafer to form a plurality of LED chips; and excluding LED chips with abnormalities, wherein the abnormality includes one of an ESD test abnormality, a breakdown voltage test abnormality, a PIP test abnormality, and an appearance abnormality.

2. The LED screening method as described in claim 1 further includes a step of half-cutting the wafer before the step of performing wafer-level electrostatic discharge testing, so that multiple dicing channels are formed between adjacent LED structures.

3. The LED screening method as described in claim 1 further includes an electrostatic discharge capability test step before the wafer-level electrostatic discharge test step, wherein an electrostatic discharge capability test is performed on a portion of the LED structure to confirm an electrostatic discharge capability level of that portion of the LED structure.

4. The LED screening method as described in claim 3, wherein the step of performing wafer-level electrostatic discharge testing is to perform the wafer-level electrostatic discharge test on each LED structure according to the electrostatic discharge capability level.

5. The LED screening method as described in claim 1 further includes a step of performing a breakdown voltage capability test before the wafer-level breakdown voltage test, wherein a breakdown voltage capability test is performed on a portion of the LED structure to confirm a breakdown voltage capability level of that portion of the LED structure.

6. The LED screening method as described in claim 5, wherein the step of performing wafer-level breakdown voltage testing is to perform the wafer-level breakdown voltage test on each LED structure according to the breakdown voltage capability level.

7. A method for screening light-emitting diodes (LEDs), comprising: providing a wafer having a plurality of LED structures; splitting each of the LED structures on the wafer to form a plurality of LED dies; performing a grain-level electrostatic discharge (ESD) test on each LED die; performing a grain-level breakdown voltage (LDV) test on each LED die; performing a grain-level photoelectric property (PIP) test on each LED die; and excluding LED dies with abnormalities, wherein the abnormality includes one of an ESD test abnormality, a breakdown voltage test abnormality, a PIP test abnormality, and an appearance abnormality.

8. The light-emitting diode screening method as described in claim 7 further includes a step of half-cutting the wafer before the step of splitting each of the light-emitting diode structures on the wafer, so that multiple cleavage paths are formed between adjacent light-emitting diode structures.

9. The LED screening method as described in claim 7 further includes an electrostatic discharge capability test step before the step of performing a grain-level electrostatic discharge test, wherein a portion of the LED grains are subjected to an electrostatic discharge capability test to confirm an electrostatic discharge capability level of that portion of the LED grains.

10. The light-emitting diode screening method as described in claim 9, wherein the step of performing a grain-level electrostatic discharge test is to perform the grain-level electrostatic discharge test on each of the light-emitting diode grains according to the electrostatic discharge capability level.

11. The LED screening method as described in claim 7 further includes a step of performing a breakdown voltage capability test before the step of performing a grain-level breakdown voltage test, wherein a breakdown voltage capability test is performed on a portion of the LED grains to confirm a breakdown voltage capability level of that portion of the LED grains.

12. The LED screening method of claim 11, wherein the step of performing a grain-level breakdown voltage test is performed on each LED die at the breakdown voltage capability level.

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