Phase interpolator (PI) with clamp circuit to limit operation to range with optimal integral nonlinearity and related methods

Abstract

A phase interpolator (PI) circuit (700) is described that generates an interpolated clock (PICLK) at a target phase in a phase range between two reference clocks to capture data in a capture circuit based on an interpolated code (S) within the interpolated code range. A clamp circuit (704) coupled to the PI circuit provides a reduced range of interpolated codes (S), where an integral nonlinearity (INL) of the interpolated clock is below a threshold such that interpolated clock-based data capture has a lower bit error rate, BER. As a result, an interpolation clock is generated within a reduced phase range corresponding to the reduced interpolation code range. When a target phase for the interpolated clock is outside a reduced phase range, the clamp circuit may adjust a target phase clock (PHAREF) relative to the reference clock to adjust the target phase to within the reduced phase range for improving the BER.

Description

Technical Field

[0001] The technology disclosed herein generally relates to phase interpolators (PIs), and more specifically, to improving the linearity of phase interpolation. Background Technology

[0002] In digital logic circuits, data can be transferred from one sequential logic circuit (e.g., a D flip-flop) to another via combinational logic in each cycle of the system clock signal. The receiving sequential logic circuit captures the data indicated by the voltage level on its inputs in the next clock cycle. If any variation in the clock signal period occurs due to uncertainties (e.g., jitter), the signal may not have enough time to stabilize at the input of the next sequential logic circuit before the next clock signal. Therefore, the clock used to capture the data needs to be synchronized with the data. Data stored in sequential logic circuits can also be provided to other types of circuits, but still requires a clock signal synchronized with the data. In some cases, a clock signal is needed to capture data at an optimal time in each cycle. The optimal time can be any phase of the system clock signal, not just the rising edge that triggers the sequential logic circuit. To generate a clock signal with precise phase, a phase interpolator can be used. A phase interpolator (PI) generates an interpolated clock over a phase range between two reference clocks with different phases (e.g., 0 degrees and 90 degrees), preferably dividing the phase range into equal increments and generating the interpolated clock with the closest increment. In this scenario, the difference between the optimal phase position and the nearest increment might be less than half the increment width. However, phase interpolators implemented in transistor circuits are subject to nonlinearity, causing the divisions between phase increments to be unequal, some too narrow and some too wide. Efforts to improve the linearity of PIs are underway. Summary of the Invention

[0003] Exemplary aspects disclosed herein include a phase interpolator (PI) with clamping circuitry to adjust operation to a finite range of integral nonlinearity. Related methods for adjusting the PI to a finite range of integral nonlinearity are also disclosed. In the clamped PI circuitry, the PI circuitry generates an interpolation clock based on interpolation codes within a range of interpolation codes to capture data in a capture circuitry at a target phase within a phase range between two reference clocks. The target phase of the interpolation clock can be indicated by a target phase clock. The interpolation clock is generated at one of a plurality of phase increments within the phase range closest to the target phase. The clamping circuitry coupled to the PI circuitry provides interpolation codes within a reduced range of interpolation codes, where the integral nonlinearity (INL) of the interpolation clock is below a threshold, resulting in a lower bit error rate (BER) for data capture based on the interpolation clock. As a result, the interpolation clock is generated within a reduced phase range corresponding to the reduced range of interpolation codes. In some examples, when the target phase for the interpolation clock is outside the reduced phase range, the clamping circuitry is configured to adjust the target phase clock relative to the reference clock to bring the target phase within the reduced phase range for improved BER.

[0004] In one exemplary aspect, a clamping phase interpolator is disclosed. The clamping phase interpolator includes a phase interpolator configured to generate an interpolator clock having a first phase within a first phase range based on a first interpolation code within a first interpolation code range. The clamping phase interpolator also includes clamping circuitry configured to receive an indication of a reduced interpolation code range comprising less than the entire first interpolation code range, wherein the reduced interpolation code range corresponds to a reduced phase range comprising a portion of the first phase range, and is further configured to receive a target phase clock having a target phase; and to provide the phase interpolator with the first interpolation code corresponding to the target phase within the reduced interpolation code range.

[0005] In another exemplary aspect, an integrated circuit (IC) is disclosed. The IC includes sequential logic circuitry configured to store data in response to a system clock; capture circuitry configured to receive data from the sequential logic circuitry in response to an interpolator clock in each cycle of the system clock; and a clamping phase interpolator. The clamping phase interpolator includes a phase interpolator configured to generate an interpolator clock having a first phase in a first phase range based on a first interpolation code in a first interpolation code range; and clamping circuitry configured to receive an indication of a reduced interpolation code range, the reduced interpolation code range including less than the entire first interpolation code range, wherein the reduced interpolation code range corresponds to a reduced phase range including a portion of the first phase range; receive a target phase clock having a target phase; and provide the phase interpolator with a first interpolation code corresponding to the target phase in the reduced interpolation code range.

[0006] In another exemplary aspect, a method in a clamped phase interpolator is disclosed. The method includes: generating an interpolator clock having an interpolator phase within a first phase range based on a first interpolation code within a first interpolation code range; and receiving a target phase clock having a target phase. The method further includes: receiving an indication of a reduced interpolation code range, the reduced interpolation code range comprising less than the entire first interpolation code range, wherein the reduced interpolation code range corresponds to a reduced phase range comprising a portion of the first phase range; and providing a first interpolation code corresponding to the target phase within the reduced interpolation code range. Attached Figure Description

[0007] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate several aspects of this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0008] Figure 1A This is a timing diagram illustrating the ideal timing of the first and second reference clocks that can be used in a phase interpolator to generate an interpolated clock with a target phase;

[0009] Figure 1B This is another timing diagram illustrating the non-ideal timing sequence of the first reference clock, the second reference clock, and multiple interpolated clocks, which have a phase between the first reference clock and the second reference clock and have phase increments that are equally divided between the reference clocks;

[0010] Figure 2A This is a radial diagram illustrating reference clocks with the same period but a 90-degree phase difference. Figure 2B This is a timing diagram showing the phase and phase difference of a reference clock in the time domain.

[0011] Figure 3A and Figure 3B This is a schematic diagram of phase interpolator (PI) circuits, which can be used independently or in a summing PI to generate an interpolated clock with improved integral nonlinearity (INL).

[0012] Figure 4A and Figure 4B They are respectively from in Figure 3A and Figure 3B Graphical representation of the INL of the interpolated clock signal generated by the PI circuit in the interpolation code range;

[0013] Figure 4C It is aimed at Figure 3A and Figure 3B The INL of the PI circuit in the middle (except through the PI circuit in the middle) Figure 3A and Figure 3B The graphical representation of the interpolation clock generated by summing the interpolation clocks of the PI circuit (INL);

[0014] Figure 5A This is a second example diagram of the INL of the interpolated clock, which identifies a reduced range of interpolated codes where the INL of the interpolated clock is below the INL threshold and has a lower bit error rate (BER).

[0015] Figure 5B These are two ideal reference clocks that can be used to generate interpolated clocks within a 90-degree phase range, and corresponding to... Figure 5A The timing diagram indicating the reduced phase range of the reduced interpolation code range;

[0016] Figure 6 This is a schematic diagram of IC 600, including a clamping PI circuit configured to provide an interpolated clock with a target phase within a reduced phase range to the capture circuit to capture data received from the sequential logic circuit.

[0017] Figure 7 This is a schematic diagram of a clamping PI circuit, as shown below. Figure 6 As shown, it includes a clamping circuit and a PI circuit, wherein the PI circuit may include a single PI circuit or two PI circuits and a summing circuit;

[0018] Figure 8 This is a flowchart illustrating a method in which a clamped PI circuit is configured to interpolate the clock within a reduced phase range corresponding to a reduced interpolation code range in order to reduce bit errors.

[0019] Figure 9 This is a schematic diagram of a clamping circuit, such as... Figure 7 As shown, the interpolation range of the PI circuit is limited to a reduced range corresponding to the reduced interpolation code range with an INL below a threshold, in order to reduce bit errors; and

[0020] Figure 10 This is a block diagram of an exemplary processor-based system, including a clamped PI circuit with clamping circuitry for limiting the interpolation range of the PI circuit to a reduced range corresponding to a reduced range of interpolated codes having an INL below a threshold, in order to reduce bit errors. Detailed Implementation

[0021] Several exemplary aspects of this disclosure are described with reference to the accompanying drawings. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” should not be construed as being more preferred or advantageous than other aspects.

[0022] Exemplary aspects disclosed herein include a phase interpolator (PI) with clamping circuitry to adjust operation to a finite range of integral nonlinearity. Related methods for adjusting the PI to a finite range of integral nonlinearity are also disclosed. In the clamped PI circuitry, the PI circuitry generates an interpolated clock at one of a plurality of phase increments within a phase range between two reference clocks, based on interpolation codes within a range of interpolation codes. The target phase of the interpolated clock can be indicated by a target phase clock. The clamping circuitry coupled to the PI circuitry provides the PI circuitry with interpolation codes within a reduced range of interpolation codes, wherein the integral nonlinearity (INL) of the interpolated clock is below a threshold. As a result, the interpolated clock is generated within a reduced phase range corresponding to the reduced interpolation code range. In some examples, when the target phase for the interpolated clock is outside the reduced phase range, the clamping circuitry is configured to adjust the target phase clock relative to the reference clocks to bring the target phase within the reduced phase range for minimizing the bit error rate (BER). Figure 1A This diagram shows the timing of two reference clocks, REF1 and REF2, which have the same frequency but a 90-degree phase difference. In this paper, phase is indicated by the presence of a rising edge (voltage step increase) within the clock cycle. In the time domain, the rising edge E1 of reference clock REF1 precedes the rising edge E2 of reference clock REF2 by a time interval T0, where T0 is equal to one-quarter (1 / 4) of the cycle period P0 of reference clocks REF1 and REF2. Therefore, the phase difference (lead) between reference clocks REF1 and REF2 is 90 degrees. Figure 1A Reference clocks REF1 and REF2 are shown to have an ideal (e.g., zero-time) transition from low voltage (e.g., VSS or 0 volts) to high voltage (e.g., VDD) at rising edges E1 and E2. Therefore, within a quarter of the period P0, reference clock REF1 is at a high voltage and reference clock REF2 is at a low voltage.

[0023] Figure 1B This is another timing diagram illustrating the first reference clock REF1 and the second reference clock REF2, with a more realistic (non-ideal) timing representation, showing the voltage step from low to high and back to low over time. The time interval T0 between the reference clock REF1 crossing the threshold voltage V1 and the reference clock REF2 crossing the threshold voltage V1 is...

[0024] Reference clocks REF1 and REF2 can be provided as system clocks to circuitry that captures received data in response to the clock. Typically, neither reference clocks REF1 nor REF2 reaches the optimal phase for data capture within the clock cycle. To address this, a PI circuit can be used to generate an interpolated clock with a phase somewhere between reference clocks REF1 and REF2. The PI circuit, implemented as a digital transistor circuit, can be configured to generate the interpolated clock at one of a plurality of incremental phases between the phases of reference clocks REF1 and REF2. Figure 1B Interpolated clocks 100(0) to 100(N) generated in a digital PI circuit are shown, their phases incrementing equidistantly between reference clocks REF1 and REF2. Figure 1B In this context, the time period T0 is divided into N equal increments, and the duration of each increment is T0 / N.

[0025] If the optimal moment for data capture is somewhere between reference clocks REF1 and REF2, the closest interpolation clock among interpolation clocks 100(0) to 100(N) can be generated to capture the data. An interpolation code can be provided to the PI to select the closest interpolation clock among interpolation clocks 100(0) to 100(N). Using equal division, the difference between the optimal point and the closest interpolation clock among interpolation clocks 100(0) to 100(N) will be less than or equal to half the duration T0 / N (e.g., T0 / 2N). However, due to transistor nonlinearity, generating interpolation clocks 100(0) to 100(N) with equal phase differences is, if not impossible, very difficult, as discussed further below. As a result, interpolation clocks generated in a CMOS PI may not be spaced with equal phase differences.

[0026] Figure 2A This is a radial plot of reference clocks clock_0, clock_90, clock_180, and clock_270, which have the same frequency but are spaced 90 degrees apart. A PI circuit can generate an interpolated clock between any two adjacent reference clocks (e.g., spaced 90 degrees apart). For example, in... Figure 2A In this context, interpolated clock PI_OUT1 can be generated by interpolating between reference clocks clock_0 and clock_90, while interpolated clock PI_OUT2 can be generated by interpolating between reference clocks clock_90 and clock_180. Figure 2B The time domain diagram shows reference clocks clock_0, clock_90, clock_180, and clock_270, as well as interpolated clocks PI_OUT1 and PI_OUT2.

[0027] Figure 3AThis is a schematic diagram of a PI circuit 300A, which is configured to generate an interpolated clock within the range between a first reference clock REF1 and a second reference clock REF2. In this example, the phase difference is 90 degrees. Figures 1A to 2B As shown. It should be understood that the PI circuit 300A is not limited to interpolation between reference clocks with a 90-degree difference. Therefore, in this example, the phase difference between reference clocks REF1 and REF2 can be greater than or less than 90 degrees. Since the PI circuit 300A is known to those skilled in the art, its structural aspects and operation are not described in detail herein, except as follows. The first circuits 302(0) to 302(N-1) and the second circuits 304(0) to 304(N-1) are activated by an interpolation code “S” with N digits. Each of the first circuits 302(0) to 302(N-1) includes P-type transistors 306P1 and 306P2 and N-type transistors 306N1 and 306N2. Each of the second circuits 304(0) to 304(N-1) includes P-type transistors 308P1 and 308P2 and N-type transistors 308N1 and 308N2. Note that the use of N To generate 1 fragment N There are interpolated phases, and these phases are actually related by... N-1 One phase space. N Each phase is typically generated using a reference clock in the next quadrant (e.g., clk_90 and clk_180 if the current inputs are clk_0 and clk_90) and interpolation code 0.

[0028] The first circuits 302(0) to 302(N-1) are based on the reference clock REF1 and the interpolation code S (and the inversion of S, in Figure 3A and 3B The value of the interpolation code S_bar is shown in the figure. In the PI circuit 300A, the voltage of the interpolation clock PI_OA is pulled up or pulled down. The second circuits 304(0) to 304(N-1) pull down or pull up the voltage of the interpolation clock PI_OA based on the value of the reference clock REF2 and the interpolation code S. Therefore, when the reference clock REF1 is high and the reference clock REF2 is low (e.g., in the case of...), the voltage of the interpolation clock PI_OA is pulled up or pulled down. Figure 1A Between E1 and E2), the first circuits 302(0) to 302(N-1) and the second circuits 304(0) to 304(N-1) are pulled in opposite directions. The number of "1"s and "0"s in the interpolation code S determines the number of each of the first circuits 302(0) to 302(N-1) and the second circuits 304(0) to 304(N-1), thus determining the transition timing of the interpolation clock PI_OA. Ideally, as the number of "1"s in the interpolation code S changes, the phase of the interpolation clock PI_OA will shift accordingly. Figure 1BThe phase difference between the time division T0 / N in the interpolation is considered. However, as mentioned above, the transistor switches non-linearly, resulting in unequal phase differences between the interpolated clocks in adjacent interpolation codes S. One measure of the non-linear behavior in the PI circuit 300A is called integral non-linearity (INL).

[0029] In description Figure 3B Before, Figure 4A A graphical representation of the interpolator clock PI_OA in the PI circuit 300A at each phase increment of the phase increment corresponding to the interpolation code S from zero (0) to thirty-two (32). For each value of the interpolation code S (at each time increment). Figure 4A In this context, INL is the difference between the time when the output of the ideal interpolator clock PI_OA will reach the voltage threshold and the measurement time. Ideally, INL will be zero ("0") for all values ​​of the interpolation code S. As the magnitude of this difference (INL) increases, the ability to capture data at the optimal time decreases. Figure 4A In this process, for smaller interpolation codes S (e.g., 0 to 10), the difference in the interpolator clock PI_OA is negative, indicating that the timing difference of the interpolator clock PI_OA for each incremental interpolation code S is initially less than the ideal value. Then the difference in the interpolator clock PI_OA becomes positive, indicating that the timing difference is greater than the ideal value. These differences, whether positive or negative, indicate... Figure 1B The unequal division of the 90-degree phase difference between the reference clocks REF1 and REF2. Although the interpolation code S has thirty-two possible values ​​in the example described herein, any suitable integer number of interpolation codes S can exist.

[0030] Improved INL timing across all interpolation codes S for clock timing that captures data at any phase within the phase interpolation range. Figure 3A Compared to the PI circuit 300A in the first part, one mechanism for improving the INL is to also use a second PI circuit 300B, such as... Figure 3B As shown. If PI circuit 300B receives the same interpolation code S, PI circuit 300B will operate in the same way as PI circuit 300A to generate the interpolated clock PI_OB. However, instead, a different interpolation code T is provided to PI circuit 300B, where T is the sum of the interpolation code S and the offset OFS (e.g., S + OFS). For example, when the interpolation code S is equal to zero ("0") and the offset OFS is set to ten ("10"), the interpolation code T is equal to ten ("10"). Figure 4BThis is a graphical representation of the interpolator clock PI_OB in the PI circuit 300B, from the minimum interpolation code (S=0) to the maximum interpolation code (S=32), which corresponds to the interpolation code T in the range of (+)10 to forty-two (42). When the sum of S+OFS is greater than 32, the interpolation code T is equal to the sum of S+OFS minus the maximum interpolation code (32) (e.g., S+OFS-32).

[0031] As shown in the figure, the interpolated clock generated by PI circuit 300B based on the offset interpolation code T can have an INL that is opposite to that generated by PI circuit 300A. For example, in Figure 4A At position S (5), the INL of the 300A PI circuit is negative, but... Figure 4B The INL of the PI circuit 300B shown is positive.

[0032] You can choose to offset OFS, so that... Figure 4B The polarity of INL in the PI circuit 300B shown is typically consistent with the polarity of INL across the entire interpolation code S range. Figure 4A The INL of the PI circuit 300A shown is opposite. By summing the interpolated clocks from each of the PI circuits 300A and 300B, the resulting interpolated clock can have a significantly better INL than those of the PI circuits 300A and 300B. Figure 4C The single diagram shows the INL 400A of PI circuit 300A at each phase increment, the INL 400B of PI circuit 300B at each phase increment, and the INL 400C of the summation interpolation clock PI_CLK, formed by summing the interpolation clock PI_OA of PI circuit 300A and the interpolation clock PI_OB of PI circuit 300B, at each phase increment. The PI circuit configured in this manner is related to... Figure 6 and Figure 7 The amplitude of the INL 400C of the summation interpolation clock PI_CLK is typically smaller than that of the interpolation clocks PI_OA and PI_OB for most of the range. However, in certain portions of the entire interpolation code range (0-X), for example, INL 400C can still reach above-acceptable amplitudes. This is achieved by limiting the interpolation code S used for data capture to a preferred range (e.g., Figure 4C The preferred range (0 to 7 or 15 to 23) corresponds to a portion of the phase range of PI circuits 300A and 300B, which can limit INL 400C to a smaller value.

[0033] in this regard, Figure 5AThis is a diagram of interpolation codes 500(0) to 500(X) (X=32 in this example) and the corresponding INLs 504(0) to 504(X). This is another example of an interpolation clock PI_CLK, which could be the interpolation clock PI_OA of a PI circuit 300A, or it could be as follows: Figure 4C The clock signal is generated by summing the interpolated clock signals PI_OA of PI circuit 300A and PI_OB of PI circuit 300B. Figure 3A and Figure 3B The interpolation code S in the interpolation code can be any interpolation code from 500(0) to 500(X). Figure 5A The examples in can be based on and Figure 4C Different code offsets OFS are used in the interpolation. In this example, INL 504(0) to 504(2) are within the maximum acceptable INL amplitude (positive and negative), referred to as the INL threshold 502. Above the maximum interpolation code value 500 (S_THRES) (also referred to as “S_THRES” in this document), in this example S_THRES=20, INL 504(21) is greater than the INL threshold 502, which means that the data captured by the interpolation clock PI_CLK (or PI_OA) is likely to be erroneous due to the timing difference between the interpolation clock PI_CLK (or PI_OA) and the ideal phase increment. The reduced phase range RPR is achieved by using only the interpolation codes 500(0) to 500(20) to generate the interpolation clock PI_CLK.

[0034] Figure 5B This is a timing diagram of reference clocks REF1 and REF2 at reference phases PH_0 and PH_90, with a 90-degree phase difference as an example. Reference clocks REF1 and REF2 can be referred to as adjacent reference clocks. Similarly, reference clocks REF2 and REF3 (not shown) are adjacent reference clocks with rising edges at reference phases PH_90 and PH_180, respectively. Figure 5B The threshold S_THRES is identified as the maximum interpolation code 500(S_THRES) of the reduced interpolation code range 500(0) to 500(S_THRES) (e.g., S_THRES=20), where INL 504(0) to 504(S_THRES) is less than or equal to the INL threshold 502. Figure 5B The ideal interpolated clock PI_O is shown at the interpolated code 500(0) to 500(X) corresponding to the interpolated code 500(0) to the interpolated code 500(20). Figure 5BA first example is also included, with a target phase clock PHA_CLK1 having a rising edge RE1 within the phase range between phases PH0 and PH90. However, the rising edge RE1 is not within the reduced phase range RPR corresponding to the reduced interpolation code range 500(0) to 500(S_THRES). Since it has been determined that most of the INLs from INL 504(21) to 504(32) exceed the INL threshold 502, where the BER is high, those codes will not be used. In other words, in this example, an interpolation code 500(S) greater than 20 (S>S_THRES) is required (where the BER can be unacceptable) to generate the interpolation clock at the rising edge RE1.

[0035] However, the timing of the target phase clock PHA_CLK1 relative to the reference clocks REF1 and REF2 can be adjusted. For example, the target phase clock PHA_CLK1 can be generated from the target phase reference PHA_REF (not shown), which is delayed by a first delay. In this respect, Figure 5B A second example of a target phase clock PHA_CLK2 is shown, which can be generated from a target phase reference PHA_REF delayed by a second delay (shorter than the first delay). The phase of the (rising edge) adjusted target phase clock PHA_CLK2 is within a reduced phase range RPR corresponding to the reduced interpolation code range 500(0) to 500(20). Therefore, by reducing the first delay used to generate the target phase clock PHA_CLK1 to the second delay used to generate the target phase clock PHA_CLK2, it is possible to generate an interpolation clock PI_CLK based on one of the interpolation codes 500(S) within the reduced interpolation code range 500(0) to 500(S_THRES) RPR, where INL 504(1) to 504(20) are less than the INL threshold 502.

[0036] Figure 6This is a schematic diagram of IC 600, including sequential logic circuitry 602 configured to receive and store data. Sequential logic circuitry 602 receives data D1 at data input IN1 and stores data D2 on output Q1. In response to transitions (e.g., rising edges) in each cycle of the system clock CLK, data D1 is propagated through sequential logic circuitry 602 and stored as data D2 on output Q1. IC 600 also includes capture circuitry 604, which receives data D2 at data input IN2. Capture circuitry 604 captures data D2 in response to interpolation clock PI_CLK and propagates data D2 to output TXD. System clock CLK and interpolation clock PI_CLK are periodic clocks operating at the same frequency F1. For example, interpolation clock PI_CLK can be timed to arrive at capture circuitry 604 at a clock phase corresponding to the optimal phase for capturing data D2 on data input IN2 with minimal error chance. In this example, system clock CLK is provided by clock circuitry 606 on IC 600. In some examples, the system clock CLK can be provided to IC 600 from external circuitry. The interpolation clock PI_CLK is provided to the capture circuit 604 by a clamp phase interpolator (PI) circuit 608. The clamp PI circuit 608 receives reference clocks CLK_0, CLK_90, CLK_180, and CLK_270, which are transitioned at frequency F1 at respective reference phases PH_0, PH_90, PH_180, and PH_270, spaced 90 degrees apart. The clamp PI circuit 608 also receives a target phase clock PHA_REF indicating the target phase for capturing data D2 at data input IN2. For example, the target phase is indicated by a transition of the target phase clock PHA_CLK, which can occur between the reference phase PH_0 of reference clock CLK_0 and the reference phase PH_90 of reference clock CLK_90. The target phase can also be between the reference phase PH_90 of reference clock CLK_90 and the reference phase PH_180 of reference clock CLK_180, between the reference phase PH_180 of reference clock CLK_180 and the reference phase PH_270 of reference clock CLK_270, or between the reference phase PH_270 of reference clock CLK_270 and the reference phase PH_0 of reference clock CLK_0.

[0037] The conversion of the target phase clock PHA_CLK is not directly used to capture data D2 at capture circuit 604, but rather to indicate the timing at which such capture should occur. Clamping PI circuit 608 is configured to generate an interpolated clock PI_CLK that is as close as possible to the phase of the target phase clock PHA_CLK by interpolation between two adjacent reference clocks. In this context, the term "adjacent reference clocks" refers to any two reference clocks CLK_0, CLK_90, CLK_180, and CLK_270 that have reference phases PH_0, PH_90, PH_180, and PH_270 separated by 90 degrees, such as reference clock CLK_0 and reference clock CLK_90. As described above, in an ideal PI circuit, clocks can be interpolated at any phase of multiple phases based on interpolation codes. The multiple phases are separated by equal phase increments, and the interpolated phase that is closest to the target phase of clock PHA_CLK among the interpolated phases is generated as the interpolated clock PI_CLK.

[0038] Figure 7 This is a schematic diagram of a clamping PI circuit (“clamping PI”) 700, including PI 702 and clamping circuit 704. PI 702 can be configured as a single PI circuit 706A to generate an interpolation clock PI_CLK based on interpolation code S. Alternatively, PI 702 can be configured as a second PI circuit 706B and a summing circuit 708. PI circuits 706A and 706B can be… Figure 3A and Figure 3B The PI circuits 300A and 300B are described. In this alternative, PI circuit 706A receives interpolation code S from clamping circuit 704, and PI circuit 706B receives interpolation code S+OFS equal to interpolation code S plus offset OFS. Offset OFS is also provided to clamping circuit 704. PI circuit 706A receives two adjacent reference clocks CLOCK_A and CLOCK_B. PI circuit 706B receives two adjacent reference clocks CLOCK_C and CLOCK_D. Reference clocks CLOCK_A to CLOCK_D can be selected by clamping circuit 704 from multiple reference clocks. Reference clock CLOCK_C can be either reference clock CLOCK_A or reference clock CLOCK_B. For example, reference... Figure 6 The described reference clocks CLK_0 and CLK_90 can be provided as reference clocks CLOCK_A and CLOCK_B. In this example, reference clock CLOCK_C can be reference clock CLK_0 at reference phase PH_0 or reference clock CLK_90 at reference phase PH_90, and reference clock CLOCK_D will be reference clock CLK_90 at reference phase PH_90 or reference clock CLK_180 at reference phase PH_180.

[0039] The clamping circuit 704 also receives an indication S_THRES of a reduced interpolation code range S, within which the interpolation clock PI_CLK has an INL below the INL threshold, as described above. The clamping circuit 704 also receives a target phase clock PHA_CLK. The interpolation clock PI_CLK generated by the PI circuit 706A or the summing circuit 708 is provided to... Figure 6 The capture circuit 604 is provided as feedback to the clamping circuit 704. Additionally, the clamping circuit 704 also receives control signals EN and RST for enabling and resetting portions of the clamping circuit 704.

[0040] Figure 8 This is a flowchart illustrating method 800 in a clamped phase interpolator. Method 800 includes generating an interpolator clock PI_CLK (block 802) having an interpolator phase in a first phase range based on interpolation code 500(S) in a first interpolation code range 500(0) to 500(X). The method includes receiving an indication of a reduced interpolation code range 500(0) to 500(S_THRES), the reduced interpolation code range including less than the entire first interpolation code range 500(0) to 500(X), wherein the reduced interpolation code range 500(0) to 500(S_THRES) corresponds to a reduced phase range RPR that includes a portion of the first phase range (block 804). Method 800 includes receiving a target phase clock PHA_CLK having a target phase (block 806) and providing interpolation codes corresponding to the target phase in the reduced interpolation code range 500(0) to 500(S_THRES) (block 808). Optionally, method 800 may further include adjusting the target phase of the target phase clock PHA_CLK relative to the first reference clock CLOCK_A so that it is within a reduced phase range RPR (box 810).

[0041] Figure 9 This is a schematic diagram of clamping circuit 900, which can be... Figure 7 The clamping circuit 704 is described below. Figure 9 The description of the middle clamping circuit 900 also includes... Figure 7 Feature reference. Clamping circuit 900 receiver. Figure 7 The summation interpolation clock PI_CLK and the target phase reference PHA_REF are generated in PI 702. The clamping circuit 900 includes a phase detector 902, which compares the phase of the summation interpolation clock PI_CLK with the phase of the target phase reference PHA_REF and generates a phase difference S_BIN, which is a multi-bit value. The phase detector 902 gradually increases or decreases the phase difference S_BIN. The phase difference S_BIN can be reset to its initial value by the reset signal RST.

[0042] The phase difference S_BIN comprises a more significant bit (MSB) 904 and a less significant bit (LSB) 906. LSB 906 changes in response to a change in the phase difference detected by phase detector 902. Therefore, a change in LSB 906 adjusts the phase of the interpolated clock PI_CLK.

[0043] Clamping circuit 900 receives an indication S_THRES of the reduced interpolation code range 500(0) to 500(S_THRES). (Refer to...) Figure 5B In the described example, a PI circuit (e.g.) Figure 7 The interpolation code range used in PI 702 can extend from the minimum interpolation code 500 (0) of zero (0) to the first maximum interpolation code 500 (X) of thirty-two (32). In this example, the indicator S_THRES is twenty (20), indicating a reduced interpolation code range from the minimum interpolation code of zero (0) to the second maximum interpolation code of twenty (20). To convert the interpolation code S to PI 702 (which includes Figure 3A and Figure 3B The clamping circuit 900, available in the form of PI circuits 300A and 300B, includes a binary-to-thermometer decoder 908. The decoder 908 receives LSB 906 and generates a reference... Figure 5A and Figure 5B The interpolation codes 500(0) to 500(S_THRES) are described and provided to PI 702.

[0044] LSB 906 identifies the interpolation code required to set the phase of the interpolation clock PI_CLK to the target phase indicated by the target phase clock PHA_CLK. Comparator 910 compares LSB 906 with indicator S_THRES to determine whether the interpolation code S generated by phase detector 902 is outside the reduced interpolation code range indicated by indicator S_THRES. If the determined interpolation code is outside the reduced interpolation code range (e.g., 500(0) to 500(X)), delay setting 912 can be adjusted to adjust the phase difference between the target phase of the target phase clock PHA_CLK and the interpolator phase of PI_CLK. Delay setting 912 is activated by enable signal EN. Delay setting 912 controls delay circuitry 914 that receives the target phase reference PHA_REF and generates the target phase clock PHA_CLK. In this respect, delay circuitry 914 can be used to adjust the target phase of the target phase clock PHA_CLK relative to the first reference clock CLOCK_A so that it is within the reduced phase range corresponding to the reduced interpolation code range S. Alternatively, delay setting 912 can be used to adjust the delay of the delay circuits providing reference clocks CLOCK_A, CLOCK_B, CLOCK_C, and CLOCK_D to adjust the target phase of the target phase clock PHA_CLK relative to the first reference clock CLOCK_A.

[0045] If the LSB 906 indicates that the interpolation code 500(S) is less than the indication S_THRES, then the target phase of the target phase clock PHA_CLK is within a reduced phase range corresponding to the reduced interpolation code range (e.g., 500(0) to 500(S_THRES)), which further indicates that the target phase of the target phase clock PHA_CLK is between the phase of the reference clock CLOCK_A and the phase of the reference clock CLOCK_B.

[0046] In some examples, due to the code offset OFS employed in the clamping circuit 900, the first PI circuit 706A can receive reference clock CLK_0 as reference CLOCK_A and reference clock CLK_90 as reference CLOCK_B, and the second PI circuit 706B can receive reference clock CLK_90 as reference CLOCK_C and reference clock CLK_180 as reference clock CLOCK_D. Examples can occur because a first portion of the reduced phase range lies between reference phase PH_0 and reference phase PH_90, and a second portion of the reduced reference phase lies between reference phase PH_90 and reference phase PH_180. In this regard, the clamping circuit 900 includes a selection circuit 916, which includes selectors 918A and 918B, for selecting one of the reference clocks CLK_0, CLK_90, CLK_180, and CLK_270 as reference clocks CLOCK_A, CLOCK_B, CLOCK_C, and CLOCK_D. Each PI circuit in PI circuits 706A and 706B receives two adjacent reference clocks (i.e., with a 90-degree phase difference). Selectors 918A and 918B are controlled by an MSB 904 generated in phase detector 902. Specifically, selector 918A can be directly controlled by MSB 904, while selector 918B can be controlled by an MSB 904 modified with a code offset OFS. In selection circuit 916, calculation circuit 920 determines the interpolation code S+OFS based on the code offset OFS and LSB 906. Modulus calculation block 922 controls selector 918B based on the code offset OFS, LSB 906, and MSB 904.

[0047] Figure 10This is a block diagram of an exemplary processor-based system 1000, including a processor 1002 (e.g., a microprocessor) that includes instruction processing circuitry 1004. The processor-based system 1000 may be one or more circuits included in an electronic board (e.g., a printed circuit board (PCB), server, personal computer, desktop computer, laptop computer, personal digital assistant (PDA), computing tablet, mobile device, or any other device), and may represent, for example, a server or a user's computer. In this example, the processor-based system 1000 includes a processor 1002. The processor 1002 represents one or more general-purpose processing circuits, such as a microprocessor, central processing unit, etc. More specifically, the processor 1002 may be an EDGE instruction set microprocessor or another processor that implements an instruction set that supports explicit consumer naming for communication of values ​​produced from the execution of producer instructions. The processor 1002 is configured to execute processing logic in instructions for performing the operations and steps discussed herein. In this example, the processor 1002 includes an instruction cache 1006 for temporary, fast access to a memory store of instructions accessible by the instruction processing circuitry 1004. Instructions fetched or prefetched from memory (such as main memory 1008) via system bus 1010 are stored in instruction cache 1006. Data may be stored in cache memory 1012 coupled to system bus 1010 for low-latency access by processor 1002. Instruction processing circuitry 1004 is configured to process the instructions fetched into instruction cache 1006 and process these instructions for execution.

[0048] Processor 1002 and main memory 1008 are coupled to system bus 1010 and can be mutually coupled to peripheral devices included in the processor-based system 1000. It is well known that processor 1002 communicates with these other devices by exchanging address, control, and data information via system bus 1010. For example, processor 1002 can communicate bus transaction requests to memory controller 1014 in main memory 1008, as an example of a slave device. Although in Figure 10 Not shown, but multiple system buses 1010 may be provided; each system bus 1010 constitutes a different structure. In this example, memory controller 1014 is configured to provide memory access requests to memory array 1016 in main memory 1008. Memory array 1016 consists of an array of storage bit cells for storing data. Main memory 1008 may be read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (such as synchronous DRAM (SDRAM)), and / or static memory (e.g., flash memory, SRAM), as a non-limiting example.

[0049] Other devices can be connected to system bus 1010. For example... Figure 10 As illustrated, these devices, by way of example, may include main memory 1008, one or more input devices 1018, one or more output devices 1020, modem 1022, and one or more display controllers 1024. Input devices 1018 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. Output devices (multiple) 1020 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. Modem 1022 may be any device configured to allow data exchange to or from network 1026. Network 1026 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), and bluetext. TM Networks and the Internet. Modem 822 can be configured to support any type of desired communication protocol. Processor 1002 can also be configured to access multiple display controllers 1024 via system bus 1010 to control information sent to one or more displays 1028. The multiple displays 1028 can include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, etc.

[0050] Figure 10 The processor-based system 1000 may include an instruction set 1030 for execution by the processor 1002 for any desired application according to the instructions. The instructions 1030 may be stored, as an example, in main memory 1008, the processor 1002, and / or the instruction cache 1006 as a non-transitory computer-readable medium 1032. The instructions 1030 may also reside wholly or at least partially in main memory 1008 and / or the processor 1002 during their execution. The instructions 1030 may also be transmitted or received via a network 1026 through a modem 1022, such that the network 1026 includes the computer-readable medium 1032.

[0051] Any circuitry in the processor-based system 1000, particularly the modem 1022 and output device 1020, may include multiple clock domains, each including a calibrated DPLL. This calibrated DPLL includes feedback circuitry configured to calibrate the resolution of the TDC to the nominal resolution in a closed-loop approach, thereby normalizing the response in the DPLL across multiple clock domains of the IC, as shown in Figure 3. Figure 4A and Figure 4B As shown.

[0052] Although computer-readable medium 1032 is shown as a single medium in the exemplary embodiments, the term "computer-readable medium" should be understood to include a single medium or multiple media (e.g., a centralized or distributed database and / or associated caches and servers) storing one or more instruction sets. The term "computer-readable medium" should also be understood to include any medium capable of storing, encoding, or carrying instruction sets for use by a processing device and causing the processing device to perform any one or more methods of the embodiments disclosed herein. Therefore, the term "computer-readable medium" should be understood to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0053] The embodiments disclosed herein include various steps. These steps may be formed by hardware components or embodied in machine-executable instructions that can be used to cause a general-purpose or special-purpose processor programmed with those instructions to perform these steps. Alternatively, these steps may be performed by a combination of hardware and software.

[0054] The embodiments disclosed herein may be provided as a computer program product or software, which may include a machine-readable medium (or computer-readable medium) having instructions stored thereon, which can be used to program a computer system (or other electronic device) to perform processes according to the embodiments disclosed herein. A machine-readable medium includes any mechanism for storing or transmitting information in a machine-readable (e.g., computer-readable) form. For example, a machine-readable medium includes machine-readable storage media (e.g., ROM, random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.).

[0055] Unless otherwise stated and apparent from the above discussion, it should be understood that throughout the description, discussions using terms such as “processing,” “computing,” “determining,” and “displaying” refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data and memory represented as physical (electronic) quantities within computer system registers into other data similarly represented as physical quantities within computer system memory or registers or other such information storage, transmission, or display devices.

[0056] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various systems can be used with programs based on the teachings herein, or it may be convenient to construct more specialized devices to perform the required method steps. The required structures for various such systems will emerge from the above description. Furthermore, the embodiments described herein are not referred to in any particular programming language. It should be understood that the teachings of the embodiments described herein can be implemented using various programming languages.

[0057] Those skilled in the art will further understand that the various illustrative logic blocks, modules, circuits, and algorithms described in conjunction with the embodiments disclosed herein can be implemented as electronic hardware, stored in memory or another computer-readable medium, and executed by a processor or other processing device, or a combination of both. The memory disclosed herein can be of any type and size and can be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How this functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the system as a whole. Those skilled in the art can implement the described functionality in different ways for each specific application, but such implementation decisions should not be construed as causing a departure from the scope of these embodiments.

[0058] The various illustrative logic blocks, modules, and circuits described in conjunction with the embodiments disclosed herein can be implemented or executed using a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to implement the functions described herein. Furthermore, the controller can be a processor. The processor can be a microprocessor, but alternatively, the processor can be any conventional processor, controller, microcontroller, or state machine. The processor can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0059] The embodiments disclosed herein can be embodied in hardware and instructions stored in the hardware, and can reside in, for example, RAM, flash memory, ROM, electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium can be integrated with the processor. The processor and storage medium can reside in an ASIC. The ASIC can reside in a remote station. Alternatively, the processor and storage medium can reside as discrete components in a remote station, base station, or server.

[0060] It should also be noted that the operational steps described in any exemplary embodiment herein are described as being for the purpose of example and discussion. The described operations can be performed in many different sequences besides the illustrated sequence. Furthermore, the operations described in a single operational step can actually be performed in multiple different steps. Additionally, one or more operational steps discussed in the exemplary embodiments can be combined. Those skilled in the art will also understand that information and signals can be represented using any of a variety of techniques and technologies. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields, light fields, particles, or any combination thereof.

[0061] Unless otherwise expressly stated, it is not intended to interpret any method described herein as requiring its steps to be performed in a particular order. Therefore, no particular order is intended to be inferred where the method claims do not actually describe the order in which the steps are to be followed, or where the claims or description do not otherwise specifically specify that these steps are to be limited to a particular order.

[0062] It will be apparent to those skilled in the art that various modifications and variations can be made without departing from the spirit or scope of the invention. Since modifications, combinations, sub-combinations, and variations of the disclosed embodiments that embody the spirit and essence of the invention will be conceived by those skilled in the art, the invention should be interpreted as encompassing all contents within the scope of the appended claims and their equivalents.

Claims

1. A clamping phase interpolator (700), comprising: A phase interpolator (706A) configured to generate an interpolator clock (PI_CLK) having a first phase in a first phase range based on a first interpolation code (S) in a first interpolation code range (S(0) to S(N)); and Clamping circuit (704), the clamping circuit being configured to: Receive an indication of a reduced interpolation code range (S_THRES), the reduced interpolation code range comprising less than the entirety of the first interpolation code range (S(0) to S(N)), wherein the reduced interpolation code range corresponds to a reduced phase range comprising a portion of the first phase range; Receive the target phase clock (PHA_REF) with the target phase; and The phase interpolator (706A) is provided with the first interpolation code (S) corresponding to the target phase in the reduced interpolation code range.

2. The clamping phase interpolator of claim 1, further configured to adjust the target phase clock relative to a first reference clock to adjust the target phase into the reduced phase range.

3. The clamping phase interpolator of claim 2, wherein the clamping circuit is further configured to adjust the target phase of the target phase clock based on the phase difference between the target phase and the interpolator phase.

4. The clamping phase interpolator according to claim 2, wherein the reduced phase range is between a first reference phase of the first reference clock and a second reference phase of the second reference clock.

5. The clamping phase interpolator of claim 1, wherein the first portion of the reduced phase range is between a first reference phase of the first reference clock and a second reference phase of the second reference clock, and the second portion of the reduced phase range is not between the first reference phase of the first reference clock and the second reference phase of the second reference clock.

6. The clamping phase interpolator of claim 2, wherein the clamping circuit is further configured to adjust the delay of the delay circuit, the delay circuit being configured to provide the target phase clock.

7. The clamping phase interpolator of claim 2, wherein the clamping circuit is further configured to adjust the delay of the delay circuit, the delay circuit being configured to provide the first reference clock.

8. The clamping phase interpolator of claim 1, wherein the clamping circuit is further configured to adjust the first interpolation code based on the phase difference between the target phase and the interpolator phase.

9. The clamping phase interpolator of claim 2, wherein the clamping circuit is further configured to select the first reference clock from a plurality of reference clocks at the first frequency based on the target phase.

10. The clamping phase interpolator according to claim 1, wherein: The first phase range extends from the minimum interpolation code to the first maximum interpolation code; The indication of the reduced interpolation code range includes a second maximum interpolation code that is smaller than the first maximum interpolation code; and The reduced range of interpolation codes extends from the minimum interpolation code to the second maximum interpolation code.

11. The clamping phase interpolator of claim 10, wherein the phase interpolator comprises: A first phase interpolation circuit is configured to generate a first interpolated clock having a second phase between a first reference phase of a first reference clock and a second reference phase of a second reference clock, wherein the first phase is based on the first interpolation code. A second phase interpolation circuit is configured to generate a second interpolation clock based on a second interpolation code having a third phase between a third reference phase of a third reference clock and a fourth reference phase of a fourth reference clock, the second interpolation code comprising the sum of the first interpolation code and a code offset; and A summing circuit configured to generate the interpolator clock having the first phase between the second phase of the first interpolation clock and the third phase of the second interpolation clock.

12. The clamping phase interpolator of claim 11, wherein the sum of the first interpolation code and the code offset is less than or equal to the second maximum interpolation code: The second interpolation code includes the above and; The third reference clock includes the first reference clock; and The fourth reference clock includes the second reference clock.

13. The clamping phase interpolator of claim 11, wherein the sum of the first interpolation code and the code offset is greater than the second maximum interpolation code: The second interpolation code includes the sum minus the first maximum interpolation code; and The third reference clock includes the second reference clock.

14. An integrated circuit (IC) (600), comprising: A sequential logic circuit (602) is configured to store data (D2) in response to a system clock (CLK). A capture circuit (604) is configured to receive the data (D2) from the timing logic circuit (602) in each cycle of the system clock (CLK) in response to the interpolator clock (PI_CLK). as well as Clamping phase interpolators (608, 700) include: A phase interpolator (706A), configured to generate an interpolator clock (PI_CLK) having a first phase in a first phase range based on a first interpolation code (S) in a first interpolation code range (S(0) to S(N)); and The clamping circuit (704) is configured as follows: Receive an indication (S_THRES) of a reduced interpolation code range, the reduced interpolation code range comprising less than the entire first interpolation code range, wherein the reduced interpolation code range corresponds to a reduced phase range comprising a portion of the first phase range; Receive the target phase clock (PHA_REF) with the target phase. The phase interpolator (706A) is provided with the first interpolation code (S) corresponding to the target phase in the reduced interpolation code range.

15. The IC of claim 14, wherein the clamping circuit is further configured to adjust the target phase of the target phase clock relative to a first reference clock to be within the reduced phase range.

16. The IC of claim 15, wherein the clamping circuit is further configured to adjust the delay to change the timing of the first reference clock.

17. The IC of claim 14, wherein the clamping circuit is further configured to adjust the first interpolation code based on the phase difference between the target phase and the interpolator phase.

18. The IC of claim 14, wherein the clamping circuit is further configured to adjust the target phase of the target phase clock relative to a first reference clock and a second reference clock based on the phase difference between the target phase and the interpolator phase.

19. The IC according to claim 14, wherein: The range of the first interpolation code extends from the minimum interpolation code to the first maximum interpolation code; The indication of the reduced interpolation code range includes a second maximum interpolation code that is within the first interpolation code range and smaller than the first maximum interpolation code; and The reduced range of interpolation codes extends from the minimum interpolation code to the second maximum interpolation code.

20. A method in a clamped phase interpolator (700), comprising: Based on the first interpolation code (S) in the first interpolation code range (S(0) to S(N)), an interpolator clock (PI_CLK) with an interpolator phase in the first phase range is generated. Receive the target phase clock (PHA_REF) with the target phase. Receive an indication (S_THRES) of a reduced interpolation code range, the reduced interpolation code range comprising less than the entirety of the first interpolation code range, wherein the reduced interpolation code range corresponds to a reduced phase range comprising a portion of the first phase range; and Provide the first interpolation code (S) corresponding to the target phase within the reduced interpolation code range.

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