Semiconductor device and memory device

Abstract

A novel semiconductor device is provided. The semiconductor device includes first to third transistors each including a gate, a first terminal of the first transistor electrically connected to a first electrode of the first capacitor and a gate of the third transistor, and a second terminal of the second transistor electrically connected to a second electrode of the third transistor. A first terminal of the second transistor is electrically connected to a second terminal of the first transistor and a first electrode of the second capacitor, gates of the first transistor and the second transistor are electrically connected to each other, and second electrodes of the first capacitor and the second capacitor are electrically connected to each other.

Description

Semiconductor devices and memory devices Technical Field

[0001] One aspect of the present invention relates to a semiconductor device and a memory device.

[0002] Note that one aspect of the present invention is not limited to the aforementioned technical fields. The technical fields of the invention disclosed in this specification relate to an object, method, or manufacturing method. Furthermore, one aspect of the present invention relates to a process, machine, manufacture, or composition of matter.

[0003] Therefore, examples of the technical field according to one aspect of the present invention include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, energy storage devices, imaging devices, storage devices, signal processing devices, processors, electronic devices, systems, their driving methods, their manufacturing methods, their inspection methods, or their usage methods. Background Technology

[0004] In recent years, research and development has been conducted on semiconductor devices such as LSI (Large Scale Integration), CPU (Central Processing Unit), and memory (storage devices). These semiconductor devices are used in various electronic devices such as computers and portable information terminals. Furthermore, various memory types are being developed to meet different needs, such as temporary storage during computation and long-term data storage. Typical memory types include DRAM, SRAM, and flash memory.

[0005] Furthermore, it is known that metal oxide transistors (hereinafter also referred to as "OS transistors") are used as the semiconductor layer in which the channel is formed. Because the off-state current of an OS transistor is very small, using an OS transistor as a write transistor for a memory cell can provide a memory cell with excellent retention characteristics. For example, Non-Patent Document 1 discloses a NOSRAM (registered trademark) using an OS transistor.

[0006] [Prior Technology Literature][Non-Patent Literature][Non-Patent Literature 1] T. Matsuzaki et al., “A 128kb 4bit / Cell Nonvolatile Memory with Crystalline In-Ga-Zn Oxide FET Using Vt Cancel Write Method,” ISSCC Dig. Tech. Papers, 2015, pp. 306-307. Summary of the Invention

[0007] Furthermore, the technical problem this invention aims to solve is that the off-state current of transistors tends to increase at high temperatures, making it difficult to retain data written into semiconductor devices used as memory cells. Therefore, the retention characteristics of semiconductor devices used as memory cells may deteriorate at high temperatures.

[0008] One objective of this invention is to provide a semiconductor device whose characteristics do not easily deteriorate even at high temperatures. Furthermore, one objective of this invention is to provide a highly reliable semiconductor device. Additionally, one objective of this invention is to provide a semiconductor device with low power consumption. Furthermore, one objective of this invention is to provide a novel semiconductor device.

[0009] Note that the description of the above objectives does not preclude the existence of other objectives. Other objectives are readily apparent from the description, drawings, and claims, and can be extracted from these descriptions. One embodiment of the invention does not necessarily require the achievement of all of the above objectives (the above objectives and others).

[0010] Means for solving technical problems (1) One aspect of the present invention is a semiconductor device comprising: a first to a third transistor; a first capacitor; and a second capacitor, wherein the first to the third transistor each includes a gate, a first terminal and a second terminal, the first terminal of the first transistor is electrically connected to the first electrode of the first capacitor and the gate of the third transistor, the first terminal of the second transistor is electrically connected to the second terminal of the first transistor and the first electrode of the second capacitor, the gates of the first transistor and the second transistor are electrically connected to each other, and the second electrodes of the first capacitor and the second capacitor are electrically connected to each other.

[0011] In (1), for example, the gates of the first transistor and the second transistor are electrically connected to the first wiring, the second terminal of the second transistor is electrically connected to the second wiring, the first terminal of the third transistor is electrically connected to the third wiring, the second terminal of the third transistor is electrically connected to the fourth wiring, and the second electrode of the first capacitor and the second capacitor is electrically connected to the fifth wiring.

[0012] In (1), both the first transistor and the second transistor preferably contain oxide semiconductor in the semiconductor layer forming the channel. Furthermore, vertical transistors can be used as the first and second transistors. Additionally, the third transistor preferably contains silicon in the semiconductor layer forming the channel. Furthermore, a Fin-type transistor can be used as the third transistor.

[0013] (2) Another aspect of the present invention is a semiconductor device comprising n (n is an integer greater than or equal to 3) first transistors, second transistors and n capacitors, wherein each of the n first transistors and second transistors includes a gate, a first terminal and a second terminal, the first terminal of the first first transistor is electrically connected to the first electrode of the first capacitor and the gate of the second transistor, the first terminal of the i-th (i is an integer greater than or equal to 2 and less than or equal to n-1) first transistor is electrically connected to the second terminal of the (i-1)-th first transistor and the first electrode of the i-th capacitor, the first terminal of the n-th first transistor is electrically connected to the second terminal of the (n-1)-th first transistor and the first electrode of the n-th capacitor, the gates of the n first transistors are electrically connected to each other, and the second electrodes of the n capacitors are electrically connected to each other.

[0014] In (2), the gates of the n first transistors are electrically connected to the first wiring, the second terminal of the nth first transistor is electrically connected to the second wiring, the first terminal of the second transistor is electrically connected to the third wiring, the second terminal of the second transistor is electrically connected to the fourth wiring, and the second electrode of the n capacitors is electrically connected to the fifth wiring.

[0015] In (2), it is preferable that the semiconductor layer forming the channel of the first transistor contains an oxide semiconductor. Furthermore, it is preferable that the semiconductor layer forming the channel of the second transistor contains silicon.

[0016] Another aspect of the present invention is a storage device comprising a storage cell array having a plurality of semiconductor devices as described in (1) or (2) and peripheral circuitry having the function of writing data to the storage cell array and reading data from the storage cell array.

[0017] According to one aspect of the present invention, a semiconductor device whose properties are not easily degraded even at high temperatures can be provided. Furthermore, a semiconductor device with high reliability can be provided. Furthermore, a semiconductor device with low power consumption can be provided. Furthermore, a novel semiconductor device can be provided.

[0018] Note that the description of the above effects does not preclude the existence of other effects. Other effects are readily apparent from the description, drawings, and claims, and can be extracted from these descriptions. One embodiment of the invention does not necessarily require all of the above-described effects (the above-described effects and other effects). Attached Figure Description

[0019] Brief Description of the Drawings: Figures 1A to 1D are diagrams illustrating examples of circuit structures for semiconductor devices.

[0020] Figure 2 is a graph showing the relationship between the operating environment temperature and the off-state current of a semiconductor device.

[0021] Figures 3A and 3B are three-dimensional schematic diagrams illustrating examples of the structure of a semiconductor device.

[0022] Figures 4A and 4B are diagrams illustrating examples of circuit structures for semiconductor devices.

[0023] Figures 5A and 5B are diagrams illustrating examples of circuit structures for semiconductor devices.

[0024] Figures 6A and 6B are diagrams illustrating examples of circuit structures for semiconductor devices.

[0025] Figures 7A and 7B are diagrams illustrating examples of circuit structures for semiconductor devices.

[0026] Figures 8A and 8B are diagrams illustrating examples of circuit structures for semiconductor devices.

[0027] Figures 9A and 9B are diagrams illustrating examples of circuit structures for semiconductor devices.

[0028] Figures 10A and 10B are diagrams illustrating examples of circuit structures for semiconductor devices.

[0029] Figure 11 is a timing diagram illustrating an example of the operation of a semiconductor device.

[0030] Figures 12A and 12B are circuit diagrams illustrating an example of the operation of a semiconductor device.

[0031] Figures 13A and 13B are circuit diagrams illustrating an example of the operation of a semiconductor device.

[0032] Figure 14 is a circuit diagram illustrating an example of the operation of a semiconductor device.

[0033] Figures 15A1 to 15A7 are diagrams illustrating examples of electrical connections. Figures 15B1 to 15B6 are diagrams illustrating examples of non-electrical connections.

[0034] Figures 16A to 16C are diagrams illustrating examples of transistor structures.

[0035] Figures 17A to 17C are diagrams illustrating examples of transistor structures.

[0036] Figures 18A and 18B are diagrams illustrating examples of transistor structures.

[0037] Figures 19A and 19B are diagrams illustrating examples of transistor structures.

[0038] Figures 20A to 20C are diagrams illustrating examples of transistor structures.

[0039] Figures 21A to 21C are diagrams illustrating examples of transistor structures.

[0040] Figures 22A to 22E are diagrams illustrating examples of transistor structures.

[0041] Figures 23A and 23B are diagrams illustrating examples of transistor structures.

[0042] Figures 24A to 24E are diagrams illustrating examples of transistor structures.

[0043] Figure 25 is a diagram illustrating an example of a transistor structure.

[0044] Figures 26A to 26E are diagrams illustrating examples of transistor structures.

[0045] Figures 27A to 27D are cross-sectional views illustrating the deposition method of metal oxides.

[0046] Figures 28A to 28D are cross-sectional views illustrating the deposition method of metal oxides.

[0047] Figures 29A and 29B are diagrams illustrating examples of the structure of a storage device.

[0048] Figure 30A is a diagram illustrating an example of a planar structure of a semiconductor device. Figure 30B is a diagram illustrating an example of a circuit structure of a semiconductor device.

[0049] Figure 31 is a diagram illustrating an example of a cross-sectional structure of a semiconductor device.

[0050] Figure 32 is a block diagram illustrating the CPU.

[0051] Figure 33 is a block diagram illustrating the CPU.

[0052] Figures 34A and 34B are perspective views of a semiconductor device.

[0053] Figures 35A and 35B are perspective views of a semiconductor device.

[0054] Figures 36A and 36B are diagrams illustrating the hierarchy of storage devices.

[0055] Figures 37A and 37B are diagrams illustrating an example of an electronic device, and Figures 37C to 37E are diagrams illustrating an example of a mainframe computer.

[0056] Figure 38 is a diagram showing an example of a space device.

[0057] Figure 39 is a diagram illustrating an example of a storage system that can be used in a data center.

[0058] Figures 40A and 40B are diagrams illustrating the circuit model used for simulation.

[0059] Figure 41 is a graph showing the simulation results.

[0060] Figure 42 is a diagram illustrating the circuit model used for simulation.

[0061] Figures 43A and 43B are graphs showing the simulation results.

[0062] Figure 44 is a diagram illustrating an example of a cross-sectional structure of a semiconductor device.

[0063] Figure 45 is a diagram illustrating an example of a planar structure of a semiconductor device.

[0064] Figure 46 is a diagram illustrating an example of a cross-sectional structure of a semiconductor device.

[0065] Figure 47 is a diagram illustrating an example of a planar structure of a semiconductor device.

[0066] Figure 48 is a diagram illustrating an example of a cross-sectional structure of a semiconductor device. Detailed Implementation

[0067] The embodiments of the invention will now be described with reference to the accompanying drawings. Note that the embodiments can be implemented in many different ways, and those skilled in the art will readily understand that the methods and details can be varied in many ways without departing from the spirit and scope of the invention. Therefore, the invention should not be construed as limited to the contents described in the following embodiments.

[0068] In this specification, etc., a semiconductor device refers to a device that utilizes the properties of semiconductors, and includes circuits containing semiconductor elements (transistors, diodes, photodiodes, etc.) and devices having such circuits. Furthermore, a semiconductor device refers to all devices capable of functioning by utilizing the properties of semiconductors. Examples of semiconductor devices include integrated circuits, chips containing integrated circuits, and electronic components that house chips in packages. In addition, storage devices, display devices, light-emitting devices, lighting devices, and electronic devices are themselves semiconductor devices, and sometimes include semiconductor devices.

[0069] In the accompanying drawings and other materials of this specification, sizes, layer thicknesses, or areas are sometimes exaggerated for ease of understanding. Therefore, the invention is not necessarily limited to the sizes or aspect ratios shown in the drawings. Furthermore, the drawings illustrate ideal examples schematically and are not limited to the shapes or values ​​shown in the drawings.

[0070] Note that in the structure of the invention as described in the embodiments, the same symbols are sometimes used in different figures to show the same part or parts with the same function, while repeated descriptions are sometimes omitted. Furthermore, when showing parts with the same function, the same shading lines are sometimes used without additional symbols. Additionally, for ease of understanding, descriptions of some constituent elements are sometimes omitted in perspective or plan views, etc.

[0071] In this specification, ordinal numbers such as "first" and "second" are added to avoid confusion regarding the constituent elements. Therefore, these ordinal numbers do not limit the number of constituent elements. Furthermore, these ordinal numbers do not limit the order of the constituent elements. For example, a constituent element marked "first" in one embodiment of this specification may be marked "second" in other embodiments or claims. Furthermore, a constituent element marked "first" in one embodiment of this specification may be omitted in other embodiments or claims. Furthermore, to avoid confusion regarding the constituent elements, even phrases not marked with ordinal numbers in this specification may sometimes be marked with ordinal numbers in the claims. Furthermore, even phrases marked with ordinal numbers in this specification may sometimes be marked with different ordinal numbers in the claims. Furthermore, even phrases marked with ordinal numbers in this specification may sometimes have those ordinal numbers omitted in the claims.

[0072] In this specification and other materials, for convenience, terms such as "upper," "lower," "above," or "below" are sometimes used to indicate the arrangement of components, referring to the accompanying drawings. Furthermore, the positional relationships of the components may be appropriately changed depending on the orientation of each structure being described. Therefore, the terminology used is not limited to that described in the specification and other materials, and may be appropriately changed as needed. For example, if the description is "an insulator located on the top surface of a conductor," it can be changed to "an insulator located on the bottom surface of a conductor" by rotating the orientation of the shown drawings by 180 degrees.

[0073] Furthermore, the use of terms such as "above" and "below" does not necessarily limit the positional relationship of the constituent elements to being directly above or below and in direct contact. For example, if the statement is "electrode B on insulating layer A," it is not necessary for electrode B to be formed in direct contact with insulating layer A; it can also include cases where other constituent elements are included between insulating layer A and electrode B.

[0074] In this specification, the term "overlapping" does not limit the state of the stacking order of the constituent elements. For example, when it is expressed as "electrode B overlapping with insulating layer A", it is not limited to the state in which electrode B is formed on insulating layer A, but may also include the state in which electrode B is formed under insulating layer A or the state in which electrode B is formed on the right (or left) side of insulating layer A.

[0075] In this specification and other documents, terms such as "adjacent" and "near" are not limited to a state in which the constituent elements are in direct contact. For example, if the description is "electrode B adjacent to insulating layer A", it does not necessarily mean that insulating layer A and electrode B are in direct contact. It may also include situations where other constituent elements are included between insulating layer A and electrode B.

[0076] Furthermore, in this specification and other materials, the terms "film" and "layer," etc., may be interchanged depending on the circumstances. For example, sometimes "conductive layer" may be replaced with "conductive film." For example, sometimes "insulating film" may be replaced with "insulating layer." Alternatively, depending on the situation or circumstances, the terms "film," "layer," etc., may not be used and may be replaced with other terms. For example, sometimes "conductive layer" or "conductive film" may be replaced with "conductive body." Or, sometimes "conductive body" may be replaced with "conductive layer" or "conductive film." For example, sometimes "insulating layer" or "insulating film" may be replaced with "insulator." Or, sometimes "insulator" may be replaced with "insulating layer" or "insulating film."

[0077] In this specification, the terms "electrode," "wiring," and "terminal" do not functionally limit their constituent elements. For example, sometimes "electrode" is used as part of "wiring," and vice versa. Furthermore, "electrode" or "wiring" may include multiple "electrodes" or multiple "wiring" formed as a single unit. Similarly, sometimes "terminal" is used as part of "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" may include multiple "electrodes," multiple "wiring," multiple "terminals," etc., formed as a single unit. Thus, for example, an "electrode" may be part of "wiring" or "terminal," and, for example, a "terminal" may be part of "wiring" or "electrode." Additionally, sometimes the terms "electrode," "wiring," and "terminal" are replaced with terms such as "area" and "conductive layer."

[0078] In this instruction manual and other documents, the terms "wiring," "signal line," and "power line" may be interchanged depending on the situation or circumstances. For example, "wiring" may sometimes be replaced with "signal line." Similarly, "wiring" may sometimes be replaced with "power line," and vice versa. Furthermore, depending on the situation or circumstances, the "potential" applied to the wiring may be replaced with "signal," and vice versa.

[0079] In this specification, "source" refers to a source region, a source electrode, or a source wiring. A source region is a region in a semiconductor layer with a resistivity below a certain value. A source electrode is a conductive layer having a portion connected to the source region. A source wiring is a conductive layer used to connect the source electrode of at least one transistor to other electrodes or other wiring.

[0080] In this specification, "drain" refers to a drain region, drain electrode, or drain wiring. A drain region is a region in a semiconductor layer with a resistivity below a certain value. A drain electrode is a conductive layer having a portion connected to the drain region. Drain wiring is a conductive layer used to connect the drain electrode of a transistor to other electrodes or other wiring.

[0081] In this specification, "gate" refers to the gate electrode or gate wiring. A gate electrode is an electrode that overlaps with the semiconductor layer of a transistor and functions to control the resistance between the source and drain of the transistor according to the supplied voltage. Gate wiring refers to the conductive layer used to connect the gate electrode of the transistor to other electrodes or other wiring.

[0082] In this specification, one of the source and drain of a transistor is sometimes referred to as the "first terminal of the transistor", and the other of the source and drain of a transistor is referred to as the "second terminal of the transistor".

[0083] In this specification, "parallel" refers to two straight lines arranged at an angle of -10° to 10°. Therefore, it also includes situations where the angle is -5° to 5°. Furthermore, "approximately parallel" or "generally parallel" refers to two straight lines arranged at an angle of -15° to 15°. Additionally, "perpendicular" refers to two straight lines arranged at an angle of 80° to 100°. Therefore, it also includes situations where the angle is 85° to 95°. Furthermore, "approximately perpendicular" or "generally perpendicular" refers to two straight lines arranged at an angle of 60° to 120°.

[0084] Furthermore, in many cases, voltage means the potential difference between a certain potential and a reference potential (such as ground potential or source potential). Therefore, voltage and potential can be interchanged in many situations. In this specification and other documents, unless otherwise specified, voltage and potential may be interchanged.

[0085] Furthermore, in this specification, the high power supply potential VDD (hereinafter also simply "VDD") refers to a power supply potential whose potential is higher than the low power supply potential VSS. Conversely, the low power supply potential VSS (hereinafter also simply "VSS") refers to a power supply potential whose potential is lower than the high power supply potential VDD. Additionally, the ground potential GND (hereinafter also simply "GND") may be used as VDD or VSS. For example, when VDD is GND, VSS is a potential lower than GND; when VSS is GND, VDD is a potential higher than GND.

[0086] In this specification, the "on state" of a transistor means that the source and drain of the transistor are in a conducting state (a state in which conduction is possible). Conversely, the "off state" of a transistor means that the source and drain of the transistor are in a non-conducting state (which can be considered as an electrically cut-off state).

[0087] Furthermore, in this specification, "on-state current" refers to the current flowing between the source and drain when the transistor is in the on-state. Similarly, "off-state current" refers to the current flowing between the source and drain when the transistor is in the off-state.

[0088] In this specification, the potential H is the potential that turns an n-channel field-effect transistor (also called an "n-type transistor") on, while the potential that turns a p-channel field-effect transistor (also called a "p-type transistor") off. Furthermore, the potential L is the potential that turns an n-type transistor off, while the potential that turns a p-type transistor on. Therefore, potential H is a higher potential than potential L. Potential H is sometimes equal to VDD. Potential L is sometimes equal to VSS. Furthermore, unless otherwise stated, the transistors shown in this specification are enhancement-mode (normally off) n-type transistors.

[0089] Furthermore, in the accompanying drawings, etc., to clearly show the potentials of wiring and electrodes, sometimes an "H" indicating potential H or an "L" indicating potential L is appended adjacent to the wiring and electrodes. Additionally, wiring and electrodes where potential changes occur are marked with an "H" or "L" in a frame. Furthermore, when a transistor is in the off state, an "×" is sometimes appended overlapping the transistor. Additionally, sometimes an arrow indicating the direction of current flow is included.

[0090] In this specification and other materials, unless otherwise stated, the terms “same,” “identical,” “equal,” or “uniform” (including synonyms of these terms) for count and measurement values ​​include an error of ±10%.

[0091] Furthermore, arrows indicating the X, Y, and Z directions are sometimes included in the accompanying drawings and other materials of this specification. In this specification, "X direction" refers to the direction along the X-axis, and unless specifically stated otherwise, the distinction between clockwise and counterclockwise directions is not always made. The same applies to "Y direction" and "Z direction." Furthermore, the X, Y, and Z directions are intersecting directions. For example, the X, Y, and Z directions are orthogonal directions. In this specification, one of the X, Y, and Z directions is sometimes referred to as the "first direction." Furthermore, one of the aforementioned directions is sometimes referred to as the "second direction." Furthermore, the remaining of the aforementioned directions is sometimes referred to as the "third direction."

[0092] Generally speaking, a "capacitor" has a structure in which two electrodes are positioned opposite each other with an insulator (dielectric). In this specification, "capacitor" includes the aforementioned "capacitor". That is, in this specification, "capacitor" includes a structure in which two electrodes are positioned opposite each other with an insulator, a structure in which two wires are positioned opposite each other with an insulator, or a structure in which two wires are arranged with an insulator.

[0093] In this specification, when multiple constituent elements use the same symbol, especially when it is necessary to distinguish them, the symbol is sometimes accompanied by a symbol for identification such as "A", "b", "_1", "[n]", "[m,n]", etc.

[0094] In this specification, the term "connection" includes, for example, "electrical connection." When describing the connection relationship of circuit elements as an object under the guise of "electrical connection," "electrical connection" includes, for example, "direct connection" and "indirect connection." "A and B directly connected" means, for example, that no circuit element (e.g., a transistor or switch, but not wiring) is between A and B. On the other hand, "A and B indirectly connected" means, for example, that A and B are connected through more than one circuit element.

[0095] Here, the term "indirectly connected between A and B" refers to a connection relationship in the following ways: That is, when it is assumed that the circuit is operating, and there is a sequence of events such as the exchange of electrical signals or the interaction of potentials between A and B during the circuit's operation, such a circuit can be defined as an object "indirectly connected between A and B." Furthermore, even if there is no sequence of events where there is an exchange of electrical signals or the interaction of potentials between A and B, but there is still a sequence of events where there is an exchange of electrical signals or the interaction of potentials between A and B during the circuit's operation, it can still be defined as "indirectly connected between A and B." Note that the expression "indirectly connected between A and B" defines the connection relationship of circuit elements as an object. Therefore, for example, even if the circuit is not operating because it is not supplied with a power supply voltage, the circuit can still be defined as an object "indirectly connected between A and B" (however, this is limited, for example, to the case where, when the circuit is operating because it is supplied with a power supply voltage, there is an exchange of electrical signals or the interaction of potentials between A and B during the circuit's operation).

[0096] The following are specific examples of the "indirect connection" case. First, as an example of "A and B indirect connection," there is the case where A and B are connected through the source and drain of one or more transistors, as shown in Figures 15A1 and 15A2. Similarly, other examples of "A and B indirect connection" include cases where A and B are connected through one or more switches. In the case of "A and B indirect connection," the timing sequence ensures that, assuming the circuit is operating, at least once, one transistor between A and B is in an on-state, a conducting state, or a state where current can flow. Furthermore, the "A and B indirect connection" case may also include a timing sequence where one transistor between A and B is in an off-state or a non-conducting state. In the case of "A and B indirect connection," if multiple transistors are connected between A and B, the timing sequence ensures that, assuming the circuit is operating, at least once, each of the multiple transistors between A and B is in an on-state, a conducting state, or a state where current can flow. In other words, in the case of "A and B being indirectly connected," multiple transistors do not necessarily need to be simultaneously in the on, conducting, or current-flowing state. Therefore, the case of "A and B being indirectly connected" includes situations where multiple transistors between A and B are simultaneously or at different times in the off or non-conducting state. As another example, as shown in Figure 15A3, when A and C are connected through the source and drain of transistor TrP and B and C are connected through the source and drain of transistor TrQ, it can be defined as "A and C being indirectly connected," "B and C being indirectly connected," or "A and B being indirectly connected." Note that, as described below, when a fixed potential V is supplied to C from the power supply or GND, etc., while it can be said that "A and C are indirectly connected" or "B and C are indirectly connected," it is not possible to say that "A and B are indirectly connected."

[0097] The above examples illustrate situations where "indirect connection" can or cannot be described. However, the following examples illustrate other situations where "indirect connection" cannot be described. Even when there is signal exchange or potential interaction between A and B during circuit operation, there are exceptions where "A and B are indirectly connected" cannot be described. An example of such an exception is when A and B are connected through an insulator. That is, when A and B are connected through an insulator, it is not permissible to say "A and B are indirectly connected." A concrete example of A and B being connected through an insulator is when a capacitor is connected between A and B, as shown in Figure 15A4. Similarly, another example of A and B being connected through an insulator is when a gate insulating film of a transistor is sandwiched between A and B, as shown in Figure 15A5. In this case, it is not permissible to say "A (the gate of the transistor) and B (the source or drain of the transistor) are indirectly connected."

[0098] As another example where it's inappropriate to say "A and B are indirectly connected," cases where there is no signal exchange or potential interaction between A and B can be cited. For example, as shown in Figures 15A6 and 15A7, multiple transistors are connected via their source and drain along the path from A to B, and a fixed potential V is supplied from the power supply or GND at the nodes between the transistors. In this case, while it's not appropriate to say "A and B are indirectly connected," it's possible to say "A and V are indirectly connected" or "B and V are indirectly connected." In Figure 15A3, A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, with a fixed potential V supplied to C from the power supply or GND. This has the same connection relationship as Figures 15A6 and 15A7, so it's inappropriate to say "A and B are indirectly connected," but rather "A and C are indirectly connected" or "B and C are indirectly connected."

[0099] Although the above examples of "indirect connection" are shown, the provisions of "indirect connection" are included in the provisions of "electrical connection", so in the case of "A and B are indirectly connected", it can be said that "A and B are electrically connected".

[0100] The following are specific examples of the "direct connection" case. As examples of "A and B directly connected," as shown in Figures 15B1, 15B2, and 15B3, there are cases where A and B are not connected through circuit elements. Furthermore, as shown in Figures 15B4 and 15B5, when A and B are not connected to a power supply or GND (which provides a fixed potential V) through circuit elements, it can be said that "A and B are directly connected," "A and V are directly connected," or "B and V are directly connected." Furthermore, as shown in Figure 15B6, even when A (or B) is connected to a fixed potential V through the source and drain of a transistor, it can be said that "A and B are directly connected." However, since A and V, or B and V, are connected through the source and drain of a transistor, it cannot be said that they are directly connected; instead, it can be said that "A and V are indirectly connected" or "B and V are indirectly connected."

[0101] Although the above examples show "direct connection", the definition of "direct connection" is included in the definition of "electrical connection", so in the case of "A and B are directly connected", it can be said that "A and B are electrically connected".

[0102] (Embodiment 1) A semiconductor device according to one aspect of the present invention will be described with reference to the accompanying drawings. FIG1A is a circuit diagram of a semiconductor device 10A according to one aspect of the present invention. The semiconductor device 10A is used as a storage element (also referred to as a "memory cell").

[0103] <Circuit Structure Example> The semiconductor device 10A shown in Figure 1A includes two transistors M1, two capacitors Cs, and a transistor M2. In Figure 1A, the first transistor M1 is referred to as transistor M1[1], and the second transistor M1 is referred to as transistor M1[2]. In addition, the first capacitor Cs is referred to as capacitor Cs[1], and the second capacitor Cs is referred to as capacitor Cs[2].

[0104] In the semiconductor device 10A shown in Figure 1A, one of the source and drain of transistor M1[1] is connected to one electrode of capacitor Cs[1] and the gate of transistor M2. One of the source and drain of transistor M1[2] is connected to one electrode of capacitor Cs[2] and the other of the source and drain of transistor M1[1]. The other of the source and drain of transistor M1[2] is connected to wiring WBL. Furthermore, the gates of transistors M1[1] and M1[2] are connected to each other and to wiring WWL. One of the source and drain of transistor M2 is connected to wiring RBL, and the other of the source and drain of transistor M2 is connected to wiring RWL. In addition, the other electrode of each of capacitors Cs[1] and Cs[2] is connected to wiring COM. Furthermore, wiring COM is supplied with a fixed potential such as GND, common potential (e.g., 0V).

[0105] In addition, the region that is connected to one of the source and drain of transistor M1[1], one electrode of capacitor Cs[1], and the gate of transistor M2, and that they are always at the same potential, is called node ND.

[0106] Furthermore, as shown in Figure 1B, the semiconductor device 10A may include n transistors M1 (n is a natural number of 3 or more), n capacitors Cs, and transistors M2. In Figure 1B, the nth transistor M1 is denoted as transistor M1[n], and the nth capacitor Cs is denoted as capacitor Cs[n]. Additionally, the i-th transistor M1 (i is an integer of 2 or more and less than n-1) is denoted as transistor M1[i], and the i-th capacitor Cs is denoted as capacitor Cs[i].

[0107] In the semiconductor device 10A shown in Figure 1B, one of the source and drain of transistor M1[1] is connected to one electrode of capacitor Cs[1] and the gate of transistor M2. Furthermore, one of the source and drain of transistor M1[i] is connected to one electrode of capacitor Cs[i] and the other of the source and drain of transistor M1[i-1]. Additionally, one of the source and drain of transistor M1[n] is connected to the other of the source and drain of transistor M1[n-1], and the other of the source and drain of transistor M1[n] is connected to wiring WBL. The gates of the n transistors M1 are connected to each other and to wiring WWL. One of the source and drain of transistor M2 is connected to wiring RBL, and the other of the source and drain of transistor M2 is connected to wiring RWL. Furthermore, the other electrode of each of the n capacitors Cs is connected to wiring COM.

[0108] In Figures 1A and 1B, the transistors included in the semiconductor device 10A are n-type transistors; however, this invention is not limited to this. P-type transistors can be used as part or all of the transistors included in the semiconductor device 10A. Compared to n-type transistors, p-type transistors are easier to implement as normally-off transistors, and circuit design is simpler. Furthermore, n-type transistors have higher field-effect mobility than p-type transistors, thus increasing the operating speed of the semiconductor device 10A. For example, n-type transistors can be used for transistor M1, and p-type transistors can be used for transistors M2 and M3. Transistor M3 will be described below.

[0109] Furthermore, as a transistor according to one aspect of the present invention, transistors with various structures can be used. For example, transistors with various structures such as planar, fin, top-gate, bottom-gate, and vertical can be used. In addition, as a transistor according to one aspect of the present invention, MOS transistors, junction transistors, bipolar transistors, etc., can be used.

[0110] As the semiconductor layer of the transistor included in the semiconductor device 10A, various semiconductor materials can be used, such as single semiconductors like silicon and germanium, compound semiconductors like silicon carbide and gallium arsenide, and oxide semiconductors, which are one type of compound semiconductors.

[0111] In the semiconductor device 10A shown in Figures 1A and 1B, a transistor including a back gate can be used as the transistor included in the semiconductor device 10A. Figure 1C shows an example of a circuit diagram symbol for a transistor including a back gate.

[0112] The gate and back gate of the transistor are configured such that a channel forming region sandwiching the semiconductor layer is formed. Furthermore, both the gate and back gate are formed using a conductive layer. Note that a semiconductor layer with low resistivity can be used as the conductive layer. The back gate can have the same function as the gate. When the gate is used to control the on and off states of the transistor, the back gate potential can be the same as the gate potential. Furthermore, the back gate potential can be GND or any other potential.

[0113] For example, when the transistor is in the on state, supplying the potential to both the gate and the back gate increases the on-state current compared to supplying only one of the gate and the back gate. As shown in Figure 1D, by connecting the gate and the back gate, the gate and the back gate can be kept at the same potential. Furthermore, the threshold voltage of the transistor can be adjusted by controlling the potential of the back gate independently of the gate.

[0114] Alternatively, a fixed potential such as GND can be supplied to the back gate. Since the gate and back gate are formed from conductive layers, the electric field generated outside the transistor is less likely to act on the channel formation region by using the gate and back gate to sandwich the semiconductor layer (also known as "electric field shielding effect"). Therefore, by providing a back gate in the transistor, the transistor operates stably. Furthermore, by providing a back gate in the transistor, characteristic inhomogeneities between multiple transistors are reduced. The reliability of the transistor can be improved by providing a back gate. Therefore, the reliability of the semiconductor device including this transistor can be improved. Note that although an electric field shielding effect can also be obtained when one or both of the gate and back gate are in an electrically floating state (also known as a "floating state"), this effect can be enhanced by supplying a potential to the gate and back gate.

[0115] Semiconductor device 10A has the function of turning transistor M1 to the on state to write data supplied from wiring WBL to node ND. Furthermore, semiconductor device 10A has the function of turning transistor M1 to the off state to retain the data written to node ND. Therefore, transistor M1 is sometimes referred to as a "write transistor" or a "hold transistor".

[0116] Furthermore, the semiconductor device 10A can switch the on and off states of transistor M2 according to the data held in node ND. Additionally, the data held in node ND can be read out by changing the potential of wiring RBL according to the state of transistor M2. Therefore, transistor M2 is sometimes referred to as a "readout transistor" or "amplification transistor".

[0117] As described above, transistor M1 is used as a holding transistor to hold the data written to node ND (here, equivalent to charge at a specific potential). Therefore, an OS transistor is preferably used as transistor M1. Since the band gap of the oxide semiconductor layer forming the channel used as an OS transistor is above 2 eV, the off-state current of the OS transistor is extremely small compared to transistors that use silicon as the semiconductor layer forming the channel (also known as "Si transistors"). Specifically, the off-state current of an OS transistor with a channel width of 1 μm at room temperature can be 1 pA (1 × 10⁻⁶). -12 A), 1aA (1×10 -18 A) Below, 1zA(1×10 -21 A) or below or 1yA (1×10 -24 A) The following.

[0118] Furthermore, OS transistors operate stably at high temperatures with minimal characteristic variation. For example, even at ambient temperatures above 100°C and below 200°C, their off-state current shows almost no increase. Similarly, even at ambient temperatures above 100°C and below 200°C, their on-state current shows almost no decrease. Semiconductor devices, including OS transistors, operate stably and reliably even at high temperatures.

[0119] Furthermore, the electrical characteristics of OS transistors are less affected by radiation such as cosmic rays. In other words, they are less prone to soft errors caused by radiation, resulting in high reliability for semiconductor devices using OS transistors.

[0120] Thus, by using an OS transistor as transistor M1, the charge held in node ND is less likely to decrease, and voltage drops in node ND can be suppressed for a long time. Therefore, data written to node ND can be retained for a long period. Furthermore, by including multiple capacitors Cs, the charge in node ND is even less likely to decrease. Therefore, voltage drops in node ND can be further suppressed.

[0121] According to one aspect of the present invention, the semiconductor device 10A requires almost no power to maintain the data written to node ND. Furthermore, the semiconductor device 10A rewrites data through the charging and discharging of node ND, so in principle there is no limit to the number of rewrites. Additionally, memory cells constructed using OS transistors are sometimes referred to as "OS memory." Furthermore, memory devices that include memory cells constructed using OS transistors are sometimes referred to as "OS memory."

[0122] Figure 2 shows the relationship between the operating environment temperature (also known as "ambient temperature") and the off-state current Ioff of Si and OS transistors. The horizontal axis of the graph in Figure 2 represents the reciprocal of the absolute temperature. Therefore, the ambient temperature gradually increases to the left of the horizontal axis and gradually decreases to the right. Note that "RT" in Figure 2 indicates that the ambient temperature is room temperature (25°C to 27°C).

[0123] Furthermore, the vertical axis of the graph shown in Figure 2 represents the value of the off-state current Ioff logarithmically. The off-state current Ioff in Figure 2 refers, for example, to the current flowing between the source and drain of transistor M1 when the potential of node ND in semiconductor device 10A shown in Figure 1A is VDD, the potential of wiring WBL is VSS, and transistor M1 is in the off state. Additionally, the off-state current Ioff in Figure 2 is, for example, equivalent to the current flowing between node ND and wiring WBL when transistor M1 is in the off state.

[0124] In the graphs shown in Figure 2, distribution 91 shows the temperature dependence of the off-state current Ioff when both transistors M1[1] and M1[2] of the semiconductor device 10A shown in Figure 1A use Si transistors. Distribution 92 shows the temperature dependence of the off-state current Ioff when both transistors M1[1] and M1[2] of the semiconductor device 10A shown in Figure 1A use OS transistors. Distribution 93 shows the temperature dependence of the off-state current Ioff when all of the n transistors M1 of the semiconductor device 10A shown in Figure 1B use OS transistors.

[0125] As shown in Figure 2, compared with the case where both transistors M1[1] and M1[2] use Si transistors (Distribution 91), the off-state current Ioff is smaller not only at room temperature but also at high temperature in the case where OS transistors are used (Distribution 92). In addition, it can be seen that by using OS transistors as transistors M1 and connecting three or more transistors M1 in series, the off-state current Ioff can be further reduced (Distribution 93).

[0126] Furthermore, the transistor M2 used as the readout transistor can be a transistor with a higher mobility than the transistor M1. For example, a Si transistor can be used as the transistor M2. The mobility of a Si transistor is higher than that of an OS transistor, thus increasing the readout speed of the data held by the semiconductor device 10A.

[0127] For example, by using an OS transistor as transistor M1 and a Si transistor as transistor M2, a memory cell with high reliability and high-speed operation can be realized.

[0128] Furthermore, transistors M1 and M2 can be stacked in the semiconductor device 10A. By stacking transistors M1 and M2, the area occupied by the semiconductor device 10A can be reduced. Figure 3A is a perspective view of the semiconductor device 10A. Figure 3B shows a perspective view illustrating the structure of the semiconductor device 10A in more detail.

[0129] The semiconductor device 10A shown in Figures 3A and 3B includes a device layer 60 overlapping with the device layer 50. Furthermore, the device layer 50 includes a transistor M2, and the device layer 60 includes a transistor M1. For example, if a Si transistor is used as the transistor M1, a single-crystal silicon substrate is used as the device layer 50, and the transistor M1 can be formed on this silicon substrate. By forming a channel formation region for the Si transistor M1 on this silicon substrate, a single-crystal Si transistor containing a single-crystal semiconductor in the channel formation region and operating at high speed can be formed.

[0130] Furthermore, for example, SOI (Silicon on Insulator) substrates can be used as element layer 50. SOI substrates can be formed using: SIMOX (Separation by Implanted Oxygen) substrates, which are formed by heating a mirror-polished thin film at high temperature after implanting oxygen ions to create an oxide layer at a certain depth from the surface and eliminating defects generated in the surface layer; smart lift-off methods or ELTRAN (Epitaxial Layer Transfer) methods, which utilize the micro-voids formed by implanting hydrogen ions to grow the semiconductor substrate through heat treatment. Si transistors fabricated using SOI substrates have reduced parasitic capacitance, thus enabling high-speed operation.

[0131] Alternatively, components or circuits other than transistor M2 can be placed in component layer 50. For example, drive circuits used to supply signals to wiring WWL, wiring WBL, etc., can be placed in component layer 50.

[0132] Furthermore, when a thin-film transistor such as an OS transistor is used as the transistor M1 included in element layer 60, it is easy to overlap element layer 60 with element layer 50. Moreover, as mentioned above, OS transistors operate stably even at high temperatures with minimal characteristic variation. Therefore, even if a transistor M1 including an OS transistor is overlapped on a transistor M2 including a Si transistor, it is less susceptible to the heat generated by transistor M2, thus achieving high reliability. Additionally, similar to element layer 50, components or circuits other than transistor M1 can be included in element layer 60.

[0133] Furthermore, the semiconductor layers of both transistors M1 and M2 can use the same semiconductor material. For example, if both transistors M1 and M2 are formed by OS transistors, the semiconductor device 10A can be provided only in the element layer 60. By using the same semiconductor material for the semiconductor layers of both transistors M1 and M2, transistors M1 and M2 can be formed simultaneously in the same process. This improves the productivity of the semiconductor device 10A.

[0134] <Modified Example 1> Figures 4A and 4B show a modified example of semiconductor device 10A, namely semiconductor device 10B. The gates of transistor M1[1] and transistor M1[2] can be connected to different wirings WWL. For example, as shown in semiconductor device 10B in Figure 4A, the following structure can be adopted: wirings WWLa and WWLb are provided as wirings WWL, the gate of transistor M1[1] is connected to wiring WWLa, and the gate of transistor M1[2] is connected to wiring WWLb.

[0135] In addition, when the semiconductor device 10B includes n transistors M1, as shown in FIG4B, for example, the following structure can be adopted: wiring WWLa and wiring WWLb are set as wiring WWL, the gate of the odd-numbered transistor M1 is connected to wiring WWLa, and the gate of the even-numbered transistor M1 is connected to wiring WWLb.

[0136] Alternatively, if the semiconductor device 10B includes n transistors M1, it can be structured as follows: n wirings WWL are provided, and the gate of the i-th transistor M1 is connected to the i-th wiring WWL.

[0137] By setting multiple wiring loops (WWLs), the area occupied by the semiconductor device 10B is increased, but the operating timing of the multiple transistors M1 can be different. For example, in the semiconductor device 10B shown in FIG4A, in a room temperature environment with low off-state current, one of transistors M1[1] and M1[2] can be kept in the on state, and only the other of transistors M1[1] and M1[2] is used for data writing and retention. By reducing the number of transistors switching between on and off states, the power consumption of the semiconductor device 10B can be reduced.

[0138] Furthermore, in high-temperature environments with high off-state current, both transistors M1[1] and M1[2] can be used for data writing and retention. Therefore, data can be retained for a long time in high-temperature environments. Thus, by adjusting the number of transistors switching between on and off states according to the ambient temperature, the power consumption of the semiconductor device 10B can be further reduced and the reliability improved.

[0139] <Modification Example 2> Figures 5A and 5B show a modified example of semiconductor device 10A, namely semiconductor device 10C. For example, as shown in semiconductor device 10C in Figure 5A, a transistor M3 can be added to the structure of semiconductor device 10A. In semiconductor device 10C shown in Figure 5A, the other of the source and drain of transistor M2 is connected to one of the source and drain of transistor M3. Furthermore, the other of the source and drain of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to wiring RWL.

[0140] When multiple semiconductor devices 10C, which serve as storage cells, are configured in a matrix, the state of other storage cells can sometimes affect the reading of data held in one storage cell. By setting transistor M3, the influence on the storage cell to be read can be suppressed. Furthermore, by setting transistor M3, a specific storage cell can be selected more accurately to read the data held in that storage cell. Therefore, transistor M3 is sometimes referred to as a "selection transistor." By setting transistor M3, the operation of the semiconductor device 10C is stabilized, and the reliability of the semiconductor device 10C can be improved.

[0141] <Modification Example 3> Figures 6A and 6B show a modified example of semiconductor device 10D, which is semiconductor device 10C. For example, the difference between Figure 6A and semiconductor device 10B is that in Figure 6A, transistor M3 is not provided, and a transistor including a back gate is used as transistor M2. In semiconductor device 10C, one of the source and drain of transistor M2 is connected to wiring SL, and the back gate is connected to wiring RWL. By using a transistor including a back gate as transistor M2, transistor M2 can have the function of a selection transistor. Since it is not necessary to form transistor M3, reliability can be improved without increasing the footprint.

[0142] In addition, when using a transistor including a back gate for transistor M2, the back gate can be connected to one of the source and drain of transistor M1[1] and one electrode of capacitor Cs[1] and the gate can be connected to wiring RWL.

[0143] In particular, when the EOT (Equivalent Oxide Thickness) of the insulating layer used as the gate insulating layer on the back gate side is smaller than the EOT of the insulating layer used as the gate side, by connecting the gate of transistor M2 to the wiring RWL, the on and off states of transistor M2 can be easily switched even if the amplitude of the potential supplied to the wiring RWL becomes smaller. As a result, the power consumption of semiconductor device 10D can be reduced. In this case, the region connected to one of the source and drain of transistor M1[1], one electrode of capacitor Cs[1], and the back gate of transistor M2 is used as node ND.

[0144] <Modified Example 4> Figures 7A and 7B show a modified example of semiconductor device 10E, which is a modified example of semiconductor device 10A. Semiconductor device 10E shown in Figure 7A is a modified example of semiconductor device 10A shown in Figure 1A. The difference between semiconductor device 10E shown in Figure 7A and semiconductor device 10A shown in Figure 1A is that, in Figure 7A, one of the source and drain of transistor M2 is connected to wiring SL, and the other electrode of capacitors Cs[1] and Cs[2] is connected to wiring RWL.

[0145] The semiconductor device 10E shown in Figure 7B is a variation of the semiconductor device 10A shown in Figure 1B. The difference between the semiconductor device 10E shown in Figure 7B and the semiconductor device 10A shown in Figure 1B is that, in Figure 7B, similar to the semiconductor device 10E shown in Figure 7A, another of the source and drain of transistor M2 is connected to wiring SL, and the other electrode of each of the n capacitors Cs is connected to wiring RWL.

[0146] By employing the structure of semiconductor device 10E, data can be read without being affected by the state of other memory cells, even without transistor M3. Therefore, the operation of semiconductor device 10E is stabilized, and its reliability is improved.

[0147] <Modification Example 5> Figures 8A and 8B show a modified example of semiconductor device 10F, which is a semiconductor device 10F of semiconductor device 10A. The semiconductor device 10F shown in Figure 8A is a modified example of semiconductor device 10A shown in Figure 1A. The semiconductor device 10F shown in Figure 8B is a modified example of semiconductor device 10A shown in Figure 1B.

[0148] Semiconductor device 10F has a structure that removes capacitors Cs[2] to Cs[n] from semiconductor device 10A. If the electrostatic capacitance of capacitor element Cs[1] is sufficient to meet the functional requirements of the memory cell, capacitors Cs[2] to Cs[n] can be omitted. By omitting capacitors Cs[2] to Cs[n], the area occupied by semiconductor device 10F can be reduced. This increases the integration density of semiconductor device 10F. Furthermore, the storage density of memory devices using semiconductor device 10F can be increased.

[0149] <Modification Example 6> Figures 9A and 9B show a modified example of semiconductor device 10A, namely semiconductor device 10G. Semiconductor device 10F shown in Figure 9A is a modified example of semiconductor device 10A shown in Figure 1A. Furthermore, semiconductor device 10G shown in Figure 9B is a modified example of semiconductor device 10A shown in Figure 1B.

[0150] Semiconductor device 10G has a structure that removes capacitor Cs[1] from semiconductor device 10A. When the parasitic capacitance of sufficient electrostatic capacitance necessary for the function required by the memory cell is generated in node ND, capacitor Cs[1] may not be provided. Alternatively, for example, the gate capacitance of transistor M2 may be used as capacitor Cs[1].

[0151] By omitting the capacitor Cs[1], the footprint of the semiconductor device 10G can be reduced. This allows for an increase in the integration density of the semiconductor device 10G. Furthermore, it allows for an increase in the storage density of memory devices using the semiconductor device 10G.

[0152] <Modification Example 7> Figures 10A and 10B show a modified example of semiconductor device 10H, which is a modified example of semiconductor device 10F shown in Figures 8A and 8B. Semiconductor device 10H shown in Figure 10A is a modified example of semiconductor device 10F shown in Figure 8A, and also a modified example of semiconductor device 10G shown in Figure 9A. Furthermore, semiconductor device 10H shown in Figure 10B is a modified example of semiconductor device 10F shown in Figure 8B, and also a modified example of semiconductor device 10G shown in Figure 9B. Therefore, semiconductor device 10H is also a modified example of semiconductor device 10A.

[0153] Semiconductor device 10H has a structure that removes capacitor Cs[1] from semiconductor device 10F. Furthermore, semiconductor device 10H has a structure that removes capacitors Cs[2] to Cs[n] from semiconductor device 10G. In cases where the parasitic capacitance of sufficient electrostatic capacitance necessary to generate the required function of the memory cell is sufficient in node ND, capacitors Cs[1] to Cs[n] can be omitted. Alternatively, for example, the gate capacitance of transistor M2 can be used as capacitors Cs[1] to Cs[n]. By omitting capacitors Cs[1] to Cs[n], the area occupied by semiconductor device 10H can be reduced. Furthermore, wiring COM is not required. Therefore, the integration density of semiconductor device 10H can be improved. Additionally, the storage density of memory devices using semiconductor device 10H can be increased.

[0154] <Operating Examples> Next, we will describe operating examples of writing and reading data from the semiconductor device 10A shown in FIG1A. Here, we will describe operating examples of writing data "1" to the semiconductor device 10A and reading data "1" from the semiconductor device 10A. Furthermore, the transistors M1 and M2 included in the semiconductor device 10A are normally off n-type transistors. FIG11 is a timing diagram used to illustrate operating examples of the semiconductor device 10A. FIG12A and FIG12B, FIG13A and FIG13B, and FIG14 are circuit diagrams used to illustrate operating examples of the semiconductor device 10A.

[0155] First, during period T0, the potentials of wiring WWL, wiring WBL, and node ND are potentials L, and the potentials of wiring RWL and wiring RBL are potentials H (see Figure 11). Additionally, assume that wiring COM is supplied with 0V.

[0156] [Data Writing Operation] During T11, wiring WWL and wiring WBL are supplied with potential H (see Figures 11 and 12A). Transistors M1[1] and M1[2] are then turned on, writing potential H to node ND as a potential equivalent to data "1". More precisely, a charge equal to potential H is supplied to node ND, representing the potential of node ND.

[0157] The gate, source, and drain of transistor M2 are all at the same potential (potential H), therefore transistor M2 is in the off state.

[0158] [Maintain Operation] During period T12, a potential L is supplied to the wiring WWL. As a result, transistors M1[1] and M1[2] are turned off, causing node ND to become floating. Thus, the data (charge) written to node ND is maintained (see Figures 11 and 12B).

[0159] As described above, the OS transistor is a transistor with extremely low off-state current. By using the OS transistor as transistor M1, data written to node ND can be retained for an extended period. Therefore, there is no need to refresh node ND, reducing the power consumption of the semiconductor device 10A.

[0160] Furthermore, OS transistors have a higher drain breakdown voltage compared to Si transistors. Therefore, by using an OS transistor as transistor M1, the range of potentials held at node ND can be increased. In other words, the potential difference between potential H and potential L can be widened. Therefore, multi-valued or analog data can be held at node ND.

[0161] Furthermore, by connecting multiple transistors M1 in series as transistors M1 positioned between node ND and wiring WBL, the off-state current can be further reduced, thereby improving the data retention capability of the semiconductor device 10A. Additionally, by incorporating multiple capacitors Cs within the semiconductor device 10A, its data retention capability can be further enhanced. By including multiple transistors M1 and multiple capacitors Cs in the semiconductor device 10A, data written to node ND can be retained for a longer period. In particular, data written to node ND can be retained for extended periods even in high-temperature environments above 100°C where off-state current tends to increase.

[0162] [Readout Operation] During period T21, the potential H is pre-charged to the wiring RBL. That is, while maintaining the potential H, the wiring RBL is kept in a floating state (refer to Figures 11 and 13A).

[0163] Next, during period T22, potential L is supplied to wiring RWL (refer to Figures 11 and 13B). With the potential of node ND at potential H, equivalent to data "1", transistor M2 turns on when the potential of wiring RWL changes from potential H to potential L. When transistor M2 is on, wiring RBL and wiring RWL are in a conducting state, and the potential of wiring RBL changes from potential H to potential L.

[0164] Note that when node ND maintains a potential L equivalent to data "0", transistor M2 will not be turned on even if a potential L is supplied to wiring RWL. At this time, the potential of wiring RBL remains at potential H. Therefore, by detecting the potential change of wiring RBL when a potential L is supplied to wiring RWL, the data held by semiconductor device 10A can be read.

[0165] Next, during period T23, a potential H is supplied to wiring RWL and wiring RBL (see Figures 11 and 14). When the potentials of wiring RWL and wiring RBL both reach potential H, transistor M2 is turned off.

[0166] According to one aspect of the present invention, a semiconductor device 10 (semiconductor device 10A, semiconductor device 10B, semiconductor device 10C, semiconductor device 10D, semiconductor device 10E, semiconductor device 10F, semiconductor device 10G, and semiconductor device 10H) is used as a storage cell in which charge is written to node ND via transistor M1. Therefore, for example, the high voltage required for flash memory is not needed, and high-speed write operations can be achieved. Furthermore, since no charge injection or extraction is performed on the floating gate or charge trapping layer, the semiconductor device 10 is substantially unrestricted in terms of the number of writes and reads. Unlike flash memory, even with repeated rewriting operations, no instability caused by the increase in electron trapping centers is observed in the semiconductor device 10. The semiconductor device 10 according to one aspect of the present invention exhibits less degradation and higher reliability compared to conventional flash memory. In particular, by using an OS transistor as transistor M1, data can be retained for a long time even at high temperatures, thereby achieving high reliability even at high temperatures.

[0167] Furthermore, unlike magnetic memories or resistive random access memories, the semiconductor device 10 according to one aspect of the present invention does not undergo atomic-level structural changes. Therefore, the rewrite resistance of the semiconductor device 10 according to one aspect of the present invention is higher than that of magnetic memories and resistive random access memories.

[0168] This embodiment can be implemented by appropriately combining the structures described in other embodiments, etc.

[0169] (Embodiment 2) In this embodiment, a transistor that can be used in a semiconductor device according to one aspect of the present invention is described.

[0170] <Example 1 of Transistor Structure> Figure 16A is a planar view of a transistor 200A that can be used in a semiconductor device according to one aspect of the present invention. Transistor 200A is an example of a planar transistor. Furthermore, in this specification, a planar transistor refers to a structure in which the source electrode and drain electrode are located at the same height or substantially at the same height and the current flowing through the semiconductor has a lateral component.

[0171] Figure 16B is a cross-sectional view along the dashed-dot line A1-A2 in Figure 16A. Figure 16C is a cross-sectional view along the dashed-dot line A3-A4 in Figure 16A. Note that in the plan view of Figure 16A, some components are omitted for clarity. Sometimes, some components are also omitted in other plan views.

[0172] Transistor 200A includes an insulating layer 202 on a substrate 201, and a semiconductor layer 203 on the insulating layer 202. Furthermore, an insulating layer 204 is included on both the insulating layer 202 and the semiconductor layer 203. Additionally, a conductive layer 205 is included on the insulating layer 204. The semiconductor layer 203 and the conductive layer 205 have regions that overlap each other across the insulating layer 204.

[0173] Semiconductor layer 203 includes region 203a, channel forming region 203b, and region 203c. Region 203a is used as one of the source and drain regions. Region 203c is used as the other of the source and drain regions. In semiconductor layer 203, the region overlapping with conductive layer 205 is used as channel forming region 203b. Therefore, conductive layer 205 is used as the gate electrode of transistor 200A. Furthermore, insulating layer 204 is used as the gate insulating layer of transistor 200A.

[0174] Furthermore, the length of the channel forming region 203b in the X direction is the channel length L of the transistor 200A (see Figure 16B). Furthermore, the length of the channel forming region 203b in the Y direction is the channel width W of the transistor 200A (see Figure 16C).

[0175] Furthermore, an insulating layer 206 is included on the insulating layer 204 and the conductive layer 205. Additionally, in the region overlapping with region 203a of the semiconductor layer 203, openings 207a are provided in the insulating layers 204 and 206. Furthermore, in the region overlapping with region 203c of the semiconductor layer 203, openings 207b are provided in the insulating layers 204 and 206.

[0176] Furthermore, a conductive layer 208a is provided on the insulating layer 206 and the opening 207a, and a conductive layer 208b is provided on the insulating layer 206 and the opening 207b. The conductive layer 208a is connected to region 203a of the semiconductor layer 203 at the bottom of the opening 207a. Furthermore, the conductive layer 208b is connected to region 203c of the semiconductor layer 203 at the bottom of the opening 207b. Therefore, the conductive layer 208a is used as one of the source electrode and drain electrode of the transistor 200A, and the conductive layer 208b is used as the other of the source electrode and drain electrode of the transistor 200A.

[0177] In addition, an insulating layer 209 is provided on the insulating layer 206 and the conductive layer 208 (conductive layer 208a and conductive layer 208b).

[0178] <Example 2 of Transistor Structure> Figure 17A is a plan view of a transistor 200B that can be used in a semiconductor device according to one aspect of the present invention. Transistor 200B is a variation of transistor 200A. Therefore, to avoid repetition, the differences between transistor 200B and transistor 200A will be described primarily.

[0179] Figure 17B is a cross-sectional view along the dashed line A1-A2 in Figure 17A. Figure 17C is a cross-sectional view along the dashed line A3-A4 in Figure 17A.

[0180] The difference between transistor 200B and transistor 200A is that transistor 200B includes a conductive layer 219 between the substrate 201 and the insulating layer 202. The conductive layer 219 serves as the back gate electrode of transistor 200B. Therefore, the conductive layer 219 overlaps with the channel formation region 203b. Furthermore, the conductive layer 219 preferably extends beyond the end of the channel formation region 203b. That is, it is preferable that the channel formation region 203b is covered by the conductive layer 219. By covering the channel formation region 203b with the conductive layer 219, the electric field shielding effect described in the above embodiment can be improved.

[0181] <Example 3 of transistor structure> Figure 18A is a plan view of a transistor 200C that can be used in a semiconductor device according to one aspect of the present invention. Figure 18B is a cross-sectional view along the dotted line A1-A2 in Figure 18A.

[0182] In transistor 200C, an insulating layer 202 is included on substrate 201, and a conductive layer 255 is included on insulating layer 202. Furthermore, an insulating layer 257 is included on conductive layer 255, an insulating layer 258 is included on insulating layer 257, and an insulating layer 259 is included on insulating layer 258. In this specification, insulating layers 257, 258, and 259 are sometimes collectively referred to as insulating layer 256 or spacer layer. Additionally, a conductive layer 261 is included on insulating layer 259.

[0183] An opening 262 is provided in a region that overlaps with a portion of the conductive layer 255, passing through the conductive layer 261, insulating layer 259, insulating layer 258, and insulating layer 257. Furthermore, a semiconductor layer 263 is provided to cover the opening 262.

[0184] Semiconductor layer 263 has a region overlapping the bottom of opening 262 and a region overlapping the side of opening 262. That is, semiconductor layer 263 has a region that contacts insulating layer 256 inside opening 262. In addition, semiconductor layer 263 has a region that contacts conductive layer 255 and conductive layer 261 inside opening 262.

[0185] Furthermore, an insulating layer 264 is provided on the insulating layer 259, the conductive layer 261, and the semiconductor layer 263. A conductive layer 265 is provided on the insulating layer 264. The conductive layer 265 has a region that overlaps with the semiconductor layer 263. The conductive layer 265 also has a region that overlaps with the semiconductor layer 263 through the insulating layer 264.

[0186] Furthermore, both the insulating layer 264 and the conductive layer 265 have regions that overlap with the opening 262. Additionally, both the insulating layer 264 and the conductive layer 265 have regions that overlap with the inner side of the opening 262. Inside the opening 262, the semiconductor layer 263 has a region that overlaps with the conductive layer 265 across the insulating layer 264 and a region that overlaps with the side surface of the opening 262 (the side surface of the insulating layer 256).

[0187] Furthermore, an insulating layer 266 is included on the insulating layer 264. The top surface of the insulating layer 266 is preferably flat. Alternatively, the height (position in the Z direction) of the top surface of the insulating layer 266 and the conductive layer 265 is preferably the same or substantially the same. For example, the flatness of the top surface of the insulating layer 266 can be improved by performing chemical mechanical polishing (CMP). Furthermore, CMP treatment can make the top surfaces of the insulating layer 266 and the conductive layer 265 coincide or substantially coincide. CMP treatment can reduce the unevenness of the sample surface, thereby improving the coverage of the subsequently formed insulating and conductive layers.

[0188] Furthermore, when an oxide semiconductor is used for semiconductor layer 263, the conductive layer 255 and the conductive layer 261 in contact with semiconductor layer 263 preferably use conductive materials that n-type the oxide semiconductor. For example, a nitrogen-containing conductive material can be used. For example, a conductive material containing titanium or tantalum and nitrogen can be used. Alternatively, other conductive materials can be provided in a manner that overlaps with the nitrogen-containing conductive material.

[0189] When an oxide semiconductor is used as the semiconductor layer 263, an insulating material containing oxygen and with reduced hydrogen content is preferably used as the insulating layer 258. For example, a material containing silicon and oxygen can be used. Specifically, silicon oxide or silicon oxynitride can be used. In oxide semiconductors, hydrogen is an impurity element, so when the semiconductor layer 263 of the oxide semiconductor is in contact with the hydrogen-reducing insulating layer 258, the semiconductor layer 263 is less likely to be n-type. Furthermore, when the semiconductor layer 263 of the oxide semiconductor is in contact with the oxygen-containing insulating layer 258, the oxygen vacancies in the semiconductor layer 263 are reduced, the transistor characteristics become more stable, and the reliability is improved.

[0190] Furthermore, when an oxide semiconductor is used for semiconductor layer 263, insulating layer 258 preferably contains excess oxygen. In this specification, excess oxygen refers to oxygen removed by heating. Material with oxygen removed by heating is defined as material with an oxygen removal amount equivalent to oxygen atoms in TDS (Thermal Desorption Spectroscopy) analysis of 1.0 × 10⁻⁶. 18 atoms / cm 3 The preferred value is 1.0 × 10⁴. 19 atoms / cm 3 The above is further preferred to be 2.0×10 19 atoms / cm 3 The above, or 3.0×10 20 atoms / cm 3 The above materials. Furthermore, the surface temperature of the membrane during the TDS analysis is preferably between 100°C and 700°C, or between 100°C and 400°C.

[0191] Furthermore, when the insulating layer 258 uses a material containing excess oxygen, the insulating layers 257 and 259 are preferably made of materials that do not readily allow oxygen to permeate. Examples of materials that do not readily allow oxygen to permeate include oxides containing one or both of aluminum and hafnium, silicon nitrides, etc. By using materials that do not readily allow oxygen to permeate in the insulating layers 257 and 259, excess oxygen contained in the insulating layer 258 is less likely to detach to the lower or upper layers. Therefore, sufficient oxygen can be supplied to the oxide semiconductor. For example, an insulating layer (insulating layer 258) containing silicon and oxygen can be included between the two insulating layers (insulating layer 257, insulating layer 259) containing silicon and nitrogen.

[0192] Furthermore, when an oxide semiconductor is used as semiconductor layer 263, by using a hydrogen-containing material as insulating layers 257 and 259, hydrogen is supplied to the regions of semiconductor layer 263 that contact insulating layer 257 and the regions of semiconductor layer 263 that contact insulating layer 259, and each region in semiconductor layer 263 is n-type. Therefore, the regions of semiconductor layer 263 that contact conductive layer 261 and the regions of semiconductor layer 263 that contact insulating layer 259 are used as one of the source and drain regions. Furthermore, the regions of semiconductor layer 263 that contact conductive layer 255 and the regions of semiconductor layer 263 that contact insulating layer 257 are used as the other of the source and drain regions.

[0193] Conductive layer 261 is used as one of the source and drain electrodes of transistor 200C. Conductive layer 255 is used as the other of the source and drain electrodes of transistor 200C. That is, transistor 200C is a transistor in which the source and drain electrodes are arranged in the Z direction. In other words, the source and drain of transistor 200C are arranged at different heights. In other words, the source and drain of transistor 200C are arranged at different positions in the Z direction. This type of transistor is also called a "vertical channel transistor", "vertical type transistor", "vertical transistor" or "VFET (Vertical Field Effect Transistor)".

[0194] In the above structure, in the VFET transistor 200C, the length of the side of the insulating layer 158 when viewed from the X or Y direction is the channel length L (channel length L1) (see Figure 18B). Therefore, the channel length L of the transistor 200C is determined according to the thickness t1 of the insulating layer 258.

[0195] Furthermore, insulating layers 257 and 259 are preferably made of materials containing no hydrogen or very little hydrogen. For example, silicon nitride or silicon oxynitride with very little hydrogen can be used. In this case, the regions where semiconductor layer 263 contacts insulating layer 257 and the regions where semiconductor layer 263 contacts insulating layer 259 are not n-type. Therefore, the region of semiconductor layer 263 that contacts conductive layer 261 is used as one of the source and drain regions. Furthermore, the region of semiconductor layer 263 that contacts conductive layer 255 is used as the other of the source and drain regions. Furthermore, the region of semiconductor layer 263 that contacts insulating layer 258 is used as a channel formation region.

[0196] In this case, the total length of the sides of insulating layers 257, 258, and 259 when viewed from the X or Y direction is the channel length L (channel length L2). Therefore, the channel length L of transistor 200C is determined based on the total thickness t2 of insulating layers 257, 258, and 259. Thus, transistor 200C has a channel forming region along the side of insulating layer 256.

[0197] Since the semiconductor layer 263 is disposed in the opening 262, the perimeter of the opening 262 when viewed in the Z direction is the channel width W of the transistor 200C (see Figure 18A). For example, the perimeter can be determined at a position where the thickness t1 or t2 of the insulating layer 258 is halfway between these points. Note that, as needed, the perimeter of any position of the opening 262 can be set as the channel width W. For example, the perimeter of the lowermost part of the opening 262 can be set as the channel width W, or the perimeter of the uppermost part of the opening 262 can be set as the channel width W. Furthermore, in Figure 18A, the outline (planar shape) of the opening 262 when viewed in the Z direction is shown as a circle, but it is not limited to this. For example, the outline of the opening 262 when viewed in the Z direction can also be elliptical or rectangular.

[0198] Furthermore, when the transistor 200C is used as a switch, the channel length L of the transistor 200C is preferably at least less than the channel width W. For example, the channel length L is preferably 0.1 times or more and 0.99 times or less of the channel width W, more preferably 0.5 times or more and 0.8 times or less.

[0199] Furthermore, in order to improve the coverage of the semiconductor layer 263, insulating layer 264, and conductive layer 265 formed inside the opening 262, it is preferable to set the cone angle θ of the side surface of the opening 262, i.e., the cone angle θ of the side surface of each of the insulating layers 257, 258, and 259, to be 45 degrees or more and 90 degrees or less, more preferably 50 degrees or more and 75 degrees or less. The cone angle θ of the side surface of a layer (insulating layer, conductive layer, or semiconductor layer) refers to the angle formed between the bottom surface and the side surface of the layer (see Figure 18B).

[0200] Compared to planar transistors (also known as channel transistors) where the channel formation region, source region, and drain region are respectively located on the XY plane, vertical-channel transistors can reduce the occupied area. Furthermore, by using vertical-channel transistors in semiconductor devices, the occupied area of ​​the semiconductor device can be reduced. Using vertical-channel transistors in semiconductor devices enables high integration of semiconductor devices.

[0201] Furthermore, the channel length of a planar transistor is limited by the exposure limit of photolithography. According to one aspect of the present invention, the channel length of a vertical-channel transistor can be set according to the thickness of the insulating layer 256 or the insulating layer 258. Therefore, the channel length of the transistor can be set to be very fine, i.e., below the exposure limit of photolithography (e.g., below 60 nm, 50 nm, 40 nm, 30 nm, 20 nm, or 10 nm, and above 1 nm or 5 nm). As a result, the on-state current of the transistor 200C increases, thereby improving frequency characteristics. By employing a vertical-channel transistor, a high-speed semiconductor device can be provided.

[0202] <Example 4 of Transistor Structure> Figure 19A is a plan view of a transistor 200D that can be used in a semiconductor device according to one aspect of the present invention. Transistor 200D is a variation of transistor 200C. To avoid repetition, the differences between transistor 200D and transistor 200C will be described primarily.

[0203] Figure 19B is a cross-sectional view along the dashed line A1-A2 in Figure 19A. Figure 19A is a cross-sectional view along the channel length of transistor 200D.

[0204] Transistor 200D includes insulating layers 258a and 258b between insulating layers 257 and 259, and a conductive layer 267 between insulating layers 258a and 258b. Insulating layers 258a and 258b can be formed using the same material and method as insulating layer 258. Furthermore, the opening 262 of transistor 200D is provided in a region overlapping a portion of conductive layer 255, extending through conductive layer 261, insulating layer 259, insulating layer 258b, conductive layer 267, insulating layer 258a, and insulating layer 257.

[0205] Additionally, in transistor 200D, an insulating layer 268 is provided along the side of opening 262. Inside opening 262, insulating layer 268 has regions overlapping with the side of conductive layer 261, regions overlapping with the side of insulating layer 259, regions overlapping with the side of insulating layer 258b, regions overlapping with the side of conductive layer 267, regions overlapping with the side of insulating layer 258a, and regions overlapping with the side of insulating layer 257.

[0206] Furthermore, the semiconductor layer 263 in transistor 200D has a region inside the opening 262 that overlaps with the side of the conductive layer 261 separated by insulating layer 268, a region that overlaps with the side of the insulating layer 259 separated by insulating layer 268, a region that overlaps with the side of the insulating layer 258b separated by insulating layer 268, a region that overlaps with the side of the conductive layer 267 separated by insulating layer 268, a region that overlaps with the side of the insulating layer 258a separated by insulating layer 268, and a region that overlaps with the side of the insulating layer 257 separated by insulating layer 268.

[0207] When conductive layer 265 is used as the gate electrode, conductive layer 267 is used as the back gate electrode. Furthermore, when conductive layer 267 is used as the gate electrode, conductive layer 265 is used as the back gate electrode. One of insulating layers 264 and 268 is used as the gate insulating layer, and the other of insulating layers 264 and 268 is used as the back gate insulating layer. Insulating layer 268 can be formed using the same material and method as insulating layer 264.

[0208] <Example 5 of Transistor Structure> Figure 20A is a plan view of a transistor 200E that can be used in a semiconductor device according to one aspect of the present invention. Figure 20B is a cross-sectional view along the dotted lines A1-A2 in Figure 20A. Figure 20C is a cross-sectional view along the dotted lines A3-A4 in Figure 20A. Note that Figure 20A is a cross-sectional view along the channel length direction of the transistor 200E, and Figure 20C is a cross-sectional view along the channel width direction of the transistor 200E.

[0209] As shown in Figures 20A to 20C, transistor 200E includes a semiconductor layer 520a disposed on a substrate 201, a semiconductor layer 520b disposed on semiconductor layer 520a, conductive layers 542a and 542b separately disposed on semiconductor layer 520b, an insulating layer 580 disposed on conductive layers 542a and 542b and having an opening formed between conductive layers 542a and 542b, a conductive layer 560 disposed in the opening, an insulating layer 550 disposed between semiconductor layer 520b, conductive layer 542a, conductive layer 542b and insulating layer 580 and conductive layer 560, and a semiconductor layer 520c disposed between semiconductor layer 520b, conductive layer 542a, conductive layer 542b and insulating layer 580 and insulating layer 550. Here, as shown in Figures 20B and 20C, the top surface of conductive layer 560 is substantially aligned with the top surfaces of insulating layers 550, 554, semiconductor layer 520c, and 580. Furthermore, semiconductor layers 520a, 520b, and 520c are sometimes collectively referred to as semiconductor layer 520. Additionally, conductive layers 542a and 542b are sometimes collectively referred to as conductive layer 542.

[0210] As shown in Figures 20A to 20C, an insulating layer 554 is disposed between an insulating layer 524, semiconductor layers 520a, 520b, conductive layers 542a, 542b, and 520c, and an insulating layer 580. The insulating layer 554 is in contact with the side surface of semiconductor layer 520c, the top and side surfaces of conductive layer 542a, the top and side surfaces of conductive layer 542b, the side surfaces of semiconductor layers 520a and 520b, and the top surface of insulating layer 524.

[0211] Note that in transistor 200E, three semiconductor layers 520a, 520b, and 520c are stacked in and around the channel formation region; however, the present invention is not limited to this. For example, a two-layer structure of semiconductor layers 520b and 520c, or a stacked structure of four or more layers, can be used. Furthermore, semiconductor layers 520a, 520b, and 520c can each have a stacked structure of two or more layers.

[0212] For example, in the case where an oxide semiconductor is used as one of the metal oxides as semiconductor layer 520 and semiconductor layer 520c has a stacked structure composed of a first metal oxide and a second metal oxide on the first metal oxide, the first metal oxide may have the same composition as semiconductor layer 520b and the second metal oxide may have the same composition as semiconductor layer 520a.

[0213] Here, conductive layer 560 is used as the gate electrode of the transistor, and conductive layers 542a and 542b are each used as the source electrode or drain electrode of the transistor. As described above, conductive layer 560 is formed by embedding it into the opening of insulating layer 580 and sandwiching it between conductive layers 542a and 542b. Here, conductive layers 560, 542a, and 542b are self-aligned relative to the opening of insulating layer 580. That is, in transistor 200E, the gate electrode can be self-aligned between the source electrode and the drain electrode. Therefore, conductive layer 560 can be formed without leaving room for position alignment, thus reducing the occupied area of ​​transistor 200E. This reduces the occupied area of ​​the semiconductor device. Furthermore, it increases the integration density of the semiconductor device.

[0214] As shown in Figures 20A to 20C, the conductive layer 560 preferably includes a conductive layer 560a disposed inside the insulating layer 550 and a conductive layer 560b disposed in a manner embedded inside the conductive layer 560a. Furthermore, in the transistor 200E, the conductive layer 560 has a two-layer stacked structure, but the present invention is not limited to this. For example, the conductive layer 560 may also have a single-layer structure or a stacked structure of three or more layers.

[0215] Transistor 200E includes an insulating layer 202 disposed on substrate 201, an insulating layer 514 disposed on insulating layer 202, an insulating layer 516 disposed on insulating layer 514, a conductive layer 505 disposed in insulating layer 516, an insulating layer 522 disposed on insulating layer 516 and conductive layer 505, and an insulating layer 524 disposed on insulating layer 522. Furthermore, a semiconductor layer 520a is disposed on insulating layer 524.

[0216] In addition, an insulating layer 574 and an insulating layer 581, which serve as interlayer films, are disposed on transistor 200E. The insulating layer 574 is disposed in contact with the top surfaces of conductive layer 560, insulating layer 550, insulating layer 554, semiconductor layer 520c, and insulating layer 580.

[0217] When an oxide semiconductor is used as the semiconductor layer 520, insulating layers 522, 554, and 574 are preferably used as insulating layers that have the function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). For example, insulating layers 522, 554, and 574 are preferably used as insulating layers with lower hydrogen permeability than insulating layers 524, 550, and 580. Furthermore, insulating layers 522 and 554 are preferably used as insulating layers that have the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules, etc.). For example, insulating layers 522 and 554 are preferably used as insulating layers with lower oxygen permeability than insulating layers 524, 550, and 580.

[0218] Here, insulating layer 524, semiconductor layer 520, and insulating layer 550 are separated by insulating layer 522 and insulating layer 574. As a result, impurities such as hydrogen and excess oxygen contained in the upper layer of insulating layer 574 and the lower layer of insulating layer 522 can be suppressed from mixing into insulating layer 524, semiconductor layer 520, and insulating layer 550.

[0219] Figure 20B shows an example of a conductive layer 545 (conductive layer 545a and conductive layer 545b) that is connected to the transistor 200E and serves as a connector. Furthermore, an insulating layer 541 (insulating layer 541a and insulating layer 541b) is provided that contacts the side surface of the conductive layer 545 used as a connector. That is, the insulating layer 541 is provided in contact with the inner wall of the openings of the insulating layers 554, 580, 574, and 581. In Figure 20B, a first conductive layer of the conductive layer 545 is provided in contact with the side surface of the insulating layer 541, and a second conductive layer of the conductive layer 545 is provided inside the first conductive layer of the conductive layer 545.

[0220] Here, the height of the top surface of the conductive layer 545 can be approximately the same as the height of the top surface of the insulating layer 581. Furthermore, transistor 200E shows a structure with a first conductive layer and a second conductive layer of the conductive layer 545 stacked together, but the present invention is not limited thereto. For example, the conductive layer 545 can have a single-layer structure or a stacked structure of three or more layers. In the case of a stacked structure, ordinal numbers are sometimes assigned according to the order of formation for distinction.

[0221] Furthermore, the thickness of the region in semiconductor layer 520b that does not overlap with conductive layer 542 is sometimes thinner than the thickness of the region that overlaps with conductive layer 542. This thinner region is formed by removing a portion of the top surface of semiconductor layer 520b during the formation of conductive layers 542a and 542b. When a conductive film is deposited on the top surface of semiconductor layer 520b to form conductive layer 542, a low-resistance region is sometimes formed near the interface with the conductive film. Thus, by removing the low-resistance region on the top surface of semiconductor layer 520b located between conductive layers 542a and 542b, channel formation in this region can be suppressed.

[0222] Next, the detailed structure of the transistor 200E, which can be used in a semiconductor device according to one aspect of the present invention, will be described.

[0223] The conductive layer 505 is configured to have an overlapping region between the semiconductor layer 520 and the conductive layer 560. Furthermore, by providing the conductive layer 505 in a manner embedded in the insulating layer 516, the unevenness of the top surfaces of the conductive layer 505 and the insulating layer 516 can be reduced, thereby improving the coverage of the layers formed in subsequent processes.

[0224] The conductive layer 505 includes conductive layers 505a, 505b, and 505c. Conductive layer 505a is disposed in contact with the bottom and sidewalls of an opening in the insulating layer 516. Conductive layer 505b is disposed embedded in a recess formed in conductive layer 505a. Here, the top surface of conductive layer 505b is lower than the top surface of conductive layer 505a and the top surface of insulating layer 516. Conductive layer 505c is disposed in contact with the top surface of conductive layer 505b and the side surface of conductive layer 505a. Here, the height of the top surface of conductive layer 505c is approximately the same as the height of the top surface of conductive layer 505a and the top surface of insulating layer 516. In other words, conductive layer 505b is surrounded by conductive layers 505a and 505c.

[0225] When using an oxide semiconductor as the semiconductor layer 520, conductive layers 505a and 505c are preferably made of conductive materials that suppress the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, or NO2, etc.), or copper atoms. Alternatively, conductive materials that suppress the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules) are preferably used.

[0226] By using a conductive material that inhibits hydrogen diffusion as conductive layers 505a and 505c, impurities such as hydrogen contained in conductive layer 505b can be prevented from diffusing to semiconductor layer 520 through insulating layer 524, etc. Furthermore, by using a conductive material that inhibits oxygen diffusion as conductive layers 505a and 505c, oxidation of conductive layer 505b and a decrease in conductivity can be prevented. Examples of conductive materials that inhibit oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, conductive layer 505a can be a single layer or a stack of the aforementioned conductive materials. For example, titanium nitride can be used as conductive layer 505a.

[0227] Furthermore, conductive layer 505b is preferably made of a conductive material with tungsten, copper, or aluminum as its main components. For example, tungsten is preferably used for conductive layer 505b. When conductive layer 560 is used as the gate electrode, conductive layer 505 is used as the back gate electrode.

[0228] The conductive layer 505 is preferably larger than the channel formation region in the semiconductor layer 520. In particular, as shown in FIG20C, the conductive layer 505 preferably extends to the region outside the end that intersects with the channel width direction of the semiconductor layer 520. That is, preferably, the conductive layer 505 and the conductive layer 560 overlap with an insulating layer on the outer side of the side of the semiconductor layer 520 in the channel width direction.

[0229] With the above structure, a region can be formed around the channel of the semiconductor layer 520 by the electric field of the conductive layer 560 used as the gate electrode and the electric field of the conductive layer 505 used as the back gate electrode.

[0230] The conductive layer 505 may extend beyond the end of the semiconductor layer 520 to serve as wiring. However, it is not limited to this; a conductive layer for wiring may be provided under the conductive layer 505.

[0231] As the insulating layer 514, it is preferable to use an insulating material that serves as a barrier insulating film to prevent impurities such as water or hydrogen from entering the transistor 200E from the substrate side. Therefore, as the insulating layer 514, it is preferable to use an insulating material that has the function of inhibiting the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms (making it difficult for the aforementioned impurities to permeate). Alternatively, it is preferable to use an insulating material that has the function of inhibiting the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules, etc.) (making it difficult for the aforementioned oxygen to permeate).

[0232] For example, it is preferable to use aluminum oxide or silicon nitride as the insulating layer 514. This can suppress the diffusion of impurities such as water or hydrogen from the side closer to the substrate than the insulating layer 514 to the transistor 200E side. Alternatively, it can suppress the diffusion of oxygen contained in the insulating layer 524, etc., to the side closer to the substrate than the insulating layer 514.

[0233] As insulating layers 516, 580, and 581 used as interlayer films, insulating materials with a lower dielectric constant than insulating layer 514 are preferably used. By using materials with low dielectric constants in the interlayer films, parasitic capacitance generated between wirings can be reduced. For example, silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, fluorinated silicon oxide, carbon-containing silicon oxide, silicon oxide containing both carbon and nitrogen, or porous silicon oxide can be appropriately used as insulating layers 516, 580, and 581.

[0234] When the conductive layer 560 is used as the gate electrode, the insulating layers 522 and 524 are used as gate insulating layers.

[0235] Here, the insulating layer 524 in contact with the semiconductor layer 520 preferably contains excess oxygen. For example, silicon oxide or silicon oxynitride can be appropriately used as the insulating layer 524. By providing an insulating layer containing oxygen in contact with the semiconductor layer 520, oxygen vacancies in the semiconductor layer 520 can be reduced, thereby improving the reliability of the transistor 200E.

[0236] As shown in Figure 20C, sometimes the thickness of the region in insulating layer 524 that does not overlap with insulating layer 554 or semiconductor layer 520b is thinner than the thickness of other regions. The thickness of the region in insulating layer 524 that does not overlap with insulating layer 554 or semiconductor layer 520b is preferably sufficient to allow the aforementioned oxygen to diffuse.

[0237] Similar to insulating layer 514, insulating layer 522 is preferably made of a material that serves as a barrier insulating film to prevent impurities such as water or hydrogen from mixing into transistor 200E from the substrate side. For example, insulating layer 522 is made of a material whose hydrogen permeability is lower than that of insulating layer 524. By surrounding insulating layer 524, semiconductor layer 520, and insulating layer 550 with insulating layer 522, insulating layer 554, and insulating layer 574, impurities such as water or hydrogen from entering transistor 200E from the outside can be prevented.

[0238] Furthermore, as the insulating layer 522, it is preferable to use a material that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules) (making it difficult for the aforementioned oxygen to permeate). For example, a material with lower oxygen permeability than the insulating layer 524 is used as the insulating layer 522. By giving the insulating layer 522 the function of suppressing the diffusion of oxygen and impurities, the amount of oxygen diffusing from the semiconductor layer 520 to the substrate side can be reduced. In addition, the reaction between the conductive layer 505 and the oxygen contained in the insulating layer 524 and the semiconductor layer 520 can be suppressed.

[0239] As the insulating layer 522, it is preferable to use an insulating layer containing an oxide of one or both of aluminum and hafnium as insulating materials. Aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate) are preferred as insulating layers containing one or both of aluminum and hafnium. When this material is used to form the insulating layer 522, the insulating layer 522 serves as a layer to suppress the release of oxygen from the semiconductor layer 520 and the entry of impurities such as hydrogen from the periphery of the transistor 200E into the semiconductor layer 520.

[0240] Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulating layer. Alternatively, the insulating layer may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may also be stacked on the insulating layer. For example, insulating layer 522 may be constructed by sequentially stacking silicon nitride, silicon oxide, and aluminum oxide.

[0241] As the insulating layer 522, for example, a single layer or a stack of insulating layers containing so-called high-k materials such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST) can be used. With the miniaturization and high integration of transistors, problems such as leakage current sometimes occur due to the thinning of the gate insulating layer. By using a high-k material as the insulating layer used as the gate insulating layer, the gate potential during transistor operation can be reduced while maintaining the physical thickness.

[0242] Furthermore, insulating layers 522 and 524 may each have a stacked structure of two or more layers. In this case, it is not limited to a stacked structure made of the same material, and thus a stacked structure made of different materials may also be possible.

[0243] Semiconductor layer 520 includes semiconductor layer 520a, semiconductor layer 520b on semiconductor layer 520a, and semiconductor layer 520c on semiconductor layer 520b. When semiconductor layer 520a is disposed under semiconductor layer 520b, the diffusion of impurities from structures formed below semiconductor layer 520a to semiconductor layer 520b can be suppressed. When semiconductor layer 520c is disposed on semiconductor layer 520b, the diffusion of impurities from structures formed above semiconductor layer 520c to semiconductor layer 520b can be suppressed.

[0244] Furthermore, when an oxide semiconductor is used as the semiconductor layer 520, the semiconductor layer 520 preferably employs a stacked structure of multiple oxide layers with different atomic ratios for each metal atom. For example, when the semiconductor layer 520 contains at least indium (In) and element M, the atomic ratio of element M in semiconductor layer 520a to all elements constituting semiconductor layer 520a is higher than the atomic ratio of element M in semiconductor layer 520b to all elements constituting semiconductor layer 520b. Furthermore, the atomic ratio of element M to In in semiconductor layer 520a is greater than the atomic ratio of element M to In in semiconductor layer 520b. Here, the semiconductor layer 520c can use a metal oxide that can be used in either semiconductor layer 520a or semiconductor layer 520b.

[0245] The conduction band bottom energies of semiconductor layers 520a and 520c are preferably higher than those of semiconductor layer 520b. Furthermore, in other words, the electron affinity of semiconductor layers 520a and 520c is preferably lower than that of semiconductor layer 520b. In this case, a metal oxide suitable for semiconductor layer 520a can be used as semiconductor layer 520c. Specifically, it is preferable that the atomic ratio of element M in semiconductor layer 520c to all elements constituting semiconductor layer 520c is higher than the atomic ratio of element M in semiconductor layer 520b to all elements constituting semiconductor layer 520b. Furthermore, it is preferable that the atomic ratio of element M to In in semiconductor layer 520c is greater than the atomic ratio of element M to In in semiconductor layer 520b.

[0246] Here, the energy level of the conduction band bottom in the junction of semiconductor layers 520a, 520b, and 520c changes gradually. In other words, the above situation can also be expressed as the energy level of the conduction band bottom at the junction of semiconductor layers 520a, 520b, and 520c changing continuously or continuously joining. For this purpose, it is preferable to reduce the defect state density of the mixed layer formed at the interface between semiconductor layers 520a and 520b and at the interface between semiconductor layers 520b and 520c.

[0247] Specifically, when semiconductor layers 520a and 520b, and semiconductor layers 520b and 520c, contain a common element other than oxygen (with the common element other than oxygen as the main component), a mixed layer with low defect state density can be formed. For example, when semiconductor layer 520b is an In-Ga-Zn oxide, In-Ga-Zn oxide, Ga-Zn oxide, and gallium oxide can also be used as semiconductor layers 520a and 520c. Furthermore, semiconductor layer 520c can also have a stacked structure. For example, a stacked structure of In-Ga-Zn oxide and Ga-Zn oxide on the In-Ga-Zn oxide can be used, or a stacked structure of In-Ga-Zn oxide and gallium oxide on the In-Ga-Zn oxide can be used. In other words, a stacked structure of In-Ga-Zn oxide and an oxide not containing In can also be used as semiconductor layer 520c.

[0248] Specifically, for semiconductor layer 520a, a metal oxide with an atomic ratio of In:Ga:Zn of 1:3:4 or similar, or an atomic ratio of 1:1:0.5 or similar, can be used. Furthermore, for semiconductor layer 520b, a metal oxide with an atomic ratio of In:Ga:Zn of 4:2:3 or similar, an atomic ratio of 3:1:2 or similar, or an atomic ratio of 1:1:1 or similar, can be used. Furthermore, for semiconductor layer 520c, a metal oxide with an atomic ratio of In:Ga:Zn of 1:3:4 or similar, an atomic ratio of In:Ga:Zn of 4:2:3 or similar, an atomic ratio of Ga:Zn of 2:1 or similar, or an atomic ratio of Ga:Zn of 2:5 or similar, can be used. Furthermore, as specific examples of semiconductor layer 520c having a stacked structure, we can cite stacked structures with In:Ga:Zn=4:2:3 [atomic ratio] or near and Ga:Zn=2:1 [atomic ratio] or near, stacked structures with In:Ga:Zn=4:2:3 [atomic ratio] or near and Ga:Zn=2:5 [atomic ratio] or near, stacked structures with In:Ga:Zn=4:2:3 [atomic ratio] or near and gallium oxide, etc.

[0249] At this point, the primary path for charge carriers is through semiconductor layer 520b. By equipping semiconductor layers 520a and 520c with the aforementioned structure, the defect state density at the interfaces between semiconductor layers 520a and 520b, and between semiconductor layers 520b and 520c, can be reduced. Therefore, the influence of interface scattering on charge carrier conduction is reduced, resulting in a large on-state current and high-frequency characteristics for transistor 200E. Furthermore, when semiconductor layer 520c employs a stacked structure, the following two effects can be expected: reducing the defect state density at the interfaces between semiconductor layers 520b and 520c, and suppressing the diffusion of constituent elements from semiconductor layer 520c to the insulating layer 550. More specifically, when semiconductor layer 520c has a stacked structure, because the oxide layer without In is located on top of the stacked structure, the diffusion of In to the insulating layer 550 can be suppressed. The insulating layer 550 is used as the gate insulating layer, and therefore, In diffusion leads to poor transistor characteristics. Therefore, by giving the semiconductor layer 520c a stacked structure, a highly reliable semiconductor device can be provided.

[0250] A conductive layer 542 (conductive layer 542a and conductive layer 542b) serving as a source electrode and a drain electrode is provided on the semiconductor layer 520b. When an oxide semiconductor is used as the semiconductor layer 520b, a conductive material that is not easily oxidized or a conductive material that maintains conductivity even when absorbing oxygen is preferably used as the conductive layer 542.

[0251] The region of the semiconductor layer 520 that contacts the conductive layer 542 is used as the source or drain region of the transistor 200E. Here, the region between the conductive layers 542a and 542b is formed in a manner that overlaps with the opening of the insulating layer 580. Therefore, the conductive layer 560 can be self-aligned between the conductive layers 542a and 542b.

[0252] An insulating layer 550 is used as a gate insulating layer. The insulating layer 550 is configured to contact the top surface of the semiconductor layer 520c. The insulating layer 550 can be silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, or porous silicon oxide. For example, silicon oxide or silicon oxynitride can be used as the insulating layer 550.

[0253] Similar to insulating layer 524, insulating layer 550 uses an insulating material with reduced concentration of impurities such as water or hydrogen. The thickness of insulating layer 550 is preferably 1 nm or more and 20 nm or less.

[0254] Furthermore, it is preferable to provide a metal oxide between the insulating layer 550 and the conductive layer 560. This metal oxide suppresses the diffusion of oxygen from the insulating layer 550 to the conductive layer 560. Thus, oxidation of the conductive layer 560 caused by oxygen in the insulating layer 550 can be suppressed.

[0255] Although the conductive layer 560 in Figures 20A to 20C has a two-layer structure, it can also have a single-layer structure or a stacked structure of three or more layers.

[0256] The conductive layer 560a preferably uses the aforementioned conductive layer that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO or NO2, etc.) or copper atoms. Alternatively, a conductive material that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules) is preferably used.

[0257] By enabling the conductive layer 560a to suppress oxygen diffusion, the decrease in conductivity caused by oxidation of the conductive layer 560b due to oxygen contained in the insulating layer 550 can be prevented. For example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide can be used as the conductive material with the function of suppressing oxygen diffusion.

[0258] Furthermore, the conductive layer 560b preferably uses a conductive material with tungsten, copper, or aluminum as its main components. Additionally, since the conductive layer 560 is also used for wiring, a conductive layer with high conductivity is preferred. For example, the conductive layer 560b can use a conductive material with tungsten, copper, or aluminum as its main components. Furthermore, the conductive layer 560b can have a laminated structure, for example, it can have a laminated structure of titanium or titanium nitride with the aforementioned conductive material.

[0259] As shown in Figures 20B and 20C, in the region of semiconductor layer 520b that does not overlap with conductive layer 542, i.e., the channel formation region of semiconductor layer 520, the sidewalls of semiconductor layer 520 are covered by conductive layer 560. Therefore, the electric field of conductive layer 560, which serves as the gate electrode of transistor 200E, can easily influence the sidewalls of semiconductor layer 520. This improves the on-state current and frequency characteristics of transistor 200E.

[0260] Similar to insulating layer 514, insulating layer 554 uses an insulating material that inhibits impurities such as water or hydrogen from mixing into transistor 200E from the insulating layer 580 side. For example, insulating layer 554 uses an insulating material with lower hydrogen permeability than insulating layer 524. Furthermore, as shown in Figures 20B and 20C, insulating layer 554 is disposed in contact with the side surface of semiconductor layer 520c, the top and side surface of conductive layer 542a, the top and side surface of conductive layer 542b, the side surface of semiconductor layers 520a and 520b, and the top surface of insulating layer 524. By adopting this structure, hydrogen contained in insulating layer 580 can be suppressed from entering semiconductor layer 520 from the top or side surface of conductive layer 542a, conductive layer 542b, semiconductor layer 520a, semiconductor layer 520b, and insulating layer 524.

[0261] Furthermore, as insulating layer 554, an insulating material is used that has the function of inhibiting the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules) (making it difficult for the aforementioned oxygen to permeate). For example, an insulating material with lower oxygen permeability than insulating layer 580 or insulating layer 524 is used as insulating layer 554.

[0262] When an oxide semiconductor is used as the semiconductor layer 520, the insulating layer 554 is preferably deposited using a sputtering method. By depositing the insulating layer 554 using a sputtering method in an oxygen-containing atmosphere, oxygen can be added to the vicinity of the region of the insulating layer 524 in contact with the insulating layer 554. This allows oxygen to be supplied from this region through the insulating layer 524 into the semiconductor layer 520. Furthermore, by making the insulating layer 554 have the function of suppressing oxygen diffusion upwards, oxygen can be prevented from diffusing from the semiconductor layer 520 to the insulating layer 580. Additionally, by making the insulating layer 522 have the function of suppressing oxygen diffusion downwards, oxygen can be prevented from diffusing from the semiconductor layer 520 to the substrate side. Thus, oxygen is supplied to the channel formation region in the semiconductor layer 520. This reduces oxygen vacancies in the semiconductor layer 520 and suppresses the constant-on state of the transistor.

[0263] As the insulating layer 554, it is preferable to deposit an insulating layer containing an oxide of one or both of aluminum and hafnium. Note that as the insulating layer containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) can be used.

[0264] An insulating layer 580 is disposed on the insulating layer 524, the semiconductor layer 520, and the conductive layer 542, with the insulating layer 554 as a buffer. For example, silicon oxide, silicon oxynitride, silicon oxynitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, or porous silicon oxide may be used as the insulating layer 580. In particular, silicon oxide and silicon oxynitride are preferred due to their thermal stability. Furthermore, materials such as silicon oxide, silicon oxynitride, and porous silicon oxide readily form regions containing oxygen released upon heating, making them preferred.

[0265] Similar to insulating layer 514, insulating layer 574 uses an insulating material that acts as a barrier insulating film to prevent impurities such as water or hydrogen from mixing into insulating layer 580 from above. Insulating layer 574 may use, for example, an insulating material that can be used in insulating layer 514 or insulating layer 554.

[0266] Figures 20A to 20C show examples of insulating layers 581 serving as interlayer films on insulating layer 574. Similar to insulating layer 524, insulating layer 581 uses an insulating material with reduced concentration of impurities such as water or hydrogen in the film.

[0267] Conductive layers 545a and 545b are disposed in openings formed in insulating layers 581, 574, 580, and 554. Conductive layers 545a and 545b are disposed such that a conductive layer 560 is sandwiched between them. Furthermore, the top surfaces of conductive layers 545a and 545b may be on the same plane as the top surface of insulating layer 581.

[0268] Furthermore, an insulating layer 541a is provided in contact with the inner wall of the opening of insulating layers 581, 574, 580, and 554, and a first conductive layer 545a is formed in contact with the side of the insulating layer 541a. A conductive layer 542a is located at least a portion of the bottom of the opening and is in contact with the conductive layer 545a. Similarly, an insulating layer 541b is provided in contact with the inner wall of the opening of insulating layers 581, 574, 580, and 554, and a first conductive layer 545b is formed in contact with the side of the insulating layer 541b. A conductive layer 542b is located at least a portion of the bottom of the opening and is in contact with the conductive layer 545b.

[0269] The conductive layers 545a and 545b are preferably made of conductive materials with tungsten, copper, or aluminum as the main components. In addition, the conductive layers 545a and 545b may also have a stacked structure of two or more layers.

[0270] When a stacked structure is used as the conductive layer 545, the conductive layer that contacts the semiconductor layer 520a, semiconductor layer 520b, conductive layer 542, insulating layer 554, insulating layer 580, insulating layer 574, and insulating layer 581 is preferably a conductive layer that has the function of suppressing the diffusion of impurities such as water or hydrogen. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide are used. By using this conductive material, oxygen contained in the insulating layer 580 can be prevented from being absorbed by the conductive layers 545a and 545b. In addition, impurities such as water or hydrogen can be prevented from entering the semiconductor layer 520 from the upper layer of the insulating layer 581 through the conductive layers 545a and 545b.

[0271] For example, insulating layers suitable for insulating layers such as insulating layer 554 can be used as insulating layers 541a and 541b. Because insulating layers 541a and 541b are disposed in contact with insulating layer 554, impurities such as water or hydrogen can be prevented from entering the semiconductor layer 520 from the insulating layer 580 via conductive layers 545a and 545b. Furthermore, insulating layers 541a and 541b can prevent the absorption of oxygen contained in the insulating layer 580 by conductive layers 545a and 545b.

[0272] <Example 6 of Transistor Structure> Figure 21 shows transistor F, a variant of transistor 200E shown in Figure 20. Figure 21A is a plan view of transistor F. Figure 21B is a cross-sectional view along the dotted lines A1-A2 in Figure 21A. Figure 21C is a cross-sectional view along the dotted lines A3-A4 in Figure 21A. Transistor F is a variant of transistor 200E, so the differences between transistor F and transistor 200E will be explained mainly.

[0273] Transistor F has a structure that removes the semiconductor layer 520c and the conductive layer 505c from the structure of transistor 200E. By reducing the number of components in the transistor, production costs can be reduced. When the number of components in the transistor is reduced, the manufacturing process is shortened, thereby increasing the manufacturing yield.

[0274] Furthermore, transistor F has a region where the outer insulating layer 554 of semiconductor layer 520 contacts the insulating layer 522, and the sides of the insulating layer 524 are covered by the insulating layer 554. When an oxide semiconductor is used as semiconductor layer 520, by covering the sides of the insulating layer 524 with the insulating layer 554, not only can oxygen be prevented from diffusing to the outside through the insulating layer 524, but also excess oxygen can be prevented from being supplied to semiconductor layer 520 from the side of the insulating layer 524.

[0275] Alternatively, an insulating layer may be provided between the insulating layer 580, the insulating layer 554, the conductive layer 542, the semiconductor layer 520b, and the insulating layer 550. Alumina and hafnium oxide are preferably used as this insulating layer. By providing this insulating layer, it is possible to prevent oxygen from escaping from the semiconductor layer 520 to the insulating layer 550 side, to prevent the supply of excess oxygen from the insulating layer 550 side to the semiconductor layer 520, and to prevent the conductive layer 542 from being oxidized.

[0276] <Example 7 of Transistor Structure> Figure 22A is a plan view of a transistor 200G that can be used in a semiconductor device according to one aspect of the present invention. Furthermore, Figure 22B is a perspective view of the transistor 200G. Furthermore, Figures 22C to 22E are cross-sectional views of the transistor 200G. Here, Figure 22C is a cross-sectional view along the dotted lines A1-A2 in Figure 22A, which is also a cross-sectional view of the channel width direction (Y direction) of the transistor 200G. Furthermore, Figure 22D is a cross-sectional view along the dotted lines A3-A4 in Figure 22A, which is also a cross-sectional view of the channel width direction of the transistor 200G. Additionally, Figure 22E is a cross-sectional view along the dotted lines A5-A6 in Figure 22A, which is also a cross-sectional view of the channel length direction (X direction) of the transistor 200G. Here, the dashed lines A5-A6 are orthogonal to the dashed lines A1-A2 and A3-A4, and the dashed lines A1-A2 and A3-A4 are parallel to each other. Note that some constituent elements are omitted from the plan view in Figure 22A and the three-dimensional schematic diagram in (B). Furthermore, Figure 23A shows an enlarged view of the vicinity of the conductive layer 260 in Figure 22E. Additionally, Figure 23B shows an enlarged view of the vicinity of the semiconductor layer 230 in Figure 22C.

[0277] The transistor 200G according to this embodiment includes an insulating layer 215 on a substrate (not shown), an insulating layer 216 on the insulating layer 215, an insulating layer 221 on the insulating layer 216, an insulating layer 222 on the insulating layer 221, a semiconductor layer 230 on the insulating layer 222, conductive layers 242a and 242b on the semiconductor layer 230 and the insulating layer 222, an insulating layer 250 on the semiconductor layer 230, and conductive layers 260 (conductive layers 260a and 260b) on the insulating layer 250. Note that in this specification, conductive layers 242a and 242b are sometimes collectively referred to as conductive layer 242.

[0278] An insulating layer 275 is disposed on the conductive layer 242, and an insulating layer 280 is disposed on the insulating layer 275. An insulating layer 250 and a conductive layer 260 are disposed inside a first opening that passes through the insulating layers 280 and 275 to reach the semiconductor layer 230. The first opening, when viewed from above, includes a region overlapping the semiconductor layer 230 and a region extending along the Y direction beyond the semiconductor layer 230. Therefore, the insulating layer 250 and the conductive layer 260 disposed inside the first opening also have a region overlapping the semiconductor layer 230 and a region extending along the Y direction beyond the semiconductor layer 230 when viewed from above. The conductive layer 260 is also used for wiring. The insulating layer 250 has a region in the first opening that contacts the semiconductor layer 230. Furthermore, an insulating layer 282 is disposed on the insulating layer 280 and the conductive layer 260. Furthermore, an insulating layer 283 is disposed on the insulating layer 282.

[0279] Additionally, an insulating layer 241a is provided in such a way that it contacts the inner wall of the second opening that extends through insulating layers 283, 282, 280, and 275 to reach conductive layer 242a, and a conductive layer 245a is provided in such a way that it contacts insulating layer 241a. Conductive layer 245a has a region at the bottom of the first opening that contacts conductive layer 242a.

[0280] Furthermore, an insulating layer 241b is provided in such a way that it contacts the inner wall of the third opening that passes through insulating layers 283, 282, 280, and 275 to reach conductive layer 242b, and a conductive layer 245b is provided in such a way that it contacts insulating layer 241b. Conductive layer 245b has a region at the bottom of the second opening that contacts conductive layer 242b.

[0281] Furthermore, in this specification, conductive layer 245a and conductive layer 245b are sometimes collectively referred to as conductive layer 245. Additionally, insulating layer 241a and insulating layer 241b are sometimes collectively referred to as insulating layer 241.

[0282] Semiconductor layer 230 includes a channel formation region for transistor 200G. Furthermore, conductive layer 260 has a region serving as the gate electrode of transistor 200G. Insulating layer 250 has a region serving as the gate insulating layer of transistor 200G. In transistor 200G, the region of semiconductor layer 230 overlapping with conductive layer 260 is used as the channel formation region. Furthermore, the region of conductive layer 260 overlapping with semiconductor layer 230 is used as the gate electrode. Additionally, the region of insulating layer 250 where insulating layer 250 overlaps with semiconductor layer 230 and where insulating layer 250 overlaps with conductive layer 260 is used as the gate insulating layer.

[0283] Conductive layer 242a has a region that serves as one of the source and drain electrodes of transistor 200G. Conductive layer 245a is used as a connector to conductive layer 242a. Conductive layer 242b has a region that serves as the other of the source and drain electrodes of transistor 200G. Conductive layer 245b is used as a connector to conductive layer 242b.

[0284] Semiconductor layer 230 is formed on insulating layer 222. As shown in Figure 23B, semiconductor layer 230 has a high aspect ratio in cross-section along the channel width direction. Therefore, semiconductor layer 230 can also be described as having a fin-like shape. Furthermore, transistors with fin-shaped semiconductor layers are also called "fin transistors," "Fin transistors," or "Fin transistors," etc.

[0285] Specifically, a Fin-type transistor refers to a transistor in which the channel forming region of the semiconductor layer in the cross-section along the channel width direction (Y direction) has two regions (two faces) extending in the Z direction, and has a shape where the length H, as described later, is greater than the length Lx, as described later. In the cross-section along the channel width direction, when the length H is greater than the length Lx, the channel width per unit area can be increased, and therefore it is preferred.

[0286] In this specification, the maximum length of the semiconductor layer 230 in the Y direction in the channel forming region is the length Lx, and the maximum length of the semiconductor layer 230 in the channel forming region in the direction perpendicular to the surface to be formed (e.g., the top surface of the insulating layer 222) is the length H.

[0287] Note that the length Lx can also be described as the maximum width of the semiconductor layer 230 in the channel formation region. Therefore, "length Lx" can be replaced with "width Lx". Furthermore, the length H can also be described as the maximum height of the semiconductor layer 230 in the channel formation region. Therefore, "length H" can be replaced with "height H".

[0288] The ratio of the length H relative to the length Lx is referred to as the aspect ratio of the semiconductor layer 230. Preferably, the aspect ratio of the semiconductor layer 230 is as large as possible within the range that the semiconductor layer 230 will not collapse during the manufacturing process of the transistor 200G. The aspect ratio of the semiconductor layer 230 is preferably greater than 1 and less than 400, more preferably greater than 2 and less than 100, further preferably greater than 5 and less than 40, and even more preferably greater than 10 and less than 20. That is, in the channel formation region of the semiconductor layer 230, the height H of the semiconductor layer 230 is preferably at least longer than the length Lx of the semiconductor layer 230. The height H of the semiconductor layer 230 is preferably greater than 1 times the length Lx of the semiconductor layer 230 and less than 400 times, more preferably more than 2 times and less than 100 times, further preferably more than 5 times and less than 40 times, and even more preferably more than 10 times and less than 20 times. In addition, for example, the height H may also be more than 2 times and less than 10 times the length Lx. For example, the length Lx is preferably 5 nm or more and 100 nm or less, more preferably 5 nm or more and 50 nm or less, and even more preferably 10 nm or more and 30 nm or less. Additionally, for example, the height H is preferably 50 nm or more and 2000 nm or less, more preferably 100 nm or more and 1000 nm or less. Alternatively, for example, the height H may also be 50 nm or more and 100 nm or less.

[0289] As shown in Figure 23B, in the cross-section along the channel width, the angle θ formed by the formation surface of the semiconductor layer 230 on the insulating layer 222 and the side surface of the semiconductor layer 230 is preferably perpendicular or substantially perpendicular. For example, the angle θ is 80° or more and 100° or less, preferably 85° or more and 95° or less.

[0290] An insulating layer 250, a conductive layer 260, and a conductive layer 242 are provided to cover the semiconductor layer 230 with the aforementioned aspect ratio. In the transistor 200G, as shown in FIG23B, a portion of the insulating layer 250 and the conductive layer 260 are provided in a folded state, sandwiching the semiconductor layer 230. Thus, in a cross-section along the channel width direction, the semiconductor layer 230 and the conductive layer 260 are disposed opposite each other, sandwiching the insulating layer 250, on each of the upper part, the side surface on the A1 side, and the side surface on the A2 side of the semiconductor layer 230. That is, the upper part, the side surface on the A1 side, and the side surface on the A2 side of the semiconductor layer 230 are all used as channel formation regions. Therefore, compared to the case where the semiconductor layer 230 is formed in a planar shape, the channel width of the transistor 200G is increased by the portion of the side surface on the A1 side and the side surface on the A2 side of the semiconductor layer 230.

[0291] As described above, increasing the channel width can improve the on-state current, transconductance, and frequency characteristics of the transistor 200G. This provides a semiconductor device with high operating speed. Furthermore, in the above structure, by providing the semiconductor layer 230, the channel width can be increased without increasing the area occupied by the transistor 200G. This allows for miniaturization or high integration of the semiconductor device.

[0292] Furthermore, as shown in FIG23B, the upper part of the semiconductor layer 230 may also have a curved shape. This curved shape prevents defects such as voids from forming in the insulating layer 250 and the conductive layer 242 near the upper part of the semiconductor layer 230. Note that in FIG23B, both the A1 side (A3 side) and the A2 side (A4 side) of the upper part of the semiconductor layer 230 have curved shapes, forming a symmetrical structure; however, the present invention is not limited to this. For example, sometimes one of the A1 side (A3 side) and the A2 side (A4 side) of the upper part of the semiconductor layer 230 has a curved shape, forming an asymmetrical structure.

[0293] Alternatively, when an oxide semiconductor is used as the semiconductor layer 230, as shown in Figures 23A and 23B, a structure including semiconductor layer 230a, semiconductor layer 230b and semiconductor layer 230c disclosed in Embodiment 3 can be adopted.

[0294] Furthermore, when an oxide semiconductor is used as the semiconductor layer 230, as shown in Figures 23A and 23B, the insulating layer 250 preferably has a stacked structure consisting of an insulating layer 250a in contact with the semiconductor layer 230, an insulating layer 250b on the insulating layer 250a, an insulating layer 250c on the insulating layer 250b, and an insulating layer 250d on the insulating layer 250c. In this case, the insulating layers 250a and 250c preferably have the function of trapping or fixing hydrogen.

[0295] Metal oxides with amorphous structures can be used as insulating layers that trap or fix hydrogen. For example, metal oxides containing one or both of magnesium oxide or aluminum and hafnium are preferred as insulating layers 250a and 250c. These metal oxides with amorphous structures sometimes have the property that oxygen atoms have dangling bonds, which trap or fix hydrogen. In other words, metal oxides with amorphous structures have a high ability to trap or fix hydrogen.

[0296] Insulating layers 250a and 250c are preferably made of high-k materials. An example of a high-k material is an oxide containing one or both of aluminum and hafnium. When a high-k material is used as insulating layers 250a and 250c, the gate potential applied during transistor operation can be reduced while maintaining the physical thickness of the gate insulating layer. Furthermore, the energy-to-voltage (EOT) of the insulating layer used as the gate insulating layer can be reduced.

[0297] As insulating layers 250a and 250c, it is preferable to use an oxide containing one or both of aluminum and hafnium, and more preferably an oxide having an amorphous structure and containing one or both of aluminum and hafnium.

[0298] In this embodiment, an aluminum oxide film is used as the insulating layer 250a. Furthermore, this aluminum oxide preferably has an amorphous structure. Here, by providing the insulating layer 250a in contact with the semiconductor layer 230, the insulating layer 250a can more effectively trap and fix hydrogen contained in the semiconductor layer 230, etc.

[0299] In this embodiment, hafnium oxide is used as the insulating layer 250c. Here, by providing the insulating layer 250c between the insulating layer 250b and the insulating layer 250d, hydrogen contained in the insulating layer 250b and the like can be captured and fixed more effectively.

[0300] Next, a thermally stable insulating layer such as silicon oxide or silicon oxynitride is preferably used as the insulating layer 250b. The silicon oxide film used as the insulating layer 250b is preferably formed using the PEALD method.

[0301] To suppress oxidation of conductive layers 242a, 242b, and 260, it is preferable to provide an oxygen barrier insulator near each of the conductive layers 242a, 242b, and 260. In the semiconductor device described in this embodiment, such insulator is, for example, insulating layers 250a, 250d, 250c, and 275.

[0302] In this specification, the term "barrier insulating layer" refers to an insulating layer that possesses barrier properties. In this specification, "barrier properties" means having the property of preventing the transmission of the corresponding substance (also known as low permeability). For example, a barrier insulating layer has the property that the corresponding substance does not easily diffuse into the interior of the insulating layer. For example, a barrier insulating layer has the function of trapping or fixing (also known as gettering) the corresponding substance within the insulating layer.

[0303] Examples of oxygen-barrier insulating layers include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, silicon nitride, and silicon oxynitride. Furthermore, examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate). For example, insulating layers 250a, 250c, 250d, and 275 preferably employ a single-layer or multilayer structure of the aforementioned oxygen-barrier insulating layers.

[0304] The insulating layer 250a preferably has oxygen-barrier properties. The insulating layer 250a is preferably at least less permeable to oxygen than the insulating layer 280. The insulating layer 250a has regions that contact the sides of the conductive layer 242a and the sides of the conductive layer 242b. When the insulating layer 250a has oxygen-barrier properties, oxidation of the sides of the conductive layers 242a and 242b, resulting in the formation of an oxide film on those sides, can be suppressed. Therefore, a decrease in the on-state current or field-effect mobility of the transistor 200G can be suppressed.

[0305] Furthermore, the insulating layer 250a is provided in contact with the top and side surfaces of the semiconductor layer 230 and the top surface of the insulating layer 222. When the insulating layer 250a has oxygen-barrier properties, oxygen can be prevented from escaping from the channel formation region of the semiconductor layer 230 during heat treatment or similar processes. As a result, oxygen vacancies formed in the semiconductor layer 230 can be reduced.

[0306] Furthermore, by providing the insulating layer 250a, excessive oxygen supply from the insulating layer 280 to the semiconductor layer 230 is suppressed, while an appropriate amount of oxygen can be supplied to the semiconductor layer 230. This suppresses the reduction in the on-state current or the decrease in the field-effect mobility of the transistor 200G caused by excessive oxidation of the source and drain regions.

[0307] Because oxides containing one or both of aluminum and hafnium have oxygen-barrier properties, they can be suitably used as insulating layer 250a.

[0308] The insulating layer 250d preferably also has oxygen-barrier properties. The insulating layer 250d is disposed between the channel formation region of the semiconductor layer 230 and the conductive layer 260, and between the insulating layer 280 and the conductive layer 260. By employing this structure, oxygen diffusion from the channel formation region of the semiconductor layer 230 to the conductive layer 260, thus preventing the formation of oxygen vacancies in the channel formation region of the semiconductor layer 230, can be suppressed. Furthermore, the diffusion of oxygen from the semiconductor layer 230 and the insulating layer 280 to the conductive layer 260, thereby preventing oxidation of the conductive layer 260, can be suppressed. The insulating layer 250d is preferably at least less permeable to oxygen than the insulating layer 280. For example, a silicon nitride film is preferably used as the insulating layer 250d. In this case, the insulating layer 250d is an insulating layer containing at least nitrogen and silicon.

[0309] Furthermore, the insulating layer 250d preferably has hydrogen-barrier properties. This prevents impurities such as hydrogen contained in the conductive layer 260 from diffusing into the semiconductor layer 230.

[0310] The insulating layer 275 preferably also has oxygen-barrier properties. The insulating layer 275 is disposed between the insulating layer 280 and the conductive layer 242a, and between the insulating layer 280 and the conductive layer 242b. The insulating layer 275 is disposed in contact with the side surface of the conductive layer 242, the side surface of the semiconductor layer 230, and the top surface of the insulating layer 222. By employing this structure, the diffusion of oxygen contained in the insulating layer 280 to the conductive layer 242 can be suppressed. Therefore, the increase in resistivity caused by oxidation of the conductive layer 242 due to oxygen contained in the insulating layer 280 can be suppressed. The insulating layer 275 is preferably at least less permeable to oxygen than the insulating layer 280. For example, silicon nitride is preferably used as the insulating layer 275. In this case, the insulating layer 275 is an insulating layer containing at least nitrogen and silicon.

[0311] To suppress the decrease in hydrogen concentration in the source and drain regions of the semiconductor layer 230, it is preferable to provide hydrogen barrier insulating layers near the source and drain regions. In the semiconductor device described in this embodiment, this hydrogen barrier insulating layer is, for example, insulating layer 275.

[0312] Examples of hydrogen barrier insulating layers include oxides such as aluminum oxide, hafnium oxide, and tantalum oxide, as well as nitrides such as silicon nitride. For example, the insulating layer 275 preferably employs a single-layer structure or a multilayer structure of the aforementioned hydrogen barrier insulating layer.

[0313] By providing the aforementioned insulating layer 275, hydrogen diffusion from the source and drain regions to the outside can be reduced, thus suppressing the decrease in hydrogen concentration in the source and drain regions. Therefore, the source and drain regions can be n-type.

[0314] By adopting the above structure, the channel forming region can be made i-type or substantially i-type, and the source and drain regions can be made n-type, thereby providing a semiconductor device with excellent electrical characteristics. By adopting the above structure, even when the semiconductor device is miniaturized or highly integrated, it can still maintain good electrical characteristics. Furthermore, miniaturizing the transistor to 200G can improve high-frequency characteristics. Specifically, the cutoff frequency can be increased.

[0315] Insulating layers 250a to 250d are used as part of the gate insulating layer. Insulating layers 250a to 250d are disposed together with the conductive layer 260 in an opening formed in the insulating layer 280. To achieve miniaturization of the transistor 200G, the thickness of insulating layers 250a to 250d is preferably small. The thickness of each of insulating layers 250a to 250d is preferably 0.1 nm or more and 10 nm or less, more preferably 0.1 nm or more and 5.0 nm or less, further preferably 0.5 nm or more and 5.0 nm or less, even more preferably 1.0 nm or more and less than 5.0 nm, and even more preferably 1.0 nm or more and 3.0 nm or less. Furthermore, at least a portion of each of insulating layers 250a to 250d may include a region having the thickness described above.

[0316] In addition, the thickness of the silicon oxide film used as the insulating layer 250 is preferably 0.7 nm or more and 3 nm or less.

[0317] To reduce the thickness of insulating layers 250a to 250d as described above, deposition using the ALD method is preferred. Furthermore, to deposit insulating layers 250a to 250d within openings in insulating layers 280, etc., deposition using the ALD method is preferred. By using the ALD method, insulating layers 250 can be deposited with high coverage on the side surfaces of the first opening formed in insulating layer 280, the side ends of conductive layers 242a, and the side ends of conductive layers 242b, etc.

[0318] Note that while the above description indicates that insulating layer 250 has a four-layer structure consisting of insulating layers 250a to 250d, the present invention is not limited thereto. Insulating layer 250 may have a structure including at least one of insulating layers 250a to 250d. By constituting insulating layer 250 with one, two, or three layers of insulating layers 250a to 250d, the manufacturing process of transistor 200G can be simplified, thereby improving the productivity of semiconductor devices including transistor 200G.

[0319] As shown in Figure 22A, the shape of the semiconductor layer 230 in top view is preferably a circumferential shape (or a frame-like, ring-like, loop-like, or closed curve-like shape) with two ends aligned. That is, the semiconductor layer 230 preferably has a structure having multiple portions extending in the channel width direction (A1-A2 direction) and multiple portions extending in the channel length direction (A5-A6 direction). Therefore, when the aspect ratio of the semiconductor layer 230 is high, it is possible to suppress the semiconductor layer 230 from collapsing during the transistor manufacturing process. Furthermore, it can be said that the semiconductor layer 230 shown in Figure 22A has an opening in the central portion. In Figure 22A, the shape of the semiconductor layer 230 in top view is an axisymmetric shape centered on A1-A2, but the present invention is not limited to this. For example, the shape of the semiconductor layer 230 in top view can also be an asymmetrical shape.

[0320] The structure shown in Figure 22A is a structure in which two circumferential semiconductor layers 230 are formed in the Y direction. As shown in Figure 22A, the semiconductor layer 230 preferably overlaps with the conductive layer 260 in two or more places when viewed from above. Therefore, the conductive layer 260 preferably has two or more regions that overlap with the semiconductor layer 230. That is, it is preferable to have two or more regions where the semiconductor layer 230 and the conductive layer 260 overlap with each other.

[0321] By employing this structure, as shown in Figure 22B, multiple fin-shaped semiconductor layers 230 are formed in the cross-section along the channel width direction. Each of the multiple fin-shaped semiconductor layers 230 includes a channel formation region. In other words, the transistor 200G is used as a multi-channel transistor. Therefore, the channel width can be further increased in the transistor 200G, thus increasing the on-state current. Consequently, the operating speed of the semiconductor device including the transistor 200G can be improved.

[0322] Furthermore, while the above description describes a structure with two circumferential semiconductor layers 230, the present invention is not limited thereto. For example, one or more circumferential semiconductor layers 230 may be provided. Additionally, the circumferential semiconductor layers 230 may be combined to form a semiconductor layer 230 with a shape having multiple openings. Furthermore, in top view, a lattice-shaped semiconductor layer 230 may be used.

[0323] <Example 8 of Transistor Structure> Next, a modified example of transistor 200G, transistor 200H, will be described. FIG24A is a plan view of transistor 200H that can be used in a semiconductor device according to one aspect of the present invention. Furthermore, FIG24B is a perspective view of transistor 200H. In addition, FIGS. 24C to 24E are cross-sectional views of transistor 200H. Here, FIG24C is a cross-sectional view along the dotted lines A1-A2 in FIG24A, which is also a cross-sectional view in the channel width direction (Y direction) of transistor 200H. In addition, FIG24D is a cross-sectional view along the dotted lines A3-A4 in FIG24A, which is also a cross-sectional view in the channel width direction of transistor 200H. Furthermore, FIG24E is a cross-sectional view along the dotted lines A5-A6 in FIG24A, which is also a cross-sectional view in the channel length direction (X direction) of transistor 200H. Here, the dashed lines A5-A6 are orthogonal to the dashed lines A1-A2 and A3-A4, and the dashed lines A1-A2 and A3-A4 are parallel to each other. Note that some constituent elements are omitted from the plan view in Figure 24A and the three-dimensional schematic diagram in (B). Furthermore, Figure 25 shows an enlarged view of the semiconductor layer 230 in Figure 24C.

[0324] As shown in Figures 24B to 24E, an insulating layer 224 can also be provided below the semiconductor layer 230. The planar shape (shape viewed from the Z direction) of the insulating layer 224 is the same as the shape of the semiconductor layer 230. Therefore, when viewed from above, the insulating layer 224 overlaps with the semiconductor layer 230. The bottom surface of the insulating layer 224 contacts the insulating layer 222, the side surface of the insulating layer 224 contacts the insulating layer 250 and the conductive layer 242a, and the top surface of the insulating layer 224 contacts the bottom surface of the semiconductor layer 230. Furthermore, the insulating layer 224 can be made of an insulating material suitable for the insulating layer 250b. For example, silicon oxide can be used as the insulating layer 224.

[0325] Note that Figures 24A to 24E correspond to Figures 22A to 22E. Additionally, Figure 25 corresponds to Figure 23B. Therefore, regarding the structures of Figures 24A to 24E and Figure 25, for matters not explained below, please refer to the above explanations of Figures 22A to 22E and Figure 23B, etc.

[0326] Here, as shown in FIG25, the thickness t2 of the insulating layer 250 at the bottom of the first opening is preferably thinner than the thickness t1 (length in the direction perpendicular to the surface of the insulating layer 224) of the insulating layer 224. By adopting this structure, the bottom surface of the conductive layer 260 (conductive layer 260a) located at the first opening can be positioned lower than the bottom surface of the semiconductor layer 230 by the difference between the thickness t1 and the thickness t2 (t1-t2).

[0327] By positioning the bottom surface of the conductive layer 260 below the bottom surface of the semiconductor layer 230, a sufficient gate electric field can be applied to the upper and lower ends of the semiconductor layer 230. In other words, the entire semiconductor layer 230 can be electrically surrounded by the electric field of the conductive layer 260 within the opening of the insulating layer 280, etc., and used as a channel formation region. By employing this structure, the lower end of the semiconductor layer 230 can be prevented from being used as a parasitic channel, thereby reducing the leakage current between the source and drain electrodes. Furthermore, characteristic defects such as always-on switching of the transistor caused by this parasitic channel can be suppressed. That is, the electrical characteristics of the transistor 200H can be improved.

[0328] As described above, by using the upper to lower ends of the semiconductor layer 230 as the channel formation region, the channel width can be increased. This, in turn, improves the on-state current, transconductance, and frequency characteristics of the transistor 200H.

[0329] Note that in this specification, the transistor structure described above, in which the electric field of the gate electrode forms a region around the channel, is referred to as a surrounded channel (S-channel) structure. In an S-channel structure, the gate electrode is arranged with at least two or more surfaces surrounding the channel (specifically, two, three, or four surfaces, etc.). By employing an S-channel structure, tolerance to short-channel effects can be improved; in other words, transistors that are less prone to short-channel effects can be realized.

[0330] The S-channel structure is a structure in which the electrical current forms a region around the channel, so it can be said that this structure is essentially the same as the GAA (Gate All Around) structure or the LGAA (Lateral Gate All Around) structure. By giving the transistor 200H an S-channel structure, a GAA structure, or an LGAA structure, the channel formation region formed at or near the interface between the semiconductor layer 230 and the insulating layer 250 used as the gate insulating layer can be regarded as the entire bulk of the semiconductor layer 230. Therefore, the current density flowing through the transistor can be increased, so an increase in the transistor's on-state current or the transistor's field-effect mobility can be expected. In addition, in one aspect of the present invention, the semiconductor layer 230 has a CAAC structure and a fin structure. By adopting this structure, it is possible for the current path flowing between the source and drain of the transistor to be parallel to the ab plane of the crystal axis. In other words, the oxide semiconductor with the CAAC structure and the fin structure has a conduction path that appears to be equal to that of a two-dimensional semiconductor material. Furthermore, by using an oxide semiconductor as the semiconductor layer of such a transistor, a device with two-dimensional conduction properties can be manufactured.

[0331] <Example 9 of Transistor Structure> Figures 26A to 26E show a modified example of transistor 200H, namely transistor 200I. The difference between transistor 200I and transistor 200G is that in transistor 200I, a conductive layer 205 is included beneath the insulating layer 221. Note that Figures 26A to 26E correspond to Figures 22A to 22E. Regarding matters not described below in the structures of Figures 26A to 26E, please refer to the above descriptions of Figures 22A to 22E, etc.

[0332] The conductive layer 205 has a region that overlaps with the channel formation region of the semiconductor layer 230. Therefore, similar to the conductive layer 260, the conductive layer 205 has a region that serves as a gate electrode. The conductive layer 260 is sometimes referred to as the first gate electrode (upper gate electrode) of the transistor 200I, and the conductive layer 205 is sometimes referred to as the second gate electrode (lower gate electrode) of the transistor 200I. Furthermore, while the conductive layer 260 is referred to as the gate electrode of the transistor 200I, the conductive layer 205 is sometimes referred to as the back gate electrode of the transistor 200I.

[0333] When a conductive layer 205 is included under the insulating layer 221, as in transistor 200I, both insulating layers 222 and 221, like insulating layer 250, include regions that serve as gate insulating layers. Specifically, the region of each of insulating layers 222 and 221 that overlaps with the conductive layer 205 is used as a gate insulating layer. Furthermore, insulating layer 250 is sometimes referred to as the first gate insulating layer (the upper gate insulating layer), and insulating layers 222 and 221 are sometimes referred to as the second gate insulating layer (the lower gate insulating layer).

[0334] In transistor 200I, conductive layer 205 is disposed in a manner that overlaps with semiconductor layer 230 and conductive layer 260. In Figures 26C and 26E, conductive layer 205 is disposed inside the fourth opening that passes through insulating layer 216 to insulating layer 215. Furthermore, the fourth opening, when viewed from above, includes a region overlapping with semiconductor layer 230 and a region extending along the Y direction beyond the end of semiconductor layer 230. Therefore, conductive layer 205 disposed inside the fourth opening also, when viewed from above, includes a region overlapping with semiconductor layer 230 and a region extending along the Y direction beyond the end of semiconductor layer 230. Conductive layer 205 is also used for wiring.

[0335] As shown in Figures 26C and 26E, the conductive layer 205 preferably includes a conductive layer 205a and a conductive layer 205b. The conductive layer 205a is disposed in contact with the bottom and sidewalls of the fourth opening. The conductive layer 205b is disposed in a recess formed along the bottom and sidewalls of the conductive layer 205a of the fourth opening. Here, the height of the top surface of the conductive layer 205 is the same as or approximately the same as the height of the top surface of the insulating layer 216.

[0336] Here, the conductive layer 205a preferably comprises a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Alternatively, it is preferable to comprise a conductive material that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules).

[0337] By using a conductive material with the function of reducing hydrogen diffusion as the conductive layer 205a, impurities such as hydrogen contained in the conductive layer 205b can be prevented from diffusing to the semiconductor layer 230 through the insulating layer 216, etc. Furthermore, by using a conductive material with the function of inhibiting oxygen diffusion as the conductive layer 205a, the oxidation of the conductive layer 205b and the resulting decrease in conductivity can be prevented. Examples of conductive materials with the function of inhibiting oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The conductive layer 205a can have a single-layer structure or a multilayer structure of the above-mentioned conductive materials. For example, the conductive layer 205a preferably contains titanium nitride.

[0338] Furthermore, the conductive layer 205b preferably uses a conductive material with tungsten, copper, or aluminum as its main components. For example, the conductive layer 205b preferably contains tungsten.

[0339] As described above, the conductive layer 205 can be used as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200I can be controlled by independently changing the potential applied to the conductive layer 205 without linking it to the potential applied to the conductive layer 260. In particular, by applying a negative potential to the conductive layer 205, the Vth of the transistor 200I can be further increased, thereby reducing the off-state current. Thus, compared to not applying a negative potential to the conductive layer 205, applying a negative potential to the conductive layer 205 can reduce the drain current when the potential of the conductive layer 260 is 0V.

[0340] Furthermore, the resistivity of the conductive layer 205 is designed taking into account the potential applied to the conductive layer 205 as described above, and the thickness of the conductive layer 205 is set according to this resistivity. Additionally, the thickness of the insulating layer 216 is approximately the same as that of the conductive layer 205. Here, it is preferable to reduce the thickness of both the conductive layer 205 and the insulating layer 216 within the design limits of the conductive layer 205. By reducing the thickness of the insulating layer 216, the absolute amount of impurities such as hydrogen contained in the insulating layer 216 can be reduced, thus suppressing the diffusion of these impurities into the semiconductor layer 230.

[0341] Note that the above structure shows a stacked structure of conductive layers 205a and 205b, but the present invention is not limited thereto. The conductive layer 205 can have a single-layer structure or a stacked structure of three or more layers. For example, when the conductive layer 205 has a three-layer stacked structure, a stacked structure can be used between the conductive layers 205a and 205b, and a conductive layer containing the same material as the conductive layer 205a can be provided on the conductive layer 205b. In this case, the conductive layer can also be formed by embedding it in a recess formed by the conductive layers 205a and 205b, wherein the top surface of the conductive layer 205b is lower than the uppermost part of the conductive layer 205a.

[0342] As materials used for conductive layers 205, 242, 245, and 260, materials for conductive layers shown in other embodiments may be used in addition to those disclosed in this embodiment. As materials used for insulating layers 215, 216, 221, 222, 241, 250, 275, 280, 282, and 283, materials for insulating layers shown in other embodiments may be used in addition to those disclosed in this embodiment.

[0343] The transistor 200I described in this embodiment can be used to construct a transistor in a semiconductor device 10. The transistor 200I can increase the on-state current without increasing the occupied area.

[0344] <Materials for Transistors> Next, the constituent materials that can be used in transistors 200 (transistor 200A, transistor 200B, transistor 200C, transistor 200D, transistor 200E, transistor 200F, transistor 200G, transistor 200H, and transistor 200I) will be described.

[0345] [Substrate] When placing a transistor on a substrate, there are no particular restrictions on the material used for the substrate. The choice depends on the purpose, taking into account factors such as the presence or absence of light transmittance and heat resistance to withstand heat treatment. For example, insulating substrates, semiconductor substrates, or conductive substrates can be used. Examples of insulating substrates include glass substrates such as borosilicate glass and aluminoborosilicate glass, ceramic substrates, quartz substrates, sapphire substrates, and stabilized zirconia substrates (yttrium-stabilized zirconia substrates, etc.). Furthermore, semiconductor substrates, flexible substrates, and resin substrates can also be used.

[0346] Examples of semiconductor substrates include those made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon-germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, semiconductor substrates with insulating regions within the aforementioned semiconductor substrates, such as SOI substrates, can also be used. In addition, the semiconductor substrate can be a single-crystal semiconductor or a polycrystalline semiconductor.

[0347] Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, examples include substrates containing metal nitrides or metal oxides. Furthermore, examples include substrates with conductive or semiconductor layers on insulating substrates, substrates with conductive or insulating layers on semiconductor substrates, and substrates with semiconductor or insulating layers on conductive substrates.

[0348] Materials used as flexible substrates or resin substrates include, for example, polyesters such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), polyacrylonitrile, acrylic resins, polyimide, polymethyl methacrylate, polycarbonate (PC), polyethersulfone (PES), polyamides (nylon, aromatic polyamides, etc.), polysiloxanes, cyclic olefin resins, polystyrene, polyamide-imide, polyurethane, polyvinyl chloride, polyvinylidene chloride, polypropylene, polytetrafluoroethylene (PTFE), ABS resin, cellulose nanofibers, etc.

[0349] By using the above-described material as a substrate, a lightweight semiconductor device can be provided. Furthermore, by using the above-described material as a substrate, a semiconductor device with high impact resistance can be provided. Additionally, by using the above-described material as a substrate, a semiconductor device that is not easily broken can be provided. Alternatively, substrates on which components are disposed can also be used. Examples of components disposed on the substrate include capacitors, resistors, switching elements, light-emitting elements, and memory elements.

[0350] [Insulating Layer] Inorganic insulating films are used as insulating layers (insulating layers 202, 204, 206, 209, 215, 216, 221, 222, 224, 241, 257, 250, 258, 258a, 258b, 259, 264, 266, 268, 516, 275, 280, 282, 283, 522, 524, 541, 554, 580, 574, 581, etc.). Examples of inorganic insulating films include oxide insulating films, nitrided insulating films, oxynitrided insulating films, and oxynitride insulating films. Examples of oxide insulating films include silicon oxide films, aluminum oxide films, magnesium oxide films, gallium oxide films, germanium oxide films, yttrium oxide films, zirconium oxide films, lanthanum oxide films, neodymium oxide films, hafnium oxide films, tantalum oxide films, cerium oxide films, gallium zinc oxide films, and hafnium aluminate films. Examples of silicon nitride insulating films include silicon nitride films and aluminum nitride films. Examples of silicon oxynitride insulating films include silicon oxynitride films, aluminum oxynitride films, gallium oxynitride films, yttrium oxynitride films, and hafnium oxynitride films. Examples of silicon oxynitride insulating films include silicon oxynitride films and aluminum oxynitride films. Furthermore, organic insulating films can also be used as insulating layers included in semiconductor devices.

[0351] Note that in this specification, etc., "oxynitride" refers to a material in which the oxygen content is greater than the nitrogen content in its composition, while "nitrogen oxide" refers to a material in which the nitrogen content is greater than the oxygen content in its composition. For example, when described as "silicon oxynitride," it refers to a material in which the oxygen content is greater than the nitrogen content in its composition, while when described as "silicon oxynitride," it refers to a material in which the nitrogen content is greater than the oxygen content in its composition.

[0352] For example, with the miniaturization and high integration of transistors, problems such as leakage current sometimes occur due to the thinning of the gate insulating layer. By using a high-k material for insulating layers such as insulating layer 204 and insulating layer 264, which serve as gate insulating layers, it is possible to achieve low voltage during transistor operation while maintaining the physical thickness. Furthermore, the EOT of the gate insulating layer can be reduced. On the other hand, by using a material with a low relative permittivity for insulating layers used as interlayer films, parasitic capacitance generated between wirings can be reduced. Therefore, it is preferable to select materials based on the function of the insulating layer. Furthermore, materials with a low relative permittivity are also materials with high dielectric strength.

[0353] Materials with relatively high permittivity (high-k) include, for example, aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0354] Examples of materials with low relative permittivity include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon oxynitride, as well as resins such as polyesters, polyolefins, polyamides (nylon, aramids, etc.), polyimides, polycarbonates, and acrylic resins. Furthermore, examples of inorganic insulating materials with low relative permittivity other than those mentioned above include fluorinated silicon oxide, carbon-containing silicon oxide, and silicon oxide containing both carbon and nitrogen. Porous silicon oxides are also an example. Moreover, these silicon oxides may contain nitrogen.

[0355] [Conductive Layer] The conductive layers (conductive layer 205, conductive layer 208, conductive layer 219, conductive layer 242, conductive layer 245, conductive layer 255, conductive layer 260, conductive layer 267, conductive layer 261, conductive layer 265, conductive layer 505, conductive layer 545, conductive layer 560, etc.) used in transistor 200 preferably use metallic elements selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., alloys with the above metallic elements as components, or alloys combining the above metallic elements. As alloys with the above metallic elements as components, nitrides or oxides of the alloys may also be used. For example, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred. In addition, semiconductors with high conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicides may also be used.

[0356] Furthermore, conductive materials containing nitrogen, such as tantalum nitrides, titanium nitrides, molybdenum nitrides, tungsten nitrides, ruthenium nitrides, tantalum and aluminum nitrides, and titanium and aluminum nitrides, as well as oxygen-containing conductive materials, such as ruthenium oxide, strontium and ruthenium oxides, and lanthanum and nickel oxides, and materials containing metallic elements such as titanium, tantalum, and ruthenium, are preferred because they are conductive materials that are not easily oxidized, have the function of inhibiting oxygen diffusion, or maintain conductivity even when absorbing oxygen. Note that examples of oxygen-containing conductive materials include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (also known as ITO), indium tin oxide containing titanium oxide, indium tin oxide with added silicon (also known as ITSO), indium zinc oxide (also known as IZO (registered trademark)), and indium zinc oxide containing tungsten oxide. In this specification, the conductive layer formed using an oxygen-containing conductive material is sometimes referred to as an oxide conductive layer.

[0357] Conductive materials with tungsten, copper, or aluminum as the main components have high conductivity and are therefore preferred.

[0358] Furthermore, multiple conductive layers formed from the aforementioned materials can be stacked. For example, a stacked structure combining materials containing the aforementioned metallic elements and conductive materials containing oxygen can also be used. Furthermore, a stacked structure combining materials containing the aforementioned metallic elements and conductive materials containing nitrogen can also be used. Additionally, a stacked structure combining materials containing the aforementioned metallic elements, conductive materials containing oxygen, and conductive materials containing nitrogen can also be used.

[0359] For example, when an oxide semiconductor, which is one of the metal oxides, is used as the semiconductor layer 203 of transistor 200A or transistor 200B, a stacked structure combining a material containing the aforementioned metal element and an oxygen-containing conductive material is preferably used as the conductive layer 205, conductive layer 219, etc., which serve as gate electrodes. In this case, it is preferable to provide the oxygen-containing conductive material on one side of the semiconductor layer 203. By providing the oxygen-containing conductive material on one side of the semiconductor layer 203, oxygen detached from this conductive material is easily supplied to the channel formation region of the semiconductor layer 203.

[0360] When an oxide semiconductor, one of the metal oxides, is used as the semiconductor layer 203, semiconductor layer 263, or semiconductor layer 520, since conductive layers 208a, 208b, 255, 261, 542a, and 542b are all conductive layers in contact with semiconductor layers 203, 263, or 520, it is preferable to use a conductive material that is not easily oxidized, a conductive material that maintains low resistance even if oxidized, a conductive metal oxide (also called an oxide conductor), or a conductive material that has the function of suppressing oxygen diffusion. Examples of such conductive materials include nitrogen-containing conductive materials and oxygen-containing conductive materials. This suppresses the decrease in conductivity of conductive layers 208a, 208b, 255, 261, 542a, and 542b.

[0361] By using an oxygen-containing conductive material as conductive layers 208a, 208b, 255, 261, 542a, and 542b, conductivity can be maintained even if conductive layers 208a, 208b, 255, 261, 542a, and 542b absorb oxygen. For example, when an insulating layer containing excess oxygen is used as an insulating layer in contact with conductive layers 208a, 208b, 255, 261, 542a, and 542b, conductivity can be maintained, which is preferred. For example, ITO, ITSO, IZO (registered trademarks) can be used as conductive layers 208a, 208b, 255, 261, 542a, and 542b.

[0362] [Semiconductor Layer] As the semiconductor layer (semiconductor layer 203, semiconductor layer 230, semiconductor layer 263, semiconductor layer 520, etc.), monomers or combinations of single-crystal semiconductors, polycrystalline semiconductors, microcrystalline semiconductors, or amorphous semiconductors can be used. As the semiconductor material, silicon, germanium, etc., can be used, for example. In addition, compound semiconductors such as silicon-germanium, silicon carbide, gallium arsenide, and nitride semiconductors can also be used. As compound semiconductors, organic materials with semiconductor properties (also called organic semiconductors), metal nitrides with semiconductor properties (also called nitride semiconductors), or metal oxides with semiconductor properties (also called oxide semiconductors) can be used. These semiconductor materials may also contain impurities as dopants.

[0363] When silicon is used as a semiconductor layer, examples of silicon that can be used in a semiconductor layer include monocrystalline silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. For example, low-temperature polycrystalline silicon (LTPS) can be cited as a polycrystalline silicon.

[0364] For example, by using silicon in the semiconductor layer 203 of transistor 200A or transistor 200B, and by including phosphorus or arsenic as n-type dopants in regions 203a and 203c of the semiconductor layer 203, the transistor can be used as an n-type transistor. Furthermore, by including boron as a p-type dopant in regions 203a and 203c of the semiconductor layer 203, the transistor can be used as a p-type transistor. Note that when both n-type and p-type dopants are present in regions 203a and 203c of the semiconductor layer 203, the transistor with the higher doping concentration tends to exhibit a higher conductivity type.

[0365] Two-dimensional materials, also known as semiconductors, can be used as the semiconductor layer in a transistor. Two-dimensional materials are collectively referred to as layered materials, a group of materials with layered crystal structures. A layered crystal structure is a structure formed by layers of covalent or ionic bonds stacked together through bonds weaker than covalent or ionic bonds, such as van der Waals bonds. Layered materials exhibit high conductivity per unit layer, i.e., high two-dimensional conductivity. By using materials with high two-dimensional conductivity, which are also semiconductors, as the semiconductor layer, transistors with high on-state current can be provided.

[0366] Examples of the aforementioned layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen elements (elements belonging to Group 16). Furthermore, examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specifically, examples of transition metal chalcogenides that can be used as semiconductor layers in transistors include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0367] When an oxide semiconductor, one of the metal oxides, is used as the semiconductor layer, the band gap of the metal oxide is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wider band gap as the semiconductor layer, the off-state current of the transistor can be significantly reduced. The off-state current of the OS transistor is small, so the power consumption of the semiconductor device can be reduced. Oxide semiconductors will be described in detail in Embodiment 3.

[0368] This embodiment can be implemented by appropriately combining the structures described in other embodiments, etc.

[0369] (Embodiment 3) In this embodiment, an oxide semiconductor layer that can be used as a semiconductor layer of a transistor is described.

[0370] [Oxide Semiconductor Layer] The oxide semiconductor layer used as the semiconductor layer of the transistor preferably comprises a crystalline metal oxide. Examples of structures with crystalline metal oxides include the CAAC (c-axis aligned crystal) structure, the polycrystalline structure, and the nanocrystalline (nc: nano-crystal) structure. By using a crystalline metal oxide in the oxide semiconductor layer, the defect state density in the oxide semiconductor layer can be reduced. This improves the reliability of the transistor according to one aspect of the invention, thereby improving the reliability of the memory device including the transistor.

[0371] According to one aspect of the invention, the oxide semiconductor layer preferably comprises a metal oxide having a CAAC structure. A CAAC structure refers to a crystal structure in which multiple microcrystals (typically multiple microcrystals with a hexagonal crystal structure) are oriented along the c-axis and connected on the ab plane in a manner where the multiple microcrystals are not oriented. Furthermore, when a cross-section of the oxide semiconductor layer having a CAAC structure is observed using a high-resolution transmission electron microscope (TEM) image, it can be confirmed that the metal atoms are arranged in layers within the crystalline regions. Therefore, the oxide semiconductor layer having a CAAC structure can also be described as a structure with layered crystalline regions.

[0372] The crystallinity of oxide semiconductor layers can be analyzed, for example, by X-ray diffraction (XRD), TEM, or electron diffraction (ED). Alternatively, a combination of these methods can be used for analysis.

[0373] Furthermore, there are no particular restrictions on the crystallinity of the semiconductor material contained in the oxide semiconductor layer. For example, the oxide semiconductor layer may sometimes contain one or more of the following: amorphous semiconductor (semiconductor with an amorphous structure), single-crystal semiconductor (semiconductor with a single-crystal structure), and crystalline semiconductor other than single crystal (microcrystalline semiconductor, polycrystalline semiconductor, or a semiconductor in which a portion has a crystalline region). When the oxide semiconductor layer is crystalline, it can sometimes suppress the degradation of transistor characteristics.

[0374] The metal oxide included in the oxide semiconductor layer according to one aspect of the present invention can be, for example, indium oxide, gallium oxide, and zinc oxide. The metal oxide of one aspect of the present invention preferably includes at least indium (In) or zinc (Zn). Furthermore, the metal oxide preferably includes two or three elements selected from indium, element M, and zinc. Element M is a metallic or semi-metallic element with a high bonding energy with oxygen, for example, a metallic or semi-metallic element with a higher bonding energy with oxygen than indium. Specific examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M included in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. When the element M included in the metal oxide is gallium, the metal oxide of one aspect of the present invention preferably includes one or more selected from indium, gallium, and zinc. Note that in this specification and other documents, metallic elements and half-metallic elements are sometimes collectively referred to as "metallic elements," and the "metallic elements" described in this specification and other documents sometimes include half-metallic elements.

[0375] As one embodiment of the present invention, the metal oxide may be indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also denoted as IGTO), gallium zinc oxide (Ga-Zn oxide, also denoted as GZO), aluminum zinc oxide (Al-Zn oxide, also denoted as AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also denoted as IAZO), indium tin zinc oxide (also denoted as In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also denoted as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also denoted as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also denoted as IGAZO or IAGZO), etc. In addition, examples include indium tin oxide (also known as ITSO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide), which contain silicon.

[0376] By increasing the proportion of indium atoms relative to the total number of atoms of all metal elements in a metal oxide, transistors can achieve large on-state current and high frequency characteristics.

[0377] Furthermore, metal oxides can also contain one or more of the periodically numbered metals in the periodic table instead of indium. Alternatively, metal oxides can contain one or more of the periodically numbered metals in the periodic table besides indium. There is a tendency that the greater the orbital overlap of the metal elements, the greater the carrier conduction in the metal oxide. Therefore, by including periodically numbered metals, the field-effect mobility of transistors can sometimes be improved. Examples of periodically numbered metals include those belonging to period 5 and period 6. Specific examples of such metals include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are referred to as light rare earth elements.

[0378] Furthermore, metal oxides may also contain one or more non-metallic elements. When metal oxides contain non-metallic elements, the field-effect mobility of transistors can sometimes be improved. Examples of non-metallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0379] Furthermore, by increasing the proportion of zinc atoms relative to the total number of atoms of all metal elements in the metal oxide, the crystallinity of the metal oxide is improved, thereby suppressing the diffusion of impurities in the metal oxide. Consequently, variations in the electrical characteristics of the transistor are suppressed, thus improving reliability.

[0380] Furthermore, by increasing the proportion of element M atoms relative to the total number of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies is suppressed, thereby enabling transistors with low off-state currents. In addition, variations in the transistor's electrical characteristics are suppressed, thus improving reliability.

[0381] In this embodiment, examples of In-Ga-Zn oxides as metal oxides are sometimes used for illustration.

[0382] The oxide semiconductor layer according to one embodiment of the present invention is crystalline. Furthermore, the oxide semiconductor layer according to one embodiment of the present invention preferably has a CAAC structure.

[0383] According to one aspect of the present invention, an oxide semiconductor layer can be fabricated by forming a metal oxide using one or more deposition methods. For example, according to one aspect of the present invention, an oxide semiconductor layer can be fabricated by forming a metal oxide using a first deposition method and a second deposition method. Note that an oxide semiconductor layer formed using at least two deposition methods can also be referred to as a Hybrid OS.

[0384] According to one aspect of the present invention, an oxide semiconductor layer can be manufactured by the following steps: forming a metal oxide as a first layer using a first deposition method, and then forming a second metal oxide layer on the first layer using a second deposition method. In this case, the first deposition method preferably uses a deposition method that causes less damage to the surface to be formed compared to the second deposition method. When a deposition method that causes less damage to the surface to be formed is used as the first deposition method, the formation of a mixed layer at the interface between the oxide semiconductor layer and the layer on the surface to be formed of the oxide semiconductor layer can be suppressed. Furthermore, the incorporation of impurities such as silicon into the second layer can be suppressed, thereby improving the crystallinity of the oxide semiconductor layer.

[0385] Examples of first deposition methods include atomic layer deposition (ALD), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), and wet deposition methods. Examples of CVD methods include plasma-enhanced CVD (PECVD), thermal CVD, photochemical CVD, and metal-organic CVD (MOCVD). Examples of wet deposition methods include spraying. Compared to sputtering methods described later, ALD and CVD methods can suppress damage to the surface being formed, making them suitable as first deposition methods.

[0386] Examples of ALD methods include thermal ALD (thermal ALD) which uses only thermal energy to react precursors and reactants, and plasma ALD (PEALD) which uses reactants excited by plasma.

[0387] When using the ALD method, atoms can be deposited layer by layer, thus offering the following advantages: extremely thin deposition is possible; deposition is possible on structures with high aspect ratios or surfaces with large steps; deposition is possible with fewer defects such as pinholes; high coverage deposition is possible; and deposition is possible at low temperatures; etc. Furthermore, the PEALD method, utilizing plasma, allows deposition at even lower temperatures, and is therefore sometimes preferred. Note that precursors used in the ALD method may contain elements such as carbon or chlorine. Therefore, films prepared using the ALD method sometimes contain more carbon or chlorine than films prepared using other deposition methods. Note that the quantification of these elements can be performed using X-ray photoelectron spectroscopy (XPS) or secondary ion mass spectrometry (SIMS). Furthermore, while the ALD method is used for depositing metal oxides according to one aspect of the present invention, due to the use of high substrate temperatures during deposition and one or both of the impurity removal treatment, the carbon and chlorine content in the film is sometimes lower than when using the ALD method without these conditions.

[0388] Unlike deposition methods that deposit particles released from a target or similar material, the ALD (Advanced Layer Deposition) method forms a film through a reaction on the surface of the workpiece. Therefore, the ALD method is less affected by the shape of the workpiece and exhibits good step coverage. In particular, the ALD method offers excellent step coverage and thickness uniformity, making it suitable for covering surfaces with high aspect ratio openings.

[0389] High-quality films can be obtained at relatively low temperatures using plasma CVD. Furthermore, because it does not use plasma, thermal CVD is a deposition method that reduces plasma damage to the workpiece. Moreover, since no plasma damage occurs during formation in thermal CVD, films with fewer defects can be obtained.

[0390] Examples of secondary deposition methods include sputtering and pulsed laser deposition (PLD). Metal oxides formed using these secondary deposition methods tend to have a CAAC structure.

[0391] Furthermore, as the first layer, a metal oxide with a microcrystalline or amorphous structure, for example, having a lower crystallinity than the CAAC structure, is sometimes formed. By forming a highly crystalline second layer on the low-crystallinity first layer, or by forming this layer and then heat-treating it, the crystallinity of the first layer is sometimes improved, with the second layer serving as the nucleus. This can thereby improve the overall crystallinity of the oxide semiconductor layer, including the area near the interface with the formed surface.

[0392] Furthermore, a third layer can be formed on the second layer. Because the second layer has high crystallinity, the third layer can crystallize and grow using the crystals of the second layer as nuclei or seeds. Thus, even if the deposition method for the third layer does not utilize a deposition method that readily produces crystals, the third layer can still be crystallized. Here, for example, when the third layer is formed using a deposition method with higher coverage than the second layer, both high crystallinity and high coverage can be achieved throughout the oxide semiconductor layer.

[0393] As an example, an oxide semiconductor layer according to one aspect of the present invention can be manufactured by the following steps: forming a metal oxide as a first layer using a first deposition method, forming a metal oxide as a second layer using a second deposition method, and then forming a metal oxide as a third layer using the first deposition method. Specifically, the first deposition method can be the ALD method, and the second deposition method can be the sputtering method. The ALD method is a deposition method with superior coverage compared to the sputtering method. When the ALD method is used as the deposition method for the first and third layers, the coverage of the oxide semiconductor layer can be improved. Therefore, the oxide semiconductor layer can be well covered on steps, openings, etc., with high aspect ratios.

[0394] [Manufacturing Method of Oxide Semiconductor Layer] The semiconductor layer 230, which is an oxide semiconductor layer, can be manufactured, for example, by the following steps: forming a semiconductor layer 230a on the layer 229 of the formed surface using the ALD method; forming a semiconductor layer 230b on the semiconductor layer 230a using the sputtering method; and forming a semiconductor layer 230c on the semiconductor layer 230b using the ALD method. Furthermore, it is preferable to perform heat treatment after forming the semiconductor layer 230. By performing heat treatment, the crystallinity of the semiconductor layer 230 can be improved. The heat treatment described herein is not limited to heating treatment. For example, heat applied during the manufacturing process can also be used.

[0395] Furthermore, layer 229 corresponds to insulating layer 202, insulating layer 256, insulating layer 258, etc., as described in the above embodiments. Layer 229 does not necessarily have crystallinity. In addition, if layer 229 has crystallinity, layer 229 may also have a crystal structure with low lattice integration with the metal oxide contained in semiconductor layer 230.

[0396] An example of a method for manufacturing semiconductor layer 230 is illustrated with reference to Figures 27A to 27D and Figures 28A to 28D.

[0397] When depositing metal oxide films using sputtering, alloying of the components contained in the metal oxide film and the components contained in the layer on the surface to be formed can sometimes occur due to damage caused by sputtering particles on the surface to be formed or by energy applied to the substrate side by sputtering particles. When alloying occurs, it is difficult to improve the crystallinity of the alloyed region even after heat treatment described later. When using an oxide semiconductor layer with alloyed regions in a transistor, there are concerns about negatively impacting the initial characteristics or reliability of the transistor. Therefore, it is preferable to suppress the alloying of the components contained in the metal oxide film and the components contained in the layer on the surface to be formed.

[0398] Therefore, a semiconductor layer 230a is first formed on layer 229 using the ALD method (Fig. 27A). Next, a semiconductor layer 230b is formed on semiconductor layer 230a using the sputtering method (Fig. 27B).

[0399] In a method for manufacturing an oxide semiconductor layer according to one aspect of the present invention, a semiconductor layer 230a is formed between a semiconductor layer 230b and a layer 229 using a deposition method that causes minimal damage to the surface to be formed. This suppresses the alloying of the components contained in the semiconductor layer 230 with the components contained in the layer 229, thereby further improving the crystallinity of the semiconductor layer 230.

[0400] By employing the above structure, the thickness of the alloyed region can be reduced or reduced to an unobservable degree. For example, the thickness of the alloyed region can be reduced to 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm. Note that Figures 27A and 27B show examples where no alloyed region is formed between layer 229 and semiconductor layer 230a.

[0401] Note that the thickness of the alloyed region can sometimes be calculated by performing a linear analysis of the composition of the region and its vicinity using SIMS or Energy Dispersive X-ray Spectroscopy (EDX).

[0402] For example, a linear analysis using EDX is performed on the aforementioned region and its vicinity, with the direction perpendicular to the surface where the semiconductor layer 230a is formed as the depth direction. Then, in the distribution of quantitative values ​​of each element relative to the depth direction obtained from this analysis, the depth at which the quantitative value of a metal (In if the semiconductor layer 230a contains In) that is a major component of the semiconductor layer 230a but not a major component of the layer where the surface is formed (here, layer 229) reaches half its value is defined as the depth (location) of the interface between the aforementioned region and the semiconductor layer 230a. Furthermore, the depth at which the quantitative value of an element that is a major component of the layer where the surface is formed but not a major component of the semiconductor layer 230a (e.g., Si) reaches half its value is defined as the depth (location) of the interface between the aforementioned region and the layer where the surface is formed. Thus, the thickness of the alloyed region can be calculated.

[0403] In an oxide semiconductor layer according to one aspect of the present invention, when observing the thickness of the alloyed region using EDX analysis, for example, the thickness is 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm.

[0404] Furthermore, for example, when a silicon oxide layer is used as layer 229 and SIMS analysis is performed on the semiconductor layer 230 formed on layer 229, the depth at which the silicon concentration reaches 50% of the maximum concentration in layer 229 is considered the interface, and the silicon concentration is reduced to 1.0 × 10⁻⁶. 21 atoms / cm 3 Preferably 5.0×10 20 atoms / cm 3 More preferably 1.0×10 20 atoms / cm 3 The distance between the depth and the interface is considered as the thickness t_s2. The thickness t_s2 is preferably less than 3 nm, and more preferably less than 2 nm.

[0405] By reducing the thickness of the alloyed region, the thickness t_s2 can be set to a value within the range mentioned above.

[0406] Furthermore, by thinning the alloyed region, a CAAC structure can be formed near the formed surface. Here, "near the formed surface" refers, for example, to a region in a substantially perpendicular direction from the formed surface of the semiconductor layer 230 that is greater than 0 nm and less than 3 nm, preferably greater than 0 nm and less than 2 nm, and more preferably more than 1 nm and less than 2 nm.

[0407] Note that CAAC structures near the formed surface can sometimes be identified using TEM observation. For example, when a cross-sectional view of semiconductor layer 230 is performed using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formed surface are identified near the formed surface.

[0408] Furthermore, when forming semiconductor layer 230a using the ALD method, sometimes a microcrystalline or amorphous oxide semiconductor layer with a lower crystallinity than the CAAC structure is formed. That is, in the manufacturing stage shown in FIG27A, semiconductor layer 230a sometimes includes regions with a lower crystallinity than semiconductor layer 230b.

[0409] The semiconductor layer 230b preferably adopts a composition suitable for the formation of a CAAC structure.

[0410] When semiconductor layer 230b is formed using sputtering, a mixed layer 231 is formed on or near the surface of semiconductor layer 230a. Furthermore, during the formation of semiconductor layer 230b, small crystalline regions may sometimes form in the mixed layer 231 due to sputtering particles or energy applied to the substrate side via sputtering particles. In subsequent heat treatment processes, the mixed layer 231 or the small crystalline regions formed in the mixed layer 231 may sometimes become nuclei, causing at least a portion of semiconductor layer 230a to crystallize.

[0411] When depositing semiconductor layer 230b using sputtering, it is preferable to heat the substrate. When forming metal oxides, it is sometimes possible to form highly crystalline metal oxides by increasing the substrate temperature (stage temperature) during metal oxide formation.

[0412] Next, semiconductor layer 230c is formed on semiconductor layer 230b using the ALD method (Fig. 27C). When forming semiconductor layer 230c using the ALD method, the method for forming semiconductor layer 230a can be referred to.

[0413] When a semiconductor layer 230c is formed on a semiconductor layer 230b having a CAAC structure using the ALD method, sometimes the semiconductor layer 230c is epitaxially grown using the semiconductor layer 230b as the core. Therefore, during the formation of the semiconductor layer 230c, the semiconductor layer 230c sometimes includes a region having a CAAC structure. Furthermore, this region having a CAAC structure is preferably formed integrally within the semiconductor layer 230c.

[0414] Next, a heat treatment process can be performed. Through this heat treatment process, the crystallinity of the region with the CAAC structure in the semiconductor layer 230c is sometimes improved. Furthermore, if the region is only formed below the semiconductor layer 230c after deposition using the ALD method, sometimes this heat treatment process expands the region to the top of the semiconductor layer 230c (Fig. 27D). In other words, through this heat treatment, sometimes the region with the CAAC structure in the semiconductor layer 230c is formed throughout the entire semiconductor layer 230c.

[0415] Furthermore, it is preferable that at least a portion of the semiconductor layer 230a is CAAC-treated via this heat treatment process (FIG. 27D). It is anticipated that the mixed layer 231 formed in the semiconductor layer 230a during the deposition of the semiconductor layer 230b will be used as a nucleus or seed crystal to facilitate CAAC treatment. Within the semiconductor layer 230a, a larger CAAC-treated area is preferable; preferably, the area near layer 229 is also CAAC-treated.

[0416] Furthermore, since CAAC is performed from the upper part to the lower part of the semiconductor layer 230a, it is not limited by the material or crystallinity of layer 229, and the vicinity of layer 229 can also be CAACed. For example, even if layer 229 has an amorphous structure, a highly crystalline semiconductor layer 230a can be formed. Thus, the method for manufacturing an oxide semiconductor layer according to one aspect of the present invention is particularly suitable for cases where the layer to be formed has an amorphous structure.

[0417] Note that Figures 27A to 27D are cross-sectional views illustrating a metal oxide deposition method according to one aspect of the present invention. Furthermore, Figures 27A to 27D can also be considered schematic diagrams of a metal oxide deposition model according to one aspect of the present invention. As shown in Figures 27A to 27D, the crystallinity of semiconductor layers 230a and 230c is improved by using a highly crystallinity semiconductor layer 230b as a nucleus or seed crystal. Specifically, the crystallinity of semiconductor layer 230a is sometimes improved by heat treatment during or after the deposition of semiconductor layer 230b. Furthermore, the crystallinity of semiconductor layer 230c is sometimes improved by heat treatment during or after the deposition of semiconductor layer 230c. Note that the aforementioned heat treatment has an auxiliary function in improving crystallinity.

[0418] Thus, in a metal oxide deposition method according to one aspect of the present invention, the crystallinity of the upper and lower oxide semiconductors (here, semiconductor layers 230a and 230c) can be improved by using a highly crystalline semiconductor layer 230b (i.e., CAAC) as a nucleus or seed. This improves the overall crystallinity of the oxide semiconductor. In other words, by using semiconductor layer 230b as a nucleus or seed, the upper and lower oxide semiconductors are epitaxially grown in a solid phase, thereby forming a highly crystalline oxide semiconductor. The oxide semiconductor formed using this deposition method, here a CAAC film, can be referred to as an axially grown CAAC (AG CAAC). Note that Figures 28A to 28D show a structure including semiconductor layers 230a, 230b, and 230c, but are not limited thereto. For example, a structure including semiconductor layers 230a and 230b can also be referred to as AG CAAC.

[0419] In semiconductor layer 230, regions with CAAC structures are preferably widely present throughout the layer. Figure 28A shows the state where semiconductor layers 230a, 230b, and 230c are all crystallized. At this point, the boundary between semiconductor layers 230a and 230b is sometimes not observable. Furthermore, the boundary between semiconductor layers 230b and 230c is sometimes not observable. Semiconductor layer 230 can sometimes be described as a layer whose interfaces are clearly not observable. Semiconductor layer 230 can sometimes be described as a single-layer structure.

[0420] Furthermore, a portion of semiconductor layer 230a or semiconductor layer 230c is sometimes not crystallized. The example shown in Figure 28B illustrates a state where the area near the interface between semiconductor layer 230a and layer 229 is not crystallized. Figure 28C shows a state where the area near the surface of semiconductor layer 230c is not crystallized. Figure 28D shows a state where neither the area near the interface between semiconductor layer 230a and layer 229 nor the area near the surface of semiconductor layer 230c is crystallized.

[0421] By improving the crystallinity of the oxide semiconductor layer, the increase in the resistance of the semiconductor layer in transistors using oxide semiconductor layers can be suppressed, and the initial characteristics of the transistor (especially the on-state current) can be improved. This makes it possible to realize transistors suitable for high-speed driving. Furthermore, the reliability of the transistor can be improved, and the on-state current can be increased.

[0422] According to one aspect of the invention, the oxide semiconductor layer exhibits high crystallinity throughout the layer. Consequently, the boundaries of the stacked films are not observable in semiconductor layers 230a, 230b, and 230c. In particular, it is difficult to confirm the boundaries of the stacked films after heat treatment. To confirm the presence or absence of the boundaries of the stacked films, for example, TEM can be used.

[0423] As described above, using metal oxides with a high In content in transistors can improve the field-effect mobility of the transistors. On the other hand, oxide semiconductors with a high In content tend to polycrystalline. Using polycrystalline metal oxides in transistors negatively impacts the initial characteristics or reliability of the transistors. Therefore, by using oxide semiconductors with a high In content in one or both of semiconductor layers 230a and 230c, a crystal reflecting the orientation of the crystals in semiconductor layer 230b is formed, thereby suppressing polycrystalline formation.

[0424] Furthermore, the lattice mismatch between the crystals in semiconductor layer 230b and those in semiconductor layer 230a or semiconductor layer 230c is preferably small. Thus, semiconductor layer 230a or semiconductor layer 230c can form crystals that reflect the orientation of the crystals in semiconductor layer 230b. At this time, for example, when a cross-section of semiconductor layer 230 is observed using a high-resolution TEM, bright spots arranged in a layered pattern parallel to the surface to be formed are identified in semiconductor layer 230a or semiconductor layer 230c.

[0425] There are no particular restrictions on the crystal structure of semiconductor layer 230a or semiconductor layer 230c, provided that the lattice mismatch between the crystal in semiconductor layer 230b and the crystal in semiconductor layer 230a or semiconductor layer 230c is small. The crystal structure of semiconductor layer 230a or semiconductor layer 230c can also be any one of the following crystal systems: cubic, tetragonal, orthorhombic, hexagonal, monoclinic, and trigonal.

[0426] [Composition of the Oxide Semiconductor Layer] As described above, the semiconductor layer 230b preferably has a composition suitable for forming a CAAC structure. When forming the semiconductor layer 230b, sputtering can be used, for example. The semiconductor layer 230b preferably contains zinc, for example. By including zinc, a highly crystalline metal oxide can be achieved. Furthermore, in addition to zinc, the semiconductor layer 230b preferably also contains element M. When the semiconductor layer 230b contains element M, for example, the formation of oxygen vacancies in the metal oxide can be suppressed. This improves the reliability of transistors using the oxide semiconductor layer. Specifically, as semiconductor layer 230b, metal oxides with an In:M:Zn ratio of 1:1:1 or similar, an In:M:Zn ratio of 1:1:1.2 or similar, an In:M:Zn ratio of 1:1:0.5 or similar, an In:M:Zn ratio of 1:1:2 or similar, an In:M:Zn ratio of 4:2:3 or similar, an In:M:Zn ratio of 1:3:2 or similar, or an In:M:Zn ratio of 1:3:4 or similar can be used. Furthermore, the "simultaneous" composition includes a range of ±30% of the desired atomic ratio. Additionally, one or more of gallium, aluminum, and tin are preferably used as element M.

[0427] Semiconductor layer 230b can also employ a structure that does not contain element M. For example, In-Zn oxide can be used. Specifically, it can employ an In:Zn ratio of 1:1 or similar, an In:Zn ratio of 2:1 or similar, or an In:Zn ratio of 4:1 or similar. Alternatively, indium oxide can also be used. Furthermore, a structure containing trace amounts of element M can also be employed. For example, it can employ an In:Ga:Zn ratio of 4:0.1:1 or similar, or an In:Ga:Zn ratio of 2:0.1:1 or similar. Additionally, it can employ an In:Sn:Zn ratio of 4:0.1:1 or similar, or an In:Sn:Zn ratio of 2:0.1:1 or similar.

[0428] Semiconductor layers 230a and 230c can be metal oxides with a high proportion of In. When forming semiconductor layers 230a and 230c, for example, the ALD method can be used. Furthermore, it is particularly preferable to use metal oxides with a high proportion of In compared to element M. By using metal oxides with a high proportion of In, the on-state current can be increased and the frequency characteristics improved when the oxide semiconductor layer is used in a transistor.

[0429] Furthermore, semiconductor layers 230a and 230c can also have a structure that does not contain element M. For example, In-Zn oxide can also be used. Specifically, a composition of In:Zn = 1:1 (atomic ratio) or nearby, In:Zn = 2:1 (atomic ratio) or nearby, or In:Zn = 4:1 (atomic ratio) or nearby can be used. Alternatively, indium oxide can also be used. Furthermore, semiconductor layers 230a and 230c can also have a structure that contains trace amounts of element M. Specifically, a composition of In:Ga:Zn = 4:0.1:1 (atomic ratio) or nearby, In:Ga:Zn = 2:0.1:1 (atomic ratio) or nearby, In:Sn:Zn = 4:0.1:1 (atomic ratio) or nearby, or In:Sn:Zn = 2:0.1:1 (atomic ratio) or nearby can be used.

[0430] Furthermore, increasing the zinc content in the oxide semiconductor can improve its crystallinity. In particular, a structure in which semiconductor layer 230a contains zinc is preferred. For example, when semiconductor layer 230a is formed using the ALD method and semiconductor layer 230b is formed using sputtering, zinc contained in semiconductor layer 230a sometimes diffuses into semiconductor layer 230b. Note that this diffusion occurs due to heat treatment during or after sputtering. When zinc diffuses from semiconductor layer 230a to semiconductor layer 230b, improved crystallinity is expected. Furthermore, when zinc diffuses from semiconductor layer 230a to semiconductor layer 230b, lateral growth of crystal portions with c-axis orientation is expected, promoting CAAC formation.

[0431] Furthermore, semiconductor layers 230a and 230c can be described as metal oxides with a higher proportion of In compared to semiconductor layer 230b.

[0432] Furthermore, for example, semiconductor layers 230a and 230c can be metal oxides with a higher Ga ratio compared to semiconductor layer 230b. For instance, semiconductor layers 230a and 230c preferably use metal oxides with an In:Ga:Zn ratio of 1:1:1 or similar, an In:Ga:Zn ratio of 1:3:2 or similar, or an In:Ga:Zn ratio of 1:3:4 or similar. By increasing the Ga ratio, the band gaps of semiconductor layers 230a and 230c can sometimes be made larger than those of semiconductor layer 230b. Thus, semiconductor layer 230b is sandwiched between semiconductor layers 230a and 230c with larger band gaps, and semiconductor layer 230b is primarily used as a current path (channel). When semiconductor layer 230b is sandwiched between semiconductor layers 230a and 230c, the trap levels at and near the interface of semiconductor layer 230b can be reduced. This allows for the realization of embedded channel transistors with the channel far from the insulating layer interface, thereby improving field-effect mobility.

[0433] Furthermore, in an oxide semiconductor layer according to one aspect of the present invention, even if the semiconductor layers 230a and 230c employ compositions that are difficult to form a CAAC structure when formed as a single layer, a structure in which the entire oxide semiconductor layer including semiconductor layers 230a and 230c has a CAAC structure can be achieved by crystal growth with semiconductor layer 230b as the nucleus. Alternatively, a region spanning at least a portion of each of semiconductor layers 230a and 230c, as well as a region of semiconductor layer 230b, can have a CAAC structure.

[0434] In particular, a high In ratio composition in semiconductor layers 230a and 230c can also achieve a crystallinity suitable for use as a transistor. In an oxide semiconductor layer according to one embodiment of the invention, the following effects can be simultaneously achieved: improved transistor on-state characteristics by increasing the In ratio; and improved reliability by employing a highly crystallinity CAAC structure.

[0435] Note that the composition of semiconductor layer 230a may also be different from that of semiconductor layer 230c.

[0436] In addition, semiconductor layers 230a and 230c can also be metal oxides having the same composition as semiconductor layer 230b.

[0437] By using the oxide semiconductor layer with CAAC structure formed by the two deposition methods described above in the channel formation region of the transistor, transistors with excellent characteristics can be realized (e.g., transistors with large on-state current, transistors with high field-effect mobility, transistors with small S-value, transistors with high frequency characteristics (also known as f-characteristics), transistors with high reliability, etc.).

[0438] When analyzing the composition of the metal oxide used in semiconductor layer 230, methods such as EDX, XPS, inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES) can be used. Alternatively, a combination of these methods can be used. Note that due to limitations in analytical precision, the actual content of elements with low content may differ from the analytically obtained content. For example, in cases where element M has a low content, the analytically obtained content of element M may sometimes be lower than the actual content.

[0439] [c-axis orientation ratio] According to one aspect of the present invention, the oxide semiconductor layer has a CAAC structure. The crystallinity of the oxide semiconductor layer according to one aspect of the present invention can be evaluated, for example, by utilizing crystal orientation.

[0440] Crystal orientation can be determined using an FFT pattern obtained by processing a TEM image using a Fast Fourier Transform (FFT). Specifically, the orientation of the crystal axes is determined using the FFT pattern. The FFT pattern obtained through FFT processing reflects the same reciprocal space information as the electron beam diffraction pattern.

[0441] By performing FFT processing on each region of the TEM image of the oxide semiconductor layer, the crystal orientation of each region can be obtained. For example, by obtaining the crystal orientation of each region within a certain area, a map showing the crystal orientation can be formed. Specifically, two high-intensity spots are identified in the FFT pattern of a region with layered crystals. The direction of the crystal axis of that region can be determined from the angle of the line segment connecting these two spots.

[0442] The c-axis orientation ratio can be calculated by determining the proportion of regions oriented towards the c-axis in a diagram showing crystal orientation. Note that, here, regions oriented towards the c-axis refer to regions whose orientation coincides with the c-axis and whose difference from the c-axis is within 20°.

[0443] In an oxide semiconductor layer according to one aspect of the invention, the c-axis orientation ratio can be calculated, for example, by TEM observation of a cross-section or plane of the oxide semiconductor layer. Furthermore, the region for performing the FFT (also called the FFT window) can, for example, be a circle with a diameter of 1.0 nm. Note that the region for performing the FFT is not limited to a circle.

[0444] In an oxide semiconductor layer according to one aspect of the present invention, the c-axis orientation ratio is 60% or more, preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more.

[0445] Furthermore, the c-axis orientation ratios of the regions deposited as semiconductor layer 230a, semiconductor layer 230b, and semiconductor layer 230c can be Rc1, Rc2, and Rc3, respectively. Rc2 and Rc3 are both 60% or more, preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. Rc3 / Rc1 is preferably greater than 1. Furthermore, Rc2 / Rc1 is preferably greater than 1.

[0446] Note that in semiconductor layer 230, sometimes the boundaries of semiconductor layers 230a, 230b and 230c are not clearly visible after manufacturing.

[0447] Semiconductor layer 230 can be divided into three regions sequentially from layer 229: a first region, a second region, and a third region. Each region is a layered region.

[0448] The first, second, and third regions all have a CAAC structure. Furthermore, the c-axis orientation ratio of the third region is preferably higher than that of the first region. Similarly, the c-axis orientation ratio of the second region is preferably higher than that of the first region. Moreover, the c-axis orientation ratios of the second and third regions are each 80% or more, more preferably 90% or more, and even more preferably 95% or more.

[0449] The first region is located on the top surface of the separation layer 229 and has a range of 0 nm to 3 nm. The third region is located on the top surface of the separation layer 230 and has a range of 0 nm to 3 nm.

[0450] Or the thickness of the layers in each region may be roughly the same.

[0451] This embodiment can be implemented by appropriately combining the structures described in other embodiments, etc.

[0452] (Embodiment 4) In this embodiment, a structural example of a storage device 300 including a semiconductor device 10 according to one aspect of the present invention will be described. As described above, the semiconductor device 10 is used as a storage unit.

[0453] <Storage Device 300> FIG29A is a block diagram illustrating a structural example of a storage device 300 including a semiconductor device 10 according to one aspect of the present invention. The storage device 300 shown in FIG29A includes a drive circuit 21 and a storage cell array 310.

[0454] The memory cell array 310 includes a plurality of semiconductor devices 10 arranged in a matrix of p rows and q columns (p and q being integers greater than or equal to 1). By arranging the plurality of semiconductor devices 10 in a matrix, a memory device with a large storage capacity can be realized.

[0455] In Figure 29A, the semiconductor device 10 in the first row and first column is represented as semiconductor device 10[1, 1], the semiconductor device 10 in the p-th row and q-th column is represented as semiconductor device 10[p, q], the semiconductor device 10 in the p-th row and first column is represented as semiconductor device 10[p, 1], the semiconductor device 10 in the first row and q-th column is represented as semiconductor device 10[1, q], and the semiconductor device 10 in the r-th row and s-th column (where r is an integer greater than or equal to 1 and less than or equal to p in any row, and s is an integer greater than or equal to 1 and less than or equal to q in any column) is represented as semiconductor device 10[r, s].

[0456] Furthermore, rows and columns extend in directions orthogonal to each other. In this embodiment, the X direction (the direction along the X-axis) is referred to as a "row" and the Y direction (the direction along the Y-axis) is referred to as a "column," but it is also possible to refer to the X direction as a "column" and the Y direction as a "row."

[0457] The drive circuit 21 includes a power switch 22, a power switch 23, and a peripheral circuit group 31. The peripheral circuit group 31 includes a peripheral circuit 41, a control circuit 32, and a voltage generation circuit 33.

[0458] In the storage device 300, circuits, signals, and voltages can be appropriately selected or omitted as needed. Alternatively, other circuits or signals not described in this embodiment may be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are signals input from the outside, and signal RDA is a signal output to the outside. Signal CLK is a clock signal.

[0459] In addition, signals BW, CE, and GW are control signals. Signal CE is the chip enable signal, signal GW is the global write enable signal, and signal BW is the byte write enable signal. Signal ADDR is the address signal. Signal WDA is for writing data, and signal RDA is for reading data. Signals PON1 and PON2 are power gating control signals. Furthermore, signals PON1 and PON2 can also be generated in control circuit 32.

[0460] The control circuit 32 is a logic circuit that controls the overall operation of the storage device 300. For example, the control circuit performs logical operations on signals CE, GW, and BW to determine the operating mode of the storage device 300 (e.g., write operation, read operation). Alternatively, the control circuit 32 generates control signals for the peripheral circuit 41 to execute the aforementioned operating mode.

[0461] The voltage generation circuit 33 has the function of generating voltage. The signal WAKE has the function of controlling the input signal CLK to the voltage generation circuit 33. For example, when the signal WAKE supplies the potential H, the signal CLK is input to the voltage generation circuit 33, and the voltage generation circuit 33 generates voltage.

[0462] The peripheral circuit 41 has the function of writing data to the memory cell array 310 and reading data from the memory cell array 310. In other words, it has the function of selecting a predetermined semiconductor device 10 from the plurality of semiconductor devices 10 included in the memory cell array 310 to write data and to read data stored in the predetermined semiconductor device 10. The peripheral circuit 41 includes a row decoding circuit 42, a column decoding circuit 44, a row driving circuit 43, a column driving circuit 45, an input circuit 47, a readout amplification circuit 46, and an output circuit 48.

[0463] Row decoding circuit 42 and column decoding circuit 44 are used to decode the signal ADDR. Row decoding circuit 42 is used to specify the row to be accessed, and column decoding circuit 44 is used to specify the column to be accessed. Row driving circuit 43 is used to select the wiring (wiring WWL, wiring RWL, etc.) specified by row decoding circuit 42. Column driving circuit 45 is used to supply data stored in semiconductor device 10 to the wiring WBL specified by column decoding circuit 44. In addition, column driving circuit 45 is used to supply potential H to the wiring RBL specified by column decoding circuit 44. Readout amplifier circuit 46 is used to detect the potential change of wiring RBL specified by column decoding circuit 44 and read the data stored in semiconductor device 10.

[0464] Input circuit 47 has the function of holding signal WDA. The data held in input circuit 47 is output to column driver circuit 45. The output data of input circuit 47 is the data (Din) written to semiconductor device 10. The data (Dout) read from semiconductor device 10 by read amplifier circuit 46 is output to output circuit 48. Output circuit 48 has the function of holding Dout. In addition, output circuit 48 has the function of outputting Dout to the outside of storage device 300. The data output from output circuit 48 is signal RDA.

[0465] Power switch 22 controls the supply of voltage VDD to the peripheral circuit group 31. Power switch 23 controls the supply of voltage VHM to the row drive circuit 43. Here, the high power supply potential of the storage device 300 is VDD, and the low power supply potential is GND. Furthermore, voltage VHM is the power supply potential used to make the word line (e.g., the wiring WWL) reach voltage H, and is a potential higher than VDD. Power switch 22 is controlled to turn on and off via signal PON1, and power switch 23 is controlled to turn on and off via signal PON2. In Figure 29A, the number of power domains in the peripheral circuit group 31 supplied with VDD is 1, but it can also be multiple. In this case, a power switch can be set for each power domain.

[0466] Additionally, as shown in Embodiment 1, the driving circuit 21 and the transistor M2 of the semiconductor device 10 can be provided in the component layer 50. Alternatively, the driving circuit 21 and the transistors M2 and M3 of the semiconductor device 10 can be provided in the component layer 50. As shown in Embodiment 1, the component layer 50 can use a single-crystal semiconductor substrate or an SOI substrate, etc.

[0467] Furthermore, the element layer 60, which includes the transistor M1 of the semiconductor device 10, can be disposed in a manner overlapping with the element layer 50. Therefore, a portion of the memory cell array 310 is formed in the element layer 50, and another portion of the memory cell array 310 is formed in the element layer 60. The memory device 300 shown in this embodiment has a structure in which the drive circuit 21 and the transistor M2 of the semiconductor device 10 are disposed in the element layer 50, and the transistor M1 is disposed in the element layer 60 (see FIG29B). As described above, the transistor M3 can also be disposed in the element layer 50.

[0468] By forming a component layer 50 including a drive circuit 21 and a component layer 60 including a transistor M1 of a semiconductor device 10, respectively, the operation of the drive circuit 21 included in the component layer 50 can be confirmed before the component layer 60 is formed on the component layer 50. Therefore, high-quality components from the component layer 50 can be selected, improving the manufacturing yield of the storage device 300. Thus, the productivity of the storage device 300 can be increased.

[0469] Furthermore, by overlapping the element layer 50 (including the driving circuit 21 and the transistor M2 of the semiconductor device 10) and the element layer 60 (including the transistor M1 of the semiconductor device 10), the signal transmission distance within the memory cell array 310 can be shortened. Additionally, the signal transmission distance between the driving circuit 21 and the memory cell array 310 can be shortened. Therefore, not only are the parasitic resistance and capacitance within the memory cell array 310 reduced, but the parasitic resistance and capacitance between the driving circuit 21 and the memory cell array 310 are also reduced, thereby achieving a reduction in power consumption and signal delay. Furthermore, the memory device 300 can be miniaturized. Additionally, the storage capacity per unit area can be increased.

[0470] <Examples of Planar and Stacked Structures of Memory Cells> Examples of planar and stacked structures of memory cells included in memory device 300 will be described. As an example of a semiconductor device 10 used as a memory cell, FIG30A shows a planar structure example of the semiconductor device 10A shown in FIG1A. FIG30B is a circuit diagram of the semiconductor device 10A shown in FIG1A. Additionally, FIG31 shows a cross-sectional structure example along the dashed line X1-X2 in FIG30A. In FIG30A, some constituent elements are omitted for clarity. For example, in FIG30A, the description of the element layer 50 including transistor M2 is omitted. Note that, to avoid repetition, the description of semiconductor device 10A is omitted here.

[0471] Additionally, in Figure 31, transistor 400 is shown as transistor M2, which is included in element layer 50. Transistor 200C is shown as transistor M1, which is included in element layer 60. Note that, to avoid repetition, descriptions related to transistor 200C are omitted here.

[0472] Transistor 400, used as transistor M2, is disposed on substrate 371 and includes a conductive layer 376 serving as a gate electrode, an insulating layer 375 serving as a gate insulating layer, a semiconductor region 373 formed by a portion of substrate 371, and low-resistance regions 374a and 374b serving as source or drain regions. Transistor 400, used as transistor M2, can be a p-channel transistor or an n-channel transistor. Substrate 371 can be, for example, a single-crystal silicon substrate.

[0473] In the transistor 400 shown in FIG. 30, the semiconductor region 373 (a portion of the substrate 371) forming the channel has a convex shape. Furthermore, a conductive layer 376 covers the sides and top surface of the semiconductor region 373 across an insulating layer 375. The conductive layer 376 can also be made of a material with an adjustable work function. Because of the convex portion of the semiconductor substrate, this type of transistor is also called a Fin-type transistor. Furthermore, an insulating layer for forming the convex portion can be provided in contact with the upper surface of the convex portion. Although the case of forming the convex portion by processing a portion of the semiconductor substrate is shown here, a semiconductor film with a convex shape can also be formed by processing an SOI substrate.

[0474] The structure of transistor 400, which is used as transistor M2, can also be used for the transistors included in drive circuit 21. Note that the structure of transistor 400 shown in Figure 31 is only an example and is not limited to the above structure. Appropriate transistors can be used depending on the circuit structure or driving method.

[0475] The component layer 50 may also include a wiring layer comprising interlayer films, wiring, and connectors. Furthermore, multiple wiring layers may be provided depending on the design. Additionally, in this specification, wiring and connectors may also be considered as components. That is, a portion of the conductive layer is sometimes used as wiring, and a portion of the conductive layer is sometimes used as a connector.

[0476] For example, in transistor 400, insulating layers 390, 391, 393, and 394 are sequentially stacked as interlayer films. Furthermore, conductive layers 392 are embedded in insulating layers 390 and 391. Furthermore, conductive layers 395 and 397 are embedded in insulating layers 393 and 394. Conductive layers 392 and 395 are used as contact plugs or wiring.

[0477] Furthermore, the insulating layer used as an interlayer film can be used as a planarization film covering the uneven shape underneath. For example, to improve flatness, the top surface of the insulating layer 391 can also be subjected to CMP treatment, etc.

[0478] Wiring layers can also be provided on insulating layer 394 and conductive layer 395. For example, in FIG31, insulating layer 396, insulating layer 382 and insulating layer 384 are sequentially stacked on insulating layer 394 and conductive layer 395. Conductive layer 385 and conductive layer 386 are formed in insulating layer 396, insulating layer 382 and insulating layer 384. Conductive layer 385 and conductive layer 386 are used as contact plugs or wiring.

[0479] Additionally, conductive layers 255a, 255b, and 255c are provided on the insulating layer 384. Conductive layers 255a, 255b, and 255c can be made of the same material as conductive layer 255 shown in the above embodiment. Conductive layer 255a is connected to conductive layer 376 via conductive layer 386. Conductive layer 255c is connected to conductive layer 397 via conductive layer 385. Conductive layer 397 is used as wiring WBL.

[0480] In addition, insulating layers 257, 258, and 259 are provided on conductive layers 255a, 255b, and 255c. Furthermore, conductive layers 261a and 261b are provided on insulating layer 259. Conductive layers 261a and 261b can be made of the same material as conductive layer 261 shown in the above embodiment.

[0481] In Figure 31, the opening 262 of transistor M1[1] is represented as opening 262[1], and the opening 262 of transistor M1[2] is represented as opening 262[2]. In addition, a portion of the conductive layer 261b is used as the conductive layer 261 of transistor M1[1], and the other portion is used as the conductive layer 261 of transistor M1[2].

[0482] Furthermore, an opening 269[1] is provided in the region overlapping a portion of the conductive layer 255a, passing through the insulating layers 259, 258, and 257. Additionally, the conductive layer 261a has a region inside the opening 269[1] that overlaps with the bottom of the opening 269[1] and a region that overlaps with the side of the opening 269[1]. Furthermore, the conductive layer 261a is connected to the conductive layer 255a at the bottom of the opening 269[1].

[0483] Furthermore, an opening 269[2] is provided in the region overlapping a portion of the conductive layer 255b, passing through the insulating layers 259, 258, and 257. Additionally, the conductive layer 261b has a region inside the opening 269[2] that overlaps with the bottom of the opening 269[2] and a region that overlaps with the side of the opening 269[2]. Furthermore, the conductive layer 261b is connected to the conductive layer 255b at the bottom of the opening 269[2].

[0484] Additionally, an insulating layer 264 is provided on the insulating layer 259, the conductive layer 261a, the conductive layer 261b, the semiconductor layer 263[1], and the semiconductor layer 263[2]. The insulating layer 264 has a region that overlaps with the opening 269[1] and overlaps with the conductive layer 261a inside the opening 269[1]. The insulating layer 264 has a region that overlaps with the opening 269[2] and overlaps with the conductive layer 261b inside the opening 269[2].

[0485] Additionally, the insulating layer 264 includes conductive layers 265a, 265b, 265c, and 265d. Conductive layer 265b is used as the conductive layer 265 of transistor M1[1]. Conductive layer 265d is used as the conductive layer 265 of transistor M1[2]. Therefore, conductive layer 265b is used as the gate electrode of transistor M1[1], and conductive layer 265d is used as the gate electrode of transistor M1[2].

[0486] The conductive layer 265a has a region inside the opening 269[1] that overlaps with the conductive layer 261a through the insulating layer 264. The region in and around the opening 269[1] where the conductive layers 261a and 265a overlap each other through the insulating layer 264 is used as a capacitor Cs[1]. Therefore, the conductive layer 261a is used as one electrode of the capacitor Cs[1], and the conductive layer 265a is used as the other electrode of the capacitor Cs[1].

[0487] The conductive layer 265c has a region inside the opening 269[2] that overlaps with the conductive layer 261b through the insulating layer 264. The region in and around the opening 269[2] where the conductive layer 261b and the conductive layer 265c overlap each other through the insulating layer 264 is used as a capacitor Cs[2]. The conductive layer 261b is used as one electrode of the capacitor Cs[2], and the conductive layer 265c is used as the other electrode of the capacitor Cs[2].

[0488] Conductive layers 265a and 265c are connected to the wiring COM. Note that Figure 30A shows an example where a portion of the wiring COM is used as conductive layer 265a and another portion is used as conductive layer 265c. Therefore, conductive layers 265a, 265b, 265c, 265d, and the wiring COM can be formed using the same materials and methods as conductive layer 265.

[0489] Furthermore, insulating layer 266 is included on insulating layer 264. The top surface of insulating layer 266 is preferably flat. Figure 31 shows the case where the top surfaces of insulating layer 266, conductive layer 265a, conductive layer 265b, conductive layer 265c, and conductive layer 265c are in the same or substantially the same position.

[0490] In addition, an insulating layer 276 is included on the insulating layer 266, conductive layer 265a, conductive layer 265b, conductive layer 265c, and conductive layer 265d, and conductive layer 271[1] and conductive layer 271[2] are included in a manner that embeds the insulating layer 276. Conductive layer 271[1] is disposed in the region overlapping with conductive layer 265b, and conductive layer 271[2] is disposed in the region overlapping with conductive layer 265d.

[0491] In addition, a conductive layer 278 is provided on the insulating layer 276, the conductive layer 271[1], and the conductive layer 271[2]. The conductive layer 265b is connected to the conductive layer 278 through the conductive layer 271[1]. The conductive layer 265d is connected to the conductive layer 278 through the conductive layer 271[2]. Therefore, the conductive layer 265b and the conductive layer 265d are connected through the conductive layer 271[1], the conductive layer 271[2], and the conductive layer 278. In addition, the conductive layer 278 is used as a wiring WWL.

[0492] Additionally, insulating layer 277 is included on insulating layer 276. Similar to insulating layer 266, the top surface of insulating layer 277 is preferably flat. Figure 31 shows the case where the top surfaces of conductive layer 278 and insulating layer 277 are positioned at the same or substantially the same level.

[0493] Additionally, an insulating layer 279 is included on the insulating layer 277 and the conductive layer 278. The insulating layers 276, 277, and 279 can be formed using the same materials and methods as the insulating layers shown in the above embodiments. The conductive layers 271[1], 271[2], and 278 can be formed using the same materials and methods as the conductive layers shown in the above embodiments.

[0494] <Example of Planar Structure and Example of Stacked Structure of Memory Cells 2> Next, another example of the stacked structure of the memory cells included in the memory device 300 will be described. As an example of the semiconductor device 10 used as a memory cell, FIG44 shows an example of the cross-sectional structure of the semiconductor device 10A shown in FIG1A. Note that, to avoid repetition, the description of the circuit structure of the semiconductor device 10A is omitted here. In addition, the structure of the element layer 50 shown in FIG44 can be referred to the description of the element layer 50 shown in FIG31. In addition, transistor 200B is shown as transistor M1 included in element layer 60. To avoid repetition, detailed descriptions related to transistor 200B are omitted here.

[0495] In the semiconductor device 10A shown in FIG44, a component layer 60 is disposed above an insulating layer 384. Specifically, a conductive layer 801 and a conductive layer 802 are disposed on the insulating layer 384. By forming a conductive layer using the same material as the conductive layer 205 shown in the above embodiment and then processing the shape of the conductive layer by etching or the like, conductive layer 801 and conductive layer 802 can be formed simultaneously. Conductive layer 802 is connected to conductive layer 376 through conductive layer 386.

[0496] In addition, an insulating layer 803 is provided on conductive layer 801 and conductive layer 802. Furthermore, a conductive layer 804 is provided on insulating layer 803. Conductive layer 804 can be formed using the same material as conductive layer 205 shown in the above embodiment. Conductive layer 804 has a region that overlaps with conductive layer 801 with the insulating layer 803 in between and a region that overlaps with conductive layer 802 with the insulating layer 803 in between. Furthermore, the region where conductive layer 804, insulating layer 803 and conductive layer 801 overlap with each other is used as capacitor Cs[2]. In addition, the region where conductive layer 804, insulating layer 803 and conductive layer 802 overlap with each other is used as capacitor Cs[1]. Therefore, it can be said that conductive layer 804 is used as the second electrode of capacitor Cs[1] and the second electrode of capacitor Cs[2]. In addition, conductive layer 802 is used as the first electrode of capacitor Cs[1] and conductive layer 801 is used as the first electrode of capacitor Cs[2]. The insulating layer 803 is used as the dielectric of capacitor Cs[1] and capacitor Cs[2].

[0497] The insulating layer 803 can be formed using the same material as the insulating layers 202 and 204 shown in the above embodiments. In particular, by using a material with a high relative permittivity (high-k), the electrostatic capacitance of capacitors Cs[1] and Cs[2] can be improved. Materials with a high relative permittivity (high-k) can include, for example, aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium. Note that a single layer of the insulating layer with these materials as its main components can be used as the insulating layer 803, or a stack of multiple such insulating layers can be used as the insulating layer 803.

[0498] Insulating layers 805, 806, and 807 are sequentially stacked on insulating layer 803 and conductive layer 804. Insulating layers 805, 806, and 807 can be formed using the same materials as insulating layers 202 and 204 shown in the above embodiment. For example, insulating layer 805 can be an organic insulating material such as an organic resin that easily achieves surface planarization; insulating layer 806 can be an inorganic insulating material with hydrogen-blocking properties; and insulating layer 807 can be an inorganic insulating material that easily supplies oxygen to the semiconductor layer containing oxide semiconductors formed above and has a relatively low dielectric constant. Specifically, as an organic resin, examples include polyimide resin, polyamide resin, acrylic resin, siloxane resin, epoxy resin, or phenolic resin. As a hydrogen-blocking inorganic insulating material, examples include materials with higher hydrogen-blocking properties than silicon oxide, such as silicon nitride, silicon oxynitride, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, etc., that is, materials that do not easily allow hydrogen diffusion. As an inorganic insulating material that can easily supply oxygen to the semiconductor layer containing oxide semiconductors and has a relatively low dielectric constant, silicon oxide, silicon oxynitride, etc. can be used, for example.

[0499] Insulating layers 805, 806, and 807 each have an opening leading to the conductive layer 804, and a conductive layer 808 connected to the conductive layer 804 is disposed in each of these openings. Additionally, insulating layers 803, 805, 806, and 807 each have an opening leading to the conductive layer 801 and an opening leading to the conductive layer 802, and each opening contains a conductive layer 809 connected to the conductive layer 801 and a conductive layer 810 connected to the conductive layer 802. The conductive layers 808, 809, and 810 are used as through electrodes, and can be formed simultaneously using a single conductive layer having the same material and stacked structure as the conductive layer 205 shown in the above embodiment.

[0500] In addition, conductive layers 811, 812, and 813, the back gate electrode of transistor 850, and the back gate electrode of transistor 851 are provided on insulating layer 807. Transistor 850 is equivalent to transistor M1[2], and transistor 851 is equivalent to transistor M1[1]. Transistor 850 and transistor 851 have the same structure as transistor 200B shown in the above embodiment, and conductive layer 219 is used as the back gate electrode. Conductive layer 219, conductive layer 811, conductive layer 812, and conductive layer 813 can be formed simultaneously using a single conductive layer having the same material and stacked structure as conductive layer 205 shown in the above embodiment.

[0501] Alternatively, the conductive layer 219 used as the back gate electrode of transistor 850 and the conductive layer 219 used as the back gate electrode of transistor 851 can be provided separately. In this case, the two conductive layers 219 can be connected to each other, or they can be electrically separated to supply different potentials to each other. Alternatively, one conductive layer 219 can be used as both the back gate electrode of transistor 850 and the back gate electrode of transistor 851.

[0502] In addition, conductive layer 811 is connected to conductive layer 808, conductive layer 812 is connected to conductive layer 809, and conductive layer 813 is connected to conductive layer 810.

[0503] Furthermore, insulating layer 202 and insulating layer 204, as shown in the above embodiment, are sequentially stacked on insulating layer 807, conductive layer 811, conductive layer 812, conductive layer 813, the back gate electrode of transistor 850, and the back gate electrode of transistor 851. Additionally, conductive layer 205, as shown in the above embodiment, is disposed on insulating layer 204. Conductive layer 205 serves as the gate electrode of transistor 850 and the gate electrode of transistor 851.

[0504] Note that in the semiconductor device 10A shown in FIG1A, the gate electrode of transistor 850 and the gate electrode of transistor 851 are connected to each other. Therefore, the conductive layer 205 used as the gate electrode of transistor 850 and the conductive layer 205 used as the gate electrode of transistor 851 can be disposed separately, but in this case, they are connected by other conductive layers. Alternatively, a single conductive layer 205 can be used as the gate electrode of both transistor 850 and transistor 851. In the cross-sectional view shown in FIG44, a single conductive layer 205 is used as the gate electrode of both transistor 850 and transistor 851. In FIG44, the conductive layer 205 is guided as wiring and disposed in a region separate from transistors 850 and 851.

[0505] Note that in the semiconductor device 10B shown in FIG4A, the gate electrode of transistor 850 and the gate electrode of transistor 851 are respectively connected to different wirings WWL (specifically, wiring WWLb and wiring WWLa), and are electrically isolated from each other. In this case, the conductive layer 205 used as the gate electrode of transistor 850 and the conductive layer 205 used as the gate electrode of transistor 851 are configured separately so that different signals can be supplied to each other.

[0506] Insulating layer 206 and insulating layer 209, as shown in the above embodiment, are sequentially stacked on insulating layer 204 and conductive layer 205. Furthermore, insulating layer 814 is provided on insulating layer 209. Insulating layer 814 can be formed using the same material as insulating layer 202 and insulating layer 204, as shown in the above embodiment.

[0507] The insulating layers 209 and 814 are provided with openings that reach the conductive layers 208a and 208b of transistors 850 and 851 respectively, as shown in the above-described embodiments. Furthermore, each of the plurality of openings is provided with a conductive layer serving as a through electrode. Specifically, a conductive layer 815 connected to the conductive layer 208a is provided in the opening reaching the conductive layer 208a of transistor 850, and a conductive layer 816 connected to the conductive layer 208b of transistor 850 is provided in the opening reaching the conductive layer 208a of transistor 851. Additionally, a conductive layer 817 connected to the conductive layer 208a is provided in the opening reaching the conductive layer 208a of transistor 851, and a conductive layer 818 connected to the conductive layer 208b of transistor 851 is provided in the opening reaching the conductive layer 208b of transistor 851.

[0508] Furthermore, insulating layers 206, 209, and 814 are provided with openings leading to conductive layer 205. Figure 44 shows an example where such openings overlap with the regions of conductive layer 205 that are separate from transistors 850 and 851. A conductive layer 819, serving as a through electrode, is provided within these openings and is connected to conductive layer 205.

[0509] Furthermore, insulating layers 202, 204, 206, 209, and 814 are provided with openings that respectively reach conductive layers 811, 812, and 818. A conductive layer 820 serving as a through electrode is provided in the opening reaching conductive layer 811, and conductive layer 820 is connected to conductive layer 811. A conductive layer 821 serving as a through electrode is provided in the opening reaching conductive layer 812, and conductive layer 821 is connected to conductive layer 812. A conductive layer 822 serving as a through electrode is provided in the opening reaching conductive layer 813, and conductive layer 822 is connected to conductive layer 813. Conductive layers 815 to 822 can be formed simultaneously using a single conductive layer having the same material and laminated structure as conductive layer 205 shown in the above embodiment.

[0510] Conductive layers 823 to 827 are disposed on the insulating layer 814. Conductive layer 823 is connected to conductive layer 819, conductive layer 824 is connected to conductive layer 820, conductive layer 825 is connected to conductive layer 815, conductive layer 826 is connected to conductive layers 816, 817, and 821, and conductive layer 827 is connected to conductive layers 818 and 822. Conductive layers 823 to 827 can be formed simultaneously using a single conductive layer having the same material and laminated structure as conductive layer 205 shown in the above embodiment.

[0511] An insulating layer 828 is provided on insulating layer 814, conductive layer 823, and conductive layer 827. Insulating layer 828 can be formed using the same material as insulating layer 202 and insulating layer 204 shown in the above embodiment. An opening is provided in insulating layer 828 leading to conductive layer 823. A conductive layer 829, serving as a through electrode, is provided in the opening leading to conductive layer 823. Conductive layer 829 can be made using the same material as conductive layer 205 shown in the above embodiment. A conductive layer 830 is provided on insulating layer 828. Conductive layer 830 is connected to conductive layer 829. Conductive layer 830 can be made using the same material as conductive layer 205 shown in the above embodiment.

[0512] An insulating layer 840 is provided on the insulating layer 828 and the conductive layer 830. The insulating layer 840 can be formed using the same material as the insulating layer 202 and insulating layer 204 shown in the above embodiment.

[0513] In addition, conductive layers 804, 808, 811, 820, and 824 have the function of wiring COM. As described above, in addition to the function of wiring COM, conductive layer 804 also functions as the second electrode of capacitor Cs[1] and the second electrode of capacitor Cs[2]. Furthermore, in FIG44, conductive layer 801, which serves as the first electrode of capacitor Cs[2], is provided with conductive layer 804, which serves as the second electrode of capacitor Cs[2] and wiring COM. Therefore, since conductive layer 804, which is supplied with a fixed potential, is provided between transistor 850 and conductive layer 801, the electric field from conductive layer 801 can be shielded by conductive layer 804, and the influence of potential fluctuations of conductive layer 801 on the electrical characteristics of transistor 850 can be suppressed. Similarly, conductive layer 802, which serves as the first electrode of capacitor Cs[1], is provided with conductive layer 804, which serves as the second electrode of capacitor Cs[1] and wiring COM. Therefore, since a conductive layer 804 with a fixed potential is provided between transistor 851 and conductive layer 802, the electric field from conductive layer 802 can be shielded by conductive layer 804, and the influence of potential fluctuations of conductive layer 802 on the electrical characteristics of transistor 851 can be suppressed.

[0514] Furthermore, conductive layers 205, 819, 823, 829, and 830 are used as wiring WWLs. In particular, the uppermost conductive layer 830 is disposed in a different layer from the conductive layers constituting transistors 850, 851, 400, capacitors Cs[1], and Cs[2], thus allowing for high layout flexibility and ensuring a large wiring width. Therefore, between multiple semiconductor devices 10A disposed in the same row, the conductive layer 830 with a large wiring width can be guided as a wiring WWL, thereby suppressing the potential drop caused by the wiring resistance of the wiring WWL. As a result, distortion of the signal input to the wiring WWL can be suppressed, thereby increasing the speed of writing data to the semiconductor device 10A or reducing the voltage of the signal required for writing data.

[0515] Furthermore, in Figure 44, capacitors Cs[1] and Cs[2] are disposed below transistors 850 and 851, and transistor 400 is disposed below capacitors Cs[1] and Cs[2]. By employing the above structure of stacking three elements, the layout area of ​​the semiconductor device 10A can be reduced. In addition, in the above structure, a larger spacing between the layer on which transistors 850 and 851 are disposed and the layer on which transistor 400 is disposed can be ensured compared to the case where capacitors Cs[1] and Cs[2] are disposed above transistors 850 and 851. Therefore, for example, when transistors 850 and 851 are OS transistors and transistor 400 is a Si transistor, hydrogen contained in the layer on which transistor 400 is disposed can be prevented from entering the layer on which transistors 850 and 851 are disposed.

[0516] <Examples of Planar and Stacked Structures of Memory Cells 3> Next, another example of the planar and stacked structure of the memory cells included in the memory device 300 will be described. As an example of the semiconductor device 10 used as a memory cell, FIG45 shows the planar structure of the semiconductor device 10B shown in FIG4A. FIG45 shows the layout of the conductive and semiconductor layers as viewed from the plane, and the positions of the openings (also called contact holes) provided in the insulating layer, but the insulating layer is not shown. In addition, FIG46 shows an example of a cross-sectional structure along the dotted line A1-A2 in FIG45. Note that, in order to avoid repetition, the description of the circuit structure of the semiconductor device 10B is omitted here.

[0517] In the semiconductor device 10B of this structural example, an insulating layer 861 is provided on a substrate 860, and a semiconductor layer 863, including a transistor 862 (equivalent to transistor M2), is provided on the insulating layer 861. The substrate 860 can be made of the same material as the substrate 201 shown in the above embodiment. Furthermore, the insulating layer 861 can be made of the same material as the insulating layer 202 shown in the above embodiment. In particular, to prevent impurities from the substrate 860 from diffusing into the semiconductor layer 863, materials such as silicon nitride, silicon oxide, silicon oxynitride, and silicon oxynitride can be used as materials for the insulating layer 861. Note that a single layer of the insulating layer with these materials as its main components can be used as the insulating layer 861, or a stack of multiple such insulating layers can be used as the insulating layer 861.

[0518] Note that in this structural example, the semiconductor elements included in the semiconductor device 10B, such as transistors and capacitors, are arranged on the substrate 860, but it is not necessary to set the substrate 860.

[0519] Furthermore, the semiconductor layer 863 can use the same material and stacked structure as the semiconductor layer 203 shown in the above embodiment. When polycrystalline silicon or monocrystalline silicon is used for the semiconductor layer 863, the on-state current of the transistor 862 can be increased, thus increasing the speed at which data can be read from the semiconductor device 10B.

[0520] Insulating layers 864, 865, 870, and 871 are sequentially stacked on semiconductor layer 863 and insulating layer 861. Insulating layer 864 functions as the gate insulating layer of transistor 862. Insulating layer 865 serves as an interlayer insulating layer. Insulating layers 864, 865, 870, and 871 can be formed using the same materials as insulating layers 202 and 204 shown in the above embodiment.

[0521] In particular, when silicon is used for semiconductor layer 863, it is preferable to use silicon nitride, silicon oxide, silicon oxynitride, silicon oxynitride, etc., as insulating layer 864, which serves as gate insulating layer, to make the electrical characteristics of transistor 862 more stable. Note that a single layer of insulating layer with these materials as the main components can be used as insulating layer 864, or a stack of multiple such insulating layers can be used as insulating layer 864.

[0522] Furthermore, in particular, organic insulating materials such as organic resins that are easy to planarize are preferably used as insulating layer 865. Examples of organic resins that can be used include polyimide resins, polyamide resins, acrylic resins, silicone resins, epoxy resins, and phenolic resins. Note that a single layer of the insulating layer with these materials as its main components can be used as insulating layer 865, or a stack of multiple such insulating layers can be used as insulating layer 864.

[0523] Furthermore, especially when oxide semiconductors are used as semiconductor layers 873 and 875, which will be described later, insulating layer 870 preferably functions to prevent impurities such as hydrogen from the underlying layer of insulating layer 870 from diffusing into semiconductor layers 873 and 875. Additionally, when oxide semiconductors are used for semiconductor layers 873 and 875, insulating layer 871 preferably functions to supply oxygen to semiconductor layers 873 and 875. In this case, inorganic insulating materials with hydrogen-blocking properties are preferably used as insulating layer 870, such as silicon nitride, silicon oxynitride, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, etc., which have higher hydrogen-blocking properties than silicon oxide; in other words, materials that do not easily allow hydrogen to diffuse. Note that a single layer of insulating layer with these materials as its main components can be used as insulating layer 870, or a stack of multiple such insulating layers can be used as insulating layer 870. Furthermore, as the insulating layer 871, it is preferable to use an inorganic insulating material that readily supplies oxygen to the semiconductor layers 873 and 875 formed on the upper layer and has a low relative permittivity, such as silicon oxide or silicon oxynitride. Note that a single layer of the insulating layer with these materials as the main components can be used as the insulating layer 871, or a stack of multiple such insulating layers can be used as the insulating layer 871.

[0524] At least two openings leading to the semiconductor layer 863 are provided in insulating layers 864, 865, 870, and 871. Conductive layers 866 and 895, respectively connected to the semiconductor layer 863, are provided in these openings. Specifically, conductive layers 866 and 895 are connected to the source or drain region of the semiconductor layer 863, respectively, and serve as the source or drain electrode of the transistor 862. Additionally, an opening leading to the insulating layer 864 is provided in insulating layers 865, 870, and 871, and a conductive layer 867 is provided in this opening. The conductive layer 867 has a region overlapping the semiconductor layer 863 across the insulating layer 864. Specifically, the conductive layer 867 has a region overlapping the channel forming region of the semiconductor layer 863 and serves as the gate electrode of the transistor 862. In other words, the region of the semiconductor layer 863 overlapping with the conductive layer 867 is used as the channel forming region. By forming a conductive layer having the same material and stacked structure as the conductive layer 205 shown in the above embodiment, and then processing the shape of the conductive layer by etching, CMP or the like, conductive layer 866, conductive layer 867 and conductive layer 895 can be formed simultaneously.

[0525] Furthermore, a semiconductor layer 873, including transistor 872 (equivalent to transistor M1[2]), and a semiconductor layer 875, including transistor 874 (equivalent to transistor M1[1]), are disposed on the insulating layer 871. Semiconductor layer 873 and semiconductor layer 875 can be formed simultaneously using a single semiconductor layer having the same material and stacked structure as the semiconductor layer 203 shown in the above embodiment. In particular, when oxide semiconductors are used as semiconductor layers 873 and 875, the off-state current of transistors 872 and 874 can be significantly reduced. Therefore, in the semiconductor device 10B, when transistors 872 and 874 are turned off while data written to node ND is retained, the charge held in node ND is less likely to decrease, thereby suppressing voltage drop at node ND for a long period. Therefore, data written to node ND can be retained for a long period. Furthermore, by including multiple capacitors Cs, the charge at node ND is even less likely to decrease. Therefore, voltage drop at node ND can be further suppressed.

[0526] Additionally, conductive layers 876 to 879 are disposed on insulating layer 871. Both conductive layers 876 and 877 have regions disposed on and connected to semiconductor layer 873. Conductive layers 876 and 877 are used as source or drain electrodes of transistor 872. Furthermore, both conductive layers 877 and 878 have regions disposed on and connected to semiconductor layer 875. Conductive layers 877 and 878 are used as source or drain electrodes of transistor 874. Conductive layer 878 has a region disposed on and connected to conductive layer 867. Conductive layer 879 has a region disposed on and connected to conductive layer 866. Conductive layers 879 and 866 are used as ground-level wiring (RWL). Conductive layer 880 has a region disposed on and connected to conductive layer 895. Conductive layers 876 to 880 can be formed simultaneously using a single conductive layer having the same material and stacked structure as conductive layer 205 shown in the above embodiment.

[0527] Furthermore, an insulating layer 881 is provided on semiconductor layers 873 and 875, as well as on conductive layers 876 to 880. Furthermore, conductive layers 882 to 885 are provided on the insulating layer 881. Conductive layers 882 to 885 can be formed using a single conductive layer having the same material and stacked structure as the conductive layer 205 shown in the above embodiment.

[0528] The conductive layer 882 has a region that overlaps with the semiconductor layer 873 through the insulating layer 881, and is used as the gate electrode and wiring WWLb of the transistor 872. The conductive layer 883 has a region that overlaps with the conductive layer 877 through the insulating layer 881. Furthermore, the region where the conductive layer 877, the insulating layer 881, and the conductive layer 883 overlap with each other is used as the capacitor Cs[2]. Specifically, the conductive layer 877 is used as the first electrode of the capacitor Cs[2], and the conductive layer 883 is used as the second electrode of the capacitor Cs[2]. The conductive layer 884 has a region that overlaps with the semiconductor layer 875 through the insulating layer 881, and is used as the gate electrode and wiring WWLa of the transistor 874. The conductive layer 885 has a region that overlaps with the conductive layer 878 through the insulating layer 881. Furthermore, the region where the conductive layer 878, the insulating layer 881, and the conductive layer 885 overlap with each other is used as the capacitor Cs[1]. Specifically, conductive layer 878 is used as the first electrode of capacitor Cs[1], and conductive layer 885 is used as the second electrode of capacitor Cs[1]. Therefore, insulating layer 881 is used as the gate insulating layer of transistors 872 and 874 and as the dielectric of capacitors Cs[1] and Cs[2].

[0529] The insulating layer 881 can be formed using the same material as the insulating layers 202 and 204 shown in the above embodiments. In particular, by using a material with a high relative permittivity (high-k), the electrostatic capacitance of capacitors Cs[1] and Cs[2] can be improved. Materials with a high relative permittivity (high-k) can include, for example, aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium. Note that a single layer of the insulating layer with these materials as its main components can be used as the insulating layer 881, or a stack of multiple such insulating layers can be used as the insulating layer 881.

[0530] Insulating layer 886, insulating layer 887, and insulating layer 888 are sequentially stacked on insulating layer 881 and conductive layers 882 to 885. Insulating layer 886, insulating layer 887, and insulating layer 888 can be formed using the same materials as insulating layer 202 and insulating layer 204 shown in the above embodiment.

[0531] In particular, when an oxide semiconductor is used for semiconductor layers 873 and 875, the insulating layer 886 preferably has the function of supplying oxygen to semiconductor layers 873 and 875. In this case, as the insulating layer 886, an inorganic insulating material that readily supplies oxygen to semiconductor layers 873 and 875 and has a low relative permittivity is preferably used, such as silicon oxide or silicon oxynitride. Note that a single layer of the insulating layer with these materials as its main components can be used as the insulating layer 886, or a stack of multiple such insulating layers can be used as the insulating layer 886.

[0532] Furthermore, the insulating layer 887 preferably has the function of preventing impurities such as hydrogen from the upper layer of the insulating layer 887 from diffusing to the semiconductor layer 873 and the semiconductor layer 875. In this case, as the insulating layer 887, an inorganic insulating material with hydrogen-blocking properties is preferably used, such as silicon nitride, silicon oxynitride, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, etc., which have higher hydrogen-blocking properties than silicon oxide; in other words, materials that do not easily allow hydrogen to diffuse. Note that a single layer of the insulating layer with these materials as the main components can be used as the insulating layer 887, or a stack of multiple such insulating layers can be used as the insulating layer 887.

[0533] In addition, when organic insulating materials such as organic resins that are easy to planarize are used as the insulating layer 888, polyimide resins, polyamide resins, acrylic resins, silicone resins, epoxy resins, phenolic resins, etc. can be used.

[0534] Additionally, conductive layers 889, 890, and 891 are provided on insulating layer 888. Conductive layer 889 is connected to conductive layer 876 through openings 892 provided in insulating layers 881 and 886 to 888. Conductive layers 876 and 889 are used as wiring WBL. Conductive layer 890 is connected to conductive layer 883 through openings 893 provided in insulating layers 886 to 888. Conductive layer 890 is also connected to conductive layer 885 through openings 894 provided in insulating layers 886 to 888. Conductive layers 890, 883, and 885 are used as wiring COM. Conductive layer 891 is connected to conductive layer 880 through openings 896 provided in insulating layers 881 and 886 to 888. Conductive layers 891, 880, and 895 are used as wiring RBL. Conductive layers 889, 890, and 891 can be formed simultaneously using a single conductive layer having the same material and stacked structure as conductive layer 205 as shown in the above embodiment.

[0535] Insulating layer 899 is provided on insulating layer 888, conductive layer 889, conductive layer 890 and conductive layer 891. Insulating layer 899 can be formed of the same material as insulating layer 202 and insulating layer 204 shown in the above embodiment.

[0536] Note that in this structural example, an example of the planar structure and stacked structure of the semiconductor device 10B shown in FIG4A is shown. However, when this structural example is applied to the semiconductor device 10A shown in FIG1A, conductive layer 882 and conductive layer 884 are connected inside or outside the cell array.

[0537] In this structural example, the conductive layer 889 used as the wiring WBL is disposed in a different layer than the conductive layers constituting transistors 872, 874, 862, capacitors Cs[1], and Cs[2], thus allowing for high layout freedom and ensuring a large wiring width. Therefore, by guiding the conductive layer 889 as the wiring WBL between multiple semiconductor devices 10B disposed in the same column, the potential drop caused by the wiring resistance of the wiring WBL can be suppressed. As a result, the speed of writing data to the semiconductor devices 10B can be improved.

[0538] Furthermore, in this structural example, the conductive layer 891 used as the wiring RBL is disposed in a different layer than the conductive layers constituting transistors 872, 874, 862, capacitors Cs[1], and Cs[2], thus allowing for high layout freedom and ensuring a large wiring width. Therefore, by guiding the conductive layer 891 as the wiring RBL between multiple semiconductor devices 10B disposed in the same column, the potential drop caused by the wiring resistance of the wiring RBL can be suppressed. As a result, when reading data from the semiconductor device 10B, the potential change of the wiring RBL can be made rapid, thus improving the data readout speed.

[0539] <Examples of Planar and Stacked Structures of Memory Cells 4> Next, another example of the planar and stacked structure of the memory cells included in the memory device 300 will be described. As an example of the semiconductor device 10 used as a memory cell, FIG. 47 shows an example of the planar structure of the semiconductor device 10A shown in FIG. 1A. FIG. 47 shows the layout of the conductive and semiconductor layers as viewed from a planar perspective, and the positions of the openings (also called contact holes) provided in the insulating layer, but does not show the insulating layer. Additionally, FIG. 48 shows an example of a cross-sectional structure along the dotted line B1-B2 in FIG. 47. Note that, to avoid repetition, the description of the circuit structure of the semiconductor device 10A is omitted here.

[0540] In the semiconductor device 10A of this structural example, an insulating layer 951 is provided on a substrate 950, and a semiconductor layer 953, including a transistor 952 (equivalent to transistor M2), is provided on the insulating layer 951. The substrate 950 can be made of the same material as the substrate 201 shown in the above embodiment. Furthermore, the material and stacked structure of the insulating layer 951 can be found in the description of the insulating layer 861 in the above embodiment. The material and stacked structure of the semiconductor layer 953 can also be found in the description of the semiconductor layer 953 in the above embodiment.

[0541] Note that in this structural example, the semiconductor elements included in the semiconductor device 10A, such as transistors and capacitors, are arranged on the substrate 950, but it is not necessary to set the substrate 950.

[0542] An insulating layer 904 is disposed on the semiconductor layer 953 and the insulating layer 951, and a conductive layer 908 having a region overlapping with the semiconductor layer 953 is disposed on the insulating layer 904. Specifically, the conductive layer 908 has a region overlapping with the channel formation region of the semiconductor layer 953 and is used as the gate electrode of the transistor 952. The region of the semiconductor layer 953 that overlaps with the conductive layer 908 is used as the channel formation region. In addition, insulating layers 905, 906, and 907 are sequentially stacked on the insulating layer 904 and the semiconductor layer 953. The materials and stacking structures of the insulating layers 904, 905, 906, and 907 can be referred to the description of the insulating layers 864, 865, 870, and 871 in the above embodiments.

[0543] At least two openings leading to the semiconductor layer 953 are provided in insulating layers 904, 905, 906, and 907. Each of these openings contains a conductive layer 909 and a conductive layer 910 connected to the semiconductor layer 953. Specifically, the conductive layer 909 and the conductive layer 910 are connected to the source region or drain region of the semiconductor layer 953, respectively, and are used as the source electrode or drain electrode of the transistor 952. Additionally, an opening leading to the conductive layer 908 is provided in insulating layers 905, 906, and 907. A conductive layer 961 connected to the conductive layer 908 is provided in this opening. By forming a conductive layer having the same material and stacked structure as the conductive layer 205 shown in the above embodiment, and then processing the shape of the conductive layer using etching, CMP, or the like, conductive layers 909, 910, and 961 can be formed simultaneously.

[0544] In addition, a semiconductor layer 935 is provided on the insulating layer 907, including a channel forming region of transistor 913 (equivalent to transistor M1[2]) and a channel forming region of transistor 914 (equivalent to transistor M1[1]). The material and stacked structure of the semiconductor layer 935 can be referred to the description of semiconductor layer 873 and semiconductor layer 875.

[0545] Furthermore, an insulating layer 915 is provided on the semiconductor layer 935, and insulating layers 916 and 917 are provided on the insulating layer 907. Additionally, a conductive layer 918 is provided on the insulating layer 915, having a region overlapping the insulating layer 915 and the semiconductor layer 935. The conductive layer 918 serves as the gate electrode of transistor 913, the gate electrode of transistor 914, and the WWL wiring. Furthermore, a conductive layer 919 is provided on the insulating layer 916, and a conductive layer 920 is provided on the insulating layer 917. The conductive layers 918 to 920 can be formed using a single conductive layer having the same material and stacked structure as the conductive layer 205 shown in the above embodiment.

[0546] Alternatively, by forming an insulating layer having the same material and stacked structure as the insulating layer 202 shown in the above embodiment, and then processing the shape of the insulating layer using etching or the like, insulating layers 915, 916, and 917 can be formed simultaneously. Insulating layer 915 is used as the gate insulating layer for transistors 913 and 914. Note that in this structural example, insulating layers 915, 916, and 917 are shown as separate insulating layers, but insulating layers 915, 916, and 917 can also be a continuous single insulating layer.

[0547] Furthermore, an insulating layer 921 is disposed on the semiconductor layer 935, insulating layers 915 to 917, and conductive layers 918 to 920. Conductive layers 922 to 926 are disposed on the insulating layer 921. Conductive layers 922 to 926 can be formed using a single conductive layer having the same material and stacked structure as the conductive layer 205 shown in the above embodiment. Conductive layer 922 is connected to the semiconductor layer 935 through an opening 927 in the insulating layer 921, conductive layer 923 is connected to the semiconductor layer 935 through an opening 928 in the insulating layer 921, and conductive layer 924 is connected to the semiconductor layer 935 through an opening 929 in the insulating layer 921. Conductive layers 922 and 923 are used as the source or drain electrodes of transistor 913. Furthermore, conductive layers 923 and 924 are used as the source or drain electrodes of transistor 914.

[0548] Additionally, conductive layer 924 is connected to conductive layer 961 through opening 975 provided in insulating layer 921. Conductive layer 924 has a region that overlaps with conductive layer 919 across insulating layer 921. The region where conductive layer 919, insulating layer 921 and conductive layer 924 overlap is used as capacitor Cs[1]. Specifically, conductive layer 924 is used as the first electrode of capacitor Cs[1], conductive layer 919 is used as the second electrode of capacitor Cs[1], and insulating layer 921 is used as the dielectric of capacitor Cs[1]. Additionally, conductive layer 923 has a region that overlaps with conductive layer 919 across insulating layer 921. The region where conductive layer 919, insulating layer 921 and conductive layer 923 overlap is used as capacitor Cs[2]. Specifically, conductive layer 923 is used as the first electrode of capacitor Cs[2], conductive layer 919 is used as the second electrode of capacitor Cs[2], and insulating layer 921 is used as the dielectric of capacitor Cs[2]. The material and stacked structure of the insulating layer 921 can be referenced from the description of the insulating layer 881 in the above embodiment.

[0549] The conductive layer 925 is connected to the conductive layer 909 through an opening 931 provided in the insulating layer 921. Additionally, the conductive layer 925 is connected to the conductive layer 920 through an opening 932 provided in the insulating layer 921. The conductive layers 909, 925, and 920 are in a conductive state and are used as a wiring RWL.

[0550] The conductive layer 926 is connected to the conductive layer 910 through an opening 933 provided in the insulating layer 921.

[0551] An insulating layer 940 is provided on insulating layer 921 and conductive layers 922 to 926. Insulating layer 940 serves as an interlayer insulating layer, and preferably uses an organic insulating material such as an organic resin that is easy to planarize. The material and stacking structure of insulating layer 940 can be referenced from the description of insulating layer 865 in the above embodiment.

[0552] Additionally, conductive layers 941 and 942 are provided on the insulating layer 940. Conductive layer 941 is connected to conductive layer 922 through an opening 944 in the insulating layer 940. Conductive layers 941 and 922 are used as wiring WBL. Conductive layer 942 is connected to conductive layer 926 through an opening 945 in the insulating layer 940. Conductive layers 942, 926, and 910 are used as wiring RBL. Conductive layers 941 and 942 can be formed simultaneously using a single conductive layer having the same material and stacked structure as the conductive layer 205 shown in the above embodiment.

[0553] An insulating layer 943 is provided on the insulating layer 940, conductive layer 941, and conductive layer 942. The insulating layer 943 can be formed of the same material as the insulating layer 202 and insulating layer 204 shown in the above embodiment.

[0554] In this structural example, the conductive layer 941 used as the wiring WBL is disposed in a different layer than the conductive layers constituting transistors 913, 914, 952, capacitors Cs[1], and Cs[2], thus allowing for high layout freedom and ensuring a large wiring width. Therefore, by guiding the conductive layer 941 as the wiring WBL between multiple semiconductor devices 10A disposed in the same column, the potential drop caused by the wiring resistance of the wiring WBL can be suppressed. As a result, the data writing speed to the semiconductor devices 10A can be improved.

[0555] Furthermore, in this structural example, the conductive layer 942 used as the wiring RBL is disposed in a different layer than the conductive layers constituting transistors 913, 914, 952, capacitors Cs[1], and Cs[2], thus allowing for high layout freedom and ensuring a large wiring width. Therefore, by guiding the conductive layer 942 as the wiring RBL between multiple semiconductor devices 10A disposed in the same column, the potential drop caused by the wiring resistance of the wiring RBL can be suppressed. As a result, when reading data from the semiconductor device 10A, the potential change of the wiring RBL can be rapid, thus improving the data readout speed.

[0556] This embodiment can be implemented by appropriately combining the structures described in other embodiments, etc.

[0557] (Embodiment 5) In this embodiment, an example of an arithmetic processing device that may include a semiconductor device 10 or a storage device 300 will be described.

[0558] Figure 32 shows a block diagram of the computing device 960. The computing device 960 shown in Figure 32 can be used, for example, as a CPU. Alternatively, the computing device 960 can also be applied to processors such as GPUs (Graphics Processing Units), TPUs (Tensor Processing Units), and NPUs (Neural Processing Units), which have multiple (tens to hundreds) processor cores capable of parallel processing compared to CPUs.

[0559] The arithmetic unit 960 shown in Figure 32 includes, on a substrate 990: an ALU 991 (ALU: Arithmetic Logic Unit); an ALU controller 992; an instruction decoder 993; an interrupt controller 994; a timing controller 995; a register 996; a register controller 997; a bus interface 998; a cache 999; and a cache interface 989. The substrate 990 may be a semiconductor substrate, an SOI substrate, a glass substrate, etc. The arithmetic unit 960 may also include a rewritable ROM and a ROM interface. The cache 999 and the cache interface 989 may also be located on different chips.

[0560] The cache 999 is connected to the main memory, which is located on a different chip, via a cache interface 989. The cache interface 989 has the function of supplying a portion of the data held in the main memory to the cache 999. Additionally, the cache interface 989 has the function of outputting a portion of the data held in the cache 999 to the ALU 991 or register 996, etc., via a bus interface 998.

[0561] As described later, the memory cell array 310 can be arranged in a manner that is stacked on the computing device 960. The memory cell array 310 can be used as a cache. In this case, the cache interface 989 can have the function of supplying data held in the memory cell array 310 to the cache 999. In addition, it is preferable that a portion of the cache interface 989 includes a drive circuit 21 for driving the memory cell array 310. The drive circuit 21 for driving the memory cell array 310 can be provided in the computing device 960.

[0562] Note that it is also possible to not set cache 999 and use only storage cell array 310 as a cache.

[0563] The computing device 960 shown in Figure 32 is merely a simplified example, and the actual computing device 960 has various structures depending on its application. For example, it is preferable to use a multi-core structure, including multiple cores and operating them simultaneously, with the structure of the computing device 960 shown in Figure 32 as a single core. The more cores, the better the computing performance. More cores are preferred; for example, 2 cores are preferred, more preferably 4 cores, further preferably 8 cores, even more preferably 12 cores, and even more preferably 16 cores or more. In addition, when used in servers or other applications requiring very high computing performance, a multi-core structure with 16 or more cores is preferred, preferably 32 or more cores, and more preferably 64 or more cores. Furthermore, the number of bits that can be processed in the internal computing circuitry, data bus, etc., of the computing device 960 can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0564] Instructions input to the arithmetic unit 960 via the bus interface 998 are input to the instruction decoder 993 and decoded before being input to the ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995.

[0565] The ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995 perform various controls based on the decoded instructions. Specifically, the ALU controller 992 generates signals to control the operation of the ALU 991. Furthermore, when executing the program of the arithmetic unit 960, the interrupt controller 994 determines and processes interrupt requests from external input / output devices, peripheral circuits, etc., based on their priority, mask state, etc. The register controller 997 generates the address of register 996 and reads or writes register 996 according to the state of the arithmetic unit 960.

[0566] In addition, the timing controller 995 generates signals to control the operating timing of the ALU 991, ALU controller 992, instruction decoder 993, interrupt controller 994, and register controller 997. For example, the timing controller 995 has an internal clock generation unit that generates an internal clock signal based on a reference clock signal and supplies the internal clock signal to the aforementioned circuits.

[0567] In the arithmetic unit 960 shown in Figure 32, the register controller 997 selects the holding operation of register 996 according to instructions from ALU 991. In other words, the register controller 997 selects whether data is held in the memory cell of register 996 by flip-flops or by capacitors. When data is held by flip-flops, power is supplied to the memory cell of register 996. When data is held by capacitors, the data is overwritten to the capacitors, and power supply to the memory cell of register 996 can be stopped.

[0568] Figure 33 shows an example in which, in addition to the aforementioned arithmetic device 960, a storage device 962, an interface circuit 964, and an input / output unit 966 are also provided on the substrate 990.

[0569] Storage device 962 can be used as a cache or main memory subordinate to cache 999. Storage device 962 is connected to cache interface 989 within arithmetic unit 960 via interface circuit 964. Furthermore, storage device 962 is connected to main memory located on different chips via interface circuit 964 and input / output unit 966.

[0570] The storage device 962 may be a storage device 300 including the storage cell array 310 described above.

[0571] The interface circuit 964 is equipped with various interface circuits and buses. In addition, the interface circuit 964 may also have power supply circuits, clock generation circuits, etc.

[0572] In the interface circuit 964, for example, I2C (Inter Integrated Circuit), SPI (Serial Peripheral Interface), GPIO (General Purpose Input / Output) can be configured.

[0573] The input / output section 966 includes an input section for receiving signals, potentials, etc. from the outside, and an output section for outputting signals to the outside. The input / output section 966 is provided with multiple connection terminals and is connected to a substrate different from the substrate 990 via connection wiring. Additionally, the input / output section 966 may also include buffer circuits, protection circuits, etc.

[0574] As a method for connecting substrate 990 to other substrates, the following can be used: wire bonding using gold or copper wiring; flip-chip bonding using bumps; or direct bonding (hybrid bonding) using direct bonding techniques such as Cu-Cu bonding. Alternatively, as a method of bonding without using a substrate, a method can be used to connect electrodes disposed in each layer by forming through electrodes after bonding two or more layers together with an insulating film. In particular, by using direct bonding or through electrodes, the spacing between the connecting electrodes can be extremely narrow, so a large number of connecting electrodes can be arranged at a high density, thereby increasing the data transmission capacity between layers, which is preferred.

[0575] The memory cell array 310 and the arithmetic unit 960 can be arranged overlappingly. Figures 34A and 34B show perspective views of the semiconductor device 970A. The semiconductor device 970A includes a layer 930 on the arithmetic unit 960, on which the memory cell arrays are disposed. The layer 930 is provided with memory cell arrays 310L1, 310L2, and 310L3. The arithmetic unit 960 and each memory cell array have overlapping areas. To facilitate understanding of the structure of the semiconductor device 970A, Figure 34B shows the arithmetic unit 960 and the layer 930 separately.

[0576] By overlapping the layer 930, which includes the memory cell array, and the computing device 960, the connection distance between them can be shortened. This improves the communication speed between them. Furthermore, the shorter connection distance reduces power consumption.

[0577] As a method for stacking a layer 930 with a memory cell array and a computing device 960, one can directly stack the layer 930 with the memory cell array on the computing device 960 (also known as monolithic stacking), or one can form the computing device 960 and the layer 930 on different substrates respectively, and connect the two substrates by using bonding techniques such as through-holes or conductive films (Cu-Cu bonding, etc.). The former method does not require consideration of misalignment during bonding, thus reducing both chip size and manufacturing cost.

[0578] Here, the storage cell arrays 310L1, 310L2, and 310L3 disposed in layer 930, excluding cache 999, can all be used as caches. For example, storage cell arrays 310L1, 310L2, and 310L3 can be used as L1 cache (also called Level 1 cache), L2 cache (also called Level 2 cache), and L3 cache (also called Level 3 cache), respectively. Among the three storage cell arrays, storage cell array 310L3 has the largest capacity and the lowest access frequency. Conversely, storage cell array 310L1 has the smallest capacity and the highest access frequency.

[0579] Note that when the cache 999 in the arithmetic unit 960 is used as an L1 cache, the memory cell arrays in layer 930 can be used as lower-level caches or main memory. Main memory is memory with a larger capacity and lower access frequency than cache.

[0580] Additionally, as shown in Figure 34B, drive circuits 21L1, 21L2, and 21L3 are provided. Drive circuit 21L1 is connected to the memory cell array 310L1 via a connection electrode 940L1. Similarly, drive circuit 21L2 is connected to the memory cell array 310L2 via a connection electrode 940L2, and drive circuit 21L3 is connected to the memory cell array 310L3 via a connection electrode 940L3.

[0581] Note that although the case shown here is a three-cell storage array used as a cache, the number of storage arrays used as a cache can be one, two, or more than four.

[0582] When the memory cell array 310L1 is used as a cache, the drive circuit 21L1 can also be used as part of the cache interface 989 or connected to the cache interface 989. Similarly, the drive circuits 21L2 and 21L3 can also be used as part of the cache interface 989 or connected to a part of the cache interface 989.

[0583] Whether the memory cell array 310 is used as a cache or as main memory depends on the control circuit 32 included in each drive circuit 21. The control circuit ...

Claims

1. A semiconductor device, comprising: First transistor to third transistor; First capacitor; The semiconductor device includes: a first layer on which the third transistor is disposed; and a second layer having a region disposed above the first layer and on which the first transistor, the second transistor, the first capacitor, and the second capacitor. The first terminal of the first transistor is electrically connected to a first electrode of the first capacitor and to the gate of the third transistor. The second terminal of the second transistor is electrically connected to a second terminal of the first transistor and to the first electrode of the second capacitor. The second electrode of the first capacitor and the second capacitor are electrically connected to a first wiring supplied with a first potential. The semiconductor device includes: a first layer on which the third transistor is disposed; and a second layer having a region disposed above the first layer and on which the first transistor, the second transistor, the first capacitor, and the second capacitor are disposed. The second layer includes: a first conductive layer serving as a first electrode of the first capacitor; a second conductive layer serving as a first electrode of the second capacitor; and a third conductive layer serving as a second electrode of the first capacitor and a second electrode of the second capacitor. The third conductive layer has a region disposed above the first conductive layer and a region disposed above the second conductive layer. The channel forming region of the first transistor has a region overlapping the first conductive layer across the third conductive layer, and the channel forming region of the second transistor has a region overlapping the second conductive layer across the third conductive layer.

2. The semiconductor device of claim 1, wherein both the first transistor and the second transistor contain an oxide semiconductor in the channel formation region.

3. The semiconductor device of claim 1, wherein the gates of the first transistor and the second transistor are electrically connected to each other.

4. The semiconductor device of claim 1, wherein the third transistor comprises silicon in the channel formation region.

5. A storage device, comprising: Includes a memory cell array of multiple semiconductor devices as described in claims 1 to 4; And peripheral circuitry that has the function of writing data to the storage cell array and reading data from the storage cell array.

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