High-voltage side current detection circuit and system based on potential translation

Abstract

The invention relates to the technical field of electronic measurement, in particular to a high-voltage side current detection circuit and system based on potential translation, which can translate high common-mode voltage borne by two ends of a sampling resistor to a safe low common-mode voltage domain without distortion by using a current mirror. A subsequent signal extraction and amplification module does not need to directly bear a high common-mode voltage, so that the withstand voltage limitation of a traditional special detection chip is broken through, hundreds of volts or even higher common-mode voltage endurance capability can be realized only by selecting an external resistor with a proper withstand voltage level, and the adoption of a special current detection and amplification chip with high manufacturing cost is avoided; and the circuit cost is obviously reduced. Besides, the influence of transistor parameter drift in a current mirror of the potential translation module appears in a common mode form in a differential signal path, and can be effectively suppressed by a subsequent signal extraction amplification module with a high common mode rejection ratio, so that the overall detection precision and temperature stability of the system are guaranteed while high withstand voltage is realized.

Description

Technical Field

[0001] This invention relates to the field of electronic measurement technology, and in particular to a high-voltage side current detection circuit and system based on potential shift. Background Technology

[0002] In power electronic systems, accurate detection of load current is crucial for achieving precise system control, reliable protection, and condition monitoring. Among numerous current sensing technologies, the high-voltage side current sensing scheme, which places the sampling resistor between the positive terminal of the power supply and the load, is widely used in various industrial and consumer electronics circuits due to its advantages such as not disrupting the grounding path and effectively detecting open-circuit faults in the load.

[0003] However, in existing high-voltage side current sensing schemes, the differential signal across the sampling resistor is typically very weak and completely submerged by a common-mode voltage that is extremely high relative to the system ground potential. Therefore, accurately extracting the useful differential signal from the high common-mode voltage becomes a challenge in current sensing. Current technologies primarily rely on dedicated high-voltage side current sensing amplifiers to address this problem (such as the TI INA240 series chips). These dedicated chips use internally integrated precision circuitry to suppress the effects of high common-mode voltage, thereby amplifying and measuring the current.

[0004] For the aforementioned dedicated chips, when facing higher requirements or special application scenarios, the common-mode voltage input range of these chips is typically limited to around 60V to 100V due to the voltage withstand capability of semiconductor devices. This makes them unsuitable for applications requiring voltages exceeding 100V, such as industrial motor drives and electric vehicle main drives. Secondly, to achieve high common-mode rejection ratio (CMRR) and low offset voltage, these chips often require complex processes such as laser trimming during manufacturing, leading to high manufacturing costs and increasing the overall cost of the current sensing system. Furthermore, existing dedicated current sensing amplifier chips have fixed voltage withstand specifications and gain settings, lacking flexibility and unable to adapt to diverse application requirements. Therefore, there is an urgent need in the field to develop a high-voltage side current sensing solution that can overcome existing voltage withstand limitations, is cost-effective, and offers superior performance, thus addressing the shortcomings of existing technologies. Summary of the Invention

[0005] The present invention aims to provide a high-voltage side current detection circuit and system based on potential shift, so as to provide a high-voltage side current detection solution with high withstand voltage, low cost and excellent performance, and to solve the shortcomings of existing high-voltage side current detection technology.

[0006] To achieve the above objectives, a first aspect of the present invention provides a high-voltage side current detection circuit based on potential shifting, comprising a sampling resistor, a potential shifting module, and a signal extraction and amplification module, wherein: The sampling resistor is positioned on the high-voltage side between the external power supply and the external load. The potential shifting module is used to shift the sampling voltage potential across the sampling resistor to the second input terminal and the first input terminal of the signal extraction and amplification module using the current mirror principle; The signal extraction and amplification module is used to extract and amplify the potential signals received by the second input terminal and the first input terminal to obtain the output voltage, and to perform current detection based on the output voltage.

[0007] The aforementioned high-voltage side current detection circuit based on potential shifting utilizes a current mirror structure implemented through specific resistors and transistors in the potential shifting module. This current mirror can distortionlessly shift the high common-mode voltage across the sampling resistor to a safe low common-mode voltage domain. This design eliminates the need for the subsequent signal extraction and amplification module to directly withstand the high common-mode voltage, thus overcoming the voltage withstand limitations of traditional dedicated detection chips. Hundreds of volts or even higher common-mode voltage withstand capabilities can be achieved simply by selecting an external resistor with an appropriate voltage rating. Furthermore, this circuit avoids the use of expensive dedicated current detection and amplification chips, consisting only of conventional discrete components, significantly reducing circuit costs. Moreover, since the influence of transistor parameter drift in the current mirror of the potential shifting module appears in common-mode form in the differential signal path, it can be effectively suppressed by the subsequent high common-mode rejection ratio signal extraction and amplification module. This ensures both high voltage withstand capability and overall system detection accuracy and temperature stability.

[0008] Further, the potential shifting module includes a first resistor, a second resistor, a third resistor, a first NPN transistor, a second NPN transistor, and a third NPN transistor, wherein: The first end of the first resistor is electrically connected to the load end of the sampling resistor, and the second end of the first resistor is electrically connected to the collector of the first NPN transistor. The first end of the second resistor is electrically connected to the load end of the sampling resistor, and the second end of the second resistor is electrically connected to the collector of the second NPN transistor. The first end of the third resistor is electrically connected to the power supply terminal of the sampling resistor, and the second end of the third resistor is electrically connected to the collector of the third NPN transistor. The collector and base of the first NPN transistor are electrically connected, and the emitter of the first NPN transistor is grounded. The collector of the second NPN transistor is electrically connected to the second input terminal of the signal extraction and amplification module, the base of the second NPN transistor is electrically connected to the base of the first NPN transistor, and the emitter of the second NPN transistor is grounded. The collector of the third NPN transistor is electrically connected to the first input terminal of the signal extraction and amplification module, the base of the third NPN transistor is electrically connected to the base of the first NPN transistor, and the emitter of the third NPN transistor is grounded. In this implementation, a highly symmetrical current mirror system is formed by connecting the collector and base of the first NPN transistor to establish a reference current branch, and connecting the bases of the second and third NPN transistors to the base of the first NPN transistor. The current mirror ensures that the current flowing through the second and third resistors can accurately mirror the reference current flowing through the first resistor. Since the resistance values ​​of the first, second, and third resistors are set to be strictly equal, the voltage drop across the second resistor is equal to the voltage drop across the first resistor, and the voltage drop across the third resistor is also equal to the voltage drop across the first resistor.

[0009] This characteristic allows the original differential voltage between the sampling resistor load terminal and the power supply terminal to be losslessly reproduced between the collectors of the second and third NPN transistors, i.e., between the second and first input terminals of the signal extraction and amplification module. The accuracy of the entire potential shifting process depends primarily on the matching accuracy of the three resistors and the consistency of the characteristics of the three transistors. The inherent parameters of the transistors, such as the emitter junction, and their temperature drift exhibit the same common-mode variation in each branch, and will not affect the accuracy of the shifted differential signal.

[0010] Meanwhile, the high common-mode voltage applied to the sampling resistor is entirely borne by the first, second, and third resistors. The overall common-mode withstand voltage capability of the system is determined by the withstand voltage values ​​of these external resistors. Thus, the withstand voltage range can be easily extended by selecting high-voltage resistors, achieving high-precision, high-voltage potential shifting function with a simple and low-cost discrete component solution.

[0011] Furthermore, the potential shifting module includes a first resistor, a second resistor, a third resistor, a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor, wherein: The first end of the first resistor is electrically connected to the load end of the sampling resistor, and the second end of the first resistor is electrically connected to the drain of the first NMOS transistor. The first end of the second resistor is electrically connected to the load end of the sampling resistor, and the second end of the second resistor is electrically connected to the drain of the second NMOS transistor. The first end of the third resistor is electrically connected to the power supply terminal of the sampling resistor, and the second end of the third resistor is electrically connected to the drain of the third NMOS transistor. The drain and gate of the first NMOS transistor are electrically connected, and the source of the first NMOS transistor is grounded. The drain of the second NMOS transistor is electrically connected to the second input terminal of the signal extraction and amplification module, the gate of the second NMOS transistor is electrically connected to the gate of the first NMOS transistor, and the source of the second NMOS transistor is grounded. The drain of the third NMOS transistor is electrically connected to the first input terminal of the signal extraction and amplification module, the gate of the third NMOS transistor is electrically connected to the gate of the first NMOS transistor, and the emitter of the third NMOS transistor is grounded.

[0012] In this implementation, a current mirror system based on an NMOS device is formed by connecting the drain and gate of the first NMOS transistor to establish a reference current branch, and connecting the gates of the second and third NMOS transistors to the gate of the first NMOS transistor. This current mirror connection ensures that the current flowing through the second and third resistors accurately mirrors the reference current flowing through the first resistor. Since the resistance values ​​of the first, second, and third resistors are set to be strictly equal, the voltage drop across the second resistor is equal to the voltage drop across the first resistor, and the voltage drop across the third resistor is also equal to the voltage drop across the first resistor.

[0013] This characteristic allows the original differential voltage between the sampling resistor load terminal and the power supply terminal to be accurately reproduced between the drains of the second and third NMOS transistors, i.e., the two input terminals of the signal extraction and amplification module. The accuracy of the entire potential shifting process depends primarily on the matching accuracy of the three resistors and the consistency of the characteristics of the three NMOS transistors, providing a feasible solution for implementation using MOS technology.

[0014] Meanwhile, the high common-mode voltage applied to the sampling resistor is entirely borne by the first, second, and third resistors. The overall common-mode withstand voltage capability of the system is determined by the withstand voltage values ​​of these external resistors, thus extending the withstand voltage range by selecting high-voltage resistors. This implementation, based on an NMOS transistor, provides a discrete component implementation method for constructing a high-precision, high-voltage-resistance potential shifting module, distinct from NPN transistors.

[0015] Furthermore, the signal extraction and amplification module includes a first operational amplifier, a fourth resistor, a fifth resistor, a sixth resistor, and a seventh resistor, wherein: The first end of the fourth resistor serves as the second input terminal of the signal extraction and amplification module, and the second end of the fourth resistor is electrically connected to the inverting input terminal of the first operational amplifier. The first end of the fifth resistor is electrically connected to the inverting input terminal of the first operational amplifier, and the second end of the fifth resistor is electrically connected to the output terminal of the first operational amplifier. The first end of the sixth resistor serves as the first input terminal of the signal extraction and amplification module, and the second end of the sixth resistor is electrically connected to the non-inverting input terminal of the first operational amplifier. The first terminal of the seventh resistor is electrically connected to the non-inverting input terminal of the first operational amplifier, and the second terminal of the seventh resistor is grounded. The output terminal of the first operational amplifier is used to output the output voltage.

[0016] In this implementation, the first operational amplifier, together with the fourth, fifth, sixth, and seventh resistors, constitutes a differential amplifier circuit. This circuit effectively converts the differential voltage signal output from the potential shift module, existing between its second and first input terminals, into a single-ended output voltage signal referenced to the system ground potential. By appropriately setting the resistance ratios of the fourth, fifth, sixth, and seventh resistors, the gain of the differential amplifier can be easily adjusted, thus flexibly adapting to current detection requirements of different ranges.

[0017] The circuit structure described above utilizes the high input impedance and low output impedance characteristics of operational amplifiers to ensure output voltage stability and driving capability while amplifying the signal. Since the pre-amplifier level shifting module effectively isolates the common-mode voltage on the high-voltage side, the common-mode level of the signal reaching the input of this differential amplifier is within a low-voltage safe range. Therefore, the first operational amplifier can be a common general-purpose operational amplifier, without needing to withstand high common-mode voltage or possess extremely high common-mode rejection ratio characteristics, significantly reducing the performance requirements and cost of the core amplification components.

[0018] Furthermore, by selecting matching resistor pairs, such as making the fourth resistor and the sixth resistor equal in value, or making the fifth resistor and the seventh resistor equal in value, the common-mode rejection capability of the differential amplifier circuit can be optimized, further suppressing common-mode noise from the preceding stage or the environment, thereby improving the accuracy and anti-interference capability of the entire current sensing system.

[0019] Furthermore, the signal extraction and amplification module includes a second operational amplifier, a third operational amplifier, a fourth operational amplifier, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, and a fourteenth resistor, wherein: The non-inverting input of the second operational amplifier serves as the second input of the signal extraction and amplification module, and the inverting input of the second operational amplifier is electrically connected to the first end of the fourteenth resistor. The non-inverting input terminal of the third operational amplifier serves as the first input terminal of the signal extraction and amplification module, and the inverting input terminal of the third operational amplifier is electrically connected to the second terminal of the fourteenth resistor. The twelfth resistor is connected in parallel to the inverting input and output of the second operational amplifier, and the thirteenth resistor is connected in parallel to the inverting input and output of the third operational amplifier. The first end of the eighth resistor is electrically connected to the output terminal of the second operational amplifier, and the second end of the eighth resistor is electrically connected to the inverting input terminal of the fourth operational amplifier. The first end of the ninth resistor is electrically connected to the inverting input terminal of the fourth operational amplifier, and the second end of the ninth resistor is electrically connected to the output terminal of the fourth operational amplifier. The first end of the tenth resistor is electrically connected to the output terminal of the third operational amplifier, and the second end of the tenth resistor is electrically connected to the non-inverting input terminal of the fourth operational amplifier. The first terminal of the eleventh resistor is electrically connected to the non-inverting input terminal of the fourth operational amplifier, and the second terminal of the eleventh resistor is grounded. The output terminal of the fourth operational amplifier is used to output the output voltage.

[0020] In this implementation, the second, third, and fourth operational amplifiers, along with the eighth to fourteenth resistors, together constitute an instrumentation amplifier circuit, serving as the signal extraction and amplification module. This circuit structure provides extremely high input impedance, completely eliminating the shunting effect of the back-end circuit input impedance on the front-end potential shifting module and improving the sampling accuracy of current detection.

[0021] Specifically, the non-inverting inputs of the second and third operational amplifiers directly serve as the input ports of the signal extraction and amplification module. Because it operates in a deep negative feedback state, the input bias current drawn from the current mirror output node of the potential shift module is extremely small, thus completely avoiding any disturbance to the operating point of the pre-stage precision current mirror caused by input current absorption, ensuring the sampling accuracy of the differential signal after potential shift. Secondly, this circuit, through the cooperation of the fourteenth resistor and the twelfth and thirteenth resistors, achieves the first stage of precise amplification of the differential input signal. Furthermore, through a precision subtractor circuit composed of the eighth to eleventh resistors and the fourth operational amplifier, the differential signal is converted into a high-precision single-ended output voltage referenced to ground. The entire instrumentation amplifier structure has an extremely high common-mode rejection ratio, effectively suppressing any residual common-mode noise from the pre-stage or power supply.

[0022] Furthermore, by precisely matching resistors, such as making the eighth resistor equal to the tenth resistor, or making the ninth resistor equal to the eleventh resistor, or adjusting the resistance of the fourteenth resistor, the total gain of the circuit can be set and adjusted, ensuring excellent dynamic response while meeting the current detection sensitivity requirements of different application scenarios.

[0023] A second aspect of the present invention provides a high-voltage side current detection system based on potential shifting, comprising a power supply, a load, and a high-voltage side current detection circuit based on potential shifting. The high-voltage side current detection circuit based on potential shifting includes a sampling resistor, a potential shifting module, and a signal extraction and amplification module, wherein: The sampling resistor is positioned on the high-voltage side between the power supply and the load; The potential shifting module is used to shift the sampling voltage potential across the sampling resistor to the second input terminal and the first input terminal of the signal extraction and amplification module using the current mirror principle; The signal extraction and amplification module is used to extract and amplify the potential signals received by the second input terminal and the first input terminal to obtain the output voltage, and to perform current detection based on the output voltage.

[0024] Further, the potential shifting module includes a first resistor, a second resistor, a third resistor, a first NPN transistor, a second NPN transistor, and a third NPN transistor, wherein: The first end of the first resistor is electrically connected to the load end of the sampling resistor, and the second end of the first resistor is electrically connected to the collector of the first NPN transistor. The first end of the second resistor is electrically connected to the load end of the sampling resistor, and the second end of the second resistor is electrically connected to the collector of the second NPN transistor. The first end of the third resistor is electrically connected to the power supply terminal of the sampling resistor, and the second end of the third resistor is electrically connected to the collector of the third NPN transistor. The collector and base of the first NPN transistor are electrically connected, and the emitter of the first NPN transistor is grounded. The collector of the second NPN transistor is electrically connected to the second input terminal of the signal extraction and amplification module, the base of the second NPN transistor is electrically connected to the base of the first NPN transistor, and the emitter of the second NPN transistor is grounded. The collector of the third NPN transistor is electrically connected to the first input terminal of the signal extraction and amplification module, the base of the third NPN transistor is electrically connected to the base of the first NPN transistor, and the emitter of the third NPN transistor is grounded.

[0025] Furthermore, the potential shifting module includes a first resistor, a second resistor, a third resistor, a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor, wherein: The first end of the first resistor is electrically connected to the load end of the sampling resistor, and the second end of the first resistor is electrically connected to the drain of the first NMOS transistor. The first end of the second resistor is electrically connected to the load end of the sampling resistor, and the second end of the second resistor is electrically connected to the drain of the second NMOS transistor. The first end of the third resistor is electrically connected to the power supply terminal of the sampling resistor, and the second end of the third resistor is electrically connected to the drain of the third NMOS transistor. The drain and gate of the first NMOS transistor are electrically connected, and the source of the first NMOS transistor is grounded. The drain of the second NMOS transistor is electrically connected to the second input terminal of the signal extraction and amplification module, the gate of the second NMOS transistor is electrically connected to the gate of the first NMOS transistor, and the source of the second NMOS transistor is grounded. The drain of the third NMOS transistor is electrically connected to the first input terminal of the signal extraction and amplification module, the gate of the third NMOS transistor is electrically connected to the gate of the first NMOS transistor, and the emitter of the third NMOS transistor is grounded.

[0026] Furthermore, the signal extraction and amplification module includes a first operational amplifier, a fourth resistor, a fifth resistor, a sixth resistor, and a seventh resistor, wherein: The first end of the fourth resistor serves as the second input terminal of the signal extraction and amplification module, and the second end of the fourth resistor is electrically connected to the inverting input terminal of the first operational amplifier. The first end of the fifth resistor is electrically connected to the inverting input terminal of the first operational amplifier, and the second end of the fifth resistor is electrically connected to the output terminal of the first operational amplifier. The first end of the sixth resistor serves as the first input terminal of the signal extraction and amplification module, and the second end of the sixth resistor is electrically connected to the non-inverting input terminal of the first operational amplifier. The first terminal of the seventh resistor is electrically connected to the non-inverting input terminal of the first operational amplifier, and the second terminal of the seventh resistor is grounded. The output terminal of the first operational amplifier is used to output the output voltage.

[0027] Furthermore, the signal extraction and amplification module includes a second operational amplifier, a third operational amplifier, a fourth operational amplifier, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, and a fourteenth resistor, wherein: The non-inverting input of the second operational amplifier serves as the second input of the signal extraction and amplification module, and the inverting input of the second operational amplifier is electrically connected to the first end of the fourteenth resistor. The non-inverting input terminal of the third operational amplifier serves as the first input terminal of the signal extraction and amplification module, and the inverting input terminal of the third operational amplifier is electrically connected to the second terminal of the fourteenth resistor. The twelfth resistor is connected in parallel to the inverting input and output of the second operational amplifier, and the thirteenth resistor is connected in parallel to the inverting input and output of the third operational amplifier. The first end of the eighth resistor is electrically connected to the output terminal of the second operational amplifier, and the second end of the eighth resistor is electrically connected to the inverting input terminal of the fourth operational amplifier. The first end of the ninth resistor is electrically connected to the inverting input terminal of the fourth operational amplifier, and the second end of the ninth resistor is electrically connected to the output terminal of the fourth operational amplifier. The first end of the tenth resistor is electrically connected to the output terminal of the third operational amplifier, and the second end of the tenth resistor is electrically connected to the non-inverting input terminal of the fourth operational amplifier. The first terminal of the eleventh resistor is electrically connected to the non-inverting input terminal of the fourth operational amplifier, and the second terminal of the eleventh resistor is grounded. The output terminal of the fourth operational amplifier is used to output the output voltage.

[0028] The high-voltage side current detection circuit and system based on potential shift provided by this invention, compared with the prior art, does not require a dedicated high-voltage detection chip, and can be implemented using only discrete components such as conventional transistors, resistors, and general-purpose operational amplifiers, thus significantly reducing circuit costs. At the same time, the current mirror structure has excellent dynamic response characteristics, and can be effectively applied to harsh working environments with high dV / dt noise, such as motor PWM drives. Attached Figure Description

[0029] Figure 1 This is a structural diagram of the first high-voltage side current detection circuit based on potential shift provided in this embodiment of the invention; Figure 2 This is a structural diagram of the second high-voltage side current detection circuit based on potential shift provided in this embodiment of the invention; Figure 3 This is a structural diagram of the third high-voltage side current detection circuit based on potential shift provided in the embodiments of the present invention; Figure 4 This is a structural diagram of the fourth high-voltage side current detection circuit based on potential shift provided in the embodiments of the present invention; Figure 5 This is a waveform diagram of the driving signal of a Buck circuit provided in an embodiment of the present invention; Figure 6 This is a node voltage waveform diagram provided in an embodiment of the present invention; Figure 7 This is a waveform diagram of the Buck circuit current and the output voltage of the detection circuit provided in an embodiment of the present invention. Detailed Implementation

[0030] The present invention will now be described in detail with reference to the accompanying drawings and embodiments. It should be noted that the following detailed descriptions are exemplary and intended to provide further detailed explanation of the invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used herein in the specification is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms "comprising" and "having," and any variations thereof, in the specification, claims, and foregoing drawings, are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the specification, claims, or foregoing drawings are used to distinguish different objects, not to describe a particular order.

[0031] Please refer to Figure 1 To address the aforementioned technical problems, the first aspect of this invention provides a high-voltage side current detection circuit based on potential shifting, comprising a sampling resistor Rsense, a potential shifting module 100, and a signal extraction and amplification module 200, wherein: The sampling resistor Rsense is positioned on the high-voltage side between the external power supply DC and the external load Co; The potential shifting module 100 is used to shift the sampling voltage potential across the sampling resistor Rsense to the second input terminal V2 and the first input terminal V1 of the signal extraction and amplification module 200 using the current mirror principle; The signal extraction and amplification module 200 is used to extract and amplify the potential signals received by the second input terminal V2 and the first input terminal V1 to obtain the output voltage Vout, and to perform current detection based on the output voltage Vout.

[0032] The aforementioned high-voltage side current detection circuit based on potential shifting utilizes a current mirror structure implemented by a specific resistor and transistor in the potential shifting module 100. This current mirror can distortionlessly shift the high common-mode voltage across the sampling resistor Rsense to a safe low common-mode voltage domain. This design eliminates the need for the subsequent signal extraction and amplification module 200 to directly withstand the high common-mode voltage, thus overcoming the voltage withstand limitations of traditional dedicated detection chips. A common-mode voltage withstand capability of several hundred volts or even higher can be achieved simply by selecting an external resistor with an appropriate voltage rating. Simultaneously, this circuit avoids the use of expensive dedicated current detection and amplification chips, consisting only of conventional discrete components, significantly reducing circuit costs. Furthermore, since the influence of transistor parameter drift in the current mirror of the potential shifting module 100 appears in common-mode form in the differential signal path, it can be effectively suppressed by the subsequent high common-mode rejection ratio signal extraction and amplification module 200, thereby ensuring the overall detection accuracy and temperature stability of the system while achieving high voltage withstand.

[0033] Please refer to Figure 2 Furthermore, the potential shifting module 100 includes a first resistor R1, a second resistor R2, a third resistor R3, a first NPN transistor Q11, a second NPN transistor Q21, and a third NPN transistor Q31, wherein: The first end of the first resistor R1 is electrically connected to the load end of the sampling resistor Rsense, and the second end of the first resistor R1 is electrically connected to the collector of the first NPN transistor Q11. The first end of the second resistor R2 is electrically connected to the load end of the sampling resistor Rsense, and the second end of the second resistor R2 is electrically connected to the collector of the second NPN transistor Q21. The first end of the third resistor R3 is electrically connected to the power supply terminal of the sampling resistor Rsense, and the second end of the third resistor R3 is electrically connected to the collector of the third NPN transistor Q31. The collector and base of the first NPN transistor Q11 are electrically connected, and the emitter of the first NPN transistor Q11 is grounded; The collector of the second NPN transistor Q21 is electrically connected to the second input terminal V2 of the signal extraction and amplification module 200, the base of the second NPN transistor Q21 is electrically connected to the base of the first NPN transistor Q11, and the emitter of the second NPN transistor Q21 is grounded. The collector of the third NPN transistor Q31 is electrically connected to the first input terminal V1 of the signal extraction and amplification module 200, the base of the third NPN transistor Q31 is electrically connected to the base of the first NPN transistor Q11, and the emitter of the third NPN transistor Q31 is grounded. In this implementation, by connecting the collector and base of the first NPN transistor Q11 to establish a reference current branch, and connecting the bases of the second and third NPN transistors Q31 to the base of the first NPN transistor Q11, a highly symmetrical current mirror system is formed. The current mirror ensures that the current flowing through the second resistor R2 and the third resistor R3 can accurately mirror the reference current flowing through the first resistor R1. Since the resistance values ​​of the first resistor R1, the second resistor R2, and the third resistor R3 are set to be strictly equal, the voltage drop across the second resistor R2 is equal to the voltage drop across the first resistor R1, and the voltage drop across the third resistor R3 is also equal to the voltage drop across the first resistor R1.

[0034] This characteristic allows the original differential voltage between the load terminal and the power supply terminal of the sampling resistor Rsense to be reproduced without loss between the collectors of the second NPN transistor Q21 and the third NPN transistor Q31, i.e., across the second input terminal V2 and the first input terminal V1 of the signal extraction and amplification module 200. The accuracy of the entire potential shifting process depends primarily on the matching accuracy of the three resistors and the consistency of the characteristics of the three transistors. The inherent parameters of the transistors, such as the emitter junction and their temperature drift, exhibit the same common-mode variation in each branch and do not affect the accuracy of the shifted differential signal.

[0035] Meanwhile, the high common-mode voltage applied to the sampling resistor Rsense is entirely borne by the first resistor R1, the second resistor R2, and the third resistor R3. The overall common-mode withstand voltage capability of the system is determined by the withstand voltage values ​​of these external resistors. Thus, the withstand voltage range can be easily extended by selecting high-voltage resistors, achieving high-precision, high-voltage potential shifting function with a simple and low-cost discrete component solution.

[0036] Please refer to Figure 3 Furthermore, the potential shifting module 100 includes a first resistor R1, a second resistor R2, a third resistor R3, a first NMOS transistor Q12, a second NMOS transistor Q22, and a third NMOS transistor Q32, wherein: The first end of the first resistor R1 is electrically connected to the load end of the sampling resistor Rsense, and the second end of the first resistor R1 is electrically connected to the drain of the first NMOS transistor Q12. The first end of the second resistor R2 is electrically connected to the load end of the sampling resistor Rsense, and the second end of the second resistor R2 is electrically connected to the drain of the second NMOS transistor Q22. The first end of the third resistor R3 is electrically connected to the power supply terminal of the sampling resistor Rsense, and the second end of the third resistor R3 is electrically connected to the drain of the third NMOS transistor Q32. The drain and gate of the first NMOS transistor Q12 are electrically connected, and the source of the first NMOS transistor Q12 is grounded. The drain of the second NMOS transistor Q22 is electrically connected to the second input terminal V2 of the signal extraction and amplification module 200, the gate of the second NMOS transistor Q22 is electrically connected to the gate of the first NMOS transistor Q12, and the source of the second NMOS transistor Q22 is grounded. The drain of the third NMOS transistor Q32 is electrically connected to the first input terminal V1 of the signal extraction and amplification module 200, the gate of the third NMOS transistor Q32 is electrically connected to the gate of the first NMOS transistor Q12, and the emitter of the third NMOS transistor Q32 is grounded.

[0037] In this implementation, a current mirror system based on NMOS devices is formed by connecting the drain and gate of the first NMOS transistor to establish a reference current branch, and connecting the gates of the second and third NMOS transistors Q32 to the gate of the first NMOS transistor Q12. This current mirror connection ensures that the current flowing through the second resistor R2 and the third resistor R3 accurately mirrors the reference current flowing through the first resistor R1. Since the resistance values ​​of the first resistor R1, the second resistor R2, and the third resistor R3 are set to be strictly equal, the voltage drop across the second resistor R2 is equal to the voltage drop across the first resistor R1, and the voltage drop across the third resistor R3 is also equal to the voltage drop across the first resistor R1.

[0038] This characteristic allows the original differential voltage between the load terminal and the power supply terminal of the sampling resistor Rsense to be accurately reproduced between the drain terminals of the second NMOS transistor Q22 and the third NMOS transistor Q32, i.e., across the two input terminals of the signal extraction and amplification module 200. The accuracy of the entire potential shifting process depends primarily on the matching accuracy of the three resistors and the consistency of the characteristics of the three NMOS transistors, providing a feasible solution for implementation using MOS technology.

[0039] Meanwhile, the high common-mode voltage applied to the sampling resistor Rsense is entirely borne by the first resistor R1, the second resistor R2, and the third resistor R3. The overall common-mode withstand voltage capability of the system is determined by the withstand voltage values ​​of these external resistors, thus extending the withstand voltage range by selecting high-voltage resistors. This implementation, based on an NMOS transistor, provides a discrete component implementation method for constructing a high-precision, high-voltage-resistance potential shifting module 100, distinct from NPN transistors.

[0040] Please refer to Figure 2 or Figure 3 Furthermore, the signal extraction and amplification module 200 includes a first operational amplifier A1, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, and a seventh resistor R7, wherein: The first end of the fourth resistor R4 serves as the second input terminal V2 of the signal extraction and amplification module 200, and the second end of the fourth resistor R4 is electrically connected to the inverting input terminal of the first operational amplifier A1. The first end of the fifth resistor R5 is electrically connected to the inverting input terminal of the first operational amplifier A1, and the second end of the fifth resistor R5 is electrically connected to the output terminal of the first operational amplifier A1. The first end of the sixth resistor R6 serves as the first input terminal V1 of the signal extraction and amplification module 200, and the second end of the sixth resistor R6 is electrically connected to the non-inverting input terminal of the first operational amplifier A1. The first terminal of the seventh resistor R7 is electrically connected to the non-inverting input terminal of the first operational amplifier A1, and the second terminal of the seventh resistor R7 is grounded. The output terminal of the first operational amplifier A1 is used to output the output voltage Vout.

[0041] In this implementation, the first operational amplifier A1, together with the fourth resistor R4, the fifth resistor R5, the sixth resistor R6, and the seventh resistor R7, constitute a differential amplifier circuit. This circuit effectively converts the differential voltage signal output from the potential shift module 100, existing between its second input terminal V2 and its first input terminal V1, into a single-ended output voltage Vout signal referenced to the system ground potential. By appropriately setting the resistance ratio between the fourth resistor R4, the fifth resistor R5, the sixth resistor R6, and the seventh resistor R7, the gain of the differential amplifier can be easily adjusted, thereby flexibly adapting to the current detection requirements of different ranges.

[0042] The circuit structure described above utilizes the high input impedance and low output impedance characteristics of operational amplifiers to ensure the stability and driving capability of the output voltage Vout while amplifying the signal. Since the pre-amplifier potential shifting module 100 effectively isolates the common-mode voltage on the high-voltage side, the common-mode level of the signal reaching the input of this differential amplifier is within a low-voltage safe range. Therefore, the first operational amplifier A1 can be a common general-purpose operational amplifier, without needing to withstand high common-mode voltage or possess extremely high common-mode rejection ratio characteristics, significantly reducing the performance requirements and cost of the core amplification components.

[0043] Furthermore, by selecting matching resistor pairs, such as making the fourth resistor R4 and the sixth resistor R6 equal, or making the fifth resistor R5 and the seventh resistor R7 equal, the common-mode rejection capability of the differential amplifier circuit can be optimized, further suppressing common-mode noise from the preceding stage or the environment, thereby improving the accuracy and anti-interference capability of the entire current sensing system.

[0044] In such Figure 2 or Figure 3 In the specific embodiment shown, the first NPN transistor Q11, the second NPN transistor Q21, and the third NPN transistor Q31 are manufactured using the same process and have highly consistent characteristics. The resistances of the first resistor R1, the second resistor R2, and the third resistor R3 are strictly equal. The first NPN transistor Q11 and the first resistor R1 form a reference branch. The current flowing through the first resistor R1, i.e., the reference current I_ref = (Vcm - Vbe_Q1) / R1, where Vcm is the voltage at the node where the sampling resistor Rsense is located, and Vbe_Q1 is the base-emitter voltage of the first NPN transistor Q11. The second NPN transistor Q21 and the third NPN transistor Q31 precisely mirror the current of the first NPN transistor Q11; therefore, the current I_Q2 of the second NPN transistor Q21 = the current I_Q3 of the third NPN transistor Q31 ≈ I_ref.

[0045] Based on the current mirror principle, since I_Q2≈I_ref and R2 = R1, according to Ohm's law, the voltage across the second resistor R2, UR2 = I_Q2 * R2, must be equal to the voltage across the first resistor R1, UR1. Similarly, UR3 = UR1. The accuracy during the translation process depends only on the absolute accuracy of the first resistor R1, the second resistor R2, and the third resistor R3, and the consistency of the first NPN transistor Q11, the second NPN transistor Q21, and the third NPN transistor Q31, and is independent of the specific transistor parameters and is unaffected by temperature drift.

[0046] After translation, the voltage difference between the first input terminal V1 and the second input terminal V2 of the signal extraction and amplification module 200, i.e., V12=V1-V2, is equal to the voltage Vsenser = I_load * Rsense across the original sampling resistor Rsense.

[0047] The differential voltage V12 is fed into the signal extraction and amplification module 200, which consists of the first operational amplifier A1 and resistors R4, R5, R6, and R7, for amplification. The final output voltage Vout is referenced to ground. Vout = G * (I_load * Rsense), where G is the gain of the signal extraction and amplification module 200.

[0048] Therefore, the high common-mode voltage applied to the sampling resistor Rsense is borne by the external first resistor R1, second resistor R2, and third resistor R3. By selecting resistors with different withstand voltage ratings, the overall system withstand voltage capability can be easily extended to several hundred volts or more.

[0049] by Figure 2 The circuit shown is for illustrative purposes only. Assume the voltage at node Vcm where the sampling resistor Rsense is located is 100V, the base-emitter voltage drop Vbe of the first NPN transistor Q11 is 0.7V, and the resistances of the first resistor R1, second resistor R2, and third resistor R3 are all 10kΩ. Then, the reference current flowing through the first resistor R1 is I_ref = (100V - 0.7V) / 10kΩ = 9.93mA. Due to the current mirror effect, the currents flowing through the second resistor R2 and the third resistor R3 are equal to the reference current, i.e., from I_Q2 = I_Q3 ≈ I_ref, we get IR1 = IR2 = IR3. Therefore, the voltage drop VR2 across the second resistor R2 is VR2 = I_Q2 * R2 = 9.93mA * 10kΩ = 99.3V, and the voltage drop VR3 across the third resistor R3 is also 99.3V, thus sharing the high common-mode voltage across the sampling resistor Rsense.

[0050] The accuracy of this potential shifting and current detection circuit relies heavily on the absolute accuracy and matching degree of the first resistor R1, the second resistor R2, and the third resistor R3, which can be ensured by selecting high-precision resistors. Meanwhile, the first NPN transistor Q11, the second NPN transistor Q21, and the third NPN transistor Q31 are manufactured using the same process, and their current amplification factor β is consistent. The inherent parameters of the transistors, such as the temperature drift of the base-emitter voltage Vbe, manifest as common-mode variations in the differential signal path, which can be effectively suppressed by the subsequent signal extraction and amplification module 200 with a high common-mode rejection ratio. The current mirror function is based on the current amplification characteristics of the transistors. When the bases of the transistors are connected in parallel, the base currents are equal, and the current amplification factor β is consistent, their collector currents remain the same. Even if the β value of the transistors changes with temperature, because they are manufactured using the same process and have consistent characteristics, their changing trends are the same, and the collector currents remain equal, thus ensuring that the voltage drop across the second resistor R2 and the third resistor R3 is always equal, achieving effective suppression of common-mode interference.

[0051] Please refer to Figure 4 Furthermore, the signal extraction and amplification module 200 includes a second operational amplifier A2, a third operational amplifier A3, a fourth operational amplifier A4, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, and a fourteenth resistor R14, wherein: The non-inverting input terminal of the second operational amplifier A2 serves as the second input terminal V2 of the signal extraction and amplification module 200, and the inverting input terminal of the second operational amplifier A2 is electrically connected to the first terminal of the fourteenth resistor R14. The non-inverting input terminal of the third operational amplifier A3 serves as the first input terminal V1 of the signal extraction and amplification module 200, and the inverting input terminal of the third operational amplifier A3 is electrically connected to the second terminal of the fourteenth resistor R14. The twelfth resistor R12 is connected in parallel to the inverting input and output of the second operational amplifier A2, and the thirteenth resistor R13 is connected in parallel to the inverting input and output of the third operational amplifier A3. The first end of the eighth resistor R8 is electrically connected to the output terminal of the second operational amplifier A2, and the second end of the eighth resistor R8 is electrically connected to the inverting input terminal of the fourth operational amplifier A4. The first end of the ninth resistor R9 is electrically connected to the inverting input terminal of the fourth operational amplifier A4, and the second end of the ninth resistor R9 is electrically connected to the output terminal of the fourth operational amplifier A4. The first end of the tenth resistor R10 is electrically connected to the output terminal of the third operational amplifier A3, and the second end of the tenth resistor R10 is electrically connected to the non-inverting input terminal of the fourth operational amplifier A4. The first end of the eleventh resistor R11 is electrically connected to the non-inverting input of the fourth operational amplifier A4, and the second end of the eleventh resistor R11 is grounded. The output terminal of the fourth operational amplifier A4 is used to output the output voltage Vout.

[0052] In this implementation, the second operational amplifier A2, the third operational amplifier A3, the fourth operational amplifier A4, and the eighth resistor R8 to the fourteenth resistor R14 together constitute an instrumentation amplifier circuit, serving as the signal extraction and amplification module 200. This circuit structure provides extremely high input impedance, completely eliminating the shunting effect of the input impedance of the back-end circuit on the front-end potential shifting module 100, and improving the sampling accuracy of current detection.

[0053] Specifically, the non-inverting input terminals of the second and third operational amplifiers A3 are directly used as the input ports of the signal extraction and amplification module 200. Because it operates in a deep negative feedback state, the input bias current drawn from the current mirror output node of the potential shifting module 100 is extremely small, thus completely avoiding any disturbance to the operating point of the preceding precision current mirror caused by input current absorption, ensuring the sampling accuracy of the differential signal after potential shifting. Secondly, this circuit, through the cooperation of the fourteenth resistor R14 and the twelfth and thirteenth resistors R13, achieves the first stage of precise amplification of the differential input signal. Furthermore, through the precision subtractor circuit composed of the eighth to eleventh resistors R11 and the fourth operational amplifier A4, the differential signal is converted into a high-precision single-ended output voltage Vout referenced to ground. The entire instrumentation amplifier structure has an extremely high common-mode rejection ratio, effectively suppressing any residual common-mode noise from the preceding stage or the DC power supply.

[0054] In addition, by precisely matching the resistors, for example, making the resistance values ​​of the eighth resistor R8 equal to those of the tenth resistor R10, or making the resistance values ​​of the ninth resistor R9 equal to those of the eleventh resistor R11, or adjusting the resistance value of the fourteenth resistor R14, the total gain of the circuit can be set and adjusted, ensuring excellent dynamic response while meeting the current detection sensitivity requirements of different application scenarios.

[0055] In such Figure 4In the specific embodiment shown, to completely eliminate the shunting effect of the input impedance of the back-end circuit on the front-end potential shifting module 100 and ensure the highest sampling accuracy, the signal extraction and amplification module 200 employs an instrumentation amplifier composed of a second operational amplifier A2, a third operational amplifier A3, a fourth operational amplifier A4, and resistors R8 to R14. This instrumentation amplifier has extremely high input impedance, typically exceeding 10^9 Ω, and its input bias current is extremely small. The current drawn from the first input terminal V1 and the second input terminal V2 is almost negligible, thereby ensuring that the operating point of the current mirror system is not disturbed. It can convert the shifted differential voltage signal V12 into a high-precision output voltage Vout referenced to the system ground potential without distortion. By using this instrumentation amplifier structure as the signal processing unit, extremely high input impedance is achieved, avoiding sampling deviations caused by input current absorption, and improving the overall detection accuracy of the system to the theoretical limit.

[0056] Please refer to Figure 2 In one specific embodiment, the above-described high-voltage side current detection circuit based on potential shift is used to detect the current of a Buck circuit. The Buck circuit includes a power supply DC, a fourth NMOS transistor Q4, a fifth NMOS transistor Q5, an inductor Lo, and a load Co, wherein: The DC power supply supplies power to the drain of the fifth NMOS transistor Q5. The source of the fifth NMOS transistor Q5 is electrically connected to the drain of the fourth NMOS transistor Q4. The source of the fourth NMOS transistor Q4 is grounded. The second terminal of the inductor Lo is electrically connected to the first terminal of the load Co. The second terminal of the load Co is grounded. The sampling resistor Rsense is disposed between the drain of the fourth NMOS transistor Q4 and the first terminal of the inductor Lo.

[0057] Please refer to Figure 5 The gate of the fifth NMOS transistor Q5 receives... Figure 5 The PWM1 signal in the above-mentioned fourth NMOS transistor Q4 receives the gate of the PWM1 signal. Figure 5 The PWM2 signal is used. The input voltage of the DC power supply is 40V, the voltage output from the Buck circuit to the load Co is 12V, the output current is set to Io=10A, the sampling resistor Rsense=0.01Ω, and the differential operational amplifier gain G=100 of the signal extraction amplification circuit.

[0058] In the above embodiments, we obtain Figure 6 shown Figure 2 The node voltage waveforms at the first input terminal V1 and the second input terminal V2, and Figure 7The waveforms of the output inductor current iLo and the output voltage Vout of the signal extraction and amplification circuit are shown. Figures 5 to 7 The experimental results and simulation results show that the highest voltage that the first input terminal V1 and the second input terminal V2 of the signal extraction and amplification circuit can withstand is only about 2V. The output voltage Vout=10V of the signal extraction and amplification circuit coincides with the output inductor current iLo=10A of the Buck circuit.

[0059] A second aspect of the present invention provides a high-voltage side current detection system based on potential shifting, comprising a power supply DC, a load Co, and a high-voltage side current detection circuit based on potential shifting. The high-voltage side current detection circuit based on potential shifting includes a sampling resistor Rsense, a potential shifting module 100, and a signal extraction and amplification module 200, wherein: The sampling resistor Rsense is positioned on the high-voltage side between the power supply DC and the load Co; The potential shifting module 100 is used to shift the sampling voltage potential across the sampling resistor Rsense to the second input terminal V2 and the first input terminal V1 of the signal extraction and amplification module 200 using the current mirror principle; The signal extraction and amplification module 200 is used to extract and amplify the potential signals received by the second input terminal V2 and the first input terminal V1 to obtain the output voltage Vout, and to perform current detection based on the output voltage Vout.

[0060] Further, the potential shifting module 100 includes a first resistor R1, a second resistor R2, a third resistor R3, a first NPN transistor Q11, a second NPN transistor Q21, and a third NPN transistor Q31, wherein: The first end of the first resistor R1 is electrically connected to the load end of the sampling resistor Rsense, and the second end of the first resistor R1 is electrically connected to the collector of the first NPN transistor Q11. The first end of the second resistor R2 is electrically connected to the load end of the sampling resistor Rsense, and the second end of the second resistor R2 is electrically connected to the collector of the second NPN transistor Q21. The first end of the third resistor R3 is electrically connected to the power supply terminal of the sampling resistor Rsense, and the second end of the third resistor R3 is electrically connected to the collector of the third NPN transistor Q31. The collector and base of the first NPN transistor Q11 are electrically connected, and the emitter of the first NPN transistor Q11 is grounded; The collector of the second NPN transistor Q21 is electrically connected to the second input terminal V2 of the signal extraction and amplification module 200, the base of the second NPN transistor Q21 is electrically connected to the base of the first NPN transistor Q11, and the emitter of the second NPN transistor Q21 is grounded. The collector of the third NPN transistor Q31 is electrically connected to the first input terminal V1 of the signal extraction and amplification module 200, the base of the third NPN transistor Q31 is electrically connected to the base of the first NPN transistor Q11, and the emitter of the third NPN transistor Q31 is grounded.

[0061] Further, the potential shifting module 100 includes a first resistor R1, a second resistor R2, a third resistor R3, a first NMOS transistor Q12, a second NMOS transistor Q22, and a third NMOS transistor Q32, wherein: The first end of the first resistor R1 is electrically connected to the load end of the sampling resistor Rsense, and the second end of the first resistor R1 is electrically connected to the drain of the first NMOS transistor Q12. The first end of the second resistor R2 is electrically connected to the load end of the sampling resistor Rsense, and the second end of the second resistor R2 is electrically connected to the drain of the second NMOS transistor Q22. The first end of the third resistor R3 is electrically connected to the power supply terminal of the sampling resistor Rsense, and the second end of the third resistor R3 is electrically connected to the drain of the third NMOS transistor Q32. The drain and gate of the first NMOS transistor Q12 are electrically connected, and the source of the first NMOS transistor Q12 is grounded. The drain of the second NMOS transistor Q22 is electrically connected to the second input terminal V2 of the signal extraction and amplification module 200, the gate of the second NMOS transistor Q22 is electrically connected to the gate of the first NMOS transistor Q12, and the source of the second NMOS transistor Q22 is grounded. The drain of the third NMOS transistor Q32 is electrically connected to the first input terminal V1 of the signal extraction and amplification module 200, the gate of the third NMOS transistor Q32 is electrically connected to the gate of the first NMOS transistor Q12, and the emitter of the third NMOS transistor Q32 is grounded.

[0062] Furthermore, the signal extraction and amplification module 200 includes a first operational amplifier A1, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, and a seventh resistor R7, wherein: The first end of the fourth resistor R4 serves as the second input terminal V2 of the signal extraction and amplification module 200, and the second end of the fourth resistor R4 is electrically connected to the inverting input terminal of the first operational amplifier A1. The first end of the fifth resistor R5 is electrically connected to the inverting input terminal of the first operational amplifier A1, and the second end of the fifth resistor R5 is electrically connected to the output terminal of the first operational amplifier A1. The first end of the sixth resistor R6 serves as the first input terminal V1 of the signal extraction and amplification module 200, and the second end of the sixth resistor R6 is electrically connected to the non-inverting input terminal of the first operational amplifier A1. The first terminal of the seventh resistor R7 is electrically connected to the non-inverting input terminal of the first operational amplifier A1, and the second terminal of the seventh resistor R7 is grounded. The output terminal of the first operational amplifier A1 is used to output the output voltage Vout.

[0063] Further, the signal extraction and amplification module 200 includes a second operational amplifier A2, a third operational amplifier A3, a fourth operational amplifier A4, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, and a fourteenth resistor R14, wherein: The non-inverting input terminal of the second operational amplifier A2 serves as the second input terminal V2 of the signal extraction and amplification module 200, and the inverting input terminal of the second operational amplifier A2 is electrically connected to the first terminal of the fourteenth resistor R14. The non-inverting input terminal of the third operational amplifier A3 serves as the first input terminal V1 of the signal extraction and amplification module 200, and the inverting input terminal of the third operational amplifier A3 is electrically connected to the second terminal of the fourteenth resistor R14. The twelfth resistor R12 is connected in parallel to the inverting input and output of the second operational amplifier A2, and the thirteenth resistor R13 is connected in parallel to the inverting input and output of the third operational amplifier A3. The first end of the eighth resistor R8 is electrically connected to the output terminal of the second operational amplifier A2, and the second end of the eighth resistor R8 is electrically connected to the inverting input terminal of the fourth operational amplifier A4. The first end of the ninth resistor R9 is electrically connected to the inverting input terminal of the fourth operational amplifier A4, and the second end of the ninth resistor R9 is electrically connected to the output terminal of the fourth operational amplifier A4. The first end of the tenth resistor R10 is electrically connected to the output terminal of the third operational amplifier A3, and the second end of the tenth resistor R10 is electrically connected to the non-inverting input terminal of the fourth operational amplifier A4. The first end of the eleventh resistor R11 is electrically connected to the non-inverting input of the fourth operational amplifier A4, and the second end of the eleventh resistor R11 is grounded. The output terminal of the fourth operational amplifier A4 is used to output the output voltage Vout.

[0064] The term "embodiment" as used herein means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described; however, any combination of these technical features that does not contradict each other should be considered within the scope of this specification.

[0065] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various improvements and substitutions without departing from the concept of this application, and these improvements and substitutions should also be considered within the scope of protection of this invention. Therefore, the scope of protection of this application should be determined by the appended claims.

Claims

1. A high-voltage side current detection circuit based on potential shifting, characterized in that, It includes a sampling resistor, a potential shifting module, and a signal extraction and amplification module, wherein: The sampling resistor is positioned on the high-voltage side between the external power supply and the external load. The potential shifting module is used to shift the sampling voltage potential across the sampling resistor to the second input terminal and the first input terminal of the signal extraction and amplification module using the current mirror principle; The signal extraction and amplification module is used to extract and amplify the potential signals received by the second input terminal and the first input terminal to obtain the output voltage, and to perform current detection based on the output voltage.

2. The high-voltage side current detection circuit based on potential shift according to claim 1, characterized in that, The potential shifting module includes a first resistor, a second resistor, a third resistor, a first NPN transistor, a second NPN transistor, and a third NPN transistor, wherein: The first end of the first resistor is electrically connected to the load end of the sampling resistor, and the second end of the first resistor is electrically connected to the collector of the first NPN transistor. The first end of the second resistor is electrically connected to the load end of the sampling resistor, and the second end of the second resistor is electrically connected to the collector of the second NPN transistor. The first end of the third resistor is electrically connected to the power supply terminal of the sampling resistor, and the second end of the third resistor is electrically connected to the collector of the third NPN transistor. The collector and base of the first NPN transistor are electrically connected, and the emitter of the first NPN transistor is grounded. The collector of the second NPN transistor is electrically connected to the second input terminal of the signal extraction and amplification module, the base of the second NPN transistor is electrically connected to the base of the first NPN transistor, and the emitter of the second NPN transistor is grounded. The collector of the third NPN transistor is electrically connected to the first input terminal of the signal extraction and amplification module, the base of the third NPN transistor is electrically connected to the base of the first NPN transistor, and the emitter of the third NPN transistor is grounded.

3. The high-voltage side current detection circuit based on potential shift according to claim 1, characterized in that, The potential shifting module includes a first resistor, a second resistor, a third resistor, a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor, wherein: The first end of the first resistor is electrically connected to the load end of the sampling resistor, and the second end of the first resistor is electrically connected to the drain of the first NMOS transistor. The first end of the second resistor is electrically connected to the load end of the sampling resistor, and the second end of the second resistor is electrically connected to the drain of the second NMOS transistor. The first end of the third resistor is electrically connected to the power supply terminal of the sampling resistor, and the second end of the third resistor is electrically connected to the drain of the third NMOS transistor. The drain and gate of the first NMOS transistor are electrically connected, and the source of the first NMOS transistor is grounded. The drain of the second NMOS transistor is electrically connected to the second input terminal of the signal extraction and amplification module, the gate of the second NMOS transistor is electrically connected to the gate of the first NMOS transistor, and the source of the second NMOS transistor is grounded. The drain of the third NMOS transistor is electrically connected to the first input terminal of the signal extraction and amplification module, the gate of the third NMOS transistor is electrically connected to the gate of the first NMOS transistor, and the emitter of the third NMOS transistor is grounded.

4. The high-voltage side current detection circuit based on potential shift according to claim 1, characterized in that, The signal extraction and amplification module includes a first operational amplifier, a fourth resistor, a fifth resistor, a sixth resistor, and a seventh resistor, wherein: The first end of the fourth resistor serves as the second input terminal of the signal extraction and amplification module, and the second end of the fourth resistor is electrically connected to the inverting input terminal of the first operational amplifier. The first end of the fifth resistor is electrically connected to the inverting input terminal of the first operational amplifier, and the second end of the fifth resistor is electrically connected to the output terminal of the first operational amplifier. The first end of the sixth resistor serves as the first input terminal of the signal extraction and amplification module, and the second end of the sixth resistor is electrically connected to the non-inverting input terminal of the first operational amplifier. The first terminal of the seventh resistor is electrically connected to the non-inverting input terminal of the first operational amplifier, and the second terminal of the seventh resistor is grounded. The output terminal of the first operational amplifier is used to output the output voltage.

5. The high-voltage side current detection circuit based on potential shift according to claim 1, characterized in that, The signal extraction and amplification module includes a second operational amplifier, a third operational amplifier, a fourth operational amplifier, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, and a fourteenth resistor, wherein: The non-inverting input of the second operational amplifier serves as the second input of the signal extraction and amplification module, and the inverting input of the second operational amplifier is electrically connected to the first end of the fourteenth resistor. The non-inverting input terminal of the third operational amplifier serves as the first input terminal of the signal extraction and amplification module, and the inverting input terminal of the third operational amplifier is electrically connected to the second terminal of the fourteenth resistor. The twelfth resistor is connected in parallel to the inverting input and output of the second operational amplifier, and the thirteenth resistor is connected in parallel to the inverting input and output of the third operational amplifier. The first end of the eighth resistor is electrically connected to the output terminal of the second operational amplifier, and the second end of the eighth resistor is electrically connected to the inverting input terminal of the fourth operational amplifier. The first end of the ninth resistor is electrically connected to the inverting input terminal of the fourth operational amplifier, and the second end of the ninth resistor is electrically connected to the output terminal of the fourth operational amplifier. The first end of the tenth resistor is electrically connected to the output terminal of the third operational amplifier, and the second end of the tenth resistor is electrically connected to the non-inverting input terminal of the fourth operational amplifier. The first terminal of the eleventh resistor is electrically connected to the non-inverting input terminal of the fourth operational amplifier, and the second terminal of the eleventh resistor is grounded. The output terminal of the fourth operational amplifier is used to output the output voltage.

6. A high-voltage side current detection system based on potential shift, characterized in that, The system includes a power supply, a load, and a high-voltage side current detection circuit based on potential shifting. The high-voltage side current detection circuit includes a sampling resistor, a potential shifting module, and a signal extraction and amplification module, wherein: The sampling resistor is positioned on the high-voltage side between the power supply and the load; The potential shifting module is used to shift the sampling voltage potential across the sampling resistor to the second input terminal and the first input terminal of the signal extraction and amplification module using the current mirror principle; The signal extraction and amplification module is used to extract and amplify the potential signals received by the second input terminal and the first input terminal to obtain the output voltage, and to perform current detection based on the output voltage.

7. A high-voltage side current detection system based on potential shift according to claim 6, characterized in that, The potential shifting module includes a first resistor, a second resistor, a third resistor, a first NPN transistor, a second NPN transistor, and a third NPN transistor, wherein: The first end of the first resistor is electrically connected to the load end of the sampling resistor, and the second end of the first resistor is electrically connected to the collector of the first NPN transistor. The first end of the second resistor is electrically connected to the load end of the sampling resistor, and the second end of the second resistor is electrically connected to the collector of the second NPN transistor. The first end of the third resistor is electrically connected to the power supply terminal of the sampling resistor, and the second end of the third resistor is electrically connected to the collector of the third NPN transistor. The collector and base of the first NPN transistor are electrically connected, and the emitter of the first NPN transistor is grounded. The collector of the second NPN transistor is electrically connected to the second input terminal of the signal extraction and amplification module, the base of the second NPN transistor is electrically connected to the base of the first NPN transistor, and the emitter of the second NPN transistor is grounded. The collector of the third NPN transistor is electrically connected to the first input terminal of the signal extraction and amplification module, the base of the third NPN transistor is electrically connected to the base of the first NPN transistor, and the emitter of the third NPN transistor is grounded.

8. A high-voltage side current detection system based on potential shift according to claim 6, characterized in that, The potential shifting module includes a first resistor, a second resistor, a third resistor, a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor, wherein: The first end of the first resistor is electrically connected to the load end of the sampling resistor, and the second end of the first resistor is electrically connected to the drain of the first NMOS transistor. The first end of the second resistor is electrically connected to the load end of the sampling resistor, and the second end of the second resistor is electrically connected to the drain of the second NMOS transistor. The first end of the third resistor is electrically connected to the power supply terminal of the sampling resistor, and the second end of the third resistor is electrically connected to the drain of the third NMOS transistor. The drain and gate of the first NMOS transistor are electrically connected, and the source of the first NMOS transistor is grounded. The drain of the second NMOS transistor is electrically connected to the second input terminal of the signal extraction and amplification module, the gate of the second NMOS transistor is electrically connected to the gate of the first NMOS transistor, and the source of the second NMOS transistor is grounded. The drain of the third NMOS transistor is electrically connected to the first input terminal of the signal extraction and amplification module, the gate of the third NMOS transistor is electrically connected to the gate of the first NMOS transistor, and the emitter of the third NMOS transistor is grounded.

9. A high-voltage side current detection system based on potential shift according to claim 1, characterized in that, The signal extraction and amplification module includes a first operational amplifier, a fourth resistor, a fifth resistor, a sixth resistor, and a seventh resistor, wherein: The first end of the fourth resistor serves as the second input terminal of the signal extraction and amplification module, and the second end of the fourth resistor is electrically connected to the inverting input terminal of the first operational amplifier. The first end of the fifth resistor is electrically connected to the inverting input terminal of the first operational amplifier, and the second end of the fifth resistor is electrically connected to the output terminal of the first operational amplifier. The first end of the sixth resistor serves as the first input terminal of the signal extraction and amplification module, and the second end of the sixth resistor is electrically connected to the non-inverting input terminal of the first operational amplifier. The first terminal of the seventh resistor is electrically connected to the non-inverting input terminal of the first operational amplifier, and the second terminal of the seventh resistor is grounded. The output terminal of the first operational amplifier is used to output the output voltage.

10. A high-voltage side current detection system based on potential shift according to claim 1, characterized in that, The signal extraction and amplification module includes a second operational amplifier, a third operational amplifier, a fourth operational amplifier, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, and a fourteenth resistor, wherein: The non-inverting input of the second operational amplifier serves as the second input of the signal extraction and amplification module, and the inverting input of the second operational amplifier is electrically connected to the first end of the fourteenth resistor. The non-inverting input terminal of the third operational amplifier serves as the first input terminal of the signal extraction and amplification module, and the inverting input terminal of the third operational amplifier is electrically connected to the second terminal of the fourteenth resistor. The twelfth resistor is connected in parallel to the inverting input and output of the second operational amplifier, and the thirteenth resistor is connected in parallel to the inverting input and output of the third operational amplifier. The first end of the eighth resistor is electrically connected to the output terminal of the second operational amplifier, and the second end of the eighth resistor is electrically connected to the inverting input terminal of the fourth operational amplifier. The first end of the ninth resistor is electrically connected to the inverting input terminal of the fourth operational amplifier, and the second end of the ninth resistor is electrically connected to the output terminal of the fourth operational amplifier. The first end of the tenth resistor is electrically connected to the output terminal of the third operational amplifier, and the second end of the tenth resistor is electrically connected to the non-inverting input terminal of the fourth operational amplifier. The first terminal of the eleventh resistor is electrically connected to the non-inverting input terminal of the fourth operational amplifier, and the second terminal of the eleventh resistor is grounded. The output terminal of the fourth operational amplifier is used to output the output voltage.

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