Power module bypass state feedback circuit and method

Abstract

The invention discloses a power module bypass state feedback circuit and method, and the circuit comprises a frequency generation module, a frequency division module, a coding and decoding module, two optical port driving modules, and two bypass switch closing detection circuits, the frequency generation module generates square waves, and the frequency division module carries out frequency division; the encoding and decoding module decodes the corresponding signals input by all the input control ends, selects the corresponding signal input by one data input end, and converts the corresponding signal into a frequency signal adaptive to the optical port driving module; one end of each of the switch tubes of the two bypass switch closing detection circuits is connected with the output end of the encoding and decoding module, and whether the switch tubes of the two bypass switch closing detection circuits are conducted or not is controlled according to whether two auxiliary contacts of the bypass switch are closed or closed; the input ends of the two optical port driving modules are both connected with the output end of the encoding and decoding module, and the two optical port driving modules respectively generate an optical port driving signal to drive the corresponding optical port. According to the invention, the overall reliability of the modularized multi-level equipment is improved.

Description

Technical Field

[0001] This invention belongs to the field of high voltage direct current transmission technology, and more specifically, relates to a power module bypass status feedback circuit and method. Background Technology

[0002] Modular multilevel topologies are widely used in DC power electronic devices such as high-voltage DC converters, DC power dissipation devices, and reactive power compensation equipment due to their advantages such as high modularity, strong design flexibility, easy expansion, low harmonic content, and high fault tolerance.

[0003] To enhance the reliability and fault ride-through capability of the modular multilevel topology, each power module is equipped with a bypass switch. During normal operation, the bypass switch is in the open state, and the module is controlled by the controller to perform switching actions. When a module malfunctions, the bypass switch closes, disconnecting the faulty module from the main circuit and ensuring the continuous normal operation of the DC equipment. The bypass switch is driven by a bypass driver board, which provides feedback on its operation status. This feedback not only affects the unit switching decision but also relates to the start-stop control and protection logic execution of the entire converter, having a critical impact on the overall reliability of the power modules and the modular multilevel equipment.

[0004] Power module bypass status typically uses fiber optic feedback signals. Existing bypass switch operation feedback relies on the presence or absence of light through the optical port, resulting in a limited feedback mechanism. This fails to distinguish between a power-down bypass driver board and an open bypass switch, hindering the transmission of accurate bypass switch status feedback to higher-level control. Improved bypass switch status feedback utilizes a 555 timer chip to build an oscillation circuit, employing different oscillation frequencies for different charging and discharging circuits to indicate the bypass switch's open / closed state and the bypass driver board's power supply status. While this method can differentiate between power-down bypass board operation and switch operation, the oscillation frequency is only in the tens to hundreds of kHz range, resulting in a receiver frequency determination delay in the millisecond range. This hinders rapid status feedback and is also affected by the precision of resistors and capacitors, leading to poor frequency consistency during mass production. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a power module bypass state feedback circuit and method.

[0006] The present invention adopts the following technical solution.

[0007] The first aspect of this invention provides a power module bypass state feedback circuit, comprising a frequency generation module, a frequency division module, an encoding / decoding module, two optical port driving modules, and two bypass switch closure detection circuits, specifically: The frequency generation module generates a square wave of a fixed frequency, which is set according to the desired feedback delay. The frequency division module divides the square wave of the fixed frequency generated by the frequency generation module to generate a set number of frequency signals. The encoding / decoding module includes an encoding chip, three state transition circuits, and peripheral circuits. The bypass trigger main power supply alarm signal, bypass trigger auxiliary power supply alarm signal, and bypass driver board power supply status alarm signal are each input to a state transition circuit. Each state transition circuit performs level conversion on the received corresponding signal and outputs a signal adapted to the input control terminal of the encoding chip. The output terminal of each state transition circuit is connected to a different input control terminal of the encoding chip. Each frequency signal generated by the frequency divider module is connected to a different data input terminal of the encoding chip. The encoding chip decodes the corresponding signals input from all input control terminals and selects a corresponding signal from a data input terminal as its output. The output terminal of the encoding chip is connected to the input terminal of the peripheral circuits. The peripheral circuits perform level conversion on the output of the encoding chip to generate a frequency signal adapted to the optical port driver module. The two bypass switch closure detection circuits have the same structure, each including a switching transistor. One end of the switching transistor in both bypass switch closure detection circuits is connected to the output of the encoding / decoding module, and the other end is grounded. The switching transistors of the two bypass switch closure detection circuits are controlled to conduct based on whether the two auxiliary contacts of the bypass switch are closed or open. The input terminals of both optical port driver modules are connected to the output terminals of the encoding / decoding module, and each generates an optical port driver signal to drive the corresponding optical port.

[0008] Preferably, the frequency generation module consists of a crystal oscillator X1, a first pull-up resistor R1, and a π-type filter circuit; The first power supply VCC is connected to the input terminal of the π-type filter circuit. One end of the first pull-up resistor R1, the power supply pin of the crystal oscillator X1, and the output terminal of the π-type filter circuit are connected. The other end of the first pull-up resistor R1 is connected to the enable pin of the crystal oscillator X1. The π-type filter circuit includes a first capacitor C1, a second capacitor C2, a third capacitor C3, and a first inductor L1. One end of the first inductor L1 and the third capacitor C3 are connected as the input terminal of the π-type filter circuit, and the other end of the first inductor L1 is the output terminal of the π-type filter circuit. The other end of the third capacitor C3 is grounded, and the first capacitor C1 and the second capacitor C2 are connected in parallel between the other end of the first inductor L1 and ground.

[0009] Preferably, the fixed frequency is set according to the desired feedback delay, specifically: The desired feedback delay is set to 'a', and the number of filtering cycles after the receiving end acquires the square wave is 'n'. Then the fixed frequency is greater than or equal to 128 multiplied by n and then divided by 'a'. The receiving end is a board connected to each optical port.

[0010] Preferably, the frequency division module generates a set number of signals with different frequencies, specifically: The frequency divider module includes a counter U1, which generates a set number of signals of different frequencies for output by performing different frequency divisions. Alternatively, the counter U1 can be used to generate a set number of signals of different frequencies by dividing the signals by one. These signals, together with the signals output by the frequency generation module, form a set number of signals of different frequencies for output.

[0011] Preferably, the peripheral circuit includes a twentieth current-limiting resistor R20, a fourth transistor Q4, a sixteenth pull-up resistor R16, and a twenty-fourth voltage divider resistor R24, comprising: The output signal fiber_tir of the encoding chip U2 is connected to the gate of the fourth transistor Q4 through the twentieth current-limiting resistor R20. The first power supply VCC is connected to the output signal fiber_tir of the encoding chip U2 through the sixteenth pull-up resistor R16. The twenty-fourth voltage divider resistor R24 ​​is connected between the gate of the fourth transistor Q4 and ground. The source of the fourth transistor Q4 is grounded, and the drain of the fourth transistor Q4 is the output of the encoding / decoding module.

[0012] Preferably, the three state transition circuits have the same structure, each including a state transition current-limiting resistor, a state transition grounding resistor, a state transition pull-up resistor, and a state transition transistor; The input terminal of the state transition circuit is connected to the gate of the state transition transistor through a state transition current-limiting resistor; The state transition grounding resistor is connected between the gate of the state transition transistor and ground; the source of the state transition transistor is grounded; the first power supply VCC is connected to the drain of the state transition transistor through the state transition pull-up resistor; the drain of the state transition transistor serves as the output terminal of the state transition circuit.

[0013] Preferably, the bypass switch closure detection circuit further includes a detection pull-up resistor, a detection current-limiting resistor, a detection voltage divider resistor, and a detection protection diode; One end of the corresponding auxiliary contact of the bypass switch is grounded, and the other end is connected to the control terminal of the switching transistor through a detection current-limiting resistor; the switching transistor is a triode, the control terminal of the switching transistor is the gate, one end of the switching transistor is the drain, and the other end is the source; the detection voltage divider resistor is connected between the control terminal of the switching transistor and ground; The second power supply VD is connected to the other end of the corresponding auxiliary contact of the bypass switch through the detection pull-up resistor; The anode of the protection diode is grounded, and the cathode is connected to the gate of the switching transistor.

[0014] Preferably, the optical port driver module includes an optical path driver current limiting resistor, an optical path driver shunt resistor, an optical path driver filter capacitor, a protection diode, and a reverse protection diode; The second power supply VD is connected to the anode of the diode in the optical port TSM1 via the optical path driving current-limiting resistor. The signal fiber_FB output by the encoding / decoding module is connected to the cathode of the anti-reverse diode, and the anode of the anti-reverse diode is connected to the cathode of the corresponding optical port diode. The protection diode, the optical path drive filter capacitor, and the optical path drive shunt resistor are connected in parallel across the anode and cathode of the corresponding optical port diode. The cathode of the protection diode is connected to the anode of the corresponding optical port diode, and the anode of the protection diode is connected to the cathode of the corresponding optical port diode.

[0015] A second aspect of the present invention provides a power module bypass state feedback method based on the circuit described in the first aspect of the present invention, comprising: Obtain the power supply status of the bypass driver board, the main power supply status of the bypass trigger, and the redundant power supply status of the bypass trigger; Generate a set number of signals of different frequencies; based on the main power supply status of the bypass trigger, the redundant power supply status of the bypass trigger, and the power supply status of the bypass driver board, select the target frequency signal from the generated set number of signals of different frequencies; If the bypass switch is open, both auxiliary contacts of the bypass switch are open, and the switching transistors of the two bypass switch closure detection circuits are not conducting; both optical port drive modules output drive signals with the same frequency as the target frequency signal. When the drive signal is low, the two optical ports emit corresponding optical signals; when the bypass switch is closed, some auxiliary contacts are closed, some bypass switch closure detection circuits are conducting, the two optical port start modules output low levels, and the two optical ports are constantly lit.

[0016] Preferably, the step of selecting the target frequency signal from a set number of signals of different frequencies based on the main power supply state of the bypass trigger, the redundant power supply state of the bypass trigger, and the power supply state of the bypass driver board specifically involves: If the main power supply status of the bypass trigger is abnormal, the main power supply alarm signal of the bypass trigger will be high, otherwise it will be low; if the redundant power supply status of the bypass trigger is abnormal, the auxiliary power supply alarm signal of the bypass trigger will be high, otherwise it will be low; if the power supply status of the bypass driver board is abnormal, the power supply status alarm signal of the bypass driver board will be high, otherwise it will be low; the binary signal corresponding to the high level is 1, otherwise it is 0. The binary signal corresponding to the bypass trigger main power supply alarm signal is the least significant bit of a binary number; the binary signal corresponding to the bypass trigger auxiliary power supply alarm signal is the second least significant bit of the corresponding binary number; the binary signal corresponding to the bypass driver board power supply status alarm signal is the most significant bit of the corresponding binary number. The binary number is decoded into a decimal number, with a set number of 8 possible values. The signals with the set number of frequencies are then sorted from high to low frequency. The decoded decimal number is the number of the sorted target frequency signal.

[0017] The beneficial effects of this invention are as follows: Compared with the prior art, this invention acquires the open / closed state and controllable state of the bypass switch (including the power supply status of the bypass driver board, the main power supply status of the bypass trigger, and the redundant power supply status). A stable square wave is generated using a frequency generation module, and multiple frequency-divided signals are obtained through a frequency division module. These signals are then encoded by an encoding module, and finally, a dual-channel optical port driver module converts the encoded signals and switch status signals into optical signals, which are synchronously transmitted to the control boards of this power module and adjacent power modules. The circuit of this invention integrates frequency generation, frequency division, encoding, dual-channel bypass switch closure detection, and dual-channel optical port driver modules, achieving multi-dimensional, fast, and highly reliable feedback of the bypass status. It can effectively distinguish between scenarios such as bypass switch operation and driver board power failure, improving the overall reliability of modular multilevel devices. Attached Figure Description

[0018] Figure 1 This is a block diagram of a power module bypass state feedback circuit; Figure 2 This is a circuit diagram of a power module bypass state feedback circuit; Figure 3 This is the circuit diagram for the frequency divider unit; Figure 4 This is a circuit diagram of an encoding chip. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of this invention. The embodiments described in this application are merely some embodiments of this invention, and not all embodiments. Based on the spirit of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this invention.

[0020] like Figure 1 As shown, Embodiment 1 of the present invention proposes a power module bypass state feedback circuit, including a frequency generation module, a frequency division module, an encoding / decoding module, two optical port driving modules, and two bypass switch closure detection circuits, specifically as follows: The frequency generation module generates a square wave F with a fixed frequency, which is set according to the desired feedback delay. The frequency division module divides the square wave generated by the frequency generation module to generate signals of a set number of frequencies. The set of signals of the set number of frequencies is F'.

[0021] like Figure 2 As shown, the encoding / decoding module includes an encoding chip, three state transition circuits, and peripheral circuits. The bypass trigger main power supply alarm signal CV_1, the bypass trigger auxiliary power supply alarm signal CV_2, and the bypass driver board power supply status alarm signal POWER are each input to a state transition circuit. Each state transition circuit performs level conversion on the received corresponding signal and outputs a signal adapted to the input control terminal of the encoding chip. The output terminal of each state transition circuit is connected to different input control terminals of the encoding chip. Each frequency signal generated by the frequency divider module is connected to different data input terminals of the encoding chip. The encoding chip decodes the corresponding signals input from all input control terminals and selects one corresponding signal from a data input terminal as its output. The output terminal of the encoding chip is connected to the input terminal of the peripheral circuits. The peripheral circuits perform level conversion on the output of the encoding chip to generate a frequency signal adapted to the optical port driver module. It should be noted that the internal structure of the encoding chip is as follows: Figure 4 As shown; The two bypass switch closure detection circuits have the same structure, each including a switching transistor. One end of the switching transistor in both bypass switch closure detection circuits is connected to the output terminal of the encoding / decoding module, and the other end is grounded. The switching transistors in the two bypass switch closure detection circuits are controlled to conduct according to whether the two auxiliary contacts of the bypass switch are closed or open. The input terminals of both optical port driver modules are connected to the output terminals of the encoding and decoding modules, and each generates an optical port driver signal to drive the corresponding optical port. The two optical port driver modules are the first optical port driver module and the second optical port driver module. The optical port driver signal of the first optical port driver module is Sin1, and the optical port driver signal of the second optical port driver module is Sin2.

[0022] In this preferred embodiment, the frequency generation module consists of a crystal oscillator X1, a first pull-up resistor R1, and a π-type filter circuit. The first power supply VCC is connected to the input terminal of the π-type filter circuit. One end of the first pull-up resistor R1, the power supply pin of the crystal oscillator X1, and the output terminal of the π-type filter circuit are connected. The other end of the first pull-up resistor R1 is connected to the enable pin of the crystal oscillator X1. The π-type filter circuit includes a first capacitor C1, a second capacitor C2, a third capacitor C3, and a first inductor L1. One end of the first inductor L1 and one end of the third capacitor C3 are connected as the input terminal of the π-type filter circuit, and the other end of the first inductor L1 is the output terminal of the π-type filter circuit. The other end of the third capacitor C3 is grounded. The first capacitor C1 and the second capacitor C2 are connected in parallel between the other end of the first inductor L1 and the other end of the third capacitor C3.

[0023] Specifically, the crystal oscillator X1 uses a quartz crystal or silicon-based crystal. The π-type filter circuit composed of the first capacitor C1, the second capacitor C2, the third capacitor C3, and the first inductor L1 provides a stable, low-ripple power supply for the crystal oscillator X1. The first pull-up resistor R1 is connected to the power supply to keep X1 in a frequency-generating operating state.

[0024] The fixed frequency is set according to the desired feedback delay, specifically as follows: The desired feedback delay is set to 'a', and the number of filtering cycles after the receiving end acquires the square wave is 'n'. Then the fixed frequency is greater than or equal to 128 multiplied by n and then divided by 'a'. The receiving end is a board connected to each optical port.

[0025] It should be noted that the feedback delay refers to the delay between the signal change at the input of the encoding / decoding module and the change in the optical output frequency that is detected by the receiving end. In actual use, the receiving end is connected to the optical port of the bypass board and acts as the control board for receiving bypass status feedback. Furthermore, to avoid interference, the control board for receiving signals typically uses a filter with n cycles. When judging the waveform of the bypass status feedback, the receiving end can determine the frequency upon receiving the first complete square wave. However, in actual use, the square wave often has duty cycle distortion, so the receiving end needs to sample several sets (n sets) to determine the received frequency. This number of sets is the number of filter cycles.

[0026] Specifically, since the action time of the auxiliary switch after the bypass switch is activated is generally greater than 3ms, 2M~12M is usually selected to ensure a bypass signal feedback delay of 0.3ms~0.03ms, so that the signal processing delay can be ignored.

[0027] In this preferred embodiment, the frequency division module generates a set number of signals of different frequencies, specifically: The frequency divider module includes a counter U1, which generates a set number of signals of different frequencies for output by performing different frequency divisions. Alternatively, the counter U1 can be used to generate a set number of signals of different frequencies by dividing the signals by one. These signals, together with the signals output by the frequency generation module, form a set number of signals of different frequencies for output.

[0028] In this embodiment, the original frequency is divided into 2, 4, 8, 16, 32, 64, and 128 divisions, and the signals output by the frequency generation module are combined to form a set number of frequencies. The set number of frequencies is 8. The counter U1 uses a general-purpose 74 series logic device.

[0029] Specifically, the frequency division module also includes a second grounding resistor R2, a third grounding resistor R3, and a fourth bypass filter capacitor C4; like Figure 3 As shown, the counter U1 integrates two frequency-division units. Each frequency-division unit consists of four asynchronous cascaded T-type flip-flops, one non-inverting logic gate, and one inverting logic gate. The clear input of each frequency-division unit is input to the reset input of the first flip-flop among the four asynchronous cascaded T-type flip-flops (i.e.,...) through the corresponding non-inverting logic gate. Figure 3 The clock signal of each frequency group unit is input to the flip-flop of four asynchronous cascaded T-type flip-flops (i.e., the R terminal in the circuit), through the corresponding inverting logic gate. Figure 3 (The T-terminal in the middle); Each T-type flip-flop performs frequency division once, outputting a signal of one frequency; The clock signal terminal 1CLK of the first frequency group unit is connected to the output terminal of the crystal oscillator X1; the clear terminal 1CLR of the first frequency group unit is grounded through the second grounding resistor R2; the output terminal of the last flip-flop of the first frequency group unit is connected to the clock signal terminal 2CLK of the second frequency group unit; the clear terminal 2CLR of the second frequency group unit is grounded through the third grounding resistor R3; the fourth bypass filter capacitor C4 is connected between VCC and ground.

[0030] In this preferred embodiment, the peripheral circuit includes a twentieth current-limiting resistor R20, a fourth transistor Q4, a sixteenth pull-up resistor R16, and a twenty-fourth voltage divider resistor R24, comprising: The output signal fiber_tir of the encoding chip U2 is connected to the gate of the fourth transistor Q4 through the twentieth current-limiting resistor R20. The first power supply VCC is connected to the output signal fiber_tir of the encoding chip U2 through the sixteenth pull-up resistor R16. The twenty-fourth voltage divider resistor R24 ​​is connected between the gate of the fourth transistor Q4 and ground. The source of the fourth transistor Q4 is grounded, and the drain of the fourth transistor Q4 is the output of the encoding / decoding module.

[0031] In this preferred embodiment, the three state transition circuits have the same structure, each including a state transition current limiting resistor, a state transition grounding resistor, a state transition pull-up resistor, and a state transition transistor; The input terminal of the state transition circuit is connected to the gate of the state transition transistor through a state transition current-limiting resistor; The state transition grounding resistor is connected between the gate of the state transition transistor and ground; the source of the state transition transistor is grounded; the first power supply VCC is connected to the drain of the state transition transistor through the state transition pull-up resistor; the drain of the state transition transistor serves as the output terminal of the state transition circuit.

[0032] Specifically, the three state transition circuits are the first state transition circuit, the second state transition circuit, and the third state transition circuit; the bypass trigger main power supply alarm signal CV_1, the bypass trigger auxiliary power supply alarm signal CV_2, and the bypass driver board power supply status alarm signal POWER are respectively input to the input terminals of the first state transition circuit, the second state transition circuit, and the third state transition circuit. The first state transition circuit includes a seventeenth state transition current-limiting resistor R17, a twenty-first state transition grounding resistor R21, a thirteenth state transition pull-up resistor R13, and a first state transition transistor Q1; The input terminal of the first state transition circuit is connected to the gate of the first state transition transistor Q1 through the seventeenth state transition current limiting resistor R17. The 21st state transition grounding resistor R21 is connected between the gate of the first state transition transistor Q1 and ground; the source of the first state transition transistor Q1 is connected to ground; the first power supply VCC is connected to the drain of the first state transition transistor Q1 through the 13th state transition pull-up resistor R13; the drain of the first state transition transistor Q1 serves as the output terminal of the first state transition circuit, outputting the signal alarm1 that the encoding chip U2 can receive.

[0033] The second state transition circuit includes an eighteenth state transition current-limiting resistor R18, a twenty-second state transition grounding resistor R22, a fourteenth state transition pull-up resistor R14, and a second state transition transistor Q2; The input terminal of the second state transition circuit is connected to the gate of the second state transition transistor Q2 through the eighteenth state transition current limiting resistor R18. The 22nd state transition grounding resistor R22 is connected between the gate of the second state transition transistor Q2 and ground; the source of the second state transition transistor Q2 is grounded; the first power supply (VCC) is connected to the drain of the second state transition transistor Q2 through the 14th state transition pull-up resistor R14; the drain of the second state transition transistor Q2 serves as the output terminal of the second state transition circuit, outputting the signal alarm2 that the encoding chip U2 can receive.

[0034] The third state transition circuit includes a nineteenth state transition current-limiting resistor R19, a twenty-third state transition grounding resistor R23, a fifteenth state transition pull-up resistor R15, and a third state transition transistor Q3; The input terminal of the third state transition circuit is connected to the gate of the third state transition transistor Q3 through the nineteenth state transition current limiting resistor R19. The 23rd state transition grounding resistor R23 is connected between the gate of the third state transition transistor Q3 and ground; the source of the third state transition transistor Q3 is grounded; the first power supply (VCC) is connected to the drain of the third state transition transistor Q3 through the 15th state transition pull-up resistor R15; the drain of the third state transition transistor Q3 serves as the output terminal of the third state transition circuit, outputting the signal alarm3 that the encoding chip U2 can receive.

[0035] In this preferred embodiment, the bypass switch closure detection circuit further includes a detection pull-up resistor, a detection current-limiting resistor, a detection voltage divider resistor, and a detection protection diode; One end of the corresponding auxiliary contact of the bypass switch is grounded, and the other end is connected to the control terminal of the switching transistor through a detection current-limiting resistor; the switching transistor is a triode, the control terminal of the switching transistor is the gate, one end of the switching transistor is the drain, and the other end is the source; the detection voltage divider resistor is connected between the control terminal of the switching transistor and ground; The second power supply VD is connected to the other end of the corresponding auxiliary contact of the bypass switch through the detection pull-up resistor; The anode of the protection diode is grounded, and the cathode is connected to the gate of the switching transistor.

[0036] Specifically, the bypass switch closure detection circuit includes a first bypass switch closure detection circuit and a second bypass switch closure detection circuit; the bypass switch auxiliary contacts include a first auxiliary contact S1 and a second auxiliary contact S2 of the bypass switch; The switching transistor in the first bypass switch closure detection circuit is the sixth switching transistor Q6; The first bypass switch closure detection circuit also includes a twenty-seventh detection pull-up resistor R27, a twenty-ninth detection current-limiting resistor R29, a thirty-second detection voltage divider resistor R32, and a third detection protection diode D3; One end of the first auxiliary contact S1 of the bypass switch is grounded, and the other end is connected to the control terminal of the sixth switch Q6 through the twenty-ninth detection current-limiting resistor R29. The sixth switch Q6 is a transistor, the control terminal of the sixth switch Q6 is the gate, one end of the sixth switch Q6 is the drain, and the other end is the source. The thirty-second detection voltage divider resistor R32 is connected between the control terminal of the sixth switch Q6 and ground. The second power supply VD is connected to the other end of the first auxiliary contact S1 of the bypass switch through the twenty-seventh detection pull-up resistor R27. The anode of the third detection protection diode D3 is grounded, and the cathode is connected to the gate of the sixth switching transistor Q6.

[0037] The switching transistor in the second bypass switch closure detection circuit is the fifth switching transistor Q5; The second bypass switch closure detection circuit also includes a twenty-sixth detection pull-up resistor R26, a twenty-eighth detection current-limiting resistor R28, a thirty-first detection voltage divider resistor R31, and a second detection protection diode D2; One end of the second auxiliary contact S2 of the bypass switch is grounded, and the other end is connected to the control terminal of the fifth switch Q5 through the twenty-eighth detection current-limiting resistor R28. The fifth switch Q5 is a transistor, with the control terminal of the fifth switch Q5 being the gate, one end of the fifth switch Q5 being the drain, and the other end being the source. The thirty-first detection voltage divider resistor R31 is connected between the control terminal of the fifth switch Q5 and ground. The twenty-sixth detection pull-up resistor R26 is connected to the other end of the second auxiliary contact S2 of the bypass switch; The anode of the second detection protection diode D2 is grounded, and the cathode is connected to the gate of the fifth switching transistor Q5. Preferably, in this embodiment, the optical port driving module includes an optical path driving current-limiting resistor, an optical path driving shunt resistor, an optical path driving filter capacitor, a protection diode, and a reverse protection diode. The second power supply VD is connected to the anode of the diode in the optical port TSM1 via the optical path driving current-limiting resistor. The signal fiber_FB output by the encoding / decoding module is connected to the cathode of the anti-reverse diode, and the anode of the anti-reverse diode is connected to the cathode of the corresponding optical port diode. The protection diode, the optical path drive filter capacitor, and the optical path drive shunt resistor are connected in parallel across the anode and cathode of the corresponding optical port diode. The cathode of the protection diode is connected to the anode of the corresponding optical port diode, and the anode of the protection diode is connected to the cathode of the corresponding optical port diode.

[0038] It should be noted that the optical path driver current limiting resistor limits the working current of the optical port, the optical path driver shunt resistor prevents the optical port from emitting light erroneously due to weak current, the optical path driver filter capacitor suppresses voltage fluctuations, the protection diode prevents electrostatic damage to the corresponding optical port, and the anti-reverse diode prevents reverse power connection. The two optical port driving circuits have the same structure, namely the first optical port driving circuit and the second optical port driving circuit.

[0039] Specifically, the first optical port driving circuit includes a 25th optical path driving current-limiting resistor R25, a 30th optical path driving shunt resistor R30, a 6th optical path driving filter capacitor C6, a first protection diode D1, and a fourth anti-reverse diode D4; the second power supply VD is connected to the anode of the diode of the first optical port TSM1 through the 25th optical path driving current-limiting resistor R25, and FB is connected to the cathode of the fourth anti-reverse diode D4, and the anode of the fourth anti-reverse diode D4 is connected to the cathode of the diode of the first optical port TSM1; the first protection diode D1, the 6th optical path driving filter capacitor C6, and the 30th optical path driving shunt resistor R30 are connected in parallel across the anode and cathode of the diode of the first optical port TSM1; wherein, the cathode of the first protection diode D1 is connected to the anode of the diode of the first optical port TSM1, and the anode of the first protection diode D1 is connected to the cathode of the diode of the first optical port TSM1.

[0040] The second optical port driving circuit includes a 33rd optical path driving current-limiting resistor R33, a 34th optical path driving shunt resistor R34, a 7th optical path driving filter capacitor C7, a 5th protection diode D5, and a 6th reverse protection diode D6. The second power supply VD is connected to the anode of the diode of the second optical port TSM2 through the 33rd optical path driving current-limiting resistor R33. FB is connected to the cathode of the 6th reverse protection diode D6, and the anode of the 6th reverse protection diode D6 is connected to the cathode of the diode of the second optical port TSM2. The 5th protection diode D5, the 7th optical path driving filter capacitor C7, and the 34th optical path driving shunt resistor R34 are connected in parallel across the anode of the diode of the second optical port TSM2 and the cathode of the diode of the second optical port TSM2. Among them, the cathode of the 5th protection diode D5 is connected to the anode of the diode of the second optical port TSM2, and the anode of the 5th protection diode D5 is connected to the cathode of the diode of the second optical port TSM2.

[0041] It should be noted that pins 3 and 4 of the optical ports of TSM1 and TSM2 are fixed pins and have no electrical significance, but they need to be connected to ground.

[0042] In addition, the second power supply VD and the first power supply VCC have different voltage levels.

[0043] Embodiment 2 of the present invention proposes a power module bypass state feedback method based on the circuit described in Embodiment 1 of the present invention, comprising: Obtain the power supply status of the bypass driver board, the main power supply status of the bypass trigger, and the redundant power supply status of the bypass trigger; Generate a set number of signals of different frequencies; based on the main power supply status of the bypass trigger, the redundant power supply status of the bypass trigger, and the power supply status of the bypass driver board, select the target frequency signal from the generated set number of signals of different frequencies; If the bypass switch is open, both auxiliary contacts of the bypass switch are open, and the switching transistors of the two bypass switch closure detection circuits are not conducting; both optical port drive modules output drive signals with the same frequency as the target frequency signal. When the drive signal is low, the two optical ports emit corresponding optical signals; when the bypass switch is closed, some auxiliary contacts are closed, some bypass switch closure detection circuits are conducting, the two optical port start modules output low levels, and the two optical ports are constantly lit.

[0044] In this preferred embodiment, the step of selecting the target frequency signal from a set number of signals of different frequencies based on the main power supply state of the bypass trigger, the redundant power supply state of the bypass trigger, and the power supply state of the bypass driver board specifically involves: If the main power supply status of the bypass trigger is abnormal, the main power supply alarm signal CV_1 of the bypass trigger will be high, otherwise it will be low; if the redundant power supply status of the bypass trigger is abnormal, the auxiliary power supply alarm signal CV_2 of the bypass trigger will be high, otherwise it will be low; if the power supply status of the bypass driver board is abnormal, the power supply status alarm signal POWER of the bypass driver board will be high, otherwise it will be low; the binary signal corresponding to the high level is 1, and the other is 0. The binary signal corresponding to the bypass trigger main power supply alarm signal CV_1 is used as the least significant bit of a binary number; the binary signal corresponding to the bypass trigger auxiliary power supply alarm signal CV_2 is used as the second least significant bit of the corresponding binary number; the binary signal corresponding to the bypass driver board power supply status alarm signal POWER is used as the most significant bit of the corresponding binary number. The binary number is decoded into a decimal number, with a set number of 8 possible values. The signals with the set number of frequencies are then sorted from high to low frequency. The decoded decimal number is the number of the sorted target frequency signal.

[0045] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the protection scope of the claims of the present invention.

Claims

1. A power module bypass status feedback circuit, comprising a frequency generation module, a frequency division module, an encoding / decoding module, two optical port driving modules, and two bypass switch closure detection circuits, characterized in that: The frequency generation module generates a square wave of a fixed frequency, which is set according to the desired feedback delay. The frequency division module divides the square wave of the fixed frequency generated by the frequency generation module to generate a set number of frequency signals. The encoding / decoding module includes an encoding chip, three state transition circuits, and peripheral circuits. The bypass trigger main power supply alarm signal, bypass trigger auxiliary power supply alarm signal, and bypass driver board power supply status alarm signal are each input to a state transition circuit. Each state transition circuit performs level conversion on the received corresponding signal and outputs a signal adapted to the input control terminal of the encoding chip. The output terminal of each state transition circuit is connected to a different input control terminal of the encoding chip. Each frequency signal generated by the frequency divider module is connected to a different data input terminal of the encoding chip. The encoding chip decodes the corresponding signals input from all input control terminals and selects a corresponding signal from a data input terminal as its output. The output terminal of the encoding chip is connected to the input terminal of the peripheral circuits. The peripheral circuits perform level conversion on the output of the encoding chip to generate a frequency signal adapted to the optical port driver module. The two bypass switch closure detection circuits have the same structure, each including a switching transistor. One end of the switching transistor in both bypass switch closure detection circuits is connected to the output of the encoding / decoding module, and the other end is grounded. The switching transistors of the two bypass switch closure detection circuits are controlled to conduct based on whether the two auxiliary contacts of the bypass switch are closed or open. The input terminals of both optical port driver modules are connected to the output terminals of the encoding / decoding module, and each generates an optical port driver signal to drive the corresponding optical port.

2. The power module bypass state feedback circuit according to claim 1, characterized in that: The frequency generation module consists of a crystal oscillator (X1), a first pull-up resistor (R1), and a π-type filter circuit; The first power supply (VCC) is connected to the input terminal of the π-type filter circuit. One end of the first pull-up resistor (R1), the power supply pin of the crystal oscillator (X1), and the output terminal of the π-type filter circuit are connected. The other end of the first pull-up resistor (R1) is connected to the enable pin of the crystal oscillator (X1). The π-type filter circuit includes a first capacitor (C1), a second capacitor (C2), a third capacitor (C3), and a first inductor (L1). One end of the first inductor (L1) and the third capacitor (C3) are connected as the input terminal of the π-type filter circuit, and the other end of the first inductor (L1) serves as the output terminal of the π-type filter circuit. The other end of the third capacitor (C3) is grounded, and the first capacitor (C1) and the second capacitor (C2) are connected in parallel between the other end of the first inductor (L1) and ground.

3. The power module bypass state feedback circuit according to claim 2, characterized in that: The fixed frequency is set according to the desired feedback delay, specifically as follows: The desired feedback delay is set to 'a', and the number of filtering cycles after the receiving end acquires the square wave is 'n'. Then the fixed frequency is greater than or equal to 128 multiplied by n and then divided by 'a'. The receiving end is a board connected to each optical port.

4. The power module bypass state feedback circuit according to claim 1, characterized in that: The frequency division module generates a set number of signals at different frequencies, specifically: The frequency divider module includes a counter (U1), which generates a set number of signals of different frequencies for output by performing different frequency divisions. Alternatively, a set number of signals of different frequencies can be generated by different frequency divisions using a counter (U1), and these signals, together with the signals output by the frequency generation module, can be combined to form a set number of signals of different frequencies for output.

5. A power module bypass state feedback circuit according to claim 1, characterized in that: The peripheral circuit includes the twentieth current-limiting resistor (R20), the fourth transistor (Q4), the sixteenth pull-up resistor (R16), and the twenty-fourth voltage divider resistor (R24), and includes: The output signal (fiber_tir) of the encoding chip (U2) is connected to the gate of the fourth transistor (Q4) through the twentieth current-limiting resistor (R20). The first power supply (VCC) is connected to the output signal (fiber_tir) of the encoding chip (U2) through the sixteenth pull-up resistor (R16). The twenty-fourth voltage divider resistor (R24) is connected between the gate of the fourth transistor (Q4) and ground. The source of the fourth transistor (Q4) is grounded, and the drain of the fourth transistor (Q4) is the output of the encoding / decoding module.

6. The power module bypass state feedback circuit according to claim 1, characterized in that: The three state transition circuits have the same structure, each including a state transition current-limiting resistor, a state transition grounding resistor, a state transition pull-up resistor, and a state transition transistor; The input terminal of the state transition circuit is connected to the gate of the state transition transistor through a state transition current-limiting resistor; The state transition grounding resistor is connected between the gate of the state transition transistor and ground; the source of the state transition transistor is grounded; the first power supply (VCC) is connected to the drain of the state transition transistor through the state transition pull-up resistor; the drain of the state transition transistor serves as the output terminal of the state transition circuit.

7. The power module bypass state feedback circuit according to claim 1, characterized in that: The bypass switch closure detection circuit also includes a pull-up resistor detection circuit, a current-limiting resistor detection circuit, a voltage divider resistor detection circuit, and a protection diode detection circuit. One end of the corresponding auxiliary contact of the bypass switch is grounded, and the other end is connected to the control terminal of the switching transistor through a detection current-limiting resistor; the switching transistor is a triode, the control terminal of the switching transistor is the gate, one end of the switching transistor is the drain, and the other end is the source; the detection voltage divider resistor is connected between the control terminal of the switching transistor and ground; The second power supply (VD) is connected to the other end of the corresponding auxiliary contact of the bypass switch by detecting the pull-up resistor; The anode of the protection diode is grounded, and the cathode is connected to the gate of the switching transistor.

8. A power module bypass state feedback circuit according to claim 1, characterized in that: The optical port driver module includes an optical path driver current limiting resistor, an optical path driver shunt resistor, an optical path driver filter capacitor, a protection diode, and a reverse protection diode; The second power supply (VD) is connected to the anode of the diode in the optical port TSM1 via the optical path driving current-limiting resistor. The signal fiber_FB output by the encoding / decoding module is connected to the cathode of the anti-reverse diode, and the anode of the anti-reverse diode is connected to the cathode of the corresponding optical port diode. The protection diode, the optical path drive filter capacitor, and the optical path drive shunt resistor are connected in parallel across the anode and cathode of the corresponding optical port diode. The cathode of the protection diode is connected to the anode of the corresponding optical port diode, and the anode of the protection diode is connected to the cathode of the corresponding optical port diode.

9. A power module bypass state feedback method based on the circuit according to any one of claims 1-8, characterized in that, include: Obtain the power supply status of the bypass driver board, the main power supply status of the bypass trigger, and the redundant power supply status of the bypass trigger; Generate a set number of signals at different frequencies; Based on the main power supply state of the bypass trigger, the redundant power supply state of the bypass trigger, and the power supply state of the bypass driver board, the target frequency signal is selected from the generated signals of a set number of frequencies. If the bypass switch is open, both auxiliary contacts of the bypass switch will be open, and the switching transistors of the two bypass switch closure detection circuits will not be turned on; both optical port drive modules will output drive signals with the same frequency as the target frequency signal. When the drive signal is low, the two optical ports will emit corresponding optical signals. When the bypass switch is closed, the auxiliary contact is closed, the switching transistor of the bypass switch closure detection circuit is turned on, the two optical port start modules output a low level, and the two optical ports are constantly lit.

10. A power module bypass state feedback method according to claim 9, characterized in that: The selection of a target frequency signal from a set number of signals based on the main power supply state, redundant power supply state, and power supply state of the bypass trigger and the bypass driver board is as follows: If the main power supply status of the bypass trigger is abnormal, the main power supply alarm signal of the bypass trigger will be high, otherwise it will be low; if the redundant power supply status of the bypass trigger is abnormal, the auxiliary power supply alarm signal of the bypass trigger will be high, otherwise it will be low; if the power supply status of the bypass driver board is abnormal, the power supply status alarm signal of the bypass driver board will be high, otherwise it will be low; the binary signal corresponding to the high level is 1, otherwise it is 0. The binary signal corresponding to the bypass trigger main power supply alarm signal is the least significant bit of a binary number; the binary signal corresponding to the bypass trigger auxiliary power supply alarm signal is the second least significant bit of the corresponding binary number; the binary signal corresponding to the bypass driver board power supply status alarm signal is the most significant bit of the corresponding binary number. The binary number is decoded into a decimal number, with a set number of 8 possible values. The signals with the set number of frequencies are then sorted from high to low frequency. The decoded decimal number is the number of the sorted target frequency signal.

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