Device layout method and device of highly accelerated stress test carrier plate, and electronic equipment

Abstract

The invention relates to the technical field of integrated circuit packaging, and provides a device layout method and device of a highly accelerated stress test carrier plate, and electronic equipment. The method comprises the following steps: determining a to-be-arranged device corresponding to each target pin line of a to-be-tested chip, and determining an initial coordinate of the corresponding to-be-arranged device based on a tail end point coordinate of the target pin line; grouping each to-be-arranged device based on the initial coordinate of each to-be-arranged device to obtain grouping information corresponding to each to-be-arranged device; based on the grouping information corresponding to each to-be-arranged device, performing offset adjustment on the initial coordinate corresponding to each to-be-arranged device to obtain a target layout coordinate of each to-be-arranged device, and through progressive adjustment of first grouping and second offset, enabling the to-be-arranged devices which are originally densely distributed in a local area and even have overlapped projections to be distributed in the local area, so as to obtain the target layout coordinate of each to-be-arranged device. And finally, a matrix type step array with standard spacing and ordered arrangement is presented on the circuit board.

Description

Technical Field

[0001] This application relates to the field of integrated circuit packaging technology, and in particular to a device layout method, apparatus and electronic device for a high-accelerated stress test substrate. Background Technology

[0002] With the rapid development of integrated circuit packaging technology, the pin density of ball grid array (BGA) chips is constantly increasing. Especially in high-density test substrate designs such as Highly Accelerated Stress Test (HAST) and Burn-in, a large number of bias resistors or decoupling capacitors need to be placed around the chip to provide stable pin bias voltage for HAST testing.

[0003] In existing PCB design workflows, the placement of such devices primarily relies on manual processing, as the chips under test typically have hundreds or even thousands of pins. Designers need to identify the pin net names one by one, find the corresponding schematic components, and manually move the resistors to the corresponding pin leads. Given the massive number of pins, manual placement is extremely time-consuming and prone to misalignment or omissions. Summary of the Invention

[0004] In view of this, embodiments of this application provide a device layout method, apparatus and electronic device for a high accelerated stress test substrate, to solve the problem that in the prior art, the device layout of a high accelerated stress test substrate is time-consuming and prone to errors due to manual operation.

[0005] A first aspect of this application provides a device layout method for a high-accelerated stress test substrate. The method includes: determining the device to be laid out corresponding to each target pin line of the chip to be tested, and determining the initial coordinates of the corresponding device to be laid out based on the coordinates of the end point of the target pin line; grouping each device to be laid out based on the initial coordinates of each device to be laid out to obtain grouping information corresponding to each device to be laid out; and adjusting the initial coordinates of each device to be laid out based on the grouping information of each device to be laid out to obtain the target layout coordinates of each device to be laid out.

[0006] A second aspect of this application provides a device placement apparatus for a high-accelerated stress test substrate. The apparatus includes: a coordinate module for determining the device to be placed corresponding to each target pin of the chip under test, and determining the initial coordinates of the corresponding device to be placed based on the coordinates of the end point of the target pin; a grouping module for grouping each device to be placed based on the initial coordinates of each device to be placed, thereby obtaining grouping information corresponding to each device to be placed; and an adjustment module for offsetting and adjusting the initial coordinates of each device to be placed based on the grouping information corresponding to each device to be placed, thereby obtaining the target placement coordinates of each device to be placed.

[0007] A third aspect of this application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the above-described method.

[0008] A fourth aspect of this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the above-described method.

[0009] The beneficial effects of this application embodiment compared with the prior art are as follows: The device layout method of the high accelerated stress test carrier board in this application embodiment determines the device to be laid out corresponding to each target pin line, and determines the initial coordinates of the corresponding device to be laid out based on the coordinates of the end point of the target pin line; each device to be laid out is grouped based on the initial coordinates of each device to be laid out to obtain the grouping information corresponding to each device to be laid out; based on the grouping information corresponding to each device to be laid out, the initial coordinates corresponding to each device to be laid out are offset and adjusted to obtain the target layout coordinates of each device to be laid out. Specifically, this application first determines the target layout coordinates based on the coordinates of the end point of the target pin line. Initial coordinates are assigned to the devices to be laid out, and a preliminary sorting is achieved using the physical distribution of the devices at their original fan-out positions. Then, each device is grouped, and the group information is determined. This group information is then used to offset and adjust the initial coordinates of each device, resulting in the target layout coordinates. This progressive adjustment, involving grouping followed by offsetting, transforms devices that were initially densely distributed or even overlapping in localized areas into a well-spaced, orderly matrix-like staircase array on the circuit board. This efficient and accurate device placement for high-accelerated stress test boards avoids the time-consuming and error-prone nature of manual device placement in related technologies. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a schematic diagram of a device layout method for a high-acceleration-stress test substrate provided in the application embodiment; Figure 2 This is a schematic diagram of the lead-out pins of a chip under test provided in an embodiment of this application; Figure 3 This is a schematic diagram of a device to be laid out after the layout is completed, provided in an embodiment of this application; Figure 4 This is a schematic diagram of another device layout method for a high-acceleration-stress test substrate provided in an embodiment of this application; Figure 5 This is a schematic diagram of another device layout method for a high-acceleration-stress test substrate provided in the embodiments of this application; Figure 6 This is a schematic diagram of another device layout method for a high-acceleration-stress test substrate provided in the embodiments of this application; Figure 7 This is a schematic diagram of a device layout method for a high-acceleration-stress test substrate provided in an embodiment of this application; Figure 8 This is a schematic diagram of a device layout device for a high-acceleration stress test carrier provided in an embodiment of this application; Figure 9 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0012] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, methods, and approaches are omitted so as not to obscure the description of this application with unnecessary detail.

[0013] The following will describe in detail, with reference to the accompanying drawings, a device layout method and apparatus for a high-acceleration stress test substrate according to an embodiment of this application.

[0014] Figure 1 This is a schematic diagram of a device layout method for a high-acceleration-stress test substrate provided in an embodiment of this application, as shown below. Figure 1As shown, the device layout method of this high-acceleration-stress test substrate includes: S101. Determine the device to be laid out corresponding to each target pin line of the chip under test, and determine the initial coordinates of the corresponding device to be laid out based on the coordinates of the end point of the target pin line. It is understood that the chip under test can be any of the following: a ball grid array (BGA) chip, a land grid array (LGA) chip, or a quad flat package (QFP) chip.

[0015] The chip under test (DUT) contains multiple pins. It's understood that these pins have various signal definitions and types, such as power supply pins, GND pins, and data signal pins. When testing the DUT, the data signal pins need to be connected in series with current-limiting resistors to pull up and down to the corresponding power supply and GND pins. This, along with a voltage divider based on the chip's internal resistance, provides a suitable accelerating voltage to the pins. The power supply pins require only a single-digit fuse and a few filter capacitors. The GND pins only need to be connected to the GND plane without any external components.

[0016] This embodiment identifies the pin type by obtaining the net name or attribute label corresponding to each pin. The identified pin type is then matched against a preset test requirement list, which records the target pin types (such as high-speed differential signal names, specific data bus labels, etc.) for which peripheral device placement is required. If the pin type of any pin successfully matches a target pin type in the test requirement list, that pin is identified as the target pin, and the pin line connected to it is designated as the target pin line. This step effectively eliminates interference data such as power, ground, and floating pins, providing a precise processing target for subsequent automated placement. This significantly reduces the computational burden on the algorithm while avoiding redundant or incorrect device placement on the circuit board.

[0017] It is understandable that, as a geometric entity on a circuit board, a pin has a variety of physical and logical attributes. Specifically, the attributes of a pin include, but are not limited to: the starting point coordinates (i.e., the center position of the pad connected to the chip pin), the ending point coordinates (i.e., the exit position of the pin as it fans out from under the chip under test to the peripheral area), the pin's net name, and the corresponding pin type.

[0018] The coordinates of the end point of the pin are calculated based on the coordinates of the starting point and the preset fan-out design specifications. In some examples, the fan-out design specifications include, but are not limited to: fan-out angle, fan-out length threshold, via position constraints, and clearance constraints.

[0019] For example, the pin line starts from the pin starting point under the chip under test and fans out to the outer open area of ​​the chip body at a preset fan-out angle (such as 45° or 90° direction); when the pin line reaches the preset length threshold, or reaches the center point of the layer switching via used for inter-layer switching, the position of the pin line end point is defined as the end point coordinate.

[0020] After determining the target pin, this application automatically retrieves and locks the pre-defined placement device (such as bias resistor, voltage divider resistor, or matching capacitor) for each target pin by analyzing the connection relationship of the circuit schematic or the netlist information. Subsequently, this application executes a coordinate mapping procedure, directly assigning the coordinates of the end point of the target pin to the corresponding placement device as the initial coordinates of the placement device, thereby logically completing the precise connection between the placement device and the target pin.

[0021] It is understandable that if the initial coordinates of the devices to be laid out are directly used as the final coordinates after assigning them initial coordinates, the high density of the pin array of the chip under test will lead to a large number of devices being too crowded in physical space or even overlapping coordinates, which will fail to meet the clearance requirements of the circuit board. Therefore, after the initial positioning, it is necessary to further offset and adjust the initial coordinates of the devices to be laid out in order to obtain the target layout coordinates that meet the design specifications.

[0022] In some examples (especially for multi-layer circuit board designs), the target pin line typically carries its layer number (i.e., layer information). The device to be placed inherits this layer information along with its initial coordinates. This layer information will serve as the core parameter for subsequent calculation of offset weights. Through this attribute inheritance mechanism, this application can transform the originally scattered physical parameters into logical objects with multi-dimensional spatial attributes, thereby solving the problem of isolated layout information caused by physical layers in multi-layer routing, and laying a solid data foundation for subsequent implementation of cross-layer, non-overlapping, step-by-step automated layout.

[0023] S102. Group each device to be laid out based on its initial coordinates to obtain the grouping information corresponding to each device to be laid out. It is understandable that the pin distribution of the chip under test (such as a BGA chip) has a distinct regional distribution. Specifically, the pins of chip under test 1 are distributed on the four sides of the chip body, such as... Figure 2 As shown, the pin line 2 corresponding to the pin on the left side of the chip under test 1 typically fan out to the left, and the pin line 2 corresponding to the pin on the right side fan out to the right. Similarly, the pin lines 2 corresponding to the pins above and below fan out to the upper and lower sides, respectively. Since the initial coordinates of the device to be placed are mapped from the coordinates of the end points of the pin lines, the spatial distribution of the device to be placed naturally forms four clustered arrays surrounding the chip under test.

[0024] This application obtains the initial coordinates of each device to be laid out and analyzes its geometric orientation in the current coordinate system, thereby dividing it into: a left group (first group on the horizontal axis), a right group (second group on the horizontal axis), an upper group (first group on the vertical axis), and a lower group (second group on the vertical axis). Specifically, by traversing the initial coordinates of all devices to be laid out, the distribution trend of the initial coordinates of the devices on the horizontal axis (X-axis) is identified. The set of devices at the negative extension end of the horizontal axis is defined as the "left group"; the set of devices at the positive extension end of the horizontal axis is defined as the "right group". Similarly, the distribution trend of the initial coordinates of the devices to be laid out on the vertical axis (Y-axis) is identified. The set of devices at the positive extension end of the vertical axis is defined as the "upper group"; the set of devices at the negative extension end of the vertical axis is defined as the "lower group".

[0025] It is understood that this application generates corresponding grouping information for each device to be laid out based on the above rules. This grouping information not only includes a logical label for the orientation (such as "left group"), but also presets the offset axis corresponding to the group. For example, if the grouping information is "left group" or "right group", its subsequent offset axis is set to the vertical axis (y-axis); if the grouping information is "top group" or "bottom group", its subsequent offset axis is set to the horizontal axis (x-axis). This method of automatically locking the orientation grouping through the initial coordinates can ensure that subsequent offset adjustments are always made along the divergence direction of the pin line fan-out, thereby fundamentally avoiding the problems of trace backtracking, crossing, and spatial interference.

[0026] S103. Based on the grouping information corresponding to each device to be laid out, the initial coordinates corresponding to each device to be laid out are offset and adjusted to obtain the target layout coordinates of each device to be laid out. It is understandable that the pins of the chip under test are highly dense. If the device to be laid out is placed directly at the end of the pin line (i.e., at the initial coordinates), the spacing between adjacent devices will be too small, failing to meet the circuit board manufacturing specifications (such as DFM spacing requirements). Therefore, this application performs a directional coordinate transformation on the initial coordinates of the device to be laid out based on the grouping information of the device to be laid out, so as to achieve the orderly expansion of the device in physical space.

[0027] Specifically, if the grouping information of the devices to be laid out corresponds to the left group or the right group, this application adjusts the initial coordinates of the devices to be laid out on the vertical axis (Y-axis). By making the devices to be laid out on the same side staggered from each other in the vertical direction, the spacing of the devices to be laid out on the Y-axis is increased, thereby avoiding physical interference when arranged vertically.

[0028] If the grouping information of the devices to be laid out corresponds to the upper or lower group, this application adjusts the initial coordinates of the devices to be laid out by offsetting them on the horizontal axis (X-axis). By making the devices on the same side staggered from each other in the horizontal direction, the spacing of the devices to be laid out on the X-axis is increased, thereby avoiding physical interference when arranged laterally.

[0029] In some examples, when multi-layer wiring designs are involved, the pin ends of different layers may overlap or be extremely close in planar projection. To solve this projection overlap problem, this application, based on the above-mentioned spacing adjustment, further performs an outward-expanding offset adjustment on the corresponding offset axis: for the left or right group, this application applies a displacement increment on the horizontal axis (X-axis) away from the chip center. For the upper or lower group, this application applies a displacement increment on the vertical axis (Y-axis) away from the chip center.

[0030] It is understood that, through the aforementioned directional coordinate transformation, this application converts the initial coordinates into mutually independent and neatly arranged target layout coordinates, and then adjusts the device 3 to be laid out according to the target layout coordinates. The adjusted device 3 is as follows: Figure 3 As shown. This step-by-step, multi-dimensional offset adjustment not only ensures the processing spacing of components within a single layer, but also solves the problem of spatial overlap in multi-layer designs, providing a clear physical path for subsequent automated routing.

[0031] According to the technical solution provided in the embodiments of this application, this application determines the target pin line corresponding to the target pin type from multiple pin lines of the chip under test; determines the device to be placed corresponding to each target pin line, and determines the initial coordinates of the corresponding device to be placed based on the coordinates of the end point of the target pin line; groups each device to be placed based on the initial coordinates of each device to be placed to obtain grouping information corresponding to each device to be placed; and adjusts the initial coordinates of each device to be placed based on the grouping information corresponding to each device to be placed to obtain the target placement coordinates of each device to be placed. Specifically, this application first determines the target pin line based on the end point of the target pin line... Point coordinates assign initial coordinates to the devices to be laid out, and the physical distribution of the devices in the original fan-out positions achieves preliminary sorting. Then, each device is grouped, and the group information to which the device belongs is determined. This group information is then used to offset and adjust the initial coordinates of each device, resulting in the target layout coordinates for each device. Through this progressive adjustment of grouping followed by offsetting, the devices, which were originally densely distributed or even overlapping in local areas, are ultimately presented as a matrix-like stepped array with standardized spacing on the circuit board. This efficiently and accurately completes the device layout of the high-accelerated stress test substrate. It avoids the time-consuming and error-prone problems associated with manual device layout of high-accelerated stress test substrates in related technologies.

[0032] In some examples, this application also provides a device layout method for a high-acceleration-stress test substrate, such as... Figure 4 As shown, the method includes: S401. Determine the device to be laid out corresponding to each target pin line, and determine the initial coordinates of the corresponding device to be laid out based on the coordinates of the end point of the target pin line. Step S401 is essentially the same as step S101 in the above embodiment, and will not be described again here.

[0033] S402. Traverse the initial coordinates of all devices to be laid out, and obtain the first coordinate group value corresponding to the first direction on the vertical axis, the second coordinate group value corresponding to the second direction on the vertical axis, the third coordinate group value corresponding to the third direction on the horizontal axis, and the fourth coordinate group value corresponding to the fourth direction on the horizontal axis. The first direction and the second direction are opposite directions, and the third direction and the fourth direction are opposite directions. In this embodiment, the present application determines the geometric boundary extreme values ​​of the outer perimeter of the chip under test by performing a global traversal of the initial coordinates of all devices to be laid out, and uses these extreme values ​​as the physical reference for subsequent automatic grouping.

[0034] Specifically, this application performs numerical retrieval along two opposite directions, the vertical axis (Y-axis) and the horizontal axis (X-axis), in the two-dimensional coordinate system of the circuit board, to obtain the first coordinate group value, the second coordinate group value, the third coordinate group value and the fourth coordinate group value.

[0035] For example, taking the horizontal axis (X-axis) as an example, this application retrieves the ordinate values ​​of all initial coordinates along the positive direction of the vertical axis (i.e., the first direction) and determines the maximum retrieved ordinate value as the first coordinate group value corresponding to the first direction; it retrieves the ordinate values ​​of all initial coordinates along the negative direction of the vertical axis (i.e., the second direction) and determines the minimum retrieved ordinate value as the second coordinate group value corresponding to the second direction.

[0036] Similarly, taking the horizontal axis (X-axis) as an example, this application retrieves the x-coordinate values ​​of all initial coordinates along the negative direction of the horizontal axis (i.e., the third direction) and determines the smallest retrieved x-coordinate value as the third coordinate group value corresponding to the third direction; it retrieves the x-coordinate values ​​of all initial coordinates along the positive direction of the horizontal axis (i.e., the fourth direction) and determines the largest retrieved x-coordinate value as the fourth coordinate group value corresponding to the fourth direction.

[0037] It is understandable that the pins of the chip under test (such as a BGA chip) are typically arranged in a matrix array. The four coordinate grouping values ​​obtained through the above traversal retrieval precisely locate the outermost rectangular boundary of the current device layout, corresponding to the upper, lower, left, and right boundaries of the fan-out region of the chip under test. This grouping benchmark, based on automatic extraction of extreme values, can dynamically adapt to chip designs of different sizes and pin densities, providing a deterministic numerical basis for the automated classification in subsequent step S404.

[0038] It is understood that the method by which this application obtains coordinate grouping values ​​(first coordinate grouping value, second coordinate grouping value, third coordinate grouping value, and fourth coordinate grouping value) is not limited to extracting the maximum / minimum horizontal and vertical coordinate values. In other embodiments, this application may also identify densely distributed regions of initial coordinate points by performing clustering analysis algorithms, and select the center coordinates or edge envelopes of each dense region as coordinate grouping values; or, based on the physical size of the chip under test (Package Size) combined with a preset fan-out length, directly calculate the theoretical boundary value as the grouping benchmark. These variations can all achieve the technical objective of classifying discrete initial coordinates into different orientation groups, and all fall within the protection scope of this application.

[0039] S403. Match the initial coordinates of each device to be laid out with the first coordinate group value, the second coordinate group value, the third coordinate group value and the fourth coordinate group value respectively, and determine the grouping information of each device to be laid out based on the matching results. Specifically, this application obtains the initial coordinates of each device to be laid out, and then matches the horizontal and vertical coordinate components of the initial coordinates with the first coordinate grouping value, the second coordinate grouping value, the third coordinate grouping value, and the fourth coordinate grouping value obtained in S402, respectively.

[0040] In some examples, a successful match is determined when the coordinate components of the initial coordinates are exactly equal to the values ​​of the corresponding coordinate groupings; a failed match is determined when the coordinate components of the initial coordinates are not equal to the values ​​of the corresponding coordinate groupings.

[0041] In some examples, due to potential accuracy loss during the conversion of circuit board design data between different EDA software, or slight offset caused by the snapping effect of the design grid, this application defines the following matching rules: that is, if the absolute value of the difference between the coordinate component of the initial coordinate and the corresponding coordinate group value is less than a preset error threshold, the match is determined to be successful; if the absolute value of the difference between the coordinate component of the initial coordinate and the corresponding coordinate group value is greater than or equal to the preset error threshold, the match is determined to be unsuccessful. This method effectively avoids missed judgments caused by coordinate accuracy conversion or slight grid offset in circuit board design.

[0042] Taking the first coordinate group value corresponding to the first vertical axis group, the second coordinate group value corresponding to the second vertical axis group as an example, the third coordinate group value corresponding to the first horizontal axis group, and the fourth coordinate group value corresponding to the second horizontal axis group as an example.

[0043] If the horizontal coordinate value (X-axis component) of the initial coordinates of the device to be laid out matches the value of the third coordinate group (the horizontal coordinate value is equal to the value of the third coordinate group, or the difference between the horizontal coordinate value and the value of the third coordinate group is less than a preset threshold, and the principle is the same thereafter, so it will not be repeated), then the device to be laid out is determined to belong to the first group of the horizontal axis corresponding to the value of the third coordinate group.

[0044] If the horizontal coordinate value of the device to be laid out matches the value of the fourth coordinate group, then the device to be laid out is determined to belong to the second group of the horizontal axis corresponding to the value of the fourth coordinate group.

[0045] If the ordinate value (Y-axis component) in the initial coordinates of the device to be laid out matches the first coordinate group value, then the device to be laid out is determined to belong to the first vertical axis group corresponding to the first coordinate group value.

[0046] If the ordinate value in the initial coordinates of the device to be laid out matches the second coordinate group value, then the device to be laid out is determined to belong to the second group of the vertical axis corresponding to the second coordinate group value.

[0047] S404. Based on the grouping information corresponding to each device to be laid out, the initial coordinates corresponding to each device to be laid out are offset and adjusted to obtain the target layout coordinates of each device to be laid out.

[0048] Step S404 is essentially the same as step S103 in the above embodiment, and will not be described again here.

[0049] According to the technical solution provided in this application, the initial coordinates of all devices to be laid out are traversed to obtain the first coordinate grouping value corresponding to the first direction on the vertical axis, the second coordinate grouping value corresponding to the second direction on the vertical axis, the third coordinate grouping value corresponding to the third direction on the horizontal axis, and the fourth coordinate grouping value corresponding to the fourth direction on the horizontal axis. The first and second directions are opposite directions, as are the third and fourth directions. The initial coordinates of each device to be laid out are matched with the first, second, third, and fourth coordinate grouping values, respectively. The grouping information of each device to be laid out is determined based on the matching results. This application actively obtains four coordinate grouping values ​​on the vertical axis (first and second directions) and the horizontal axis (third and fourth directions) by traversing the initial coordinates of all devices to be laid out. This achieves automatic identification of the outer boundary of the pin array of the chip under test, eliminating the need for manually preset complex boundary parameters or manually delineating grouping areas, greatly improving the efficiency of pre-layout preparation. Furthermore, by matching the initial coordinates of each device with the above four coordinate grouping values, this application can accurately group hundreds or thousands of discrete devices to be laid out into corresponding orientation arrays. This matching method based on physical coordinate grouping values ​​effectively avoids the common problems of omission and incorrect selection in manual operations, and provides a reliable logical basis for subsequent targeted offset adjustments.

[0050] In some examples, this application also provides a device layout method for a high-acceleration-stress test substrate, such as... Figure 5 As shown, the method includes: S501. Determine the device to be laid out corresponding to each target pin line, and determine the initial coordinates of the corresponding device to be laid out based on the coordinates of the end point of the target pin line. This step S501 is essentially the same as step S101 in the above embodiment, and will not be described again here.

[0051] S502. Group each device to be laid out based on its initial coordinates to obtain the grouping information corresponding to each device to be laid out. Step S502 is essentially the same as step S102 in the above embodiment, and will not be described again here.

[0052] S503. Sort the devices to be laid out that have the same grouping information to obtain the sorting result; It is understood that, in order to ensure that the arrangement of the devices to be placed is consistent with the pin fan-out order, the sorting reference dimension should be orthogonal to the offset axis of the corresponding group information of the device to be placed. Specifically, for the horizontal axis grouping (the first horizontal axis group and the second horizontal axis group), this application selects the vertical axis (Y-axis) as the sorting reference axis. For the vertical axis grouping (the first vertical axis group and the second vertical axis group), this application selects the horizontal axis (X-axis) as the sorting reference axis.

[0053] Continuing the previous example, this application extracts the coordinate components of each device to be laid out on the sorting reference axis and performs an ascending or descending sorting from smallest to largest (or largest to smallest). That is, for devices in the first or second group of the horizontal axis, this application obtains the ordinate (Y value) of the initial coordinates of the devices and sorts them in ascending order of value. Each device is then assigned a sorting number. It is understood that if multiple devices in the first or second group of the horizontal axis have the same ordinate (e.g., due to being in the same physical location but belonging to different wiring layers, their initial coordinates lie on the same horizontal line in the planar projection), this application assigns these devices the same sorting number. This mechanism ensures that multiple cross-layer devices in the same column maintain vertical alignment in subsequent layouts.

[0054] For the devices to be laid out in the first and second vertical axis groups, this application obtains the x-coordinate values ​​(X-values) in the initial coordinates of the devices to be laid out, and sorts them in ascending order. Similarly, if the x-coordinates are the same, they are assigned the same sorting number.

[0055] The "sorting result" obtained through the above sorting process essentially establishes the relative topological order between the devices to be placed. Since the initial coordinates are mapped from the end points of the pin lines, this sorting logic ensures that the arrangement order of the devices to be placed is completely aligned with the physical lead-out order of the pins of the chip under test.

[0056] S504. Obtain the preset device spacing and the first offset axis corresponding to each group information; In this embodiment, in order to convert the logical sequence number into precise coordinates in physical space, this application needs to extract preset geometric constraint parameters and orientation offset references.

[0057] Specifically, the first step is to obtain the pre-set device spacing, which refers to the minimum physical distance between the center points of adjacent devices to be placed in the same arrangement sequence. It is understandable that the setting of this device spacing takes into account the physical size of the device itself, the pad spacing, the silkscreen safety spacing, and the processing accuracy requirements of the automatic placement machine (e.g., set to 60mil or 80mil).

[0058] In this application, the device spacing can be obtained from a preset design rule check (DRC) library or a user-defined configuration.

[0059] This application also obtains the first offset axis corresponding to each group information. It is understood that, based on the group information determined in S502, this application assigns a first offset axis for queuing within the same group. To ensure the regularity of the arrangement, the first offset axis is typically consistent with the sorting reference axis used by the devices to be laid out under that group information in S503. That is, for horizontal axis groups (horizontal axis first group and horizontal axis second group), the vertical axis (Y-axis) is used as the corresponding first offset axis. This means that the devices to be laid out on the left / right sides will be arranged sequentially along the Y-axis direction.

[0060] For the horizontal grouping (the first horizontal group and the second horizontal group), this application uses the horizontal axis (X-axis) as the first offset axis corresponding to the horizontal group. This means that the devices to be laid out on the upper / lower sides will be arranged sequentially along the X-axis direction.

[0061] S505. Based on the first offset axis, device spacing, and sorting result corresponding to each group information, the initial coordinates of the devices to be laid out under each group information are offset and adjusted to obtain the target layout coordinates of each device to be laid out.

[0062] In this embodiment, this application uses a coordinate transformation algorithm to convert abstract sorting logic into specific physical displacements, thereby eliminating problems such as layout overlap in the initial coordinates. It is understood that this application considers the sorting result in S504 as the "placement weight" of each device in the queue. By combining a preset device spacing, a linear displacement relative to its initial coordinates is calculated for each device to be laid out, thus transforming devices that were originally densely packed or overlapping at the ends of the corresponding target pin lines into an ordered arrangement that does not obstruct each other in space, according to their order in the topology sequence.

[0063] It is understood that this application first determines the relative displacement within a group of each device to be laid out based on the product of the sequence index of each device in the sorting result and the device spacing. Specifically, this application uses the sequence index (e.g., 0, 1, 2 … n) of each device to be laid out as a coefficient and multiplies it by the aforementioned device spacing. Since the devices to be laid out under the same grouping information obtain displacements distributed in an arithmetic sequence according to their order on the reference axis, they are thus equally spaced apart in physical space.

[0064] Then, the coordinate components corresponding to the first offset axis in the initial coordinates of each device to be laid out are accumulated with the relative displacement within the group to determine the target layout coordinates of each device. Specifically, this application performs directional component transformation based on the first offset axis (queue axis) determined by the grouping information. If the first offset axis is a vertical axis (Y-axis): this application extracts the ordinate component from the initial coordinates of the device to be laid out. Compare it with the relative displacement within the group Perform summation operation ( ), while keeping the x-axis component unchanged, then (x, The first offset axis is used as the target layout coordinate. If the first offset axis is the horizontal axis (X-axis): this application extracts the horizontal coordinate component from the initial coordinates. Compare it with the relative displacement within the group Perform summation operation ( ), while keeping the ordinate component y unchanged.

[0065] The cumulative calculation also includes polarity determination logic. This application automatically adjusts the sign of the displacement based on the orientation of the group. For example, for a group located below the chip, its displacement direction along the Y-axis is negative, so the negative displacement is accumulated; for a group located to the right of the chip, its displacement direction along the X-axis is positive, so the positive displacement is accumulated.

[0066] Through the aforementioned offset adjustments, the potential issues of overlapping or insufficient spacing of components in the initial coordinate state are completely eliminated. The resulting target layout coordinates not only meet the PCB's DFM manufacturing specifications but also ensure a highly regular matrix distribution of all components.

[0067] According to the solution provided in this application, devices to be laid out with the same grouping information are sorted to obtain a sorting result; a pre-set device spacing and a first offset axis corresponding to each grouping information are obtained; then, based on the product of the sequence index of each device to be laid out in the sorting result and the device spacing, the relative displacement within the group of each device to be laid out is determined; the coordinate components corresponding to the first offset axis in the initial coordinates of each device to be laid out are accumulated with the relative displacement within the group to determine the target layout coordinates of each device to be laid out. This application introduces the mathematical model of "product of sequence index and device spacing" to directly transform the originally abstract sorting logic into a precise physical displacement. This calculation method ensures that all devices to be laid out within the same group can be linearly unfolded according to the preset device spacing, eliminating visual errors and dimensional deviations caused by manual spacing adjustments, and making the layout result strictly conform to the spacing specifications in PCB manufacturing.

[0068] Furthermore, since devices at the same initial coordinates but different levels are assigned the same sorting number in step S503, these devices will obtain completely consistent relative displacements within the group, thus maintaining alignment after subsequent offsets. It is understandable that although the offset adjustment in step S505 increases the spacing between devices with different sequence indices along the first offset axis, resolving the crowding problem of devices in the same layer, devices with the same sequence index but belonging to different wiring levels will have the same coordinate components after executing S505, thus remaining overlapping in the planar projection. To avoid interference between these cross-layer devices in physical space and to ensure that each level's pin lines have independent fan-out extension space, this application also provides a device layout method for a high-accelerated stress test substrate. Figure 6 As shown, the method includes: S601. Determine the device to be laid out corresponding to each target pin line, and determine the initial coordinates of the corresponding device to be laid out based on the coordinates of the end point of the target pin line. This step S601 is essentially the same as step S501 in the above embodiment, and will not be described again here.

[0069] S602. Group each device to be laid out based on its initial coordinates to obtain the grouping information corresponding to each device to be laid out. Step S602 is essentially the same as step S502 in the above embodiment, and will not be described again here.

[0070] S603. Sort the devices to be laid out that have the same grouping information to obtain the sorting result; Step S603 is essentially the same as step S503 in the above embodiment, and will not be described again here.

[0071] S604. Obtain the preset device spacing and the first offset axis corresponding to each group information; Step S604 is essentially the same as step S504 in the above embodiment, and will not be described again here.

[0072] S605. Based on the product of the sequence index of each device to be laid out in the sorting result and the device spacing, determine the relative displacement within the group of each device to be laid out. This step is the same as the method for obtaining the relative displacement in step S505 above, and will not be described again here.

[0073] S606. The coordinate components corresponding to the first offset axis in the initial coordinates of each device to be laid out are accumulated with the relative displacement within the group to obtain the intermediate layout coordinates. Specifically, this application performs directional component transformation based on the first offset axis (queue axis) determined by the grouping information. If the first offset axis is a vertical axis (Y-axis): this application extracts the ordinate component from the initial coordinates of the device to be laid out. Compare it with the relative displacement within the group Perform summation operation ( ), while keeping the x-axis component unchanged, then (x, This is used as the intermediate layout coordinate. Similarly, if the first offset axis is the horizontal axis (X-axis): this application extracts the horizontal coordinate component from the initial coordinates. Compare it with the relative displacement within the group Perform summation operation ( ), while keeping the ordinate component y unchanged, then ( , y) are used as the intermediate layout coordinates.

[0074] S607. Obtain the layer information of the target pin line corresponding to each device to be laid out, and determine the relative layer displacement of each device to be laid out according to the layer information and the preset layer spacing. In this embodiment, the present application utilizes the spatial depth information of the circuit board to guide the distribution of the devices to be laid out on the plane.

[0075] Specifically, this application identifies the routing layer (e.g., Layer 1 or Layer 3) of the target pin line of each device to be laid out. Then, based on a preset layer spacing (a preset physical step size used to distinguish devices at different layers, such as 120 mil), and combined with the layer information of the device to be laid out, the relative layer displacement is calculated. For example, if the layer spacing is L and the layer information of the device to be laid out is n, then the relative layer displacement is... Through this logic, the devices to be laid out corresponding to pins at different depths will obtain the corresponding hierarchical relative displacement.

[0076] S608. The coordinate components corresponding to the second offset axis in the intermediate layout coordinates of each device to be laid out are accumulated with the relative displacement of the layers to obtain the target layout coordinates of each device to be laid out. The second offset axis and the first offset axis are different coordinate axes.

[0077] Specifically, the second offset axis determined in this application is orthogonal to the aforementioned first offset axis (queue axis), together forming the plane for device expansion. For horizontal axis grouping, if the first offset axis is the vertical axis (Y-axis), then the corresponding second offset axis is the horizontal axis (X-axis). The devices to be laid out are queued at equal intervals along the Y-axis and perform hierarchical avoidance along the X-axis. For vertical axis grouping, if the first offset axis is the horizontal axis (X-axis), then the corresponding second offset axis is the vertical axis (Y-axis). The devices to be laid out are queued at equal intervals along the X-axis and perform hierarchical avoidance along the Y-axis.

[0078] Specifically, this application extracts the intermediate layout coordinates generated in step S606, and accumulates their components in the second offset axis direction with the hierarchical relative displacement determined in step S607. Taking horizontal axis grouping as an example, the intermediate layout coordinates (x, y) are extracted. Calculate the x-coordinate component x in the given information. Relative displacement of layers. The final target layout coordinates are ( , ).

[0079] According to the solution provided in this application, devices to be laid out with the same grouping information are sorted to obtain a sorting result; a pre-set device spacing and a first offset axis corresponding to each grouping information are obtained, and then the intra-group relative displacement of each device to be laid out is determined based on the product of the sequence index of each device to be laid out in the sorting result and the device spacing; the coordinate components corresponding to the first offset axis in the initial coordinates of each device to be laid out are accumulated with the intra-group relative displacement to obtain intermediate layout coordinates; the layer information of the target pin line corresponding to each device to be laid out is obtained, and the layer relative displacement of each device to be laid out is determined according to the layer information and the preset layer spacing; the coordinate components corresponding to the second offset axis in the intermediate layout coordinates of each device to be laid out are accumulated with the layer relative displacement to obtain the target layout coordinates of each device to be laid out. The second offset axis and the first offset axis are different coordinate axes. This application solves the problem of mutual interference between devices to be laid out in multilayer circuit board design by introducing an orthogonal superposition mechanism of the first offset axis and the second offset axis. Since devices at the same initial coordinates but different levels share the same sorting index, their intermediate layout coordinates on the first offset axis still overlap. This application uses a double accumulation of layer information and layer spacing on the second offset axis to sequentially stagger these devices in planar space. This mechanism ensures that even with extremely high-density pin fanout, each device can be assigned a unique, non-interfering physical location. Furthermore, since the second offset axis and the first offset axis are different coordinate axes, the final generated target layout coordinates present an extremely neat matrix-like stepped distribution on the circuit board. This layout method is not only visually highly regular, but more importantly, it minimizes the space occupied by the devices while meeting manufacturing design safety clearances, leaving valuable board space for the routing of other functional circuits.

[0080] This application also provides a device layout method for a high-acceleration-stress test substrate, such as... Figure 7 As shown, the method includes: S701. Determine the device to be laid out corresponding to each target pin line, and determine the initial coordinates of the corresponding device to be laid out based on the coordinates of the end point of the target pin line. Step S701 is essentially the same as step S101 in the above embodiment, and will not be described again here.

[0081] S702. Group each device to be laid out based on its initial coordinates to obtain the grouping information corresponding to each device to be laid out. Step S702 is essentially the same as step S102 in the above embodiment, and will not be described again here.

[0082] S703. Based on the grouping information corresponding to each device to be laid out, the initial coordinates corresponding to each device to be laid out are offset and adjusted to obtain the target layout coordinates of each device to be laid out. Step S703 is essentially the same as step S103 in the above embodiment, and will not be described again here.

[0083] S704. Based on the target layout coordinates of each device to be laid out and the end point coordinates of the target pin line of each device to be laid out, determine the routing path between each device to be laid out and the corresponding target pin line. Specifically, the target layout coordinates determined in step S703 are extracted as the termination point of the trace, and the coordinates of the end point of the target pin line determined in step S701 are extracted as the starting point of the trace. Then, the trace path between each device to be laid out and the corresponding target pin line is determined based on the starting point and the termination point.

[0084] Specifically, since the devices to be placed are obtained by orderly offset along a specific axis (first offset axis or second offset axis) in the aforementioned steps, the target placement coordinates and the initial coordinates (coordinates of the end points of the target pin lines) are usually on the same axis or distributed at regular angles. For the above reasons, this application preferentially uses a direct line method to generate the routing path between the devices to be placed and the corresponding target pin lines to ensure the shortest routing distance and the lowest signal transmission delay.

[0085] During the routing process, this application will detect in real time whether there are existing obstacles on the routing path (such as other unrelated devices, prohibited routing areas, or existing critical signal lines). If interference is detected, this application will automatically introduce a turning point and bypass the obstacle at a preset angle (such as 45° or 90°) to generate a smooth avoidance path.

[0086] Understandably, since this application has already solved the physical interference problem of the devices to be placed through "sorting" and "step displacement" in S703, the routing paths generated in S704 have the characteristic of not intersecting each other. Each routing path maintains an approximately parallel topology with its adjacent routing paths, which greatly simplifies the utilization of routing space and provides a guarantee for signal integrity under high-density design.

[0087] S705. Based on the routing path, generate electrical connections connecting the device to be laid out and the corresponding target pin lines.

[0088] In this embodiment, the abstract routing path determined in the previous step is transformed into a connection with physical characteristics, thus completing the physical connection of the circuit.

[0089] According to the scheme provided in this application, the target pin line corresponding to the target pin type is determined from multiple pin lines of the chip under test; the device to be placed corresponding to each target pin line is determined, and the initial coordinates of the corresponding device to be placed are determined based on the coordinates of the end point of the target pin line; each device to be placed is grouped based on the initial coordinates of each device to be placed to obtain the grouping information corresponding to each device to be placed; the initial coordinates of each device to be placed are offset and adjusted based on the grouping information, to obtain the target layout coordinates of each device to be placed; the routing path between each device to be placed and the corresponding target pin line is determined based on the target layout coordinates of each device to be placed and the coordinates of the end point of the target pin line of each device to be placed; and the electrical connection connecting the device to be placed and the corresponding target pin line is generated according to the routing path. This application ensures the consistency of hardware location and electrical connection by deeply coupling the determination of target layout coordinates with the planning of routing path. Since the spatial distribution of pin ends has been fully considered in the placement stage, the system can directly establish a direct connection from the pin end to the device pad when generating the routing path, avoiding secondary routing adjustments caused by improper placement and ensuring the rigor of the design logic.

[0090] This application also provides a chip testing system, which includes at least one chip socket under test, a high accelerated stress test carrier board, and a digital measurement board. The high accelerated stress test carrier board is used to lay out the device to be laid out using the device layout method of the high accelerated stress test carrier board provided in any of the above embodiments.

[0091] The chip under test socket is used to place the chip under test so that the chip under test can be electrically connected to the high accelerated stress test carrier board.

[0092] High-accelerated stress test (HAST) carriers are used to support and connect chips under test (DUTs). They provide a mounting platform for multiple DUTs, ensuring accurate positioning. Simultaneously, via spring pins or cables, the HAST connects the DUTs to the digital measurement boards of an automated test equipment (ATE), establishing an electrical connection that enables accurate transmission of test signals to the DUTs and feedback of DUT response signals to the measurement boards, thus facilitating DUT testing.

[0093] High-accelerated stress test carriers are also used to achieve parallel testing. Since high-accelerated stress test carriers can load multiple DUTs at the same time, multiple DUTs can be tested simultaneously, which greatly improves testing efficiency, meets the needs of rapid chip testing in engineering testing, and helps to reduce testing costs and shorten testing cycles.

[0094] Digital measurement boards (DPCs) provide the bias voltage required for experimental testing. These boards offer power supplies of varying voltages and currents, integrating overall board voltage and current monitoring to monitor voltage and current changes in real time and set current limits. These power supplies provide appropriate bias voltages and limited currents for HAST testing, ensuring the safety and stability of the DUT during experiments and preventing power supply overload from affecting other experiments. Simultaneously, the DPCs work in conjunction with the high-accelerated stress test carrier to ensure precise bias application, improve test repeatability and data reliability, and provide crucial support for reliability experiments such as HAST.

[0095] To better understand this application, this embodiment provides a more specific example for illustration, wherein the example uses a BGA chip as the chip to be tested and a resistor to be laid out as the device to be laid out.

[0096] 1. The pin lines determine the initial coordinates of the external resistors; S11: Establish the pin lines for each pad of the BGA chip.

[0097] S12: Get the attributes of the pin line, including: the coordinates of the two endpoints of the line (the coordinates of the start endpoint and the end endpoint), the layer number of the pin line, the network name of the pin line, and the pin type.

[0098] S13: Select the resistors to be laid out (external resistors) based on the pin type of the pin line.

[0099] BGA chips have various types of output pins, such as power pins, GND pins, and data pins. During HAST testing, power pins and GND pins do not require pull-up or pull-down resistors, while data pins do. Therefore, based on the target pin type of the BGA chip, the target pin line of the BGA chip that requires matching resistors is determined, and the net name, layer name, and coordinates of the two endpoints of the target pin line are obtained.

[0100] S14: Based on the net name of the resistor to be laid out and the net name of the target pin, establish the mapping relationship between the resistor to be laid out and the pin (i.e., the one-to-one correspondence between the resistor to be laid out and the target pin). The attributes of the resistor to be laid out include: the resistor package and the net names at both ends of the resistor.

[0101] S15: Based on the established mapping relationship between the resistors to be laid out and the target pin lines, as well as the coordinates of the end points of the target pin lines, sort the resistors to be laid out and determine the initial coordinates of the resistors to be laid out.

[0102] First, select the pin line for which the resistor needs to be matched and obtain the corresponding NET Name, Layer Name, and Contiguous Length End Point coordinates of the two endpoints of the trace.

[0103] Next, based on the obtained network name, match the resistor to be laid out with the corresponding NET Name PIN.

[0104] Furthermore, the corresponding layer name and the coordinate information of the two endpoints of the trace are assigned to the resistor to be laid out. Compare all the coordinate data obtained from the resistors to be placed, and retain the X and Y coordinates that include the maximum and minimum values, i.e., keep the endpoint coordinates of all pin lines. The relative position corresponding to this coordinate is the relative position of the resistor after the jumper wires are straightened.

[0105] 2. Determine the target layout coordinates of the resistors to be placed.

[0106] S21: Obtain the resistor to be laid out corresponding to the target pin line with the same coordinates of the end point of the target pin line.

[0107] S22: Perform a second sorting on the resistors corresponding to the target pins with the same end point coordinates to determine the second position of the resistor to be laid out.

[0108] S23: Based on the package size of the resistors to be laid out, set the relative positional relationship between the resistors to be laid out.

[0109] S24: Determine the target layout coordinates of the resistors to be laid out based on the relative positional relationship between them.

[0110] According to the routing requirements, all traces on different layers must terminate at the same point. The final organized data is sorted and grouped, and based on the smallest, largest, largest, and smallest X-axis coordinates, all resistors to be placed are divided into four groups: left group, right group, top group, and bottom group. With the power pin as the zero point, the angles of the resistors are as follows: left group: 0 degrees; bottom group: 90 degrees; right group: 180 degrees; top group: 270 degrees.

[0111] The coordinates of the resistors to be laid out in the left group are processed as follows: sort the Y-coordinate data and increase the spacing of the corresponding Y-coordinates so that the Y-axis spacing between two adjacent resistors to be laid out is 60 mil (the spacing between resistors to be laid out can be adjusted under HAST testing). The X-coordinate is adjusted according to the position of different layers, with a spacing of 120 mil between different layers. For example, for the second layer, the X-coordinate of the resistor to be laid out is reduced by 120 mil x 2; for the third layer, the X-coordinate of the resistor to be laid out is reduced by 120 mil x 3; for the fourth layer, the X-coordinate of the resistor to be laid out is reduced by 120 mil x 4, and so on. The X-coordinate of all coordinates is adjusted once. Finally, the Y-coordinate is uniformly increased by 20000 mil and moved outside the board frame, and the pre-layout on the left is completed.

[0112] The coordinates of the resistors to be laid out in the right group are processed as follows: sort the Y-coordinate data and increase the spacing between corresponding coordinates so that the Y-axis spacing between two adjacent resistors to be laid out is 60 mil (the spacing between resistors to be laid out can be adjusted under HAST testing). The X-coordinate is adjusted according to the position of different layers, with a spacing of 120 mil between different layers. For example, for the second layer, the X-coordinate of the resistor to be laid out is increased by 120 mil x 2; for the third layer, it is increased by 120 mil x 3; for the fourth layer, it is increased by 120 mil x 4, and so on. The X-coordinate of all coordinates is adjusted to one side. Finally, the Y-coordinate is uniformly increased by 20000 mil and moved outside the board frame. The pre-layout on the right is then completed.

[0113] The coordinates of the resistors to be laid out in the upper group are processed as follows: sort the X-coordinate data and increase the spacing between corresponding coordinates so that the X-axis spacing between two adjacent resistors to be laid out is 60 mil (the spacing between resistors to be laid out can be adjusted under HAST testing). The Y-coordinate is adjusted according to the arrangement of different layers, with a spacing of 120 mil between different layers. For example, for the second layer, the Y-coordinate of the resistor to be laid out is reduced by 120 mil x 2; for the third layer, the Y-coordinate of the resistor to be laid out is reduced by 120 mil x 3; for the fourth layer, the Y-coordinate of the resistor to be laid out is reduced by 120 mil x 4, and so on. The Y-coordinate of all coordinates is adjusted to one side. Finally, the Y-coordinate is uniformly increased by 20000 mil and moved outside the board frame, thus completing the pre-layout above.

[0114] The coordinates of the resistors to be laid out in the lower group are processed as follows: sort the X-coordinate data and increase the spacing between corresponding coordinates so that the X-axis spacing between two adjacent resistors to be laid out is 60 mil (the spacing between resistors to be laid out can be adjusted under HAST testing). The Y-coordinate is adjusted according to the arrangement of different layers, with a spacing of 120 mil between different layers. For example, for the second layer, the Y-coordinate of the resistor to be laid out is increased by 120 mil x 2; for the third layer, the Y-coordinate of the resistor to be laid out is increased by 120 mil x 3; for the fourth layer, the Y-coordinate of the resistor to be laid out is increased by 120 mil x 4, and so on. The Y-coordinate of all coordinates is adjusted to one side. Finally, the Y-coordinate is uniformly increased by 20000 mil and moved outside the board frame, and the pre-layout of the lower group is completed.

[0115] 3. Based on the target layout coordinates of the resistor to be placed and the coordinates of the end point of the target pin line, determine the routing path between the resistor to be placed and the target pin line.

[0116] In some examples, after generating the target layout coordinates of the resistor to be placed, the target layout coordinates of the resistor to be placed can also be sent to the user for confirmation. If a confirmation instruction is received, the routing path between the resistor to be placed and the target pin line is determined directly based on the target layout coordinates and the end point coordinates of the target pin line. If an adjustment instruction is received, the target layout coordinates are adjusted according to the adjustment instruction, and the routing path between the resistor to be placed and the target pin line is determined based on the adjusted target layout coordinates and the end point coordinates of the target pin line.

[0117] All of the above-mentioned optional technical solutions can be combined in any way to form the optional embodiments of this application, and will not be described in detail here.

[0118] This embodiment also provides a device layout device for a high-acceleration-stress test substrate, such as... Figure 8 As shown, the device layout arrangement of the high-acceleration-stress test substrate includes: The coordinate module 801 is used to determine the device to be laid out corresponding to each target pin line in the chip under test, and to determine the initial coordinates of the corresponding device to be laid out based on the coordinates of the end point of the target pin line. Grouping module 802 is used to group each device to be laid out based on the initial coordinates of each device to be laid out, and to obtain the grouping information corresponding to each device to be laid out. The adjustment module 803 is used to offset and adjust the initial coordinates of each device to be laid out based on the grouping information corresponding to each device to be laid out, so as to obtain the target layout coordinates of each device to be laid out.

[0119] In some examples, the grouping module 802 is also used to traverse the initial coordinates of all devices to be laid out, obtain the first coordinate grouping value corresponding to the first direction on the vertical axis, the second coordinate grouping value corresponding to the second direction on the vertical axis, the third coordinate grouping value corresponding to the third direction on the horizontal axis, and the fourth coordinate grouping value corresponding to the fourth direction on the horizontal axis, wherein the first direction and the second direction are opposite directions, and the third direction and the fourth direction are opposite directions; match the initial coordinates of each device to be laid out with the first coordinate grouping value, the second coordinate grouping value, the third coordinate grouping value, and the fourth coordinate grouping value respectively, and determine the grouping information of each device to be laid out based on the matching results.

[0120] In some examples, the grouping module 802 is also used to determine the grouping information of the device to be laid out as the first vertical axis group if the matching result indicates that the initial coordinates of the device to be laid out match the first coordinate grouping value; and to determine the grouping information of the device to be laid out as the second vertical axis group if the matching result indicates that the initial coordinates of the device to be laid out match the second coordinate grouping value.

[0121] In some examples, the adjustment module 803 is also used to sort the devices to be laid out with the same grouping information to obtain the sorting result; obtain the pre-set device spacing and the first offset axis corresponding to each grouping information; and adjust the initial coordinates of the devices to be laid out under each grouping information according to the first offset axis, device spacing and sorting result to obtain the target layout coordinates of each device to be laid out.

[0122] In some examples, the adjustment module 803 is also used to determine the intra-group relative displacement of each device to be laid out based on the product of the sequence index of each device to be laid out in the sorting result and the device spacing; and to accumulate the coordinate components corresponding to the first offset axis in the initial coordinates of each device to be laid out with the intra-group relative displacement to determine the target layout coordinates of each device to be laid out.

[0123] In some examples, the adjustment module 803 is also used to accumulate the coordinate components corresponding to the first offset axis in the initial coordinates of each device to be laid out with the relative displacement within the group to obtain intermediate layout coordinates; obtain the layer information of the target pin line corresponding to each device to be laid out, and determine the layer relative displacement of each device to be laid out according to the layer information and the preset layer spacing; accumulate the coordinate components corresponding to the second offset axis in the intermediate layout coordinates of each device to be laid out with the layer relative displacement to obtain the target layout coordinates of each device to be laid out, wherein the second offset axis and the first offset axis are different coordinate axes.

[0124] In some examples, the adjustment module 803 is also used to determine the routing path between each device to be laid out and the corresponding target pin based on the target layout coordinates of each device to be laid out and the end point coordinates of the target pin of each device to be laid out; and to generate electrical connections connecting the device to be laid out and the corresponding target pin based on the routing path.

[0125] According to the technical solution provided in the embodiments of this application, this application determines the device to be laid out corresponding to each target pin line, and determines the initial coordinates of the corresponding device to be laid out based on the coordinates of the end point of the target pin line; based on the initial coordinates of each device to be laid out, each device to be laid out is grouped to obtain the grouping information corresponding to each device to be laid out; based on the grouping information corresponding to each device to be laid out, the initial coordinates corresponding to each device to be laid out are offset and adjusted to obtain the target layout coordinates of each device to be laid out. In this application, the initial coordinates of the devices to be laid out are first assigned based on the coordinates of the end point of the target pin line, and the physical distribution of the devices to be laid out in the original fan-out position is used to achieve preliminary sorting; then, each device to be laid out is grouped to determine the group information to which the device to be laid out belongs, and then the initial coordinates corresponding to each device to be laid out are offset and adjusted using the grouping information to obtain the target layout coordinates of each device to be laid out. Through the progressive adjustment of grouping first and then offsetting, the devices to be laid out that were originally densely distributed or even overlapping in local areas are finally presented as a matrix-like stepped array with regular spacing and orderly arrangement on the circuit board, thereby efficiently and accurately completing the device layout of the high-accelerated stress test carrier board. This avoids the time-consuming and error-prone problem of manually laying out components on the high-acceleration-stress test substrate in related technologies.

[0126] Figure 9 This is a schematic diagram of the electronic device 9 provided in an embodiment of this application. Figure 9 As shown, the electronic device 9 of this embodiment includes a processor 901, a memory 902, and a computer program 903 stored in the memory 902 and executable on the processor 901. When the processor 901 executes the computer program 903, it implements the steps in the various method embodiments described above. Alternatively, when the processor 901 executes the computer program 903, it implements the functions of each module / unit in the various device embodiments described above.

[0127] Electronic device 9 can be a desktop computer, laptop, handheld computer, cloud server, or other electronic device. Electronic device 9 may include, but is not limited to, processor 901 and memory 902. Those skilled in the art will understand that... Figure 9 This is merely an example of electronic device 9 and does not constitute a limitation on electronic device 9. It may include more or fewer components than shown, or different components.

[0128] The processor 901 can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.

[0129] The memory 902 can be an internal storage unit of the electronic device 9, such as a hard disk or RAM of the electronic device 9. The memory 902 can also be an external storage device of the electronic device 9, such as a plug-in hard disk, Smart Media Card (SMC), Secure Digital (SD) card, Flash Card, etc., equipped on the electronic device 9. The memory 902 can also include both internal and external storage units of the electronic device 9. The memory 902 is used to store computer programs and other programs and data required by the electronic device.

[0130] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0131] If an integrated module / unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program may include computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. A computer-readable medium may include: any entity or device capable of carrying computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in a computer-readable medium can be appropriately added to or subtracted according to the requirements of legislation and patent practice in a jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0132] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A device layout method for a high-acceleration-stress test substrate, characterized in that, The method includes: The device to be laid out is determined for each target pin of the chip under test, and the initial coordinates of the corresponding device to be laid out are determined based on the coordinates of the end point of the target pin. Based on the initial coordinates of each device to be laid out, each device to be laid out is grouped to obtain the grouping information corresponding to each device to be laid out. Based on the grouping information corresponding to each of the devices to be laid out, the initial coordinates corresponding to each of the devices to be laid out are offset and adjusted to obtain the target layout coordinates of each of the devices to be laid out.

2. The method according to claim 1, characterized in that, Based on the initial coordinates of each device to be laid out, each device is grouped to obtain grouping information corresponding to each device, including: Traverse the initial coordinates of all the devices to be laid out, and obtain the first coordinate group value corresponding to the first direction on the vertical axis, the second coordinate group value corresponding to the second direction on the vertical axis, the third coordinate group value corresponding to the third direction on the horizontal axis, and the fourth coordinate group value corresponding to the fourth direction on the horizontal axis, wherein the first direction and the second direction are opposite directions, and the third direction and the fourth direction are opposite directions; The initial coordinates of each device to be laid out are matched with the first coordinate grouping value, the second coordinate grouping value, the third coordinate grouping value, and the fourth coordinate grouping value, and the grouping information of each device to be laid out is determined based on the matching results.

3. The method according to claim 2, characterized in that, Based on the matching results, the grouping information for each device to be laid out is determined, including: If the matching result indicates that the initial coordinates of the device to be laid out match the first coordinate grouping value, then the grouping information of the device to be laid out is determined to be the first grouping of the vertical axis. If the matching result indicates that the initial coordinates of the device to be laid out match the second coordinate grouping value, then the grouping information of the device to be laid out is determined to be the second grouping of the vertical axis.

4. The method according to any one of claims 1-3, characterized in that, Based on the grouping information corresponding to each of the devices to be laid out, the initial coordinates corresponding to each device to be laid out are offset and adjusted to obtain the target layout coordinates of each device to be laid out, including: The devices to be laid out that have the same grouping information are sorted to obtain a sorting result; Obtain the pre-set device spacing and the first offset axis corresponding to each group information; Based on the first offset axis, the device spacing, and the sorting result corresponding to each group information, the initial coordinates of the devices to be laid out under each group information are offset and adjusted to obtain the target layout coordinates of each device to be laid out.

5. The method according to claim 4, characterized in that, Based on the first offset axis, the device spacing, and the sorting result corresponding to each group information, the initial coordinates of the devices to be laid out under each group information are offset and adjusted to obtain the target layout coordinates of each device to be laid out, including: The intra-group relative displacement of each of the devices to be laid out is determined based on the product of the sequence index of each device in the sorting result and the spacing between the devices. The coordinate components corresponding to the first offset axis in the initial coordinates of each device to be laid out are accumulated with the relative displacement within the group to determine the target layout coordinates of each device to be laid out.

6. The method according to claim 5, characterized in that, The coordinate components corresponding to the first offset axis in the initial coordinates of each device to be laid out are accumulated with the relative displacement within the group to determine the target layout coordinates of each device to be laid out, including: The coordinate components corresponding to the first offset axis in the initial coordinates of each device to be laid out are accumulated with the relative displacement within the group to obtain the intermediate layout coordinates. Obtain the layer information of the target pin line corresponding to each device to be laid out, and determine the relative layer displacement of each device to be laid out based on the layer information and the preset layer spacing. The coordinate components corresponding to the second offset axis in the intermediate layout coordinates of each device to be laid out are accumulated with the relative displacement of the layer to obtain the target layout coordinates of each device to be laid out. The second offset axis and the first offset axis are different coordinate axes.

7. The method according to any one of claims 1-3, characterized in that, The method further includes: Based on the target layout coordinates of each device to be laid out and the end point coordinates of the target pin line of each device to be laid out, the routing path between each device to be laid out and the corresponding target pin line is determined. Based on the routing path, an electrical connection is generated to connect the device to be laid out and the corresponding target pin line.

8. A device layout apparatus for a high-acceleration-stress testing carrier, characterized in that, The device includes: The coordinate module is used to determine the device to be laid out corresponding to each target pin line of the chip under test, and to determine the initial coordinates of the corresponding device to be laid out based on the coordinates of the end point of the target pin line. The grouping module is used to group each of the devices to be laid out based on the initial coordinates of each device to be laid out, so as to obtain the grouping information corresponding to each device to be laid out. The adjustment module is used to offset and adjust the initial coordinates of each device to be laid out based on the grouping information corresponding to each device to be laid out, so as to obtain the target layout coordinates of each device to be laid out.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method as described in any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method as described in any one of claims 1 to 7.

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