Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device includes a substrate of a first conductivity type and a barrel-like structure of a second conductivity type formed in the substrate. The second conductivity type is opposite to the first conductivity type. The barrel-like structure comprises a bottom layer of a second conductivity type embedded in an initial substrate layer of the substrate, and a predetermined embedding depth exists between a peak doping concentration plane of the bottom layer and a top surface of the initial substrate layer and is substantially greater than 0.5 [mu] m. By adopting the barrel-like structure, the technical bottleneck of manufacturing a high-voltage semiconductor device in the prior art can be broken through, for example, the breakdown voltage of a transistor formed in the part, located in the barrel-like structure, of the substrate can exceed 70 V, and even particularly can exceed 100 V.

Description

Technical Field

[0001] The embodiments of this application generally relate to semiconductor devices, and more specifically, but not limited to, high-voltage semiconductor devices and methods of manufacturing the same. Background Technology

[0002] Power transistors, such as high-voltage metal-oxide-semiconductor (MOS) transistors, are widely used in various power management scenarios, including as power switching elements in power management devices for industrial and / or consumer electronic devices. In most high-current or high-power applications such as laptops, servers, and automotive applications, transistors with high voltage withstand capabilities are required. Summary of the Invention

[0003] According to one embodiment of the present invention, a semiconductor device is provided, the semiconductor device having a substrate of a first conductivity type and a barrel-like structure of a second conductivity type formed in the substrate, the second conductivity type being opposite to the first conductivity type. In one embodiment, the substrate includes an initial substrate layer of the first conductivity type and an epitaxial layer of the first conductivity type formed on the initial substrate layer. In one embodiment, the barrel-like structure includes a bottom layer of the second conductivity type buried in the initial substrate layer. In one embodiment, the bottom layer has a peak doping concentration plane, the peak doping concentration plane having a predetermined buried depth substantially greater than 0.5 μm from the top surface of the initial substrate layer.

[0004] In one embodiment, the barrel-like structure further includes a plurality of sidewalls that contact or connect with the underlying layer, each of the plurality of sidewalls extending downward from the top surface of the substrate until it contacts or connects with at least the underlying layer.

[0005] In one embodiment, the semiconductor device further includes a transistor formed on the substrate and located within a portion of the barrel-like structure. In one embodiment, the transistor has a breakdown voltage exceeding 70V, and particularly exceeding 100V.

[0006] According to one embodiment of this disclosure, a semiconductor device is provided. The semiconductor device has a substrate of a first conductivity type and a barrel-like structure of a second conductivity type formed in the substrate, the second conductivity type being opposite to the first conductivity type. In one embodiment, the barrel-like structure includes a bottom layer and a plurality of sidewalls in contact with the bottom layer, each of the plurality of sidewalls including a buried connection region, i.e., a first buried layer, the bottom layer including a second buried layer, wherein the second buried layer has a greater burial depth in the substrate than the buried connection region in the substrate when measured with reference to the top surface of the substrate. In one embodiment, the semiconductor device further includes a transistor formed within the barrel-like structure. In one embodiment, the transistor has a breakdown voltage exceeding 70V, and particularly exceeding 100V.

[0007] According to one embodiment of this disclosure, a method of manufacturing a semiconductor device is also provided. The method includes forming a substrate of a first conductivity type, the substrate including the bottom layer of the barrel-like structure. The bottom layer is of a second conductivity type opposite to the first conductivity type; and its peak doping concentration plane has a predetermined bottom layer embedment depth substantially greater than 0.5 μm from the top surface of an initial substrate layer of the substrate. In one embodiment, the step of forming the substrate further includes fabricating embedded connection regions in the substrate for each of a plurality of sidewalls of the barrel-like structure, and the embedded connection regions are at least in contact with the bottom layer. The embedment depth of the bottom layer in the substrate is greater than the embedment depth of the embedded connection regions in the substrate.

[0008] In one embodiment, forming the substrate further includes forming an epitaxial layer on the initial substrate layer with a thickness in the range of 8 μm to 16 μm.

[0009] In one embodiment, the method further includes forming a drift region of a second conductivity type for each of a plurality of transistor cells of a high-voltage transistor to be fabricated in the substrate.

[0010] In one embodiment, the method may optionally further include forming a RESURF region of a first conductivity type in an epitaxial layer for each of the plurality of transistor cells of the high-voltage transistor.

[0011] In one embodiment, the method may optionally further include forming a sidewall connection region of a second conductivity type in the epitaxial layer for each of the plurality of sidewalls of the barrel-like structure. The sidewall connection region may be a buried doped region embedded in the epitaxial layer and having a predetermined sidewall connection depth.

[0012] In one embodiment, the method may optionally further include a body well region of a first conductivity type for each of a plurality of transistor cells of a high-voltage transistor to be fabricated in the substrate, wherein the body well region is located adjacent to the drift region.

[0013] In one embodiment, the method further includes: forming a gate region for each of the plurality of transistor cells of the high-voltage transistor; forming a body region of a first conductivity type for each of the plurality of transistor cells of the high-voltage transistor, the body region being separate from the drift region; forming a source region and a drain region of a second conductivity type for each of the plurality of transistor cells of the high-voltage transistor; forming a lead-out region for each of the plurality of sidewalls of the barrel-like structure, the lead-out region sharing the same formation process as the source region and the drain region; and forming a body contact region of the first conductivity type for each of the plurality of transistor cells of the high-voltage transistor.

[0014] According to one embodiment of this disclosure, a method for manufacturing a semiconductor device is also provided. The method includes forming an initial substrate layer in a substrate having a first conductivity type; forming a bottom layer in a barrel-like structure of a second conductivity type in the initial substrate layer, the second conductivity type being opposite to the first conductivity type; and forming a buried connection region for each of a plurality of sidewalls of the barrel-like structure, such that the buried connection region is in contact with at least the bottom layer, and the buried depth of the bottom layer in the substrate is greater than the buried depth of the buried connection region in the substrate when measured with reference to the top surface of the initial substrate layer. The method further includes forming an epitaxial layer with a thickness ranging from 8 μm to 16 μm on the initial substrate layer. The method further includes forming a plurality of sidewalls of the barrel-like structure and forming a high-voltage transistor within the barrel-like structure. Attached Figure Description

[0015] The detailed description of the various embodiments of the present invention can be better understood by reading the following accompanying drawings, wherein the illustrated features are not drawn to scale, but are drawn to clearly show the key features.

[0016] Figure 1 This is a partial cross-sectional view of a semiconductor device 100 according to an embodiment of the present invention.

[0017] Figure 2 for Figure 1 The top view corresponding to the partial cross-sectional view of the semiconductor device 100 shown.

[0018] Figure 3 The waveform diagram 300 shows the doping concentration Cx cm⁻¹ as a function of the distance Dx μm from the top surface S5 of the initial substrate layer 101. -3 The curve graph.

[0019] Figure 4 This is a partial cross-sectional view of a semiconductor device 400 according to an alternative embodiment of the present invention.

[0020] Figure 5 This is a partial cross-sectional view of a semiconductor device 500 according to an alternative embodiment of the present invention.

[0021] Figure 6 This is a partial cross-sectional view of a semiconductor device 600 according to an alternative embodiment of the present invention.

[0022] Figure 7 This is a partial cross-sectional view of a semiconductor device 700 according to an alternative embodiment of the present invention.

[0023] Figures 8A to 8Q This is a cross-sectional view of several process stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. Detailed Implementation

[0024] Several embodiments of the present invention will now be described. Specific details, such as circuit examples and exemplary parameters of their circuit elements, are included in the following description to fully illustrate the embodiments of the invention. Those skilled in the art will understand that the invention can be implemented without one or more of the specific details described, or using other methods, elements, materials, etc. In other instances, well-known structures, materials, processes, or operations have not been shown or described in detail to avoid obscuring various aspects of the invention.

[0025] In this specification and claims, the term "coupled" as used is defined as a direct or indirect connection in an electrical or non-electrical manner. When an element is described as "connected" or "coupled" to another element, the element may be directly connected or coupled to said other element, or one or more intermediate elements may be present. Conversely, when an element is stated as "directly connected" or "directly coupled" to another element, no intermediate elements are present. Furthermore, "electrically connected" or "electrically coupled" includes the concept of electrical coupling between elements in both physically connected and physically disconnected states. It should be understood that when an element is referred to as "first" or "second," such designation does not constitute a limitation. Terms such as "first" or "second" are used only to distinguish different elements and should not limit the order or importance of elements unless the context clearly indicates otherwise. The terms "a" and "the" have plural meanings, and the term "within" includes "within" and "on." The phrase "in one embodiment" as used herein may, but does not necessarily, refer to the same embodiment. The term "or" is an inclusive "or" operator, meaning the same as the term "and / or" herein, unless the context clearly indicates otherwise. The term "based on" is not exclusive, allowing for basing on other factors not described, unless the context clearly indicates otherwise. The term "circuit" refers to at least one single discrete element or a combination of multiple active and / or passive elements coupled together to provide a desired function. The term "signal" refers to at least one current, voltage, charge, temperature, data, or other signal. Those skilled in the art will understand that the above definitions of terms are intended to provide illustrative examples of the terms and not to limit the terms themselves.

[0026] The terms “comprising,” “including,” “having,” and any variations thereof all imply non-exclusive inclusion, meaning that a process, method, article, or apparatus that comprises a series of elements is not necessarily limited to those elements, but may also include other elements not expressly listed or inherent in the process, method, article, or apparatus.

[0027] In this specification and claims, the terms “left,” “right,” “inner,” “outer,” “front,” “back,” “upper,” “lower,” “top,” “at the top of,” “at the bottom of,” “above,” “below,” “lower than,” “higher than,” etc., are used for descriptive purposes and ease of explanation only, and are not necessarily used to describe permanent relative positions. It should be understood that such terms can be used interchangeably where appropriate; for example, embodiments of the invention described herein can operate in other orientations shown or otherwise described herein, and the claims are not specifically limited to the positions or orientations described by these terms.

[0028] This disclosure uses an N-channel semiconductor device as an example for illustrative purposes only and is not intended to be limiting. Those skilled in the art will understand that the structures and principles described herein are equally applicable to P-channel semiconductor devices. For example, the conductivity type of each region may be replaced with its opposite conductivity type, and this applies to other types of semiconductor materials and devices. Although polysilicon is preferred for forming the gate in the embodiments of this disclosure, this embodiment is not limited to this choice of conductor; other materials compatible with the device fabrication process (e.g., metals, other semiconductors, half-metals, and / or combinations thereof) may also be used. Therefore, the terms "poly" and "poly-silicon" include not only polysilicon but also other types of materials and combinations thereof.

[0029] Figure 1 A partial cross-sectional view of a semiconductor device 100 including, for example, transistors according to an embodiment of the present disclosure is shown. Figure 1 The cross-sectional view is presented in a three-dimensional coordinate system where the x, y, and z axes are perpendicular to each other. It is understood that this cross-sectional view is observed / obtained from a cut surface parallel to the xy plane defined by the x and y axes. In this disclosure, "lateral" refers to the direction parallel to the x-axis, while "vertical" refers to the direction parallel to the y-axis. "Width" refers to the dimension measured in the direction parallel to the x-axis, while "height" refers to the dimension measured in the direction parallel to the y-axis. A semiconductor device 100 is formed on a substrate 100S, which includes an initial substrate layer 101 of a first conductivity type (e.g., P-type). The initial substrate layer 101 may contain one or more semiconductor materials, such as silicon, germanium, silicon carbide, or other forms of semiconductor layers. In one embodiment, the thickness of the initial substrate layer 101 typically ranges from 100 μm to 200 μm. However, this is intended to provide an example and not a limitation. In one example, the initial substrate layer 101 is doped with a dopant of the first conductivity type to have a first doping concentration (also referred to as substrate doping concentration). In one embodiment, the first doping concentration is 1e13 cm⁻¹. -3 up to 1e16 cm -3 Within the range. As those skilled in the art will understand, the doping concentration of any single doped region or doped layer in a semiconductor device will not be ideally uniformly distributed due to the diffusive physical properties of dopants. Typically, the location where dopants are implanted to form a doped region or doped layer may have a substantially peak doping concentration value. Generally, in actually manufactured semiconductor devices, the peak doping concentration value of a single doped region or single doped layer can characterize the doping degree or doping concentration of that single doped region or single doped layer. Therefore, those skilled in the art will understand that, in this disclosure, the term "doping concentration" refers to a substantially detectable or measurable peak doping concentration value for a particular single doped region or particular single doped layer.

[0030] A relatively thick epitaxial layer 102 of a first conductivity type (e.g., P-type) can be formed on the initial substrate layer 101. According to various embodiments of the invention, "relatively thick" means that the thickness of the epitaxial layer 102 is sufficient to support the fabrication of a high-voltage transistor with a breakdown voltage of not less than 70V. For example, the thickness of the epitaxial layer 102 exceeds 5 μm. In one embodiment, the thickness of the epitaxial layer 102 is between 8 μm and 16 μm to support the formation of a high-voltage transistor with a breakdown voltage of 80V to 250V. In another embodiment, the thickness of the epitaxial layer 102 is between 10 μm and 12 μm to support the formation of a high-voltage transistor with a breakdown voltage of 100V to 140V. In yet another alternative embodiment, the thickness of the epitaxial layer 102 is between 12 μm and 14 μm to support the formation of a high-voltage transistor with a breakdown voltage of 120V to 200V. In yet another alternative embodiment, the thickness of the epitaxial layer 102 is between 14 μm and 16 μm to support the formation of a high-voltage transistor with a breakdown voltage of 180V to 250V. The breakdown voltage of a transistor typically characterizes its voltage withstand capability, and is one of many characteristics or parameters of a transistor known to those skilled in the art. For example, the breakdown voltage of a MOS transistor with a drain, source, and gate refers to the maximum drain-source voltage that the transistor can withstand in its off-state (or non-conducting state).

[0031] In one embodiment, the epitaxial layer 102 comprises one or more of silicon, germanium, silicon carbide, or any other suitable semiconductor material. In one embodiment, the epitaxial layer 102 is formed of the same semiconductor material as the initial substrate layer 101. In one embodiment, a dopant of a first conductivity type is implanted into the epitaxial layer 102 to form a second doping concentration (also referred to as epitaxial doping concentration). The second doping concentration is lower than the first doping concentration. For example, the epitaxial layer 102 is in... Figure 1 The layer is shown as a P-type layer. For example, in one embodiment, the second doping concentration ranges from 1e13 cm⁻¹. -3 Up to 1e16 cm -3 In one embodiment, the second doping concentration ranges from 1e14 cm⁻¹. -3 up to 1e15 cm -3 .

[0032] The substrate 100S of the semiconductor device 100 described in the example includes an initial substrate layer 101 and an epitaxial layer 102. Those skilled in the art will understand that this is not a limiting description; in another embodiment, the substrate 100S of the semiconductor device 100 may include more or fewer semiconductor layers without departing from the spirit of this disclosure. In other alternative embodiments, for example, the substrate 100S of the semiconductor device 100 comprises a single layer and / or multiple layers of non-epitaxial or epitaxial semiconductor layers made of one or more semiconductor materials such as silicon, germanium, and silicon carbide.

[0033] According to an exemplary embodiment of the present invention, the semiconductor device 100 includes a barrel-like structure formed in a substrate 100S of the semiconductor device 100. The barrel-like structure may have a bottom layer 14 of a second conductivity type (e.g., N-type) buried in the initial substrate layer 101. The barrel-like structure may also have a plurality of sidewalls 10 of a second conductivity type (e.g., N-type). The second conductivity type (e.g., N-type) is the opposite of the first conductivity type (e.g., P-type). Here, the term "a plurality of" is not limited to more than one, but also includes one. Each of the plurality of sidewalls 10 has a predetermined well width (or well thickness) w1. The plurality of sidewalls 10 are in physical contact with the bottom layer 14 to achieve electrical connection, so that the barrel-like structure can act as a container for a second conductivity type embedded in the substrate 100S of the first conductivity type, thereby establishing isolation of the second conductivity type between a portion of the substrate 100S located within the barrel-like structure and a portion of the substrate 100S outside the barrel-like structure.

[0034] like Figure 1 The partial cross-sectional schematic diagram shown, as an example, illustrates one of the left side wall 10-1 and the right side wall 10-2 among the plurality of side walls 10 of the barrel-like structure. Those skilled in the art will understand that, when viewed in a top view plane defined by the x-axis and z-axis, the plurality of side walls 10 of the barrel-like structure can form a closed loop and define the top view shape of the structure.

[0035] Figure 2 It shows the relationship with Figure 1 The top view corresponding to a partial cross-sectional view of semiconductor device 100. Figure 1 The partial cross-sectional view shown is considered as an exemplary embodiment according to this disclosure, corresponding to... Figure 2 The cross-section taken along the cutting line A-A' in the top view shows the barrel-like structure as a roughly rectangular ring. It should be understood that the top view shape of the structure is not limited and can be generally rectangular, quadrilateral, polygonal, circular, or other shapes compatible with the manufacturing process.

[0036] According to an exemplary embodiment of the present invention, each of the plurality of sidewalls 10 may include an outlet region 11, a trap region 12, and an embedded connection region 13, for example, referring to Figure 1 The diagrams of the left side wall 10-1 or the right side wall 10-2 are provided for easier understanding.

[0037] Each of the plurality of sidewalls 10 (e.g., 10-1 and 10-2) has an outlet region 11 formed in the substrate 100S and located near the top surface S1 of the substrate 100S, the top surface S1 being opposite the bottom surface S0 of the substrate 100S. Figure 1 In the example shown, the lead-out region 11 is formed in the epitaxial layer 102 and near the top surface of the epitaxial layer 102 (also labeled S1). The top surface of the epitaxial layer 102 is also labeled S1 because in Figure 1 In the example shown, the top surface of the epitaxial layer 102 can be considered as the top surface of the substrate 100S, which may include an initial substrate layer 101 and an epitaxial layer 102. The lead-out region 11 is of a second conductivity type (e.g., N-type) and has a lead-out region doping concentration that enables the lead-out region 11 to serve as a contact region of the barrel-like structure, thereby achieving electrical connection between the barrel-like structure and the metal contact points formed above the lead-out region 11 (hereinafter referred to as the metal contact points of the barrel-like structure). The lead-out region 11 facilitates the formation of ohmic contacts between each sidewall 10 and the metal contact points of the barrel-like structure; therefore, those skilled in the art may refer to it as a "highly doped" or "heavily doped" region (e.g., in...). Figure 1 (As shown in the N+ region). In one embodiment, the doping concentration of the lead-out region is higher than the first doping concentration and / or the second doping concentration. In one embodiment, for example, the doping concentration range of the lead-out region is 1e18cm. -3 up to 1e21 cm -3 .

[0038] Trap regions 12 of each sidewall 10 are formed and disposed around the lead-out region 11, and from the top surface S1 of the substrate 100S (i.e. Figure 1 The top surface S1 of the epitaxial layer 102 shown extends vertically into the substrate 100S at a well depth d1 (e.g., in...). Figure 1 (As shown, extending into the epitaxial layer 102). Those skilled in the art will understand that the well depth d1 can be considered substantially from the top surface S1 of the substrate 100S (i.e., Figure 1 The distance shown is the direct vertical distance from the top surface S1 of the epitaxial layer 102 to the bottom surface S2 of the well region 12. The well region 12 can be of a second conductivity type (e.g., N-type). The well region doping concentration of the well region 12 is lower than the doping concentration of the lead-out region. Those skilled in the art will understand that... Figure 1In the example shown, the well region 12 is schematically shown as an N-type region, which can characterize that the doping concentration of the well region is lower than that of the lead-out region 11, shown as an N+ region. In one embodiment, the well region doping concentration ranges from 5e16 cm⁻¹. -3 up to 1e18cm -3 .

[0039] The well region 12 can be doped with a dopant of a second conductivity type (e.g., phosphorus P), which is suitable for and compatible with medium-to-high energy implantation processes. The energy level of this implantation process can range from several hundred keV to several MeV depending on the required well depth d1 and the thickness of the epitaxial layer 102 for the actual application. The well region 12 can be formed by implanting a dopant of the second conductivity type (e.g., phosphorus P) from the top surface S1 into the epitaxial layer 102 using a medium-to-high energy implantation process, which is suitable for and compatible with medium-to-high energy implantation processes.

[0040] In one exemplary embodiment, the embedded connection area 13 of each sidewall 10 is formed and disposed below the trap area 12, such as Figure 1 As shown. The embedded connection area 13 may be of a second conductive type (e.g., Figure 1 (N-type in). In one embodiment, the embedded connection region 13 may contain a second conductivity type (e.g., N-type). Figure 1 The first buried layer (of type N) is buried beneath the well region 12 of each of the plurality of sidewalls 10. In one embodiment, the buried connection region (i.e., the first buried layer) 13 is formed in an initial substrate layer 101 and has a first portion (e.g., a lower portion) extending vertically downward into the initial substrate 101, which is formed by an implantation process and a subsequent drive-in process. The buried connection region (i.e., the first buried layer) 13 typically also has a second portion (e.g., ... Figure 1 The upper part of the second part extends vertically upward into the epitaxial layer 102 due to self-doping. Those skilled in the art should understand that self-doping refers to the phenomenon of dopant automatically diffusing without the intentional use of a propagation process step. Figure 1 In the illustrated embodiment, the embedded connection region 13 is in physical contact with the well region 12 above and with the bottom layer 14 below, thereby providing an electrical connection between the well region 12 and the bottom layer 14, allowing them to be electrically coupled, and forming a current path of a second conductivity type (e.g., N-type) from the lead-out region 11 to the bottom layer 14. In one embodiment, the embedded connection region 13 has a vertical height d4. Figure 1In this context, the vertical height d4 can be considered essentially as the direct vertical distance from the top surface S2' of the embedded connection region 13 to its bottom surface S3. For example, the top surface S2' of the embedded connection region 13 is located in the epitaxial layer 102, while its bottom surface S3 is located in the initial substrate layer 101. Figure 1 In this configuration, the top surface S2' of the embedded connection region 13 extends at least to contact the bottom surface S2 of the well region 12, and the embedded connection region 13 extends vertically downward from its top surface S2' into the substrate 100S, for example, into the initial substrate layer 101. The bottom surface S3 of the embedded connection region 13 is located at a distance substantially equal to the connection depth d2 from the top surface S1 of the substrate 100S and contacts and connects with the bottom layer 14. Those skilled in the art will understand that in... Figure 1 In this embodiment, the bottom surface S2 of the well region 12 and the top surface S2' of the buried connection region 13 substantially coincide and / or are coplanar. Those skilled in the art should also understand that in actual semiconductor devices, the interfaces between adjacent doped regions (e.g., the interface S2 or S2' between the well region 12 and the buried connection region 13) may not be as neat and clear as theoretically shown in the illustrations of the various embodiments of the present invention. During manufacturing, due to the diffusion of dopants or dopant ions, adjacent doped regions may interpenetrate at the interface, resulting in a blurred interface that is still generally identifiable.

[0041] According to an exemplary embodiment, the buried connection region 13 may be doped with a second conductivity type dopant (e.g., antimony or arsenic), which is suitable for and compatible with low-energy implantation processes, such as keV levels (i.e., 10⁻⁶ kHz). 3 The buried connection region 13 is formed by implanting a second conductivity type dopant (e.g., antimony or arsenic) suitable for and compatible with low-energy (e.g., keV level) implantation processes into the initial substrate layer 101 from the top surface S5 of the initial substrate layer 101. This formation process is completed before the epitaxial layer 102 is formed above the initial substrate layer 101. In one embodiment, the low-energy (e.g., keV level) implantation process includes implanting a dopant with an implantation energy not exceeding 200 keV. In another embodiment, the low-energy (e.g., keV level) implantation process includes implanting a dopant with an implantation energy ranging from 20 keV to 50 keV. The buried connection region 13 has a connection doping concentration. In one embodiment, the connection doping concentration of the buried connection region 13 is higher than the well region doping concentration of the well region 12. In another embodiment, the connection doping concentration of the buried connection region 13 is on the same order of magnitude or the same as the lead-out region doping concentration of the lead-out region 11. Figure 1In the illustrated example, the buried connection region 13 is schematically shown as an N+ region, characterized by a higher connection doping concentration than the well region doping concentration of the well region 12, shown as an N-type region. However, those skilled in the art will understand that the connection doping concentration of the buried connection region 13 may differ from the lead-out region doping concentration of the lead-out region 11. In one embodiment, the connection doping concentration ranges from 1e17 cm⁻¹. -3 Up to 1e20 cm -3 .

[0042] The bottom layer 14 contains a second conductivity type (e.g.) Figure 1 The second buried layer (type N) is embedded in the substrate 100S. In one embodiment, the bottom layer 14 is embedded in the substrate 100S, and the distance between its top surface S4 and the top surface S1 of the substrate 100S is substantially the embedment depth d3. In other words, the embedment depth d3 is substantially characterized as the direct vertical distance from the top surface S1 of the substrate 100S to the top surface S4 of the bottom layer 14 embedded in the substrate 100S. In one embodiment, the embedment depth of the bottom layer (i.e., the second buried layer) 14 in the substrate 100S is greater than the embedment depth of the embedded connection region (i.e., the first buried layer) 13 in the substrate 100S relative to (or when measured with reference to) the top surface S1 of the substrate 100S. In one embodiment, the bottom layer (i.e., the second buried layer) 14 is formed or embedded in the initial substrate layer 101. In one embodiment, the embedment depth of the bottom layer 14 (or the second embedded layer 14) in the substrate 100S is greater than the embedment depth of the embedded connection area 13 (or the first embedded layer 13) in the substrate 100S, because the depth of the bottom surface S14 of the bottom layer 14 is greater than the depth of the bottom surface S3 of the embedded connection area 13 relative to the top surface S1 of the substrate 100S.

[0043] In one embodiment, the bottom surface S3 of the embedded connection area 13 extends at least to contact the top surface S4 of the bottom layer 14, thereby substantially coinciding with and coplanar with the top surface S4 of the bottom layer 14, so that the embedded connection area 13 and the bottom layer 14 are interconnected. In one embodiment, such as Figure 1As shown, the bottom surface S3 of the buried connection region 13 is slightly deeper than the top surface S4 of the bottom layer 14 relative to the top surface S1 of the substrate 100S. As previously mentioned, those skilled in the art should understand that in actual semiconductor devices, the interfaces between adjacent doped regions (e.g., the interface S2 / S2' between the well region 12 and the buried connection region 13, and the interface between the bottom surface S3 of the buried connection region 13 and the top surface S4 of the bottom layer 14, etc.) may not be as neat and clear as theoretically shown in the illustrations of the various embodiments of the present invention. Adjacent doped regions may interpenetrate at the interface, which is caused by the diffusion of dopant ions during manufacturing, making the interface blurred but still roughly identifiable. This explanation will not be repeated later in this specification.

[0044] In one embodiment, the bottom layer 14 is embedded in the initial substrate layer 101, and the embedment depth of its peak doping concentration plane S6 from the top surface S5 of the initial substrate layer 101 is d5. In other words, the embedment depth d5 ​​refers to the direct vertical distance from the top surface S5 of the initial substrate layer 101 to the peak doping concentration plane S6 of the bottom layer 14 embedded in the initial substrate layer 101. Those skilled in the art will understand that the peak doping concentration plane S6 refers to the plane at which the peak doping concentration value of the bottom layer 14 is measured. As is known to those skilled in the art, the doping concentration distribution of any single doped region in a semiconductor device is not ideally uniform due to the diffusive physical properties of dopants. Typically, the dopant implantation location used to form the doped region has a peak doping concentration value. This dopant implantation location is referred to herein as the implantation location for ease of description. As is known to those skilled in the art, the doping concentration of the doped region typically decreases gradually from the implantation location away from that location. Therefore, the peak doping concentration plane S6 may also be referred to as the implantation plane forming the bottom layer 14, and the embedment depth d5 ​​may also be referred to as the implantation depth forming the bottom layer 14. According to various embodiments of the present invention, the embedment depth d5 ​​is substantially greater than 0.5 μm. In an exemplary embodiment, the embedment depth d5 ​​is substantially in the range of 1 μm to 5 μm. In an alternative exemplary embodiment, the embedment depth d5 ​​is substantially in the range of 1 μm to 3.5 μm.

[0045] In one embodiment, the embedment depth of the bottom layer 14 (i.e., the second buried layer 14) in the substrate 100S relative to the top surface S5 of the initial substrate layer 101 is greater than the embedment depth of the buried connection region 13 (i.e., the first buried layer 13) in the substrate 100S. This is because, relative to the top surface S5 of the initial substrate layer 101, the embedment depth of the peak doping concentration plane S6 of the bottom layer 14 is greater than the embedment depth of the peak doping concentration plane S13 of the buried connection region 13. Those skilled in the art will understand that the peak doping concentration plane S13 refers to the position plane where the peak doping concentration value of the buried connection region 13 is measured. The peak doping concentration plane S13 of the buried connection region 13 may also be referred to as the implantation plane used to form the buried connection region 13. In one embodiment, the peak doping concentration plane S6 of the bottom layer 14 is 0.5 μm to 3.5 μm deeper than the peak doping concentration plane S13 of the buried connection region 13 relative to the top surface S5 of the initial substrate layer 101. In one embodiment, the peak doping concentration plane S6 of the bottom layer 14 is 1 μm to 2 μm deeper than the peak doping concentration plane S13 of the buried connection region 13 relative to the top surface S5 of the initial substrate layer 101.

[0046] In one embodiment, the bottom layer 14 is doped with a second conductivity type dopant (e.g., phosphorus), which is suitable for and compatible with high-energy implantation processes, such as MeV-level (i.e., 10⁻⁶ voltammetric ... 6 In one embodiment, the high-energy (e.g., MeV level) implantation process includes a dopant with an implantation energy of not less than 1 MeV. In another embodiment, the high-energy (e.g., MeV level) implantation process includes a dopant with an implantation energy of 1 MeV to 4 MeV. The bottom layer 14 is formed by implanting a second conductivity type dopant (e.g., phosphorus) suitable for and compatible with high-energy (e.g., MeV level) implantation processes from the top surface S5 of the initial substrate layer 101 into the initial substrate layer 101, the formation process being completed before the epitaxial layer 102 is formed above the initial substrate layer 101. In one embodiment, the bottom layer doping concentration of the bottom layer 14 is less than (e.g., less than 1e1cm). -3 up to 1e3cm -3 The doping concentration of the buried regions formed in the initial substrate layer 101 by a relatively low-energy (e.g., keV level) implantation process. For example, in one embodiment, the bottom layer 14 has a lower bottom layer doping concentration than the connection doping concentration of the buried connection region 13. Further, the bottom layer doping concentration is 1e1 cm lower than the connection doping concentration of the buried connection region 13 formed by the relatively low-energy (e.g., keV level) implantation process. -3 up to 1e3cm -3In other words, the doping concentration of the bottom layer 14 is one to three orders of magnitude lower than the doping concentration of the buried regions (e.g., the connection doping concentration of the buried connection region 13) formed in the initial substrate layer 101 through a relatively low-energy (e.g., keV level) implantation process. In one embodiment, the bottom layer doping concentration ranges from 5e15 cm⁻¹. -3 up to 1e18 cm -3 This range is not limited to this; it can also be higher, but not exceeding 1e19 cm. -3 .exist Figure 1 In the example shown, the bottom layer 14 is schematically shown as an N-type region, indicating that its bottom layer doping concentration is lower than the connection doping concentration of the buried connection region 13, which is schematically shown as an N+ region, as will be understood by those skilled in the art. Figure 1 The region near the implantation plane S6, indicated by a darker stripe, shows that the doping concentration of the underlying layer in this region is relatively high, and the doping concentration of the underlying layer gradually decreases from the region near the implantation plane S6 to the region of the underlying layer 14 that is far away from the implantation plane S6.

[0047] Traditionally, a second buried layer (e.g., a second buried layer 14) with a greater buried depth than the first buried layer 13 cannot be formed in the substrate 100S, except for the first buried layer 13. Unlike conventional processes that use relatively low-energy (e.g., keV level) implantation processes to implant a second conductivity type dopant (e.g., antimony or arsenic) suitable for and compatible with low-energy implantation processes into the initial substrate layer 101, which cannot form a buried layer with a peak doping concentration plane located below the top surface S5 of the initial substrate layer 101 and a buried depth (hereinafter denoted as di) greater than 0.5 μm, according to various embodiments of this disclosure, a bottom layer 14 doped with a second conductivity type dopant (e.g., phosphorus) suitable for and compatible with high-energy (e.g., MeV level) implantation processes can advantageously result in a buried depth d5 ​​greater than 0.5 μm. For example, in one embodiment, the buried depth d5 ​​is greater than 1 μm. This helps to increase the well depth d1 of the well region 12 of the semiconductor device 100, and / or the connection depth d2 of the bottom surface S3 of the first buried connection region 13, and / or the burial depth d3 of the top surface S4 of the bottom layer 14, and / or the vertical height d4 of the buried connection region 13, thereby facilitating the formation of a high-voltage transistor within the well region and enabling the high-voltage transistor to obtain an improved breakdown voltage.

[0048] Figure 3 Waveform diagram 300 is shown, in which the first curve 301 shows the doping concentration Cx (unit: cm⁻¹) of the semiconductor device 100 along the dicing line BB' in one embodiment of the present invention. -3The relationship between the doping concentration Cx and the distance Dx (unit: μm), where Dx is the distance measured from the top surface S5 of the initial substrate layer 101, is shown in the second curve 302. This curve illustrates the relationship between the doping concentration Cx and the distance Dx (measured in μm), where Dx is the distance measured from the top surface S5 of the initial substrate layer 101. The second curve 302 shows the relationship between the doping concentration Cx and the distance Dx (measured in μm) when the semiconductor device 100 is formed as a buried layer to be used as the bottom layer 14 using a relatively low-energy (e.g., keV) implantation process. -3 The waveform 300 shows the relationship between the distance Dx (in μm) and the doping concentration Cx (in cm⁻¹). Dx is the distance measured from the top surface S5 of the initial substrate layer 101. In waveform 300, the horizontal axis represents the distance Dx (in μm), and the vertical axis perpendicular to the horizontal axis represents the doping concentration Cx (in cm⁻¹). -3 The zero point (Dx = 0 μm) represents the location of the top surface S5 of the initial substrate layer 101. The distance Dx from the top surface S5 of the initial substrate layer 101 towards the top surface S1 of the epitaxial layer 102 is represented by a negative value, and the distance Dx from the top surface S5 of the initial substrate layer 101 towards the bottom surface S0 of the substrate 100S is represented by a positive value. Those skilled in the art will understand that Figure 300 only shows a portion of the initial substrate layer 101 (represented by the positive distance Dx) (e.g., the portion including the bottom layer 14), and the remaining unshown portions are represented by… Figure 3 The dashed ellipsis in the text indicates... (The sentence is incomplete and requires more context to translate accurately.) Figure 3 As can be seen, referring to the first curve 301, the buried depth d5 ​​of the bottom layer 14 of the semiconductor device 100 according to an embodiment of the present invention is 2.1 μm. In contrast, referring to the second curve 302, if the semiconductor device 100 uses a relatively low-energy (e.g., keV level) implantation process to form the buried layer intended to serve as the bottom layer 14, the buried depth di of the buried layer (i.e., the direct vertical distance from the top surface S5 of the initial substrate layer 101 to the plane of the peak doping concentration of the buried layer) is only substantially 0.5 μm.

[0049] According to various embodiments of the present invention, the buried depth d5 ​​of the bottom layer 14 of the semiconductor device 100 is greater than the buried depth achievable by implanting a second conductivity type dopant (e.g., antimony or arsenic) suitable for and compatible with a low-energy (e.g., keV level) implantation process into the initial substrate layer 101 (e.g., greater by 0.5 μm to 3.5 μm). For example, the buried depth d5 ​​is 1 μm to 2 μm greater than the buried depth achievable by the bottom layer 14 doped with a second conductivity type dopant, such as antimony or arsenic, suitable for and compatible with an implantation process of low energy (e.g., keV level) implantation into the initial substrate layer 101. As another example, the buried depth d5 ​​of the bottom layer 14 is 0.5 μm to 3.5 μm greater than the buried depth di of the buried region (e.g., buried connection region 13) formed in the initial substrate layer 101 by a relatively low-energy (e.g., keV level) implantation process. For example, the embedment depth d5 ​​of the bottom layer 14 is 1 μm to 2 μm greater than the embedment depth di of the embedment region (e.g., the embedment connection region 13) formed in the initial substrate layer 101 by a relatively low-energy (e.g., keV level) implantation process.

[0050] Depend on Figure 3 As can be seen, in the semiconductor device 100 according to the embodiment of the present invention, the peak doping concentration value of the bottom layer 14 at the peak doping concentration plane S6 is 1e16cm. -3 (Refer to the first curve 301). As previously mentioned, those skilled in the art can use the peak doping concentration value of the underlying layer 14, measured in an actual manufactured semiconductor device 100, to represent the doping concentration of the underlying layer 14. In contrast, referring to the second curve 302, if the semiconductor device 100 uses a relatively low-energy (e.g., keV level) implantation process to form the buried layer intended as the underlying layer 14, the peak doping concentration value of this buried layer at the peak doping concentration plane is substantially 6e17 cm⁻¹. -3 .

[0051] According to various embodiments of the present invention, the semiconductor device 100 may have a bottom layer 14 with a peak doping concentration value lower than (e.g., lower than 1e1 cm⁻¹). -3 up to 1e3 cm -3 If the bottom layer 14 is doped with a second conductivity type dopant (e.g., antimony or arsenic) at a concentration level that is suitable for and compatible with low-energy (e.g., keV level) implantation processes applied to the initial substrate layer 101, this is beneficial for improving the breakdown voltage of the semiconductor device 100. That is, the bottom layer doping concentration of the bottom layer 14 is 1e1cm lower than the doping concentration of the buried region (e.g., buried connection region 13) formed in the initial substrate layer by the low-energy implantation process. -3 up to 1e3 cm -3 .

[0052] According to an exemplary embodiment of the present invention, the semiconductor device 100 may include a high-voltage transistor formed on a portion of the substrate 100S in the barrel-like structure. In one embodiment, for example, the high-voltage transistor includes a plurality of transistor units. Here, the term "plural" is not limited to more than one, but also includes the case of one. Figure 1 In the example shown, only two transistor units are schematically illustrated to aid in understanding the embodiment, and not as a limiting description.

[0053] For each of the plurality of transistor units, a source region (e.g., in one example, it may serve as the source region of a MOSFET) 103 may be formed in a substrate 100S and located near the top surface S1 of the substrate 100S. Figure 1 In the example shown, for each of the plurality of transistor cells, a source region 103 is formed in the epitaxial layer 102 and close to the top surface of the epitaxial layer 102 (also labeled S1). The source region 103 is of a second conductivity type (e.g., N-type) and has a source doping concentration that enables it to serve as the source region of a high-voltage transistor formed in the barrel-like structure; therefore, those skilled in the art refer to it as a "highly doped" region (e.g., in...). Figure 1 (shown as N+ region). In one embodiment, the source doping concentration is higher than the well doping concentration of the well region 12. In one embodiment, the source doping concentration ranges from 1e19 cm⁻¹. -3 up to 5e20 cm -3 .

[0054] According to an exemplary embodiment of the present invention, for each of the plurality of transistor cells, a drain region (e.g., in one example, it may serve as the drain region of a MOSFET) 104 may be formed in the substrate 100S and located near the top surface S1 of the substrate 100S. Figure 1 In the example shown, for each of the plurality of transistor cells, a drain region 104 is formed in the epitaxial layer 102 and close to the top surface of the epitaxial layer 102 (also labeled S1). For each of the plurality of transistor cells, the drain region 104 is separated from the source region 103. The drain region 104 is of a second conductivity type (e.g., N-type) and has a drain doping concentration that enables it to serve as the drain region of a high-voltage transistor formed in a barrel-like structure; therefore, those skilled in the art refer to it as a "highly doped" region (e.g., in...). Figure 1 (shown as N+ region). In one embodiment, the drain doping concentration is higher than the well doping concentration of the well region 12. In one embodiment, the drain doping concentration ranges from 1e19 cm⁻¹. -3 up to 5e20cm -3 .

[0055] According to an exemplary embodiment, the barrel-like structure is electrically coupled to the drain region 104 of a high-voltage transistor formed therein, for example... Figure 1 As shown, the drain region 104 is coupled to the lead-out region 11 through the connecting wire structure 18.

[0056] According to an exemplary embodiment, for substrate 100S (e.g., in Figure 1 In the example shown, a body region 105 of a first conductivity type (e.g., P-type) may be disposed around the source region 103 of each of the plurality of transistor cells in the epitaxial layer 102. Figure 1 In the example shown, body region 105 is schematically shown as a P-type region. Body region 105 has a body region doping concentration. In one embodiment, the body region doping concentration ranges from 5e16 cm⁻¹. -3 up to 1e18 cm -3 .

[0057] According to an exemplary embodiment, for each of the plurality of transistor cells, a body contact region 106 of a first conductivity type (e.g., P-type) is formed in the substrate 100S, immediately adjacent to the source region 103 in the substrate 100S. The body contact region 106 is located near the top surface S1 of the substrate 100S and laterally adjacent to the source region 103. Figure 1 In the example shown, in each of the plurality of transistor cells, a body contact region 106 is formed in the epitaxial layer 102 and immediately adjacent to the source region 103. Figure 1 In the example shown, the body contact region 106 is schematically shown as a P+ region. The body contact region 106 has a body contact doping concentration that is higher than the body region doping concentration. In one embodiment, the body contact doping concentration ranges from 5e18 cm⁻¹. -3 Up to 1e20cm -3 According to an exemplary embodiment of the present invention, the body contact region 106 may contact the source region 103 and the body region 105 to achieve electrical connection with the source region 103 and the body region 105.

[0058] According to an exemplary embodiment of the present invention, for each of the plurality of transistor cells, a gate region 107 is formed between the source region 103 and the drain region 104 and is close to the source region 103. For each of the plurality of transistor cells, the gate region 107 is located on the top surface S1 of the substrate 100S (e.g., on...). Figure 1 The example shown has an epitaxial layer 102 on its top surface S1, and at least covers a portion of the body region 105 to form a channel region. The gate region 107 includes a gate dielectric layer 1071 and a gate conductive layer 1072. Those skilled in the art will understand that... Figure 1The gate region 107 shown is merely a simplified, illustrative example. The gate region 107 can take various structures without departing from the spirit and scope of the invention. For example, in one embodiment, the gate dielectric layer 1071 includes a portion of thin gate dielectric and a portion of thicker gate dielectric than the thin gate dielectric. The thin gate dielectric portion is located above the epitaxial layer 102 near the source region 103, and the thick gate dielectric portion is located above the epitaxial layer 102 between the thin gate dielectric portion and the drain region 104. The gate conductive layer 1072 at least covers a portion of the thin gate dielectric portion and a portion of the thick gate dielectric portion. Alternatively, the thick gate dielectric portion can be replaced by a shallow trench dielectric structure located in a shallow trench formed in a portion of the epitaxial layer 102, between the thin gate dielectric portion and the drain region 104. Furthermore, a conductive field plate can be formed, at least a portion of which is located within the shallow trench dielectric structure.

[0059] According to an exemplary embodiment of the present invention, for each of the plurality of transistor cells, a drift region 109 may be further formed in the substrate 100S surrounding the drain region 104. For each of the plurality of transistor cells, the drift region 109 extends toward and is separated from the source region 103. In one embodiment, the drift region 109 of each of the plurality of transistor cells extends laterally from the drain region 104 toward the source region 103, such that a portion of the drift region 109 is located below a portion of the gate region 107. In other words, the gate region 107 includes a region covering a portion of the drift region 109. In one embodiment, the drift region 109 of each of the plurality of transistor cells is of a second conductivity type (e.g., N-type) and has a drift doping concentration. In one embodiment, this drift doping concentration is lower than the drain doping concentration. Figure 1 In the example shown, drift region 109 is schematically shown as an N-well region, indicating that its drift doping concentration is lower than the drain doping concentration of drain region 104, which is schematically shown as an N+ doped region. In one embodiment, the drift doping concentration of drift region 109 ranges from 5e15 cm⁻¹. -3 up to 5e17 cm -3 .

[0060] According to an exemplary embodiment of the present invention, for each of the plurality of transistor cells, a body well region 108 may be selectively formed in the substrate 100S and surrounds the body region 105 of each of the plurality of transistor cells (e.g., in...). Figure 1 The surrounding area of ​​the epitaxial layer 102 in the example shown. In one embodiment, the body well region 108 of each of the plurality of transistor cells is of a first conductivity type (e.g., P-type). Figure 1In the example shown, the body well region 108 is schematically shown as a P-type region. This body well region 108 has a body well doping concentration. In one embodiment, the body well doping concentration of the body well region 108 is lower than the body doping concentration of the body region 105. In one embodiment, the body well doping concentration of the body well region 108 ranges from 5e16cm. -3 up to 1e18 cm -3 The body well region 108 helps reduce the on-resistance of high-voltage transistors that contain multiple transistor cells.

[0061] According to an exemplary embodiment of the present invention, for each of the plurality of transistor cells, a RESURF (Reduced Surface Field) region 110 is optionally formed in the substrate 100S, located below and / or around the body region 105, body well region 108 (if present), and drift region 109 of the substrate 100S of each of the plurality of transistor cells (e.g., in the...). Figure 1 (Example shown in epitaxial layer 102). In one embodiment, the RESURF region 110 of each of the plurality of transistor cells is of a first conductivity type (e.g., P-type). Figure 1 In the example shown, the RESURF region 110 is schematically shown as a P-type region. The RESURF region 110 has a RESURF doping concentration. In one embodiment, the RESURF doping concentration of the RESURF region 110 is lower than the body doping concentration of the body region 105 and / or lower than the body well doping concentration of the body well region 108 (if present). In one embodiment, the RESURF doping concentration of the RESURF region 110 ranges from 5e15 cm⁻¹. -3 up to 5e17 cm -3 The RESURF region 110 helps to reduce the on-resistance of the high-voltage transistor and / or improve the breakdown voltage of the high-voltage transistor.

[0062] According to various embodiments of the present invention, the semiconductor device 100 has a vertical junction breakdown control distance d6, in Figure 1In the example shown, this distance refers to the direct vertical distance from the bottom surface S7 of the RESURF region 110 to the peak doping concentration plane S6 of the bottom layer 14 of the barrel-like structure. The maximum value of the vertical junction breakdown control distance d6 of the semiconductor device 100 achievable or manufacturable according to embodiments of the present invention is improved to a value superior to that achievable in prior art semiconductor devices. This is at least in one aspect because the burial depth d5 ​​of the bottom layer 14 in the semiconductor device 100 according to embodiments of the present invention is greater than the burial depth achievable in prior art semiconductor devices. The vertical junction breakdown control distance d6 is one of several key factors affecting the high-voltage withstand performance of the semiconductor device 100. For example, a larger vertical junction breakdown control distance d6 is beneficial to increasing the vertical junction breakdown voltage Vjbt between the body region 105 and the bottom layer 14, thereby benefiting the breakdown voltage of the high-voltage transistor or the overall high-voltage withstand capability of the semiconductor device 100. That is, the vertical junction breakdown voltage Vjbt between the body region 105 and the bottom layer 14 increases with increasing vertical junction breakdown control distance d6 or burial depth d5 ​​of the bottom layer 14.

[0063] One of the major bottlenecks in developing transistors suitable for high-voltage applications (requiring high voltage withstand capabilities, such as exceeding 70V, and especially exceeding 100V) – such as high-voltage MOS transistors – lies in the limited vertical junction breakdown voltage (Vjbt) between the body region and the buried layer formed in the initial substrate layer beneath the transistor's epitaxial layer. The buried layer is typically used to isolate the body region from the transistor's initial substrate layer. In the prior art, for example, increasing the vertical junction breakdown voltage (Vjbt) of conventional transistors to above 70V, especially above 100V, is very difficult. One method to increase the vertical junction breakdown voltage (Vjbt) is to thicken the epitaxial layer of conventional transistors, as a thicker epitaxial layer allows for a greater distance between the body region and the buried layer. This method is effective for manufacturing transistors that meet the voltage withstand requirements of low- to medium-voltage (e.g., not exceeding 70V) applications. However, when attempting to fabricate high-voltage transistors with high withstand voltages (e.g., exceeding 70V, or even exceeding 100V), further thickening the epitaxial layer (e.g., using two- or multi-step epitaxial processes to create a multilayer thick epitaxial layer) presents other technical challenges, including the difficulty, or even inability, to connect the buried layer formed in the initial substrate layer beneath the multilayer (e.g., two or more) thick epitaxial layer to the lead-out region formed near the top surface of the multilayer thick epitaxial layer. It is crucial to connect the buried layer and the lead-out region using a doped well region with the same conductivity type as the buried layer and the lead-out region to form a barrel-like structure, so that the high-voltage transistor can be positioned within the well region as described in the semiconductor device 100 example. Unfortunately, even with the introduction of high-energy implantation processes and long-duration, high-temperature (e.g., 1100–1200°C) process steps, it is difficult to form a doped well region within a multilayer thick epitaxial layer that can sufficiently diffuse to connect the lead-out region to the buried layer. This multilayer thick epitaxial layer (e.g., exceeding 10 μm in thickness) must be thick enough to support a sufficiently high vertical junction breakdown voltage Vjbt (e.g., exceeding 70V, and even exceeding 100V) between the body region and the buried layer of a conventional transistor. Furthermore, current semiconductor manufacturing processes have limited space for high-temperature, long-duration implantation steps.

[0064] An alternative could be a deep trench take-off zone that reaches the embedded layer, but this involves complex and expensive process steps. Furthermore, the process of forming the deep trench take-off zone itself may introduce reliability and defect issues. Moreover, even using deep trench technology, the maximum achievable embedment depth (e.g., keV level) of the embedded layer formed by the aforementioned conventional low-energy (e.g., keV level) injection process is limited. Figure 3 As shown in di), there are limitations. The maximum distance that can be achieved or manufactured from the body region to the buried layer is still limited, which makes it a bottleneck to manufacture transistors with high voltage tolerance (e.g., over 70V, or even over 100V).

[0065] The semiconductor device 100 according to various embodiments of the present invention can overcome this long-standing technical bottleneck. The advantages of the various embodiments of the present invention include, but are not limited to, the ability to manufacture semiconductor devices with high-voltage transistors (e.g., exceeding 70V, and even particularly exceeding 100V), which is difficult to achieve even with very thick multilayer (e.g., two or more) epitaxial layers using conventional techniques, and these epitaxial layers require two or more epitaxial processes and / or long-duration drive-in and high-temperature (e.g., 1100–1200°C) implantation processes and / or deep trench lead-out techniques. For example, the semiconductor device 100 according to embodiments of the present invention has a high-voltage transistor with a breakdown voltage of 100V to 250V, formed using an epitaxial layer 102 with a thickness of 8μm to 16μm, which is almost impossible to achieve in the prior art. The manufacturing process of the semiconductor device 100 according to various embodiments of the present invention only requires an additional masking step compatible with typical manufacturing processes, making it simple and cost-effective.

[0066] According to an exemplary embodiment of the present invention, the semiconductor device 100 further includes a substrate wiring structure, the structure including a substrate lead-out region 111 and a substrate connection well region 112. The substrate wiring structure is used to provide a path of a first conductivity type to electrically lead out the substrate 100S. The substrate lead-out region 111 is formed in the substrate 100S and is located near the top surface S1 of the substrate 100S. The substrate lead-out region 111 can be isolated from the lead-out region 11 by a shallow trench isolation structure (STI) 114. The substrate lead-out region 111 is of a first conductivity type (e.g., P-type) and has a substrate lead-out doping concentration that allows the substrate lead-out region 111 to serve as a contact region of the substrate 100S, thereby allowing the substrate 100S to be electrically connected to a metal contact point (hereinafter referred to as a substrate metal contact point) formed above the substrate lead-out region 111. The substrate lead-out region 111 facilitates the formation of an ohmic contact between the substrate 100S and the substrate metal contact point, and is therefore referred to by those skilled in the art as a "highly doped" region (e.g., in...). Figure 1 (Seen as the P+ region). The substrate connection well region 112 is formed in the substrate 100S and surrounds the substrate lead-out region 111 (e.g., in...). Figure 1 (Example shown in epitaxial layer 102). In one embodiment, the substrate connection well region 112 is of a first conductivity type (e.g., P-type). Figure 1 In the example shown, the substrate connection well region 112 is schematically shown as a P-type region. The substrate connection well region 112 has a lower substrate connection well doping concentration than the substrate lead-out region 111. The substrate connection well region 112 helps to reduce the wiring resistance from the substrate 100S to the metal contact point that realizes the electrical lead-out of the substrate 100S.

[0067] According to an exemplary embodiment of the present invention, the substrate wiring structure of the semiconductor device 100 may optionally further include a substrate connection deep well region 113. The substrate connection deep well region 113 may optionally be formed in the substrate 100S (e.g., in...). Figure 1 The substrate connection well region 112 is located below and / or around the epitaxial layer 102 shown in the example. In one embodiment, the substrate connection deep well region 113 may be of a first conductivity type (e.g., P-type). Figure 1 In the example shown, substrate connection deep well region 113 is schematically shown as a P-type region. Substrate connection deep well region 113 has a lower substrate connection deep well doping concentration than the substrate connection well doping concentration of substrate connection well region 112. Substrate connection deep well region 113 helps to further reduce the wiring resistance from substrate 100S to the metal contact used to realize the electrical lead-out of substrate 100S.

[0068] The accompanying drawings exemplarily illustrate a limited portion of the high-voltage transistor in the semiconductor device 100, but it should be understood that the semiconductor device 100 may also include other elements not shown.

[0069] Figure 4 A partial cross-sectional schematic diagram of a semiconductor device 400 is shown, which includes a transistor according to an alternative embodiment of the present invention. Figure 1 Compared to the semiconductor device 100 shown, Figure 4 The semiconductor device 400 shown may optionally omit the body well region 108 of each of the plurality of transistor units. Those skilled in the art will understand that, in addition to the body well region 108, Figure 4 Except where not formed in the example, refer to Figure 1 The foregoing description of most of the semiconductor device 100 applies to Figure 4 Semiconductor device 400 in the example.

[0070] Figure 5 A partial cross-sectional schematic diagram of a semiconductor device 500 is shown, which includes a transistor according to an alternative embodiment of the present invention. Figure 1 Compared to the semiconductor device 100 shown, Figure 5 The semiconductor device 500 shown may optionally omit the RESURF region 110 of each of the plurality of transistor units. Those skilled in the art will understand that, in addition to the RESURF region 110... Figure 5 Except where not formed in the example, refer to Figure 1 Most of the above description of semiconductor device 100 applies Figure 5 The example uses semiconductor device 500. In this case, Figure 5 In the example, the vertical junction breakdown control distance d6 refers to the direct vertical distance from the bottom surface S8 of the drift region 109 to the peak doping concentration plane S6 of the bottom layer 14.

[0071] Figure 6 A partial cross-sectional schematic diagram of a semiconductor device 600 is shown, which includes a transistor according to an alternative embodiment of the present invention. Figure 1 Compared to the semiconductor device 100 shown, Figure 6 The semiconductor device 600 shown may optionally omit the body well region 108 and the RESURF region 110 of each of the plurality of transistor units. Those skilled in the art will understand that, in addition to the body well region 108 and the RESURF region 110... Figure 6 Except where not formed in the example, refer to Figure 1 Most of the above description of semiconductor device 100 applies Figure 6 The example shows semiconductor device 600. In this case, Figure 6 In the example, the vertical junction breakdown control distance d6 refers to the direct vertical distance from the bottom surface S8 of the drift region 109 to the peak doping concentration plane S6 of the bottom layer 14.

[0072] Figure 7 A partial cross-sectional schematic diagram of a semiconductor device 700 is shown, which includes a transistor according to an alternative embodiment of the present invention. Those skilled in the art will understand that, with reference to... Figure 1 Most of the above description of semiconductor device 100 applies Figure 7 The semiconductor device 700 in the example. One difference is that, in the semiconductor device 700, each of the plurality of sidewalls 10 within the barrel-like structure further includes a sidewall connection region 15, for example, see reference to Figure 1 A diagram of the left side wall 10-1 or the right side wall 10-2 is provided to aid understanding.

[0073] Each sidewall 10 has a sidewall connection region 15 formed and positioned between the sink region 12 and the embedded connection region 13. This sidewall connection region 15 is of a second conductivity type (e.g., ...). Figure 7 (N-type in the example shown). The sidewall connection area 15 is in physical contact with the lower part of the well area 12 and the upper part of the buried connection area 13, thereby providing an electrical connection between the well area 12 and the buried connection area 13. Since the buried connection area 13 is in physical contact with the bottom layer 14, a current path of a second conductivity type (e.g., N-type) is formed from the lead-out area 11 to the bottom layer 14.

[0074] exist Figure 7In the example shown, the sidewall connection region 15 extends vertically downward from the bottom surface S2 of the well region 12 into the substrate 100S, for example, into the epitaxial layer 102, such that the bottom surface S9 of the sidewall connection region 15 contacts the buried connection region 13. The buried connection region 13 extends vertically downward from the bottom surface S9 of the sidewall connection region 15 into the substrate 100S, for example, extending to the bottom surface S3 of the buried connection region 13 at a distance of connection depth d2 from the top surface S1 of the substrate 100S, such that it contacts the bottom layer 14. Those skilled in the art should understand that in... Figure 7 In the example shown, the bottom surface S2 of the well region 12 is substantially coincident and coplanar with the top surface of the sidewall connection region 15, while the bottom surface S9 of the sidewall connection region 15 is substantially coincident and coplanar with the top surface S2' of the buried connection region 13. Those skilled in the art will also understand that in actual semiconductor devices, the interfaces between adjacent doped regions (e.g., the interface S2 between the well region 12 and the sidewall connection region 15, and the interfaces S9 / S2' between the sidewall connection region 15 and the buried connection region 13) may not be as neat and clear as theoretically shown in the illustrations of the various embodiments of the present invention. During manufacturing, due to the diffusion of dopant ions, adjacent doped regions may interpenetrate at the interface, resulting in blurred interfaces that are still generally identifiable. The sidewall connection region 15 helps to further improve the breakdown voltage of the high-voltage transistor formed in the barrel-like structure 10 of the semiconductor device 700.

[0075] It should also be understood that, based on semiconductor device 700, similar references can also be made. Figures 4 to 6 The aforementioned variations. For example, in one embodiment, compared to Figure 7 The semiconductor device 700 shown, in a variant of the semiconductor device 700, each of the plurality of transistor units may optionally not form a body well region 108. In one embodiment, compared to Figure 7 In the semiconductor device 700 shown, as another variation of the semiconductor device 700, each of the plurality of transistor units may optionally not form a RESURF region 110. In one embodiment, compared to Figure 7 In the semiconductor device 700 shown, as another variation of the semiconductor device 700, each of the plurality of transistor units may optionally not form a body well region 108 and a RESURF region 110.

[0076] Figures 8A to 8Q A partial cross-sectional schematic diagram of a semiconductor device manufacturing method according to an embodiment of the present invention is shown. For example, referring to... Figures 1 to 7 It can form at least one of the semiconductor devices mentioned in the above examples. Figures 8A to 8QThe cross-sectional schematics are presented in a three-dimensional coordinate system with mutually perpendicular x, y, and z axes. It should be understood that these schematic cross-sectional views are observed / obtained with a cutting plane parallel to the xy-plane defined by the x and y axes. Each schematic cross-sectional view is a schematic cross-sectional image showing the area of ​​a high-voltage transistor in a semiconductor device (e.g., semiconductor devices 100, 400, 500, 600, 700, or variations thereof) to be formed at a specific process stage. Those skilled in the art will understand that the high-voltage transistor may include multiple (i.e., one or more) transistor units and may be referenced to… Figures 1 to 7 The barrel-like structure disclosed in the various embodiments is disposed in the substrate (e.g., substrate 100S) of the semiconductor device to be manufactured.

[0077] Reference Figures 8A to 8D A substrate of a first conductivity type (e.g., P-type) (e.g., substrate 100S) can be prepared. In one example, substrate 100S includes a semiconductor layer of the first conductivity type (e.g., P-type) (e.g., Figure 1 The initial substrate layer 101 shown and the epitaxial layer 102 formed on the initial substrate layer 101. It should be understood that, according to some embodiments, during the preparation of the substrate 100S, buried doped regions and / or buried layers may be formed in the substrate 100S, for example, in the initial substrate layer 101 or the epitaxial layer 102 by a doping process.

[0078] like Figure 8A In the process steps of the illustrated example structure 800A, a semiconductor layer (e.g., an initial substrate layer 101) is first provided. Subsequently, under the cover of a patterned implantation mask 801, a second conductivity type (e.g., N-type) dopant (e.g., phosphorus), suitable for and compatible with high-energy implantation processes, is implanted into the initial substrate layer 101 from its top surface S5. The patterned implantation mask 801 is formed on the top surface S5 of the initial substrate layer 101 and is patterned to expose predefined regions on the top surface S5 of the initial substrate layer 101, which will be implanted with dopant to form the bottom layer 14 of the barrel-like structure of the semiconductor device 100. This dopant is implanted into the initial substrate layer 101 to form a buried implantation region 14D located at the implantation plane S6 of the bottom layer 14. After the implantation process for forming the bottom layer 14 is completed, the patterned implantation mask 801 can be removed. More details about the bottom layer 14, such as its formation location, conductivity type (or dopant type), and doping concentration, can be found in the references. Figure 1 The existing descriptions are understood and will not be repeated here for the sake of simplicity.

[0079] like Figure 8BIn the process steps of the illustrated example structure 800B, a second conductivity type (e.g., N-type) dopant (e.g., antimony or arsenic), suitable for and compatible with low-energy implantation processes, is implanted from the top surface S5 of the initial substrate layer 101 into the initial substrate layer 101 under the cover of a patterned implantation mask 802. The patterned implantation mask 802 may be formed on the top surface S5 of the initial substrate layer 101 and patterned to expose predefined regions on the top surface S5 of the initial substrate layer 101, which will be implanted with dopant to form buried connection regions 13 of each of the plurality of sidewalls 10 of the barrel-shaped structure of the semiconductor device 100. For example, the left sidewall 10-1 and right sidewall 10-2 of the plurality of sidewalls 10 are schematically shown in a cross-sectional view. The dopant used to form the buried connection regions 13 is implanted into the initial substrate layer 101 to form buried implantation regions 13D located at the implantation plane S13 of the buried connection regions 13 of each of the plurality of sidewalls 10. After the implantation process for forming the buried connection region 13 is completed, the patterned first implantation mask 801 can be removed. More details regarding the formation location, conductivity type (or dopant type), and doping concentration of the buried connection region 13 can be found in the reference. Figure 1 The existing descriptions are understood and will not be repeated here for simplicity. Those skilled in the art should understand that... Figure 8A and Figure 8B The steps shown may not be performed in the order described herein. In alternative embodiments, they may be performed first. Figure 8B Follow the steps shown, then execute. Figure 8A The steps are shown.

[0080] Reference Figure 8C To execute the propulsion process, so that in Figure 8A and Figure 8B In the steps shown, the second conductivity type (e.g., N-type) dopant implanted into the initial substrate layer 101 diffuses. The buried implantation region 13D diffuses to form a buried connection region 13 in each of the plurality of sidewalls 10, and the buried implantation region 14D diffuses to form the bottom layer 14, as shown. Figure 8C The example structure shown is 800C.

[0081] like Figure 8D In the process steps of the illustrated 800D structure, an epitaxial layer 102 is formed on the initial substrate layer 101. The epitaxial layer 102 can be a single-layer epitaxial layer formed by a single-step epitaxial process, or a multi-layer epitaxial layer formed by two or more steps, depending on the actual device specifications of the high-voltage transistor formed in the substrate 100S, such as breakdown voltage and on-resistance. More details regarding the composition, conductivity type (or dopant type), and doping concentration of the epitaxial layer 102 can be found in the reference [reference needed]. Figure 1 The existing descriptions are understood and will not be repeated here for simplicity. Those skilled in the art should understand that, as... Figure 1 The above and Figure 8DAs shown, the buried connection region 13 of each of the plurality of sidewalls 10 may extend partially into the epitaxial layer 102 after its formation due to the self-doping phenomenon described above. It should also be understood that during the formation of the epitaxial layer 102, some buried doped regions and / or buried layers may be formed in the epitaxial layer 102 through doping processes.

[0082] In one embodiment, for example, refer to Figure 8E The illustrated example structure 800E allows for the selective formation of sidewall connection regions 15, each of a plurality of sidewalls 10 having a second conductivity type (e.g., N-type), within the epitaxial layer 102 of the substrate 100S via any suitable doping process. It should be understood that the process for forming these sidewall connection regions 15 can be used to fabricate semiconductor device embodiments having said sidewall connection regions 15, for example, with reference to… Figure 7 The semiconductor device 700 shown and described. For example, a second conductivity type (e.g., N-type) dopant can be implanted into a plurality of predefined locations in the epitaxial layer 102 under the masking of a patterned implantation mask to form a sidewall connection region 15 for each of a plurality of sidewalls 10. After the implantation process for forming the sidewall connection region 15 of each of the plurality of sidewalls 10 is completed, the patterned implantation mask used to form the sidewall connection region 15 can be removed. The sidewall connection region 15 of each of the plurality of sidewalls 10 can be a buried doped region embedded in the epitaxial layer 102, embedded in the epitaxial layer 102 at a predetermined sidewall connection depth (substantially equal to the well depth d1 of the well region 12 to be formed), for example, embedded in the lower portion 1021 of the epitaxial layer 102. In this case, the epitaxial layer 102 can be as follows: Figure 8D The multilayer epitaxial layer is formed through two or more epitaxial processes. The doping process for forming the sidewall connection region 15 of each of the plurality of sidewalls 10 (e.g., implanting a second conductivity type dopant into the lower portion 1021 of the epitaxial layer 102) can be performed between the epitaxial steps forming the lower portion 1021 and the upper portion 1022 of the epitaxial layer 102, as will be readily understood by those skilled in the art and will not be detailed here. Further details regarding the location, conductivity type (or dopant type), and doping concentration of the sidewall connection region 15 of each of the plurality of sidewalls 10 are provided in the references. Figure 7 As described in the description, this will not be repeated here for simplicity. It should also be understood that for semiconductor device embodiments where each of the plurality of sidewalls 10 in a barrel-like structure does not include a sidewall connection region 15 (e.g., refer to...), the following applies. Figure 1 The semiconductor device 100 shown and described does not require the process of forming the sidewall connection region 15.

[0083] In one embodiment, for example, refer to Figure 8FThe illustrated example structure 800F allows for the selective formation of a RESURF region having a first conductivity type (e.g., P-type) in each of a plurality of transistor cells of a high-voltage transistor to be fabricated in the substrate 100S (e.g., in the epitaxial layer 102) via any suitable doping process. The substrate connection deep well region 113 having the first conductivity type (e.g., P-type) can be formed by sharing the same doping process as the RESURF region 110 of each of the plurality of transistor cells in the high-voltage transistor. For example, a first conductivity type (e.g., P-type) dopant can be implanted into a plurality of predefined locations in the epitaxial layer 102 under the cover of a patterned implantation mask to form the RESURF region 110 and the substrate connection deep well region 113. In one embodiment, the patterned implantation mask used to form the RESURF region 110 and the substrate connection deep well region 113 can be removed after the implantation process used to form the RESURF region 110 and the substrate connection deep well region 113 of each of the plurality of transistor cells is completed. In one embodiment, the RESURF region 110 of each of the plurality of transistor units can be a buried doped region embedded in the epitaxial layer 102, with a buried depth of a predefined RESURF buried depth d7, for example... Figure 8F As shown. The predefined RESURF embedment depth d7 may be less than or shallower than the predefined well connection depth (e.g., equal to the well depth d1), which is obtained relative to the top surface S1 of the epitaxial layer 102. Figure 8F In the example shown, the substrate-connected deep well region 113, which is formed using the same doping process as the RESURF region 110, also appears as a buried doped region.

[0084] In an alternative embodiment, for example, refer to Figure 8G In the example structure 800G shown, the RESURF region 110 of each of the plurality of transistor cells is not necessarily formed as a buried doped region, but may instead be formed as a doped region extending from the top surface S1 to a predefined depth d8 into the epitaxial layer. Figure 8G In the example shown, the substrate-connected deep well region 113, formed using the same doping process as the RESURF region 110, also appears as a doped region extending from the top surface S1 to a predefined depth d8 into the epitaxial layer. The first conductivity type (e.g., P-type) dopant used to form the RESURF region 110 and the substrate-connected deep well region 113 is implanted from the top surface S1 of the epitaxial layer 102 into the epitaxial layer 102, which will be readily understood by those skilled in the art and will not be described in detail here. Further details regarding the RESURF region 110 and the substrate-connected deep well region 113 of each of the plurality of transistor cells of the high-voltage transistor to be fabricated in the substrate 100S, such as location, conductivity type (or dopant type), and doping concentration, can be found in the references. Figure 1 The existing descriptions are understood and will not be repeated here for the sake of simplicity.

[0085] exist Figure 8F and 8G In the example shown, the process for forming the RESURF region 110 of each of the plurality of transistor cells forming the high-voltage transistor and the process for forming the substrate interconnect deep well region 113 can be based on Figure 8E The structure 800E is implemented, which is suitable for manufacturing a semiconductor device embodiment comprising a plurality of sidewalls 10 in a well region, each having a sidewall connection region 15, and the high voltage transistor of the semiconductor device having the RESURF region 110, such as semiconductor device 700.

[0086] In an alternative embodiment, for example, refer to Figure 8H The example structure shown is 800H or Figure 8I The example structure 800I shown, in which the process of forming the RESURF region 110 of each of the plurality of transistor cells forming the high-voltage transistor and the process of forming the substrate interconnect deep well region 113 are considered to be based on Figure 8D The structure 800D is implemented, which is suitable for manufacturing semiconductor device embodiments in which each of the plurality of sidewalls 10 in a barrel-like structure does not have a sidewall connection region 15, and the high voltage transistor of the semiconductor device has the RESURF region 110, such as semiconductor device 100 or 400.

[0087] Therefore, it should be understood that the process for forming the RESURF region 110 of each of the plurality of transistor cells of the high-voltage transistor is suitable for manufacturing semiconductor device embodiments including a high-voltage transistor having the RESURF region 110, such as semiconductor devices 100, 400, or 700. It should also be understood that for manufacturing semiconductor device embodiments including the high-voltage transistor but where none of the plurality of transistor cells contains the RESURF region 110 (e.g., semiconductor devices 500 or 600), it is not necessary to perform the process for forming the RESURF region 110 of each of the plurality of transistor cells of the high-voltage transistor.

[0088] like Figure 8J In the process steps of the example structure 800J shown, it can be performed in the substrate 100S (e.g., in...). Figure 1In the example shown, the epitaxial layer 102 is used to form a drift region 109 of a second conductivity type (e.g., N-type) for each of the plurality of transistor cells of the high-voltage transistor using any suitable doping process. For example, dopants of a second conductivity type (e.g., N-type) can be implanted into a plurality of predefined locations on the epitaxial layer 102 under the cover of a patterned implantation mask 803 to form the drift regions 109 of the plurality of transistor cells of the high-voltage transistor to be manufactured. In one embodiment, the patterned implantation mask 803 is formed on the top surface S1 of the epitaxial layer 102 and patterned to expose predefined regions on the top surface S1 of the epitaxial layer 102 where dopants will be implanted to form the drift region 109 of each of the plurality of transistor cells of the high-voltage transistor. After the implantation process for forming the drift region 109 of each of the plurality of transistor cells is completed, the patterned implantation mask 803 can be removed. Figure 8J In the example shown, the doping process of the drift region 109 forming the plurality of transistor cells of the high-voltage transistor is based on Figure 8H The example structure 800H shown is implemented. However, it should be understood that the doping process described herein for forming the drift region 109 can be based on... Figures 8D to 8I The implementation of any of the structures 800D to 800I shown respectively depends on whether each of the plurality of sidewalls 10 of the barrel-like structure included in the semiconductor device to be manufactured has a sidewall connection region 15, and / or whether each of the plurality of transistor cells of the high-voltage transistor has a RESURF region 110. Further details regarding the drift region 109 of each of the plurality of transistor cells of the high-voltage transistor to be manufactured in the substrate 100S, such as location, conductivity type (or dopant type), and doping concentration, can be found in conjunction with reference to [reference needed]. Figure 1 The existing descriptions are understood and will not be repeated here for the sake of simplicity.

[0089] like Figure 8K In the process steps of the example structure 800K shown, a plurality of shallow trench isolation ("STI") structures 114 are formed. In one embodiment, the plurality of STI structures 114 are formed by etching a corresponding number of shallow trenches from the top surface S1 of the epitaxial layer 102 into the epitaxial layer 102 under the cover of a patterned trench etching mask, and then these shallow trenches are filled with an insulating material.

[0090] like Figure 8LIn the process steps of the illustrated example structure 800L, well regions 12 of a second conductivity type (e.g., N-type) in the plurality of sidewalls 10 (e.g., 10-1 and 10-2 schematically shown in the cross-sectional view) of the barrel-like structure to be formed in the substrate 100S can be formed by any suitable doping process. For example, a dopant of the second conductivity type (e.g., N-type) can be implanted into a plurality of predefined locations of the epitaxial layer 102 under the cover of a patterned implantation mask 804 to form a well region 12 for each of the plurality of sidewalls 10 of the barrel-like structure. In one embodiment, the patterned implantation mask 804 is formed on the top surface S1 of the epitaxial layer 102 and patterned to expose predefined regions on the top surface S1 of the epitaxial layer 102 that will be used for implantation to form the well region 12 for each of the plurality of sidewalls 10. According to one example, under the cover of a patterned implantation mask 804, a second conductivity type (e.g., phosphorus) dopant suitable for and compatible with this process can be implanted from the top surface S1 into the epitaxial layer 102 using a medium-to-high energy implantation process to form a well region 12 for each of the plurality of sidewalls 10. After the implantation process for forming the well region 12 for each of the plurality of sidewalls 10 is completed, the patterned implantation mask 804 can be removed. More details regarding the well region 12 for each of the plurality of sidewalls 10 to be fabricated in the substrate 100S, such as location, conductivity type (or dopant type), and doping concentration, can be found in the references. Figure 1 The existing descriptions are understood and will not be repeated here for the sake of simplicity.

[0091] like Figure 8MIn the process steps of the illustrated example structure 800M, a body well region 108 of a first conductivity type (e.g., P-type) for each of the plurality of transistor cells of the high-voltage transistor can be selectively formed in the substrate 100S (e.g., in the epitaxial layer 102) by any suitable doping process. A substrate connection well region 112 can share the same doping process as the body well region 108 of each of the plurality of transistor cells of the high-voltage transistor. For example, a first conductivity type (e.g., P-type) dopant can be injected into a plurality of predefined locations in the epitaxial layer 102 under the cover of a patterned injection mask 805 to form the body well region 108 and the substrate connection well region 112. In one embodiment, the patterned injection mask 805 is formed on the top surface S1 of the epitaxial layer 102 and patterned to expose predefined regions on the top surface S1 of the epitaxial layer 102, which will be doped to form the body well region 108 and the substrate connection well region 112 of each of the plurality of transistor cells in the high-voltage transistor. According to one example, under the cover of a patterned implantation mask 805, a dopant of a first conductivity type (e.g., P-type) can be implanted from the top surface S1 into the epitaxial layer 102 to form the body well region 108 and substrate connection well region 112 of a plurality of transistor cells in a high-voltage transistor. The patterned implantation mask 80 can be removed after the implantation process forming the body well region 108 and the substrate connection well region 112 is completed. More details regarding the body well region 108 of each of the plurality of transistor cells of the high-voltage transistor to be fabricated in the substrate 100S, such as location, conductivity type (or dopant type), and doping concentration, can be found in references. Figure 1 The existing descriptions are understood and will not be repeated here for simplicity. It should be understood that the process for forming the body well region 108 of each of the plurality of transistor cells of the high-voltage transistor is applicable to semiconductor device embodiments containing the body well region 108, such as semiconductor devices 100, 500, or 700. It should also be understood that for semiconductor device embodiments containing high-voltage transistors but where none of the plurality of transistor cells contains the body well region 108 (e.g., semiconductor devices 400 or 600), the process for forming the well region 108 is not required.

[0092] like Figure 8N In the process steps of the illustrated example structure 800N, a gate region 107 can be formed for each of the plurality of transistor cells of the high-voltage transistor to be manufactured in the substrate 100S. The gate region 107 can adopt various structures without departing from the spirit and scope of the invention, as shown in reference... Figure 1 As stated above.

[0093] like Figure 8OIn the process steps of the illustrated example structure 800O, a body region 105 of a first conductivity type (e.g., P-type) for each of the plurality of transistor cells to be fabricated in the substrate 100S can be formed by any suitable doping process. For example, a first conductivity type (e.g., P-type) dopant can be implanted into a plurality of predefined locations on the epitaxial layer 102 under the cover of a patterned implantation mask to form the body region 105 of each of the plurality of transistor cells. In one embodiment, the patterned implantation mask used to form the body region 105 can be removed after the implantation process for forming the body region 105 of each of the plurality of transistor cells is completed. More details about the body region 105 of each of the plurality of transistor cells to be fabricated in the substrate 100S, such as location, conductivity type (or dopant type), and doping concentration, can be found in the references. Figure 1 The existing descriptions are understood and will not be repeated here for the sake of simplicity.

[0094] like Figure 8P In the process steps of the illustrated example structure 800P, the source region 103 and drain region 104 (both having a second conductivity type, such as N-type) of each of the plurality of transistor cells to be fabricated in the substrate 100S for a high-voltage transistor can be formed by any suitable doping process. The lead-out region 11 of each of the plurality of sidewalls 10 (e.g., 10-1 and 10-2) in the barrel-like structure can share the same doping process as the source region 103 and drain region 104 of the plurality of transistor cells. For example, a second conductivity type (e.g., N-type) dopant can be implanted into a plurality of predefined locations on the epitaxial layer 102 under the cover of a patterned implantation mask to form the source region 103, the drain region 104, and the lead-out region 11. In one embodiment, the patterned implantation mask forming the source region 103, drain region 104, and lead-out region 11 can be removed after the implantation process forming these regions is completed. More details about the source region 103, the drain region 104, and the lead-out region 11, such as their location, conductivity type (or dopant type), and doping concentration, can be found in the references. Figure 1 The existing descriptions are understood and will not be repeated here for the sake of simplicity.

[0095] like Figure 8QIn the process steps of the illustrated example structure 800Q, the body contact region 106 of the first conductivity type (e.g., P-type) of each of the plurality of transistor cells of the high-voltage transistor to be fabricated in the substrate 100S can be formed by any suitable doping process. The substrate lead-out region 111 of the substrate wiring structure is used to electrically lead out the substrate 100S; this substrate lead-out region 111 can be formed by sharing the same doping process as the body contact regions 106 of the plurality of transistor cells. For example, a first conductivity type (e.g., P-type) dopant can be implanted into a plurality of predefined locations on the epitaxial layer 102 under the cover of a patterned implantation mask to form the body contact region 106 and the substrate lead-out region 111. In one embodiment, the patterned implantation mask used to form the body contact region 106 and the substrate lead-out region 111 can be removed after the implantation process forming these regions is completed. More details about the body contact region 106 and the substrate lead-out region 111, such as location, conductivity type (or dopant type), and doping concentration, can be found in the references. Figure 1 The existing descriptions are understood and will not be repeated here for the sake of simplicity.

[0096] exist Figures 8J to 8Q In the examples shown, the relevant manufacturing steps described with reference to these figures are based on Figure 8H The example structure shown executes 800H. However, it should be understood that references here are not valid. Figures 8J to 8Q The described manufacturing steps can be based on Figures 8D to 8I The implementation of any of the structures 800D to 800I shown respectively depends on whether each of the plurality of sidewalls 10 of the barrel-like structure contained in the semiconductor device to be manufactured has a sidewall connection region 15, and / or whether each of the plurality of transistor units of the high-voltage transistor contained in the semiconductor device to be manufactured has a RESURF region 110.

[0097] For example, a method of manufacturing a semiconductor device (e.g., a semiconductor 500 or 600 in which each of the plurality of sidewalls 10 in the included barrel-like structure does not have a sidewall connection region 15 and the included high-voltage transistor does not have a RESURF region 110) may include reference to Figures 8A to 8D as well as Figures 8J to 8Q The manufacturing steps shown and described, wherein reference is made to Figures 8J to 8Q The described manufacturing steps can be based on Figure 8D The structure shown is executed by 800D.

[0098] For example, a method of manufacturing a semiconductor device (e.g., a semiconductor device 100 or 400 in which each of the plurality of sidewalls 10 in the included barrel-like structure does not have a sidewall connection region 15 and the included high-voltage transistor has a RESURF region 110) may include reference to Figures 8A to 8D , Figure 8H or Figure 8I as well as Figures 8J to 8Q The manufacturing steps shown and described, wherein reference is made to Figures 8J to 8Q The described manufacturing steps can be based on Figure 8H The structure shown is 800H or Figure 8I The structure shown is executed by 800I.

[0099] For example, a method of manufacturing a semiconductor device (e.g., a semiconductor device 700 comprising a plurality of sidewalls 10 in a barrel-like structure each having a sidewall connection region 15 and a RESURF region 110 in a high-voltage transistor) may include reference to Figures 8A to 8D , Figure 8E , Figure 8F or Figure 8G as well as Figures 8J to 8Q The manufacturing steps shown and described, wherein reference is made to Figures 8J to 8Q The described manufacturing steps can be based on Figure 8F The structure shown is 800F or Figure 8G The structure shown is executed at 800G.

[0100] For example, a method for manufacturing a semiconductor device (a semiconductor device comprising a plurality of sidewalls 10 in a barrel-like structure, each having a sidewall connection region 15 and a high-voltage transistor therein lacking a RESURF region 110) may be combined with Figure 5 and Figure 7 , or combination Figure 6 and Figure 7 Understanding can include reference. Figures 8A to 8D , Figure 8E as well as Figures 8J to 8Q The manufacturing steps shown and described, wherein reference is made to Figures 8J to 8Q The described manufacturing steps can be based on Figure 8E The structure shown is executed by 800E.

[0101] Those skilled in the art will understand that references in this disclosure are... Figures 1 to 8Q The semiconductor devices (e.g., semiconductor devices 100, 400 to 700) and the related manufacturing methods in the various embodiments are for illustrative purposes only and are not intended to be limiting. The advantages of the embodiments of the present invention are not limited to those described above. These and other advantages of the embodiments of the present invention will become more apparent upon reading the full detailed description and studying the various illustrations in the accompanying drawings.

[0102] As can be seen from the foregoing, specific embodiments of the present invention have been described for illustrative purposes, but various modifications can be made without departing from the technology of the present invention. Many elements of one embodiment may be combined with or replace elements of other embodiments.

Claims

1. A semiconductor device, comprising: A substrate comprising an initial substrate layer of a first conductivity type and an epitaxial layer of a first conductivity type formed on the initial substrate layer; as well as A barrel-like structure of a second conductivity type formed in the substrate, wherein the second conductivity type is opposite to the first conductivity type; wherein The barrel-like structure has a bottom layer of a second conductivity type embedded in the initial substrate layer, and the peak doping concentration plane of the bottom layer has a predetermined embedment depth from the top surface of the initial substrate layer, the predetermined embedment depth being substantially greater than 0.5 μm.

2. The semiconductor device of claim 1, wherein the underlying substrate is doped with phosphorus.

3. The semiconductor device of claim 1, wherein the underlying layer is doped with a second conductivity type dopant suitable for and compatible with high-energy implantation processes.

4. The semiconductor device of claim 1, wherein the underlying layer has an underlying doping concentration lower than the doping concentration of a buried region or buried layer formed in the initial substrate layer by a low-energy implantation process.

5. The semiconductor device of claim 1, wherein the bottom layer has a bottom layer doping concentration that is 1e1 cm lower than the doping concentration of the buried region or buried layer formed in the initial substrate layer by a low-energy implantation process. -3 up to 1e3 cm -3 .

6. The semiconductor device of claim 1, wherein the barrel-like structure further includes a plurality of sidewalls in contact with or connected to the underlying layer, and each of the plurality of sidewalls extends downward from the top surface of the substrate into the substrate until it is in contact with or connected to at least the underlying layer.

7. The semiconductor device of claim 6, wherein, When viewed from a top view, the plurality of sidewalls form a closed loop and define the top view shape of the barrel-like structure, and the top view shape of the barrel-like structure is rectangular, quadrilateral, polygonal, or circular.

8. The semiconductor device of claim 6, wherein each of the plurality of sidewalls includes a buried connection region that contacts at least the underlying layer.

9. The semiconductor device of claim 8, wherein the buried connection region of each of the plurality of sidewalls is a first buried layer formed in the initial substrate layer, and the bottom layer is a second buried layer formed in the initial substrate layer, the second buried layer being buried at a depth in the substrate greater than the buried depth of the buried connection region in the substrate.

10. The semiconductor device of claim 8, wherein the buried connection region is doped with antimony or arsenic.

11. The semiconductor device of claim 8, wherein the buried connection region is doped with a second conductivity type dopant suitable for and compatible with low-energy implantation processes.

12. The semiconductor device of claim 1, further comprising: A transistor is formed in a portion of the substrate located within the barrel-like structure.

13. The semiconductor device of claim 12, wherein the transistor comprises a plurality of transistor units, and each of the plurality of transistor units comprises: A source region of a second conductivity type formed in the substrate and located near the top surface of the substrate; A drain region of a second conductivity type is formed in the substrate and located near the top surface of the substrate, and the drain region is separated from the source region; A body region of a first conductivity type is disposed around the source region; A bulk contact region of the first conductivity type is formed immediately adjacent to the source region; A drift region of a second conductivity type is formed in the substrate, the drift region surrounding the drain region and being separated from the source region; as well as A gate region is formed between the source region and the drain region, and closer to the source region.

14. The semiconductor device of claim 13, wherein each of the plurality of transistor units further comprises a body well region of a first conductivity type formed in the substrate surrounding the body region.

15. The semiconductor device of claim 13 or 14, wherein the transistor has a vertical junction breakdown voltage between the body region and the bottom layer, the vertical junction breakdown voltage increasing with increasing vertical junction breakdown control distance, the vertical junction breakdown control distance being substantially the vertical distance between the bottom surface of the drift region and the peak doping concentration plane of the bottom layer.

16. The semiconductor device of claim 13, wherein each of the plurality of transistor units further comprises: A RESURF region having a first conductivity type is formed around and below the body region and the drift region, and surrounds the body region and the drift region.

17. The semiconductor device of claim 16, wherein the transistor has a vertical junction breakdown voltage between the body region and the bottom layer, the vertical junction breakdown voltage increasing with increasing vertical junction breakdown control distance, the vertical junction breakdown control distance being substantially the vertical distance between the bottom surface of the RESURF region and the peak doping concentration plane of the bottom layer.

18. The semiconductor device of claim 12, wherein the transistor has a breakdown voltage of not less than 70V.

19. The semiconductor device of claim 12, wherein the transistor has a breakdown voltage of not less than 100V.

20. The semiconductor device of claim 1, wherein the thickness of the epitaxial layer is in the range of 8 μm to 16 μm.

21. The semiconductor device of claim 1, wherein the thickness of the epitaxial layer is in the range of 10 μm to 16 μm.

22. A semiconductor device, comprising: Substrate of the first conductivity type; as well as A barrel-like structure of a second conductivity type formed in the substrate, wherein the second conductivity type is opposite to the first conductivity type; in The barrel-like structure includes a bottom layer and a plurality of sidewalls in contact with the bottom layer, each of the plurality of sidewalls including a buried connection area, i.e., a first buried layer, and the bottom layer including a second buried layer, wherein the second buried layer is buried at a depth in the substrate greater than the buried connection area in the substrate when measured with reference to the top surface of the substrate.

23. The semiconductor device of claim 22, wherein the bottom layer is connected to the buried connection region of each of the plurality of sidewalls.

24. The semiconductor device of claim 22, wherein when measured with reference to the top surface of the substrate, the depth of the bottom surface of the underlying layer is greater than the depth of the bottom surface of the buried interconnect region.

25. The semiconductor device of claim 22, wherein the peak doping concentration plane of the underlying layer has a predetermined embedment depth from the top surface of the initial substrate layer of the substrate, the predetermined embedment depth being substantially greater than 0.5 μm.

26. The semiconductor device of claim 1 or 25, wherein the predetermined embedment depth is substantially greater than 1 μm.

27. The semiconductor device of claim 1 or 25, wherein the predetermined embedment depth is substantially in the range of 1 μm to 5 μm.

28. The semiconductor device of claim 1 or 25, wherein the predetermined embedment depth is substantially in the range of 1 μm to 3.5 μm.

29. The semiconductor device of claim 22, wherein when measured with reference to the top surface of the initial substrate layer of the substrate, the depth of the peak doping concentration plane of the bottom layer is greater than the depth of the peak doping concentration plane of the buried interconnect region.

30. The semiconductor device of claim 22, wherein when measured with reference to the top surface of the initial substrate layer of the substrate, the depth of the peak doping concentration plane of the bottom layer is substantially greater than the depth of the peak doping concentration plane of the buried interconnect region by 0.5 μm to 3.5 μm.

31. The semiconductor device of claim 22, wherein when measured with reference to the top surface of the initial substrate layer of the substrate, the depth of the peak doping concentration plane of the bottom layer is substantially greater than the depth of the peak doping concentration plane of the buried interconnect region by 1 μm to 2 μm.

32. The semiconductor device of claim 22, wherein the substrate comprises an initial substrate layer and an epitaxial layer formed on the initial substrate layer, and the thickness of the epitaxial layer is in the range of 8 μm to 16 μm.

33. The semiconductor device of claim 22, wherein the bottom layer has a connection doping concentration 1e1 cm lower than that of the buried connection region. -3 up to 1e3 cm -3 The underlying doping concentration.

34. The semiconductor device of claim 22, wherein the underlying layer has a substantially 5e15cm depth. -3 up to 1e19cm -3 The range of bottom layer doping concentrations.

35. The semiconductor device of claim 22, wherein the buried interconnect region has a substantially 1e17 cm -3 Up to 1e20 cm -3 The range of connection doping concentrations.

36. The semiconductor device of claim 22, wherein the underlying layer is doped with phosphorus or other suitable dopants of a second conductivity type that are compatible with high-energy implantation processes.

37. The semiconductor device of claim 8 or 22, wherein each of the plurality of sidewalls further comprises: The lead-out region is formed in the substrate and located near the top surface of the substrate; as well as A trap region is formed and disposed around the lead-out region, and the trap region extends vertically downward from the top surface of the substrate into the substrate until it contacts or connects with the embedded connection region.

38. The semiconductor device of claim 8 or 22, wherein each of the plurality of sidewalls further comprises: The lead-out region is formed in the substrate and located near the top surface of the substrate; A well region is formed and disposed around the lead-out region, and the well region extends vertically downward from the top surface of the substrate into the substrate and has a predetermined well region depth; as well as A sidewall connection area is formed and disposed between the trap area and the embedded connection area. The sidewall connection area contacts or connects with the upper trap area and the lower embedded connection area to provide an electrical connection between the trap area and the embedded connection area.

39. The semiconductor device of claim 22, further comprising: A transistor is formed in a portion of the substrate located within the barrel-like structure, wherein the transistor has a breakdown voltage of not less than 70V.

40. The semiconductor device of claim 39, wherein the transistor has a breakdown voltage of not less than 100V.

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