Transistor and manufacturing method thereof

Abstract

The invention provides a transistor and a manufacturing method thereof. The transistor comprises a channel layer, a barrier layer, a first grid electrode, a second grid electrode, a first electrode, a second electrode and a third electrode, the barrier layer is stacked on the channel layer, the first grid electrode and the second grid electrode are located on the barrier layer, and the first electrode, the second electrode and the third electrode are respectively inserted into the barrier layer; along a first direction a, the first electrode, the first grid electrode, the second electrode, the second grid electrode and the third electrode are arranged in sequence; the first gate and the second gate are connected in series.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor devices, and in particular to a transistor and a method for manufacturing the same. Background Technology

[0002] GaN-based transistors are candidates for next-generation power switching applications due to their superior device characteristics (low specific on-resistance, low switching losses, and high breakdown voltage).

[0003] However, optimizing transistor performance remains a major challenge. Summary of the Invention

[0004] This disclosure provides a transistor and a method for manufacturing the same, which can optimize transistor performance. The technical solution is as follows: On one hand, a transistor is provided, the transistor comprising: a channel layer, a barrier layer, a first gate, a second gate, a first electrode, a second electrode, and a third electrode; The barrier layer is stacked on the channel layer, the first gate and the second gate are located on the barrier layer, and the first electrode, the second electrode and the third electrode are respectively inserted into the barrier layer; Along the first direction a, the first electrode, the first gate, the second electrode, the second gate, and the third electrode are arranged sequentially; The first gate and the second gate are connected in series.

[0005] Optionally, the orthographic projections of the first electrode and the second electrode on the channel layer surface are symmetrical about the orthographic projection of the first gate on the channel layer surface. The orthographic projections of the second electrode and the third electrode on the channel layer surface are symmetrical about the orthographic projection of the second gate on the channel layer surface.

[0006] Optionally, the transistor further includes a first field plate structure, a second field plate structure, a third field plate structure, and a fourth field plate structure; The first field plate structure is located between the first electrode and the first gate, the second field plate structure is located between the first gate and the second electrode, the third field plate structure is located between the second electrode and the second gate, and the fourth field plate structure is located between the second gate and the third electrode. The orthographic projections of the first field plate structure on the channel layer surface and the second field plate structure on the channel layer surface are symmetrical about the orthographic projection of the first gate on the channel layer surface; the orthographic projections of the third field plate structure on the channel layer surface and the fourth field plate structure on the channel layer surface are symmetrical about the orthographic projection of the second gate on the channel layer surface.

[0007] Optionally, the first field plate structure is insulated from the first electrode, the second electrode, and the third electrode, respectively; the second field plate structure is insulated from the first electrode, the second electrode, and the third electrode, respectively; the third field plate structure is insulated from the first electrode, the second electrode, and the third electrode, respectively; and the fourth field plate structure is insulated from the first electrode, the second electrode, and the third electrode, respectively.

[0008] Optionally, the transistor further includes a fifth field plate structure, a sixth field plate structure, a seventh field plate structure, and an eighth field plate structure; One end of the fifth field plate structure is connected to the second electrode, and the other end of the fifth field plate structure is away from the second electrode along the first direction a; one end of the sixth field plate structure is connected to the second electrode, and the other end of the sixth field plate structure is away from the second electrode along the opposite direction of the first direction a; one end of the seventh field plate structure is connected to the second electrode, and the other end of the seventh field plate structure is away from the second electrode along the first direction a; one end of the eighth field plate structure is connected to the second electrode, and the other end of the eighth field plate structure is away from the second electrode along the opposite direction of the first direction a; the fifth field plate structure, the sixth field plate structure, the seventh field plate structure, and the eighth field plate structure are arranged sequentially along the second direction b, which is perpendicular to the first direction a.

[0009] Optionally, the transistor further includes a ninth field plate structure and a tenth field plate structure; one end of the ninth field plate structure is connected to the first electrode, and the other end of the fifth field plate structure is away from the first electrode along a first direction a; one end of the tenth field plate structure is connected to the first electrode, and the other end of the tenth field plate structure is away from the first electrode along a first direction a; the ninth field plate structure and the tenth field plate structure are arranged sequentially along the second direction b.

[0010] Optionally, the sixth field plate structure is located between the ninth field plate structure and the tenth field plate structure, and the tenth field plate structure is located between the sixth field plate structure and the eighth field plate structure.

[0011] Optionally, the transistor further includes an eleventh field plate structure and a twelfth field plate structure; one end of the eleventh field plate structure is connected to the third electrode, and the other end of the eleventh field plate structure is away from the third electrode along the opposite direction of the first direction a; one end of the twelfth field plate structure is connected to the third electrode, and the other end of the twelfth field plate structure is away from the third electrode along the opposite direction of the first direction a; the eleventh field plate structure and the twelfth field plate structure are arranged sequentially along the second direction b.

[0012] Optionally, the eleventh field plate structure is located between the fifth field plate structure and the seventh field plate structure, and the seventh field plate structure is located between the eleventh field plate structure and the twelfth field plate structure.

[0013] On the other hand, a method for manufacturing a transistor is provided, the method comprising: A channel layer and a barrier layer are fabricated sequentially, with the barrier layer stacked on top of the channel layer; A first gate and a second gate are fabricated on the barrier layer, and the first gate and the second gate are connected in series. A first electrode, a second electrode, and a third electrode are fabricated, and the first electrode, the second electrode, and the third electrode are respectively inserted into the barrier layer; along a first direction a, the first electrode, the first gate electrode, the second electrode, the second gate electrode, and the third electrode are arranged sequentially.

[0014] The beneficial effects of the technical solutions provided in this disclosure are: In this transistor, when the transistor is operating, the first gate and the second gate control currents flow in opposite directions. For example, the first gate control current flows from the first electrode on one side to the second electrode on the other side, and the second gate control current flows from the third electrode on the other side to the second electrode on one side, thus realizing a bidirectional transistor; or, the first gate control current flows from the second electrode on the other side to the first electrode on one side, and the second gate control current flows from the second electrode on one side to the third electrode on the other side, thus realizing a bidirectional transistor. Furthermore, the first and second gates form a symmetrical design, ensuring that both gates provide completely consistent control capability regardless of the current direction, guaranteeing the symmetry of bidirectional conduction. Since the first and second gates are electrically connected, the first electrode and the third electrode can also be electrically connected, so the transistor can still be a three-terminal device, simplifying the driving process.

[0015] In this transistor, the first gate and the second gate control different regions respectively, thereby reducing the length of the active region controlled by each gate, which is beneficial for realizing high-frequency and high-reliability transistor design. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the structure of a transistor provided in an embodiment of this disclosure; Figure 2 This is a top view schematic diagram of the electrode distribution of a transistor provided in an embodiment of this disclosure; Figure 3 This is a symmetrical schematic diagram of the first electrode and the second electrode about the first gate provided in an embodiment of this disclosure; Figure 4 This is a flowchart of a transistor fabrication method provided in an embodiment of this disclosure; Figure 5 This is a flowchart of a transistor fabrication method provided in an embodiment of this disclosure.

[0018] Figure Labels 100: Substrate; 101: Channel layer; 102: Barrier layer; 103: First gate; 104: Second gate; 105: First electrode; 106: Second electrode; 107: Third electrode; 108: First passivation layer; 109: First field plate; 110: Second passivation layer; 111: Second field plate; 112: Third passivation layer; 113: Interconnect structure; 114: Dielectric layer; 115: Buffer layer; 116: Gate interconnect structure; 117: Metal interconnect structure; 118: Protective layer; 119: Nucleation layer; 201: P-type gallium nitride layer; 202: Gate metal layer; 203: Groove; 151: AlGaN / GaN / AlN superlattice structure; 152: GaN buffer layer; 191: First-stage slab structure; 192: Second-stage slab structure; 193: Third-stage slab structure; 194: Fourth-stage slab structure; 1111: Fifth slab structure; 1112: Sixth slab structure; 1113: Seventh slab structure; 1114: Eighth slab structure; 1115: Ninth slab structure; 1116: Tenth slab structure; 1117: Eleventh slab structure; 1118: Twelfth slab structure. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0020] In related technologies, the high on-current density is the biggest advantage of multi-channel transistors, but it also brings challenges to gate control capabilities. Generally, a fin gate structure is used to achieve effective turn-off of the gate channel. However, the asymmetric characteristics of multi-channel transistors cause the top two-dimensional electron gas channel to be controlled by the top gate, and it cannot maintain synchronous turn-on or turn-off with the lower two-dimensional electron gas channel. This is reflected in the device characteristics, namely poor subthreshold characteristics and multi-segment conduction phenomenon.

[0021] Figure 1 This is a schematic diagram of the structure of a transistor provided in an embodiment of this disclosure. Figure 2 This is a top view of the electrode distribution of a transistor provided in an embodiment of this disclosure, such as a projection distribution on the surface of the channel layer. Figure 1 It can be Figure 2 The cross-sectional view corresponding to point A-A' in the middle.

[0022] See Figure 1 and Figure 2 The transistor includes: a channel layer 101, a barrier layer 102, a first gate 103, a second gate 104, a first electrode 105, a second electrode 106, and a third electrode 114.

[0023] The barrier layer 102 is stacked on the channel layer 101, the first gate 103 and the second gate 104 are located on the barrier layer 102, and the first electrode 105 and the second electrode 106 are respectively inserted into the barrier layer 102.

[0024] Along the first direction a, the first electrode 105, the first gate 103, the second electrode 106, the second gate 104 and the third electrode 107 are arranged in sequence; the first gate 103 and the second gate 104 are connected in series.

[0025] Wherein, the first direction a is parallel to the surface of the barrier layer 102 that contacts the gate, and the first direction a is the direction from the first electrode 105 to the second electrode 106.

[0026] In this transistor, when the transistor is operating, the first gate and the second gate control currents flow in opposite directions. For example, the first gate control current flows from the first electrode on one side to the second electrode on the other side, and the second gate control current flows from the third electrode on the other side to the second electrode on one side, thus realizing a bidirectional transistor; or, the first gate control current flows from the second electrode on the other side to the first electrode on one side, and the second gate control current flows from the second electrode on one side to the third electrode on the other side, thus realizing a bidirectional transistor. Furthermore, the first and second gates form a symmetrical design, ensuring that both gates provide completely consistent control capability regardless of the current direction, guaranteeing the symmetry of bidirectional conduction. Since the first and second gates are electrically connected, the first electrode and the third electrode can also be electrically connected, so the transistor can still be a three-terminal device, simplifying the driving process.

[0027] In this transistor, the first gate and the second gate control different regions respectively, thereby reducing the length of the active region controlled by each gate, which is beneficial for realizing high-frequency and high-reliability transistor design.

[0028] In this embodiment of the disclosure, the transistor adopts a periodic design. For example, along a first direction a, the first electrode 105, the first gate 103, the second electrode 106, the second gate 104 and the third electrode 107 are periodically arranged. All the first gates 103 and the second gates 104 are electrically connected. An odd number of electrodes (e.g., the first, third, and fifth electrodes...) are electrically connected, and an even number of electrodes (e.g., the second, fourth, and sixth electrodes...) are electrically connected.

[0029] In the above cycle, the first electrode of the next cycle is the third electrode, which coincides with the last electrode of the previous cycle.

[0030] That is, the transistor includes multiple control cycles arranged along the first direction a. Figure 1 This shows one of the control cycles.

[0031] In addition, both odd-numbered and even-numbered electrode electrical connections are made through wiring during packaging.

[0032] In this transistor, the first and second gates are periodically distributed, which further reduces the length of the active region controlled by each gate, thus facilitating the design of high-frequency, high-reliability transistors.

[0033] See you again Figure 1The first gate 103 and the second gate 104 include a P-type gallium nitride layer 201 located on the barrier layer 102 and a gate metal layer 202 located on the P-type gallium nitride layer 201. A groove 203 is formed on the surface of the P-type gallium nitride layer 201, and the gate metal layer 202 is located in the groove 203.

[0034] In this transistor, a P-type gallium nitride layer acts as a cap layer, depleting the underlying two-dimensional electron gas channel to achieve a normally-off device. A groove is formed on the surface of the P-type gallium nitride layer to form a gate metal layer. This groove structure allows for more precise control of the transistor's threshold voltage (Vth) and reduces Vth drift under high voltage conditions.

[0035] The transistor provided in this embodiment is a bidirectional GaN-based high electron mobility transistor (HEMT), which is a transistor capable of controlling current flow in two directions.

[0036] See you again Figure 1 The transistor may further include: a first passivation layer 108, a first field plate 109, and a second passivation layer 110.

[0037] The first passivation layer 108 covers the barrier layer 102, the first gate 103, the second gate 104, the first electrode 105, the second electrode 106, and the third electrode 107. The first field plate 109 passes through the first passivation layer 108, and the second passivation layer 110 covers the first field plate 109 and the first passivation layer 108.

[0038] The first field plate 109 is electrically connected to the first gate 103 or the second gate 104.

[0039] The first field plate 109 is electrically connected to the first gate 103 or the second gate 104 via wiring during packaging.

[0040] In this implementation, by designing a first field plate and connecting it to the gate, the peak electric field at the gate edge can be adjusted to avoid excessive peak electric field leading to breakdown.

[0041] See you again Figure 2 The first layer field plate 109 includes a first field plate structure 191, a second field plate structure 192, a third field plate structure 193 and a fourth field plate structure 194.

[0042] The first field plate structure 191 is located between the first electrode 105 and the first gate 103, the second field plate structure 192 is located between the first gate 103 and the second electrode 106, the third field plate structure 193 is located between the second electrode 106 and the second gate 104, and the fourth field plate structure 194 is located between the second gate 104 and the third electrode 107.

[0043] The orthographic projections of the first field plate structure 191 and the second field plate structure 192 on the surface of the channel layer 101 are symmetrical about the orthographic projection of the first gate 103 on the surface of the channel layer 101; the orthographic projections of the third field plate structure 193 and the fourth field plate structure 194 on the surface of the channel layer 101 are symmetrical about the orthographic projection of the second gate 104 on the surface of the channel layer 101.

[0044] In this implementation, by designing the first to fourth field plates, the peak electric field at the edges of the first and second gates can be adjusted to avoid excessive peak electric field leading to breakdown.

[0045] Specifically, the first field plate structure 191 is insulated from the first electrode 105, the second electrode 106, and the third electrode 107, respectively; the second field plate structure 192 is insulated from the first electrode 105, the second electrode 106, and the third electrode 107, respectively; the third field plate structure 193 is insulated from the first electrode 105, the second electrode 106, and the third electrode 107, respectively; and the fourth field plate structure 194 is insulated from the first electrode 105, the second electrode 106, and the third electrode 107, respectively.

[0046] In this implementation, short circuits are avoided through insulation.

[0047] For example, the first field plate structure 191 and the second field plate structure 192 on both sides of the first gate 103 are electrically connected to the first gate 103, and the third field plate structure 193 and the fourth field plate structure 194 on both sides of the second gate 104 are electrically connected to the second gate 104.

[0048] See you again Figure 1 The transistor may further include: a second field plate 111, a third passivation layer 112, and a connection structure 113.

[0049] The second field plate 111 is located on the second passivation layer 110. The connection structure 113 passes through the second passivation layer 110. The second field plate 111 is electrically connected to the first electrode 105, the second electrode 106 or the third electrode 107 through the connection structure 113. The third passivation layer 112 covers the second passivation layer 110 and the second field plate 111.

[0050] See you again Figure 2 The second field plate 111 extends along the first direction a, one end of the second field plate 111 is electrically connected to the first electrode 105, the second electrode 106 or the third electrode 107, and the other end of the second field plate 111 faces the first gate 103 or the second gate 104.

[0051] The second layer field plate 111, which faces the same first gate 103 or second gate 104 at the other end, is arranged at intervals in the second direction b, which intersects (e.g., is perpendicular to) the first direction a.

[0052] In this implementation, a second field plate is designed, which is connected to the first, second, or third electrode on the opposite side through a connection structure to form a virtual drain. When operating in both directions, the electric field distribution can be adaptively adjusted according to the potential change.

[0053] In addition, the first and second field plates together form a dual-gradient field plate, which can significantly optimize the lateral electric field distribution in the channel, increase the breakdown voltage by more than 1.5 times (>2000V), and effectively suppress current collapse and optimize dynamic resistance characteristics.

[0054] like Figure 2 As shown, the second-layer field plate 111 includes a fifth field plate structure 1111, a sixth field plate structure 1112, a seventh field plate structure 1113, and an eighth field plate structure 1114.

[0055] One end of the fifth field plate structure 1111 is connected to the second electrode 106, and the other end of the fifth field plate structure 1111 is away from the second electrode 106 along the first direction a; one end of the sixth field plate structure 1112 is connected to the second electrode 106, and the other end of the sixth field plate structure 1112 is away from the second electrode 106 along the opposite direction of the first direction a; one end of the seventh field plate structure 1113 is connected to the second electrode 106, and the other end of the seventh field plate structure 1113 is away from the second electrode 106 along the first direction a; one end of the eighth field plate structure 1114 is connected to the second electrode 106, and the other end of the eighth field plate structure 1114 is away from the second electrode 106 along the opposite direction of the first direction a; the fifth field plate structure 1111, the sixth field plate structure 1112, the seventh field plate structure 1113 and the eighth field plate structure 1114 are arranged sequentially along the second direction b, which is perpendicular to the first direction a.

[0056] In this implementation, the electric field distribution around the second electrode is adaptively adjusted by designing the fifth field plate structure 1111, the sixth field plate structure 1112, the seventh field plate structure 1113, and the eighth field plate structure 1114.

[0057] like Figure 2 As shown, the second field plate 111 further includes a ninth field plate structure 1115 and a tenth field plate structure 1116; one end of the ninth field plate structure 1115 is connected to the first electrode 105, and the other end of the fifth field plate structure 1111 is away from the first electrode 105 along the first direction a; one end of the tenth field plate structure 1116 is connected to the first electrode 105, and the other end of the tenth field plate structure 1116 is away from the first electrode 105 along the first direction a; the ninth field plate structure 1115 and the tenth field plate structure 1116 are arranged sequentially along the second direction b.

[0058] The sixth field plate structure 1112 is located between the ninth field plate structure 1115 and the tenth field plate structure 1116, and the tenth field plate structure 1116 is located between the sixth field plate structure 1112 and the eighth field plate structure 1114.

[0059] In this implementation, the electric field distribution around the first electrode is adaptively adjusted by designing the ninth field plate structure 1115 and the tenth field plate structure 1116.

[0060] like Figure 2As shown, the second field plate 111 further includes an eleventh field plate structure 1117 and a twelfth field plate structure 1118; one end of the eleventh field plate structure 1117 is connected to the third electrode 107, and the other end of the eleventh field plate structure 1117 is away from the third electrode 107 along the opposite direction of the first direction a; one end of the twelfth field plate structure 1118 is connected to the third electrode 107, and the other end of the twelfth field plate structure 1118 is away from the third electrode 107 along the opposite direction of the first direction a; the eleventh field plate structure 1117 and the twelfth field plate structure 1118 are arranged sequentially along the second direction b.

[0061] The eleventh field plate structure 1117 is located between the fifth field plate structure 1111 and the seventh field plate structure 1113, and the seventh field plate structure 1113 is located between the eleventh field plate structure 1117 and the twelfth field plate structure 1118.

[0062] In this implementation, the electric field distribution around the third electrode is adaptively adjusted by designing the eleventh field plate structure 1117 and the twelfth field plate structure 1118.

[0063] See you again Figure 1 The transistor further includes a dielectric layer 114.

[0064] The dielectric layer 114 covers the barrier layer 102, the first gate 103 and the second gate 104, and the first electrode 105, the second electrode 106 and the third electrode 107 pass through the dielectric layer 114 and contact the barrier layer 102.

[0065] In this transistor, the gate employs a combination of a P-type gallium nitride layer and a gate metal layer, forming a sandwich structure together with the dielectric layer. The dielectric layer effectively suppresses gate leakage current and improves gate reliability.

[0066] In this embodiment of the disclosure, the first passivation layer 108 is located on the dielectric layer 114, and the first field plate 109 passes through the first passivation layer 108 and contacts the dielectric layer 114.

[0067] See you again Figure 1 The transistor further includes a substrate 100 and a buffer layer 115, wherein the buffer layer 115 and the channel layer 101 are sequentially stacked on the substrate 100.

[0068] In one example of an embodiment of this disclosure, the first gate 103 and the second gate 104 can be electrically connected via wiring during packaging.

[0069] In another example of the embodiments of this disclosure, the first gate 103 and the second gate 104 may also be electrically connected within the film layer.

[0070] See Figure 2 The transistor further includes a gate connection structure 116, which is electrically connected to the end of the first gate 103 and the end of the second gate 104, respectively.

[0071] The gate connection structure 116 is arc-shaped and extends around the second electrode 106 or the third electrode 107.

[0072] In this implementation, the arc-shaped gate connection structure bypasses the second or third electrode, which simplifies the driving circuit and avoids coupling caused by excessively close gate and source distances. Furthermore, compared to external traces, it can improve parasitic parameters and enhance breakdown voltage performance.

[0073] In other examples, the gate connection structure 116 described above can also be in other shapes, such as U-shaped, V-shaped, L-shaped, etc.

[0074] See you again Figure 1 The transistor may further include a metal interconnect structure 117 and a protective layer 118.

[0075] The metal interconnect structure 117 is located on the third passivation layer 112, the connection structure 113 passes through the third passivation layer 112, the metal interconnect structure 117 is electrically connected to the connection structure 113, the protective layer 118 covers the third passivation layer 112 and the metal interconnect structure 117, and the protective layer 118 exposes at least a portion of the surface of the metal interconnect structure 117 through openings.

[0076] See you again Figure 1 The transistor may further include a nucleation layer 119, which is located between the substrate 100 and the buffer layer 115.

[0077] In this embodiment of the disclosure, the substrate 100 may be a Si substrate, a silicon carbide substrate, or a sapphire substrate.

[0078] For example, substrate 100 is a Si substrate.

[0079] In this embodiment of the disclosure, the nucleation layer 119 can be an AlN nucleation layer.

[0080] For example, the thickness of the AlN nucleation layer is 180~240nm, such as 200nm.

[0081] In this embodiment of the disclosure, the buffer layer 115 includes an AlGaN / GaN / AlN superlattice structure 151.

[0082] Among them, the AlGaN / GaN / AlN superlattice structure forms a polarized superjunction. Utilizing the polarization effect of group III-V materials, alternating n-type and p-type charge regions are generated, which can effectively deplete the longitudinal electric field, significantly improve the longitudinal breakdown voltage of the device, and suppress substrate leakage current.

[0083] For example, the AlGaN / GaN / AlN superlattice structure is Al 0.3 Ga 0.7 The N / GaN / AlN superlattice structure has a thickness of 8-12 nm for each sublayer, for example, 10 nm.

[0084] The period number of the AlGaN / GaN / AlN superlattice structure is 5 to 15, for example 10.

[0085] Optionally, the buffer layer 115 further includes a GaN buffer layer 152, which is located between the AlGaN / GaN / AlN superlattice structure and the channel layer.

[0086] For example, the thickness of the GaN buffer layer is 1.5~2.5μm, such as 2μm.

[0087] In this embodiment of the disclosure, the channel layer 101 is a GaN channel layer, and the barrier layer 102 is an AlGaN layer.

[0088] For example, the thickness of the channel layer 101 is 80~120nm, such as 100nm.

[0089] For example, barrier layer 102 is Al 0.22 Ga 0.78 The N-layer has a thickness of 15~20nm, for example, 18nm.

[0090] In one example, the first, second, and third electrodes pass through the dielectric layer and then through the entire barrier layer to contact the channel layer.

[0091] In another example, the first, second, and third electrodes penetrate the dielectric layer and then further penetrate a portion of the barrier layer without contacting the channel layer. For example, the barrier layer is 18 nm thick, and the depth of the first, second, and third electrodes within the barrier layer is 15 nm.

[0092] In this embodiment of the disclosure, the thickness of the P-type gallium nitride layer 201 is 75~100nm, and the depth of the groove 203 is 8~12nm.

[0093] In this implementation, the aforementioned thickness design ensures control over the threshold voltage (Vth) of the transistor and reduces Vth drift under high voltage.

[0094] For example, the thickness of the P-type gallium nitride layer 201 is 80 nm, and the depth of the groove 203 is 10 nm.

[0095] For example, the p-type gallium nitride layer 201 is a Mg-doped GaN layer with a Mg doping concentration of 5E19cm⁻¹. -3 .

[0096] In this embodiment of the disclosure, the gate metal layer 202 can be a TiW layer.

[0097] For example, the thickness of the gate metal layer 202 is 50~150nm, such as 100nm.

[0098] In this embodiment, the gate connection structure 116 is the same as the gate structure, includes the same film layer, and is formed in the same layer.

[0099] In this embodiment of the disclosure, the first electrode 105, the second electrode 106, and the third electrode 107 can be a Ti / Al / TiW stack.

[0100] For example, in the first electrode 105, the second electrode 106 and the third electrode 107, the thickness of the Ti layer is 10~50nm, for example 20nm; the thickness of the Al layer is 100~500nm, for example 200nm; and the thickness of the TiW layer is 100~500nm, for example 200nm.

[0101] In this embodiment of the disclosure, the dielectric layer 114 can be an Al2O3 layer, an AlN layer, or an HfO2 layer.

[0102] In this implementation, the aforementioned high dielectric constant material is used as the dielectric layer, and its interface state density is <5E11cm. -2 ·eV -1 It can effectively suppress gate leakage and improve gate reliability.

[0103] In this embodiment of the disclosure, the first passivation layer 108, the second passivation layer 110, the third passivation layer 112 and the protective layer 118 can be a SiN layer, a SiO2 layer, or a stack of SiN layers and SiO2 layers.

[0104] For example, the first passivation layer 108 is a SiN layer with a thickness of 400~600nm, for example 500nm; the second passivation layer 110 is a SiN layer with a thickness of 800~1200nm, for example 1000nm; the third passivation layer 112 is a stack of two SiO2 layers with thicknesses of 1~2μm and 0.4~0.6μm, for example 1.5μm and 0.5μm; and the protective layer 118 is a stack of SiO2 and SiN layers with thicknesses of 0.5~1.5μm and 0.4~0.6μm, for example 1μm and 0.5μm.

[0105] In this embodiment of the disclosure, the first field plate 109 includes a TiN / Al / TiN stack.

[0106] The thickness of the TiN layer in the TiN / Al / TiN stack is 40~60nm, and the thickness of the Al layer in the TiN / Al / TiN stack is 300~500nm.

[0107] In the second direction b, the length of the first field plate 109 (any one of the first field plate structure to the fourth field plate structure) is 0.4~0.6μm, and the second direction b intersects with the first direction a.

[0108] For example, the thickness of the TiN layer in the TiN / Al / TiN stack is 50 nm, the thickness of the Al layer in the TiN / Al / TiN stack is 400 nm, and the length of the first field plate 109 is 0.5 μm.

[0109] In this embodiment of the disclosure, the second field plate 111 includes a TiN / Al / TiN stack.

[0110] The thickness of the TiN layer in the TiN / Al / TiN stack is 40~60nm, and the thickness of the Al layer in the TiN / Al / TiN stack is 800~1200nm.

[0111] In the first direction a, the length of the second field plate 111 (any one of the fifth field plate structure to the twelfth field plate structure) is 0.8~1.2μm.

[0112] For example, the thickness of the TiN layer in the TiN / Al / TiN stack is 50 nm, the thickness of the Al layer in the TiN / Al / TiN stack is 1000 nm, and the length of the second field plate 111 is 1 μm.

[0113] In this embodiment of the disclosure, the connection structure 113 includes a TiN / Al / TiN stack.

[0114] In this embodiment of the disclosure, the metal interconnect structure 117 includes a TiN / W / Ti / Al / TiW stack.

[0115] The thickness of the TiN layer in the TiN / W / Ti / Al / TiW stack is 40~60nm, the thickness of the W layer in the TiN / W / Ti / Al / TiW stack is 0.5~0.7μm, the thickness of the Ti layer in the TiN / W / Ti / Al / TiW stack is 80~120nm, the thickness of the Al layer in the TiN / W / Ti / Al / TiW stack is 3500~4500nm, and the thickness of the TiW layer in the TiN / W / Ti / Al / TiW stack is 80~120nm.

[0116] For example, the thickness of the TiN layer in the TiN / W / Ti / Al / TiW stack is 50 nm, the thickness of the W layer in the TiN / W / Ti / Al / TiW stack is 0.6 μm, the thickness of the Ti layer in the TiN / W / Ti / Al / TiW stack is 100 nm, the thickness of the Al layer in the TiN / W / Ti / Al / TiW stack is 4000 nm, and the thickness of the TiW layer in the TiN / W / Ti / Al / TiW stack is 100 nm.

[0117] See you again Figure 2 Each of the first gate 103, the second gate 104, the first electrode 105, the second electrode 106, the third electrode 107, the first field plate 109, and the second field plate 111 is an elongated strip.

[0118] In one example, any one of the first gate 103, the second gate 104, the first electrode 105, the second electrode 106, the third electrode 107, the first field plate 109, and the second field plate 111 is rectangular.

[0119] For example, the first gate 103, the second gate 104, the first electrode 105, the second electrode 106, the third electrode 107, and the first field plate 109 are arranged in parallel, and the second field plate 111 is arranged perpendicular to the first gate 103, the second gate 104, the first electrode 105, the second electrode 106, the third electrode 107, and the first field plate 109.

[0120] In other examples, only the spacing between the first gate 103, the second gate 104, the first electrode 105, the second electrode 106, the third electrode 107, and the first field plate 109 can be maintained, without using a parallel arrangement. The second field plate 111 intersects with, but is not perpendicular to, the first gate 103, the second gate 104, the first electrode 105, the second electrode 106, the third electrode 107, and the first field plate 109.

[0121] In other examples, any one of the first gate 103, the second gate 104, the first electrode 105, the second electrode 106, the third electrode 107, the first field plate 109, and the second field plate 111 may be of other shapes, such as arc-shaped, wavy, or other shapes.

[0122] In this embodiment of the disclosure, the distance between adjacent first electrode 105, second electrode 106 and third electrode 107 is 15~20μm, for example 18μm.

[0123] like Figure 2 As shown, the first gate 103 or the second gate is equidistant from the adjacent first electrode 105, second electrode 106 and third electrode 107.

[0124] In other examples, the distances mentioned above may also be unequal.

[0125] The first field plate 109 is equidistant from the adjacent electrodes (first, second, or third electrodes) and gates (first gate or second gate).

[0126] In other examples, the distances mentioned above may also be unequal.

[0127] One end of the second field plate 111 is electrically connected to the first electrode 105, the second electrode 106, or the third electrode 107, and the other end of the second field plate 111 passes through the first gate 103 or the second gate 104. That is, the length of the second field plate 111 is greater than the distance between the connected electrode and the gate, which is greater than half the distance between the first electrode 105, the second electrode 106, and the third electrode 107, thereby forming an interdigitated structure.

[0128] In other examples, the other end of the second field plate 111 can be longer or shorter.

[0129] In this embodiment of the disclosure, with the central axis extending along the length direction of the first gate 103 as the axis of symmetry, the first electrode 105 and the second electrode 106 on both sides of the first gate 103 are symmetrically arranged, and the first field plate structure 191 and the second field plate structure 192 on both sides of the first gate 103 are symmetrically arranged.

[0130] In this embodiment of the present disclosure, with the central axis extending along the length direction of the second gate 104 as the axis of symmetry, the second electrode 106 and the third electrode 107 on both sides of the second gate 104 are symmetrically arranged, and the third field plate structure 193 and the fourth field plate structure 194 on both sides of the second gate 104 are symmetrically arranged.

[0131] In this embodiment, with the central axis extending along the length of the second electrode 106 as the axis of symmetry, the first electrode 105 and the third electrode 107 on both sides of the second electrode 106 are symmetrically arranged, the first field plate structure 191 and the fourth field plate structure 194 on both sides of the second electrode 106 are symmetrically arranged, the first gate 103 and the second gate 104 on both sides of the second electrode 106 are symmetrically arranged, and the second field plate structure 192 and the third field plate structure 193 on both sides of the second electrode 106 are symmetrically arranged.

[0132] The aforementioned symmetrical arrangement may refer to the orthographic symmetry on the surface of the channel layer 101.

[0133] For example, the orthographic projection of the first electrode 105 on the surface of the channel layer 101 and the orthographic projection of the second electrode 106 on the surface of the channel layer 101 are symmetrical about the central axis of the extension of the first gate 103 on the surface of the channel layer 101 along the second direction b. The orthographic projection of the second electrode 106 on the surface of the channel layer 101 and the orthographic projection of the third electrode 107 on the surface of the channel layer 101 are symmetrical about the central axis of the extension of the second direction b with respect to the orthographic projection of the second gate 104 on the surface of the channel layer 101.

[0134] Figure 3 This is a symmetrical schematic diagram of the first electrode and the second electrode about the first gate provided in an embodiment of this disclosure. Figure 3 As shown, the central axis of the first gate 103 extending along the second direction b is L, and the first electrode 104 and the second electrode 105 are symmetrical about the axis of symmetry L.

[0135] In this embodiment, the first electrode 105, the second electrode 106, and the third electrode 107 function as source or drain electrodes depending on the applied voltage, thereby achieving different current flow directions.

[0136] Figure 4 This is a flowchart illustrating a method for fabricating a transistor according to an embodiment of this disclosure. See also... Figure 4 The method includes the following steps: 301. The channel layer and the barrier layer are fabricated sequentially, with the barrier layer stacked on top of the channel layer.

[0137] 302. A first gate and a second gate are fabricated on the barrier layer, and the first gate and the second gate are connected in series.

[0138] 303. Fabricate a first electrode, a second electrode, and a third electrode, and insert the first electrode, the second electrode, and the third electrode into the barrier layer respectively; arrange the first electrode, the first gate, the second electrode, the second gate, and the third electrode sequentially along the first direction a.

[0139] In this transistor, when the transistor is operating, the first gate and the second gate control currents flow in opposite directions. For example, the first gate control current flows from the first electrode on one side to the second electrode on the other side, and the second gate control current flows from the third electrode on the other side to the second electrode on one side, thus realizing a bidirectional transistor; or, the first gate control current flows from the second electrode on the other side to the first electrode on one side, and the second gate control current flows from the second electrode on one side to the third electrode on the other side, thus realizing a bidirectional transistor. Furthermore, the first and second gates form a symmetrical design, ensuring that both gates provide completely consistent control capability regardless of the current direction, guaranteeing the symmetry of bidirectional conduction. Since the first and second gates are electrically connected, the first electrode and the third electrode can also be electrically connected, so the transistor can still be a three-terminal device, simplifying the driving process.

[0140] In this transistor, the first gate and the second gate control different regions respectively, thereby reducing the length of the active region controlled by each gate, which is beneficial for realizing high-frequency and high-reliability transistor design.

[0141] Figure 5 This is a flowchart illustrating a method for fabricating a transistor according to an embodiment of this disclosure. See also... Figure 5 The flowchart of this method includes: 401. Provide a substrate.

[0142] For example, substrate 100 is an N-type 4H-SiC 6-inch wafer substrate.

[0143] In one example, step 401 may include: First, clean the substrate using a wet chemical cleaning method (such as the RCA standard cleaning method); Rapid thermal annealing (RTA) was performed at 1050℃ in a hydrogen atmosphere for 10 minutes to repair the substrate surface.

[0144] 402. A core layer, a buffer layer, a channel layer, a barrier layer, and a p-type gallium nitride layer are sequentially fabricated on the substrate.

[0145] In one example, step 402 may include: An AlN nucleation layer with a thickness of 200 nm was grown at a growth temperature of 780℃; then, 10 cycles of Al were grown. 0.3 Ga 0.7 The superlattice structure of N (10nm) / GaN (10nm) / AlN (10nm) and the GaN buffer layer with a thickness of 2μm; A GaN channel layer with a thickness of 100 nm was grown at a growth temperature of 1020 °C; then an Al layer with a thickness of 18 nm was grown. 0.22 Ga 0.78 N-barrier layer; A P-type GaN layer with a thickness of 80 nm was grown at a growth temperature of 850℃.

[0146] After growth is complete, step 402 may further include: The above-mentioned film layers are patterned on the wafer to form isolation and markings that separate the various devices (transistors).

[0147] For example, a 1.2 μm thick positive photoresist is first spin-coated, and the mesa region (transistor structure region) and marking pattern (isolation and marking) are defined by exposure and development. The above film layer is then etched using a capacitively coupled plasma (CCP) etching process, with the etching gas being Cl2 (30 sccm) / BCl3 (10 sccm) / Ar (5 sccm), the RF power being 300W, the bias power being 100W, and the etching depth being 400 nm, to form device isolation and marking.

[0148] After isolation and labeling are formed, step 402 may further include: The first step is to pattern the p-type gallium nitride layer by etching.

[0149] For example, a TiN mask is deposited on the surface of a P-type gallium nitride layer; a photoresist + TiN dual-gate mask pattern is formed by photolithography and etching; and the P-type gallium nitride layer is selectively etched under the cover of the TiN dual-gate mask pattern.

[0150] The etching of the TiN mask and the etching of the P-type gallium nitride layer can be performed using the same etching process. For example, the etching process can be inductively coupled plasma (ICP) etching, with the etching gas being Cl2 (35 sccm) / Ar (5 sccm) / O2 (10 sccm), the RF power being 250W, and the bias power being 55W.

[0151] By employing endpoint detection to control the etching depth, a curve at a wavelength of 417 nm (Ga) was captured, and second-order differentiation was performed. Capturing was initiated 50 seconds after the curve stabilized, and etching depth control was stopped once the average intensity of the 417 nm signal decreased by 5%. Ultimately, Al... 0.22 Ga 0.78 The N-barrier layer is etched to a thickness of less than 1 nm. The etching selectivity ratio is required to be greater than 20:1.

[0152] After etching, the photoresist is removed and surface treatment and repair are performed: At 70-80℃, the surface is first treated with a sulfuric acid-peroxide mixture (SPM) for 5 minutes; then treated with a 35% KOH solution for 5 minutes; finally, it is rinsed and dried. In the above process, SPM simultaneously removes both the photoresist and the hard mask TiN.

[0153] The volume ratio of concentrated sulfuric acid, hydrogen peroxide, and deionized water in SPM is 3:1:4.

[0154] The second step is to form a groove on the P-type gallium nitride layer.

[0155] For example, the groove area is defined by photolithography, and ICP etching is used to etch 10nm. After etching, wet resist removal and damage repair are performed: at an environment of 70~80℃, SPM is first used for 5 minutes; then 35% KOH solution is used for 5 minutes; finally, it is rinsed and dried.

[0156] 403. Fabricate a gate metal layer on a P-type gallium nitride layer.

[0157] A first gate, a second gate, and a gate connection structure are formed through a P-type gallium nitride layer and a gate metal layer.

[0158] The first gate 103 and the second gate 104 are located on the barrier layer 102, and the gate connection structure 116 is electrically connected to the end of the first gate 103 and the end of the second gate 104, respectively.

[0159] In one example, step 403 may include: The gate region is defined by photolithography, which forms a photoresist pattern. The grooves in the photoresist pattern correspond to the positions where the gate is located. Then, a vapor deposition and lift-off process is used to fabricate the gate metal (200nm TiW). The photoresist pattern and the gate metal on it are then removed, leaving the gate metal in the grooves, forming the first gate, the second gate, and the gate connection structure.

[0160] 404. Create the media layer.

[0161] The dielectric layer 114 covers the barrier layer 102, the first gate 103, and the second gate 104.

[0162] In one example, step 404 may include: A 5 nm Al2O3 layer was deposited using atomic layer deposition (ALD) at a deposition temperature of 250 °C. The precursor was trimethylaluminum TMA (aluminum source) + H2O (oxygen source).

[0163] 405. Fabricate the first electrode, the second electrode, and the third electrode.

[0164] The first electrode 105, the second electrode 106, and the third electrode 107 pass through the dielectric layer 114 and contact the barrier layer 102.

[0165] In one example, step 404 may include: First, the ohmic contact region is defined by negative photoresist lithography with a source-drain spacing of 18 μm. Dry etching is performed using ICP to form a groove that penetrates the dielectric layer and extends 15 nm into the barrier layer. A evaporation lift-off process is used to form a Ti (20 nm) / Al (200 nm) / TiW (200 nm) metal stack as the first, second, and third electrodes. RTA is performed at 850 °C in a nitrogen atmosphere for 30 s.

[0166] 406. Create the first passivation layer.

[0167] The first passivation layer 108 is located on the dielectric layer 114.

[0168] In one example, step 406 may include: A 500 nm SiN layer was deposited using plasma-enhanced chemical vapor deposition (PECVD) at a temperature of 300 °C, a pressure of less than 100 MPa, and a bias power of 0 W. The refractive index of the first passivation layer was 1.869. Then, a groove to accommodate the first field plate was formed by photolithography and etching.

[0169] 407. Make the first layer of the field board.

[0170] The first field plate 109 passes through the first passivation layer 108 and contacts the dielectric layer 114.

[0171] In one example, step 407 may include: A TiN (50nm) / Al (400nm) / TiN (50nm) metal stack was formed using a sputtering lift-off process, serving as the first field layer with a length of 0.5μm.

[0172] 408: Create the second passivation layer.

[0173] The second passivation layer 110 covers the first field plate 109 and the first passivation layer 108.

[0174] In one example, step 408 may include: A 1000nm SiN layer was deposited using PECVD. Then, vias connecting the first, second, and third electrodes were formed by photolithography and etching.

[0175] 409: Fabricate the second layer of the field panel and the connecting structure.

[0176] The second field plate 111 is located on the second passivation layer 110, the connection structure 113 passes through the through hole of the second passivation layer 110, and the second field plate 111 is electrically connected to the first electrode 105, the second electrode 106 or the third electrode 117 through the connection structure 113.

[0177] In one example, step 409 may include: A TiN (50nm) / Al (1000nm) / TiN (50nm) metal stack was formed using a sputtering lift-off process, serving as the second field plate and connection structure. The length of the second field plate was 1μm.

[0178] 410: Create the third passivation layer.

[0179] The third passivation layer 112 covers the second passivation layer 110 and the second field plate 111.

[0180] In one example, step 410 may include: First, a 3μm SiO2 layer is deposited, then thinned to 1.5μm using chemical mechanical polishing (CMP); next, a 0.5μm SiO2 layer is deposited to eliminate cracks and ensure the overall planarity of the wafer. Then, through-holes with interconnecting structures are formed by photolithography and etching; these through-holes can be circular holes with a diameter of 0.5μm.

[0181] 411: Fabricate metal interconnect structures.

[0182] The metal interconnect structure 117 is located on the third passivation layer 112, the connection structure 113 passes through the third passivation layer 112, and the metal interconnect structure 117 is electrically connected to the connection structure 113.

[0183] In one example, step 411 may include: First, a 50 nm TiN layer is sputtered as a seed layer for W deposition; then, a 0.6 μm W layer is deposited using wet chemical vapor deposition (WCVD); an etch-back process is used to remove excess W from the surface; then, a evaporation process is used to form a Ti (100 nm) / Al (4000 nm) / Ti (100 nm) metal stack; a metal interconnect structure is formed by photolithography and dry etching; finally, the resist is removed and the surface is cleaned.

[0184] 412: Create a protective layer.

[0185] The protective layer 118 covers the third passivation layer 112 and the metal interconnect structure 117, and the protective layer 118 exposes at least a portion of the surface of the metal interconnect structure 117 through openings.

[0186] In one example, step 412 may include: First, a 1 μm SiO2 layer is deposited; then a 0.5 μm SiN layer is deposited. Next, vias are formed by photolithography and etching to expose at least a portion of the surface of the metal interconnect structure.

[0187] The structure and shape of each film layer formed by the above manufacturing steps can be found in [reference needed]. Figure 1 and Figure 2 The corresponding text description.

[0188] Optionally, the method may further include: sending the package to a packaging plant for thinning and packaging, followed by testing.

[0189] The final transistor parameters are as follows: breakdown voltage > 2000V; specific on-resistance < 10mΩ·cm 2 Threshold voltage > 1.5V; bidirectional conduction resistance deviation < 3%; gate leakage current < 10e-8A / mm. Providing ideal device solutions for next-generation high-efficiency, high-power-density power electronic systems (such as converters for new energy vehicles and energy storage systems).

[0190] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A transistor, characterized in that, The transistor includes: a channel layer (101), a barrier layer (102), a first gate (103), a second gate (104), a first electrode (105), a second electrode (106), and a third electrode (107). The barrier layer (102) is stacked on the channel layer (101), the first gate (103) and the second gate (104) are located on the barrier layer (102), and the first electrode (105), the second electrode (106) and the third electrode (107) are respectively inserted into the barrier layer (102). Along the first direction a, the first electrode (105), the first gate (103), the second electrode (106), the second gate (104), and the third electrode (107) are arranged sequentially; The first gate (103) and the second gate (104) are connected in series.

2. The transistor according to claim 1, characterized in that, The orthographic projection of the first electrode (105) on the surface of the channel layer (101) and the orthographic projection of the second electrode (106) on the surface of the channel layer (101) are symmetrical about the orthographic projection of the first gate (103) on the surface of the channel layer (101). The orthographic projection of the second electrode (106) on the surface of the channel layer (101) and the orthographic projection of the third electrode (107) on the surface of the channel layer (101) are symmetrical about the orthographic projection of the second gate (104) on the surface of the channel layer (101).

3. The transistor according to claim 1 or 2, characterized in that, The transistor also includes a first field plate structure (191), a second field plate structure (192), a third field plate structure (193), and a fourth field plate structure (194). The first field plate structure (191) is located between the first electrode (105) and the first gate (103), the second field plate structure (192) is located between the first gate (103) and the second electrode (106), the third field plate structure (193) is located between the second electrode (106) and the second gate (104), and the fourth field plate structure (194) is located between the second gate (104) and the third electrode (107). The orthographic projection of the first field plate structure (191) on the surface of the channel layer (101) and the orthographic projection of the second field plate structure (192) on the surface of the channel layer (101) are symmetrical about the orthographic projection of the first gate (103) on the surface of the channel layer (101); the orthographic projection of the third field plate structure (193) on the surface of the channel layer (101) and the orthographic projection of the fourth field plate structure (194) on the surface of the channel layer (101) are symmetrical about the orthographic projection of the second gate (104) on the surface of the channel layer (101).

4. The transistor according to claim 3, characterized in that, The first field plate structure (191) is insulated from the first electrode (105), the second electrode (106) and the third electrode (107) respectively; the second field plate structure (192) is insulated from the first electrode (105), the second electrode (106) and the third electrode (107) respectively; the third field plate structure (193) is insulated from the first electrode (105), the second electrode (106) and the third electrode (107) respectively; the fourth field plate structure (194) is insulated from the first electrode (105), the second electrode (106) and the third electrode (107) respectively.

5. The transistor according to claim 3, characterized in that, The transistor also includes a fifth field plate structure (1111), a sixth field plate structure (1112), a seventh field plate structure (1113), and an eighth field plate structure (1114). One end of the fifth field plate structure (1111) is connected to the second electrode (106), and the other end of the fifth field plate structure (1111) is away from the second electrode (106) along the first direction a; one end of the sixth field plate structure (1112) is connected to the second electrode (106), and the other end of the sixth field plate structure (1112) is away from the second electrode (106) along the opposite direction of the first direction a; one end of the seventh field plate structure (1113) is connected to the second electrode (106), and the other end of the seventh field plate structure (1113) is away from the second electrode (106) along the opposite direction of the first direction a; The other end of the eighth field plate structure (1114) is away from the second electrode (106) along the first direction a; one end of the eighth field plate structure (1114) is connected to the second electrode (106), and the other end of the eighth field plate structure (1114) is away from the second electrode (106) along the opposite direction of the first direction a; the fifth field plate structure (1111), the sixth field plate structure (1112), the seventh field plate structure (1113) and the eighth field plate structure (1114) are arranged in sequence along the second direction b, which is perpendicular to the first direction a.

6. The transistor according to claim 5, characterized in that, The transistor further includes a ninth field plate structure (1115) and a tenth field plate structure (1116); one end of the ninth field plate structure (1115) is connected to the first electrode (105), and the other end of the fifth field plate structure (1111) is away from the first electrode (105) along a first direction a; one end of the tenth field plate structure (1116) is connected to the first electrode (105), and the other end of the tenth field plate structure (1116) is away from the first electrode (105) along a first direction a; the ninth field plate structure (1115) and the tenth field plate structure (1116) are arranged sequentially along a second direction b.

7. The transistor according to claim 6, characterized in that, The sixth field plate structure (1112) is located between the ninth field plate structure (1115) and the tenth field plate structure (1116), and the tenth field plate structure (1116) is located between the sixth field plate structure (1112) and the eighth field plate structure (1114).

8. The transistor according to claim 5, characterized in that, The transistor further includes an eleventh field plate structure (1117) and a twelfth field plate structure (1118); one end of the eleventh field plate structure (1117) is connected to the third electrode (107), and the other end of the eleventh field plate structure (1117) is away from the third electrode (107) along the opposite direction of the first direction a; one end of the twelfth field plate structure (1118) is connected to the third electrode (107), and the other end of the twelfth field plate structure (1118) is away from the third electrode (107) along the opposite direction of the first direction a; the eleventh field plate structure (1117) and the twelfth field plate structure (1118) are arranged sequentially along the second direction b.

9. The transistor according to claim 8, characterized in that, The eleventh field plate structure (1117) is located between the fifth field plate structure (1111) and the seventh field plate structure (1113), and the seventh field plate structure (1113) is located between the eleventh field plate structure (1117) and the twelfth field plate structure (1118).

10. A method for manufacturing a transistor, characterized in that, The method includes: A channel layer and a barrier layer are fabricated sequentially, with the barrier layer stacked on top of the channel layer; A first gate and a second gate are fabricated on the barrier layer, and the first gate and the second gate are connected in series. A first electrode, a second electrode, and a third electrode are fabricated, and the first electrode, the second electrode, and the third electrode are respectively inserted into the barrier layer; along a first direction a, the first electrode, the first gate electrode, the second electrode, the second gate electrode, and the third electrode are arranged sequentially.

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