Calibration method in test machine channel and chip test machine

Abstract

The invention relates to a test machine in-channel calibration method and a chip test machine, single-edge signals are respectively sent to a PE chip through each link in a channel, the PE chip performs internal loopback after receiving the single-edge signals, and the delay time of the corresponding link is determined according to the time of returning the single-edge signals by the PE chip. And according to the delay time of each link, delaying the corresponding link, and adjusting the time of each link to be the same from the time of sending the single-edge signal to the time of receiving the single-edge signal returned by the PE chip, so that the signals of each link are aligned in phase. A single-edge signal is returned in a PE chip inner loopback mode, and a signal transmission link is shortened, so that attenuation is reduced, and calibration precision is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor testing technology, and in particular to a test machine in-channel calibration method and a chip test machine. Background Technology

[0002] Currently, the test signals of digital testers are all generated based on PE (electronic pin circuit) chips. The quality of the signal transmitted to the PE chip directly determines the quality of the test signal. Therefore, calibration and alignment are extremely important in the use of testers.

[0003] Traditional TDR calibration methods involve the control module outputting a pulse signal to the PE chip, which then transmits the pulse signal to the POGO terminal and reflects it back to the PE chip. The signal then returns from the PE chip to the FPGA, where it performs calibration based on the received pulse signal. However, signal reflection causes attenuation, which increases with the length of the link, leading to decreased calibration accuracy. This traditional method suffers from low calibration precision. Summary of the Invention

[0004] Therefore, it is necessary to provide an in-channel calibration method and chip tester that can improve calibration accuracy to address the above problems.

[0005] The first aspect of this application provides a calibration method for an in-channel test machine, comprising:

[0006] Each link within the channel sends a single-edge signal to the PE chip, and the delay time of the corresponding link is determined based on the time it takes for the PE chip to return the single-edge signal; wherein, the PE chip performs an internal loopback after receiving the single-edge signal;

[0007] The corresponding links are delayed according to their delay time, and each link is adjusted so that the time from sending a single-edge signal to receiving a single-edge signal returned by the PE chip is the same, so that the signals of each link are aligned in phase.

[0008] In one embodiment, the step of sending single-edge signals to the PE chip through each link within the channel, and determining the delay time of the corresponding link based on the time when the PE chip returns the single-edge signal, includes:

[0009] Single-edge signals are sent to the PE chip through each link, and the corresponding IOdelay delay module is used for adjustment so that the single-edge signal returned by the PE chip is received within a preset proportional clock cycle.

[0010] The time from the transmission of a single-edge signal to the acquisition of the single-edge signal returned by the PE chip is adjusted using the fine delay module of each link. The preset proportional clock cycle of each link is aligned, and the delay time of the corresponding link is recorded.

[0011] The delay accuracy of the IOdelay delay module is greater than that of the fine delay module.

[0012] In one embodiment, the preset number of bits for the single-edge signal of each link is the reciprocal of a preset ratio.

[0013] In one embodiment, the step of sending single-edge signals to the PE chip via each link and adjusting the delay using a corresponding IOdelay module to ensure that the single-edge signal returned by the PE chip is received within a preset proportional clock cycle includes:

[0014] Select one link to send a single-edge signal, while keeping the other links sending a preset number of bits of data in one clock cycle. Adjust the delay value of the IOdelay module corresponding to the link sending the single-edge signal so that the single-edge signal returned by the PE chip is acquired in a preset proportional clock cycle.

[0015] In one embodiment, the link includes a first data link, a second data link, a first control link, and a second control link.

[0016] In one embodiment, the step of selecting one link to send a single-edge signal, while keeping the other links sending a preset number of bits of data in one clock cycle, and adjusting the delay value of the IOdelay module corresponding to the link sending the single-edge signal, so that the single-edge signal returned by the PE chip is acquired in a preset proportional clock cycle, includes:

[0017] Select the first data link to send a single-edge signal, keep the other links sending 0 bits of a preset number of bits in one clock cycle, and adjust the delay value of the IOdelay delay module corresponding to the first data link so that the single-edge signal returned by the PE chip is acquired in a preset proportional clock cycle.

[0018] Select the second data link to send a single-edge signal, keep the first data link and the second control link sending 0 bits of a preset number of bits in one clock cycle, keep the first control link sending 1 bits of a preset number of bits in one clock cycle, and adjust the delay value of the IOdelay delay module corresponding to the second data link so that the single-edge signal returned by the PE chip is acquired in a preset proportional clock cycle.

[0019] Select the first control link to send a single-edge signal, keep the first data link and the second control link sending a preset number of 0 bits in one clock cycle, keep the second data link sending a preset number of 1 bits in one clock cycle, and adjust the delay value of the IOdelay delay module corresponding to the first control link so that the single-edge signal returned by the PE chip is acquired in a preset proportional clock cycle.

[0020] Select the second control link to send a single-edge signal, keep the first data link and the first control link sending a preset number of 0 bits in one clock cycle, keep the second data link sending a preset number of 1 bits in one clock cycle, and adjust the delay value of the IOdelay delay module corresponding to the second control link so that the single-edge signal returned by the PE chip is acquired in a preset proportional clock cycle.

[0021] In one embodiment, the step of adjusting the time from the transmission of a single-edge signal to the acquisition of the single-edge signal returned by the PE chip using the fine delay module of each link, and aligning the preset proportional clock cycle of each link, includes:

[0022] The timing of each link's single-edge signal transmission and the acquisition of the single-edge signal returned by the PE chip are adjusted using the fine delay module of each link, so that the single-edge signal is acquired in the same phase within the clock cycle, thus completing the preset ratio clock cycle alignment.

[0023] In one embodiment, the step of delaying the corresponding links according to their delay times, and adjusting each link to have the same time from sending a single-edge signal to receiving a single-edge signal returned by the PE chip, includes:

[0024] The link with the longest delay time is selected as the benchmark. The time from the transmission of the single-edge signal to the acquisition of the single-edge signal returned by the PE chip is adjusted by the corresponding coarse delay module to align the full clock cycles of each link. The delay accuracy of the fine delay module is greater than that of the coarse delay module.

[0025] In one embodiment, after delaying the corresponding links according to their delay times to adjust each link so that the time from sending a single-edge signal to receiving a single-edge signal returned by the PE chip is the same, so that the signals of each link are aligned in phase, the method further includes:

[0026] Delay compensation is performed on other links based on the reference link in the aforementioned links, so that the phase between each link reaches the preset condition.

[0027] In one embodiment, the delay compensation of other links based on a reference link in the link, so that the phase between the links reaches a preset condition, includes:

[0028] Choose any link as the reference link, and use the IOdelay delay module and the fine delay module to adjust the delay of the corresponding link so that the remaining links achieve the phase relationship required by the PE chip; wherein, the delay accuracy of the IOdelay delay module is greater than the delay accuracy of the fine delay module.

[0029] A second aspect of this application provides a chip testing machine, including a controller and a PE chip, wherein the controller is connected to the PE chip and is used to perform in-channel calibration according to the method described above.

[0030] In one embodiment, the controller includes a driver module and a comparison module. Each serial generator in the driver module is connected to the PE chip via a corresponding link, and the serial receiver in the comparison module is connected to the PE chip.

[0031] In one embodiment, the serial generator includes a data selector, a delay module, and a waveform driver. The data selector is connected to a host computer and the delay module, the waveform driver is connected to the delay module, and is connected to the PE chip through a corresponding link.

[0032] The delay module includes an IOdelay delay module, a fine delay module, and a coarse delay module arranged in series. The delay accuracy of the IOdelay delay module is greater than that of the fine delay module, and the delay accuracy of the fine delay module is greater than that of the coarse delay module.

[0033] The aforementioned in-channel calibration method and chip tester transmit single-edge signals to the PE chip via each link within the channel. The PE chip receives the single-edge signal and performs an internal loopback. The delay time of the corresponding link is determined based on the return time of the single-edge signal from the PE chip. By adjusting the delay time of each link, the time from transmitting the single-edge signal to receiving the returned single-edge signal from the PE chip is the same, ensuring phase alignment of the signals across all links. Employing an internal loopback method within the PE chip to return the single-edge signal shortens the signal transmission link, thereby reducing attenuation and improving calibration accuracy. Furthermore, this method does not rely on test vectors to generate calibration signals, making the calibration process simpler and more efficient. Attached Figure Description

[0034] Figure 1 This is a flowchart of a calibration method within a test machine channel in one embodiment;

[0035] Figure 2 This is a block diagram of the calibration circuit within the test machine channel in one embodiment;

[0036] Figure 3 A flowchart of the calibration method within the test machine channel in another embodiment;

[0037] Figure 4 This is a timing diagram for multi-serial generator calibration in one embodiment;

[0038] Figure 5 This is a block diagram of the calibration structure within the test machine channel in one embodiment;

[0039] Figure 6 This is a flowchart illustrating the calibration implementation within a test machine channel in one embodiment;

[0040] Figure 7 Here is a flowchart illustrating the implementation of edge alignment for the first data link in one embodiment;

[0041] Figure 8 This is a sampled image when the first data link edge is not aligned in one embodiment;

[0042] Figure 9 This is a sampled image when the first data link edge is aligned in one embodiment;

[0043] Figure 10 Here is a flowchart illustrating the implementation of second data link edge alignment in one embodiment;

[0044] Figure 11 Here is a flowchart illustrating the implementation of edge alignment for the first control link in one embodiment;

[0045] Figure 12 Here is a flowchart illustrating the implementation of edge alignment for the second control link in one embodiment;

[0046] Figure 13 This is a sampled image before compensation for 1 / 8 of a cycle in one embodiment;

[0047] Figure 14 This is a sampled image after 1 / 8 period compensation in one embodiment. Detailed Implementation

[0048] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. It is understood that the term "connection" in the following embodiments, if the connected circuits, modules, units, etc., transmit electrical signals or data to each other, should be understood as "electrical connection," "communication connection," etc.

[0050] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0051] In one embodiment, such as Figure 1 As shown, a test machine in-channel calibration method is provided, including:

[0052] Step S110: Send single-edge signals to the PE chip through each link in the channel, and determine the delay time of the corresponding link based on the time when the PE chip returns the single-edge signal.

[0053] In this context, the PE chip's internal loopback refers to returning the input signal. During the loopback process, the input signal itself remains unchanged. For example, if the input is a single-edge signal, the internal loopback will return a single-edge signal; if the input is all zeros, the internal loopback will return all zeros. The number and type of links within a channel are not unique. In chip testing equipment, the phase relationship between the data link and the control link is crucial to the quality of the test signal. Figure 2 As shown, the controller 100 can be connected to the PE chip 200. The controller 100 sends single-edge signals to the PE chip 200 through each link in the channel. The controller 100 can be an FPGA, MCU, CPU, etc. In this embodiment, the controller 100 is an FPGA. The controller 100 sends single-edge signals to the PE chip 200 through each link in the channel, and determines the delay time of the corresponding link based on the time when the PE chip 200 returns the single-edge signal.

[0054] Continue to refer to Figure 2The controller 100 includes a driver module 110 and a comparison module 120. Each serial generator 112 in the driver module 110 is connected to the PE chip 200 via a corresponding link. The serial receiver 122 in the comparison module 120 is connected to the PE chip 200. The number of serial generators 112 corresponds to the number of links within the channel. Specifically, the links within the channel include a first data link (for transmitting data signal DATA0), a second data link (for transmitting data signal DATA1), a first control link (for transmitting control signal RCV0), and a second control link (for transmitting control signal RCV1). The number of links is not unique, provided the PE chip satisfies the loopback condition for all links within the channel. Each serial generator 112 is connected to the PE chip 200 via its corresponding first data link, second data link, first control link, or second control link, and sends a single-edge signal to the PE chip 200. The serial receiver 122 is connected to the PE chip 200 via the comparison link CMPL and receives the single-edge signal loopback within the PE chip 200. A single-edge signal can be a rising edge signal (low level to high level) or a falling edge signal (high level to low level). In this embodiment, a rising edge signal is used for convenient in-channel calibration. A single-edge signal means that the signal waveform has one and only one edge. If there are two or more edges, the in-channel calibration will be inaccurate.

[0055] Step S120: Delay the corresponding links according to the delay time of each link, and adjust each link so that the time from sending a single-edge signal to receiving a single-edge signal returned by the PE chip is the same, so that the signals of each link are aligned in phase.

[0056] Continue to refer to Figure 2 After determining the delay times of the first data link, the second data link, the first control link, and the second control link, the controller 100 also delays the corresponding links according to their delay times. Combined with the loopback and link delay processing inside the PE chip, the controller 100 sequentially achieves edge alignment, preset proportional clock cycle alignment, and full cycle alignment of each link, so that the time from sending a single edge signal to receiving a single edge signal returned by the PE chip 200 is the same for each link, thereby aligning the signals of each link in phase.

[0057] The controller 100 can adjust the delay time of each link by adjusting the parameters of the delay module in the serial generator 112. The type of delay module is not unique; it can include at least two of the following: IOdelay delay module, fine delay module, and coarse delay module. The IOdelay delay module is an IOdelay delay chain composed of cascaded Idelay and Odelay delay units. The delay accuracy of the IOdelay delay module is greater than that of the fine delay module, and the delay accuracy of the fine delay module is greater than that of the coarse delay module. The controller 100 adjusts the delay value of the corresponding delay module according to actual needs to complete the edge alignment, preset proportional clock cycle alignment, and full cycle alignment of each link.

[0058] Each link within the channel sends a single-edge signal to the PE chip. Upon receiving the single-edge signal, the PE chip performs an internal loopback. The delay time of the corresponding link is determined based on the return time of the single-edge signal from the PE chip. By adjusting the delay times of each link, the time from sending the single-edge signal to receiving the returned single-edge signal from the PE chip is made the same for all links, ensuring phase alignment. This internal loopback method within the PE chip shortens the signal transmission link, reducing attenuation and improving calibration accuracy. Furthermore, this method does not rely on test vectors to generate calibration signals, making the calibration process simpler and more efficient.

[0059] In one embodiment, such as Figure 3 As shown, after step S120, the method further includes:

[0060] Step S130: Perform delay compensation on other links based on the reference link in the link, so that the phase between each link reaches the preset condition.

[0061] The reference link can be any one of the first data link, the second data link, the first control link, and the second control link. The specific content of the preset conditions is not unique and can be set according to the requirements of the PE chip during actual testing. After adjusting the phase alignment of the signals on each link, the controller 100 selects one link as the reference link and adjusts the parameters of the delay modules corresponding to the other links to complete the multi-serial generator (mult_drive) calibration, so that the phase between each link reaches the preset conditions and meets the requirements of the PE chip.

[0062] Figure 4 The diagram shown is a timing diagram for multi-serial generator calibration. The purpose of multi-serial generator calibration is to adjust the test signals (RCV0, RCV1, DATA0, DATA1) of the four links to a fixed phase (corresponding to preset conditions) to achieve minimal data jitter. Multi-serial generator calibration is based on the PE chip 200's own mult_drive mode characteristics, such as... Figure 5 As shown, the PE chip 200 includes an XOR gate circuit 210 and a multiplexer (MUX) circuit 220. The XOR gate circuit 210 XORs the control signals RCV0 and RCV1 to generate a sampling signal S0, which is sent to the multiplexer circuit 220. When the sampling signal S0 is high, the multiplexer circuit 220 uses the data signal DATA1 as the output signal DUT0; conversely, when the sampling signal S0 is low, the multiplexer circuit 220 uses the data signal DATA0 as the output signal DUT0.

[0063] Taking a single-edge signal using a rising edge signal as an example, the controller 100 causes the four links to send rising edge signals respectively. The rising edge signal loops back through the PE chip 200 and then enters the comparison module 120. Figure 5 As shown, the comparison module 120 includes a serial receiver 122 and timers 124. The number of timers 124 is consistent with the number of links in the channel. The serial receiver 122 collects the current rising edge signal, and the timers 124 record the time from the emission of the four rising edge signals to the receipt of the rising edge by the serial receiver 122. By using several delay modules with different precisions, the time from the emission of the rising edge of the four links to the receipt of the rising edge by the serial receiver 122 is adjusted to be the same. At this point, the four links can be considered to be perfectly aligned in phase. After the phase is perfectly aligned, any one link (e.g., the first data link) is selected as the reference, and the delay modules are used to adjust the delay of the other three links so that the phase between the four links reaches the preset condition, thus completing the calibration.

[0064] In one embodiment, step S110 includes steps 112 and 114.

[0065] Step 112: Send single-edge signals to the PE chip through each link respectively, and adjust them using the corresponding IOdelay module so that the single-edge signal returned by the PE chip is received within a preset proportional clock cycle.

[0066] Step 114: Adjust the time from the transmission of a single-edge signal to the reception of the single-edge signal from the PE chip using the fine delay module of each link, align the clock cycles of each link to a preset ratio, and record the delay time of the corresponding link. The delay accuracy of the IOdelay module is greater than that of the fine delay module. The preset number of bits for the single-edge signal of each link is the reciprocal of the preset ratio.

[0067] Continue to refer to Figure 5Each serial generator 112 includes a data selector, a delay module, and a waveform driver. The delay module includes an IOdelay delay module, a fine delay module, and a coarse delay module. The IOdelay, fine, and coarse delay modules are connected in series, with one end connected to the data selector and the other end connected to the waveform driver. The waveform driver is connected to the PE chip 200 via a corresponding link. It is understood that the connection order between the IOdelay, fine, and coarse delay modules is not unique and can be set according to actual needs. In this embodiment, the data selector, coarse delay module, fine delay module, IOdelay module, and waveform driver are connected sequentially. The data selector is connected to the host computer 300, and the waveform driver is connected to the PE chip 200 via a corresponding link. The coarse delay module is used to compensate for the period of each data channel with an accuracy of 1 ns-10 ns; the fine delay module is used to compensate for the fractional period of each data channel with an accuracy of 200 ps-800 ps; the IOdelay delay module is used to adjust the data channel at the picosecond level with an accuracy of 1 ps-10 ps; and the waveform driver is used to convert the signal determined by the data selector into a serial signal and drive it to the corresponding pin of the PE chip 200.

[0068] Furthermore, the data selector is connected to the host computer 300, and determines the data (RCV0, RCV1, DATA0, DATA1) for each channel during calibration according to the instructions of the host computer 300, and sends the corresponding signals to the PE chip 200. In addition, the timer 124 in the comparison module 120 is also connected to the host computer 300, records the time when the signals of the four links are sent to the serial receiver and received, and uploads this information to the host computer 300. The host computer 300 obtains the specific delay time of each link recorded by the timer 124, thereby calculating the delay value that needs to be compensated for each link, and configuring the parameters of the corresponding delay module. The host computer 300 can be, but is not limited to, various personal computers, laptops, smartphones, tablets, and portable wearable devices, such as smartwatches, smart bracelets, and head-mounted devices.

[0069] It is understood that in other embodiments, the controller 100 can also configure the data transmission of each link and configure the parameters of the corresponding delay module according to the delay time recorded by the timer 124.

[0070] In one embodiment, step 112 includes: selecting one of the links to send a single-edge signal, keeping the other links to send a preset number of bits of preset data in one clock cycle, and adjusting the delay value of the IOdelay delay module corresponding to the link sending the single-edge signal so that the single-edge signal returned by the PE chip is acquired in a preset proportional clock cycle.

[0071] The preset data can be 0 (low level) or 1 (high level). The preset ratio will vary depending on the preset number of bits, which is determined by the controller's resources. The clock cycle is the domainclk master clock issued by the communication board, and each resource board performs its services according to the master clock. For example, each link sends 8 bits of data in one clock cycle: bit0, bit1, ..., bit7. This is equivalent to dividing one clock cycle into 8 phases, where bit0 is the 0th phase, bit1 is the 1st phase, and so on, with bit7 being the 7th phase. Therefore, the preset number of bits is 8, and the preset ratio can be 1 / 8, 2 / 8, etc. In this embodiment, the preset ratio is 1 / 8. Thus, the single-edge signal returned by the PE chip is acquired during the preset ratio clock cycle, which indicates at which phase the single-edge signal is acquired.

[0072] Figure 6 The diagram shows the calibration process within the test machine channel. For ease of description, the first data link, second data link, first control link, and second control link are referred to as DATA0 link, DATA1 link, RCV0 link, and RCV1 link, respectively. The DATA0 link sends a single rising edge signal from 0 to 1, adjusting the delay value of the IOdelay delay chain so that the serial receiver 122 acquires the rising edge exactly within a certain 1 / 8 cycle, which can be any number of phases. The DATA1 link sends a rising edge signal from 0 to 1, adjusting the delay value of the IOdelay delay chain so that the serial receiver 122 acquires the rising edge exactly within a certain 1 / 8 cycle, which can be any number of phases. The RCV0 link sends a rising edge signal from 0 to 1, adjusting the delay value of the IOdelay delay chain so that the serial receiver 122 acquires the rising edge exactly within a certain 1 / 8 cycle, which can be any number of phases. The RCV1 link sends a rising edge signal from 0 to 1, adjusting the delay value of the IOdelay delay chain so that the serial receiver 122 acquires the rising edge exactly at a certain 1 / 8 cycle, which can be any phase. Through the above steps, edge alignment of the four links is completed. The specific process of edge alignment is as follows:

[0073] First step, such as Figure 7 As shown, the first data link is selected to send a single-edge signal, while other links are kept sending 0 bits of a preset number of bits in one clock cycle. The delay value of the IOdelay delay module corresponding to the first data link is adjusted so that the single-edge signal returned by the PE chip 200 is acquired in a preset proportional clock cycle.

[0074] Specifically, using corresponding data selectors and waveform drivers, the DATA1, RCV0, and RCV1 links transmit 8 bits of 0. The DATA0 link transmits a single rising edge from 0 to 1. At this time, according to the multiply_drive mode characteristics of the PE chip 200, the sampling signal S0, which is the result of the XOR operation of the control signals RCV0 and RCV1, is all 0, and data from the DATA0 link is transmitted. After the DATA0 link transmits the single rising edge, it loops back to the serial receiver 122 through the internal loop of the PE chip 200 for acquisition. At this time, the rising edge will be acquired at a certain 1 / 8 cycle, which is assumed to be 11110000 (the 4th phase) in this embodiment. Figure 8 As shown, the 1 sampled on the 4th phase sampling edge may not be exactly at the rising edge position; there may be an error in between. In this case, the delay value is adjusted using the IOdelay delay chain on the DATA0 link. To verify edge alignment, the DATA0 link is sent again with a single rising edge. The serial receiver 122 collects the first non-zero data 1 at a certain clock cycle position. The steps of adjusting the delay value using the IOdelay delay chain and sending a single rising edge are repeated until it is exactly at the 5th phase sampling edge. Figure 9 As shown, the DATA0 link edge alignment is completed.

[0075] The second step, as Figure 10 As shown, the second data link is selected to send a single-edge signal, while the first data link and the second control link send a preset number of 0 bits in one clock cycle, and the first control link sends a preset number of 1 bits in one clock cycle. The delay value of the IOdelay delay module corresponding to the second data link is adjusted so that the single-edge signal returned by the PE chip is acquired in a preset proportional clock cycle.

[0076] In this process, using corresponding data selectors and waveform drivers, the DATA0 and RCV1 links transmit 8 bits of 0, and the RCV0 link transmits 1. The DATA1 link transmits a single rising edge from 0 to 1. At this time, according to the characteristics of the PE chip 200's mut_drive mode, the sampling signal S0, which is XORed with the control signal RCV0 and the control signal RCV1, is all 1, and the data of the DATA1 link is transmitted. After the DATA0 link transmits the single rising edge, it loops back to the serial receiver 122 through the internal loop of the PE chip 200 for acquisition. At this time, the rising edge will be acquired at a certain 1 / 8 cycle, which is assumed to be 11100000 (the 5th phase) in this embodiment. The delay value is adjusted using the IOdelay delay chain on the DATA1 link. To verify whether the edge is aligned, the DATA1 link transmits a single rising edge again. The serial receiver 122 acquires the first non-zero data 1 at a certain clock cycle position. The steps of adjusting the delay value using the IOdelay delay chain and transmitting the single rising edge are repeated until it is exactly at the 6th phase sampling edge, completing the edge alignment of the DATA1 link.

[0077] The third step, as Figure 11 As shown, the first control link is selected to send a single-edge signal, the first data link and the second control link are kept sending 0 bits of a preset number of bits in one clock cycle, the second data link is kept sending 1 bits of a preset number of bits in one clock cycle, and the delay value of the IOdelay delay module corresponding to the first control link is adjusted so that the single-edge signal returned by the PE chip is acquired in a preset proportional clock cycle.

[0078] Specifically, using corresponding data selectors and waveform drivers, the DATA0 and RCV1 links transmit 8 bits of 0, the DATA1 link transmits 1, and the RCV0 link transmits a single rising edge from 0 to 1. After the RCV0 link transmits the single rising edge, it loops back to the serial receiver 122 through the PE chip 200 for acquisition. At this point, a rising edge will be acquired at a certain 1 / 8 cycle, which is assumed to be 11111110 (the first phase) in this embodiment. The delay value is adjusted using the IOdelay delay chain on the RCV0 link. To verify whether the edges are aligned, the RCV0 link transmits a single rising edge again. The serial receiver 122 acquires the first non-zero data 1 at a certain clock cycle position. The steps of adjusting the delay value using the IOdelay delay chain and transmitting a single rising edge are repeated until it is exactly at the second phase sampling edge, completing the edge alignment of the RCV0 link.

[0079] Step four, as Figure 12As shown, the second control link is selected to send a single-edge signal, while the first data link and the first control link send a preset number of 0 bits in one clock cycle, and the second data link sends a preset number of 1 bits in one clock cycle. The delay value of the IOdelay delay module corresponding to the second control link is adjusted so that the single-edge signal returned by the PE chip is acquired in a preset proportional clock cycle.

[0080] Specifically, using corresponding data selectors and waveform drivers, the DATA0 and RCV0 links transmit 8 bits of 0, the DATA1 link transmits 1, and the RCV1 link transmits a single rising edge from 0 to 1. After the RCV1 link transmits the single rising edge, it loops back to the serial receiver 122 through the PE chip 200 for acquisition. At this point, a rising edge will be acquired at a certain 1 / 8 cycle, which is assumed to be 11111110 (the first phase) in this embodiment. The delay value is adjusted using the IOdelay delay chain on the RCV1 link. To verify whether the edges are aligned, the RCV1 link transmits a single rising edge again. The serial receiver 122 acquires the first non-zero data 1 at a certain clock cycle position. The steps of adjusting the delay value using the IOdelay delay chain and transmitting a single rising edge are repeated until it is exactly at the second phase sampling edge, completing the edge alignment of the RCV1 link.

[0081] In one embodiment, step 114 includes: adjusting the time from the transmission of a single-edge signal to the acquisition of a single-edge signal returned by the PE chip using the fine delay module of each link, so that the single-edge signal is acquired in the same phase within the clock cycle, thereby completing the clock cycle alignment of the preset ratio.

[0082] The setting of the same phase is not unique; it can be the 7th phase (the last phase) within the clock cycle or other phases, depending on the specific situation. (Continue to refer to...) Figure 6 In this embodiment, the rising edge time of the four single-edge signals is adjusted by using a fine delay module to ensure that the rising edge is collected by the serial receiver 122 and is uniformly collected in the 7th phase, thus completing 1 / 8 cycle alignment.

[0083] After edge alignment is completed in step 112, the delay difference from transmission to reception of the rising edge of each link is N*1 / 8+M (clock cycles). It can be understood that the values ​​of N and M will vary depending on the actual sampling conditions. As in the example above, assuming that after edge alignment, serial receiver 122 samples at phase 5 when the DATA0 link transmits its rising edge, at phase 6 when the DATA1 link transmits its rising edge, and at phase 2 when the RCV0 and RCV1 links transmit their rising edges... Figure 13As shown. Using a fine delay module, all four links are adjusted so that the 7th phase is acquired, completing 1 / 8 cycle alignment. At this point, N... DATA0 =(7-5)=2, N DATA1 =1, N RCV0 =5, N RCV1 =5, such as Figure 14 As shown, the time difference between the data sent from the four links to the data being collected is a multiple of the whole cycle.

[0084] In one embodiment, step S120 includes: selecting the link with the longest delay time as a reference, adjusting the time from the transmission of a single-edge signal to the acquisition of the single-edge signal returned by the PE chip through the corresponding coarse delay module, and aligning the full clock cycles of each link.

[0085] Among them, the delay accuracy of the fine delay module is greater than that of the coarse delay module. (Continue to refer to...) Figure 6 By adjusting the rising edge time of the four links to be collected by the serial receiver 122, and based on the count value of the timer 124, the link with the maximum value is selected as the reference, and the coarse delay module is used to adjust to a uniform value to complete the whole cycle alignment.

[0086] Specifically, the four timers 124 in the comparison module 120 record the integer cycle time from the rising edge of the transmission to the receiving edge of the four links, with a resolution of 5ns. The link with the longest delay is selected as the baseline, and a coarse delay module is used to compensate for the other links. For example, if the transmission cycle of link DATA0 is 10, link DATA1 is 9, link RCV0 is 8, and link RCV1 is 7, then link DATA1 will be compensated for 1 cycle, link RCV0 for 2 cycles, and link RCV1 for 3 cycles, achieving integer cycle alignment. At this point, M... DATA0 =0, M DATA1 = 1, M RCV0 =2,M RCV1 =3.

[0087] Further, step S130 includes: selecting any one link as a reference link, and adjusting the delay of the corresponding link using the IOdelay delay module and the fine delay module to ensure that the remaining links achieve the phase relationship required by the PE chip. The delay accuracy of the IOdelay delay module is greater than that of the fine delay module. (Continue referring to...) Figure 6 The data phase of each link is adjusted using a fine delay module and an Iodelay delay chain to achieve the phase relationship required by the PE chip 200, thus completing the final calibration. The required phase relationship for the PE chip will vary depending on the application scenario.

[0088] The calibration method within the test machine channel provided in this application, based on the multiply-drive mode characteristics of the PE chip 200, designs a simple, efficient, and stable calibration signal transmission method. This proposal does not rely on test vector patterns to generate calibration signals; instead, it uses a single-edge signal as the calibration signal, making the calibration process simpler, and the single-edge signal is more stable, eliminating errors caused by signal reflection. This proposal does not require storing large amounts of data; it only retains the data from the last acquired rising edge, making it more efficient. Finally, this proposal does not require calculating the absolute delay of the path; it only needs to calculate the relative delay, take the longest path, and compensate for the delay difference to perform calibration.

[0089] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0090] In one embodiment, such as Figure 2 As shown, a chip testing machine is also provided, including a controller 100 and a PE chip 200. The controller 100 is connected to the PE chip 200 and is used for in-channel calibration according to the method described above. The controller 100 includes a driver module 110 and a comparison module 120. Each serial generator 112 in the driver module 110 is connected to the PE chip via a corresponding link, and the serial receiver 122 in the comparison module 120 is connected to the PE chip 200. The controller 100 can be an FPGA, MCU, CPU, or other device; in this embodiment, the controller 100 is an FPGA.

[0091] Furthermore, such as Figure 5 As shown, the serial generator 112 includes a data selector, a delay module, and a waveform driver. The data selector is connected to the host computer 300 and the delay module, and the waveform driver is connected to the delay module and, through a corresponding link, to the PE chip 200. The delay module includes an IOdelay delay module, a fine delay module, and a coarse delay module configured in series. The delay accuracy of the IOdelay delay module is greater than that of the fine delay module, and the delay accuracy of the fine delay module is greater than that of the coarse delay module.

[0092] It is understood that the specific embodiments of the chip tester described above have been explained in detail in the calibration method within the tester channel, and will not be repeated here.

[0093] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0094] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A calibration method within a test machine channel, characterized in that, include: Each link within the channel sends a single-edge signal to the PE chip, and the delay time of the corresponding link is determined based on the time it takes for the PE chip to return the single-edge signal; wherein, the PE chip performs an internal loopback after receiving the single-edge signal; The corresponding links are delayed according to their delay time, and each link is adjusted so that the time from sending a single-edge signal to receiving a single-edge signal returned by the PE chip is the same, so that the signals of each link are aligned in phase.

2. The method according to claim 1, characterized in that, The step of sending single-edge signals to the PE chip through each link within the channel, and determining the delay time of the corresponding link based on the time it takes for the PE chip to return the single-edge signal, includes: Single-edge signals are sent to the PE chip through each link, and the corresponding IOdelay delay module is used for adjustment so that the single-edge signal returned by the PE chip is received within a preset proportional clock cycle. The time from the transmission of a single-edge signal to the acquisition of the single-edge signal returned by the PE chip is adjusted using the fine delay module of each link. The preset proportional clock cycle of each link is aligned, and the delay time of the corresponding link is recorded. The delay accuracy of the IOdelay delay module is greater than that of the fine delay module.

3. The method according to claim 2, characterized in that, The preset number of bits for the single-edge signal of each link is the reciprocal of a preset ratio.

4. The method according to claim 2, characterized in that, The step of sending single-edge signals to the PE chip through each link and adjusting the delay using the corresponding IOdelay module to ensure that the single-edge signal returned by the PE chip is received within a preset proportional clock cycle includes: Select one link to send a single-edge signal, while keeping the other links sending a preset number of bits of data in one clock cycle. Adjust the delay value of the IOdelay module corresponding to the link sending the single-edge signal so that the single-edge signal returned by the PE chip is acquired in a preset proportional clock cycle.

5. The method according to claim 4, characterized in that, The links include a first data link, a second data link, a first control link, and a second control link.

6. The method according to claim 5, characterized in that, The step of selecting one link to send a single-edge signal while keeping the other links sending a preset number of bits of data within one clock cycle, and adjusting the delay value of the IOdelay module corresponding to the link sending the single-edge signal, so that the single-edge signal returned by the PE chip is acquired within a preset proportional clock cycle, includes: Select the first data link to send a single-edge signal, keep the other links sending 0 bits of a preset number of bits in one clock cycle, and adjust the delay value of the IOdelay delay module corresponding to the first data link so that the single-edge signal returned by the PE chip is acquired in a preset proportional clock cycle. Select the second data link to send a single-edge signal, keep the first data link and the second control link sending 0 bits of a preset number of bits in one clock cycle, keep the first control link sending 1 bits of a preset number of bits in one clock cycle, and adjust the delay value of the IOdelay delay module corresponding to the second data link so that the single-edge signal returned by the PE chip is acquired in a preset proportional clock cycle. Select the first control link to send a single-edge signal, keep the first data link and the second control link sending a preset number of 0 bits in one clock cycle, keep the second data link sending a preset number of 1 bits in one clock cycle, and adjust the delay value of the IOdelay delay module corresponding to the first control link so that the single-edge signal returned by the PE chip is acquired in a preset proportional clock cycle. Select the second control link to send a single-edge signal, keep the first data link and the first control link sending a preset number of 0 bits in one clock cycle, keep the second data link sending a preset number of 1 bits in one clock cycle, and adjust the delay value of the IOdelay delay module corresponding to the second control link so that the single-edge signal returned by the PE chip is acquired in a preset proportional clock cycle.

7. The method according to claim 2, characterized in that, The step of adjusting the time from the transmission of a single-edge signal to the receipt of the single-edge signal from the PE chip using the fine delay module of each link, and aligning the preset proportional clock cycle of each link, includes: The timing of each link's single-edge signal transmission and the acquisition of the single-edge signal returned by the PE chip are adjusted using the fine delay module of each link, so that the single-edge signal is acquired in the same phase within the clock cycle, thus completing the preset ratio clock cycle alignment.

8. The method according to claim 2, characterized in that, The step of delaying the corresponding links according to their delay times, and adjusting each link to have the same time from sending a single-edge signal to receiving a single-edge signal returned by the PE chip, includes: The link with the longest delay time is selected as the benchmark. The time from the transmission of the single-edge signal to the acquisition of the single-edge signal returned by the PE chip is adjusted by the corresponding coarse delay module to align the full clock cycles of each link. The delay accuracy of the fine delay module is greater than that of the coarse delay module.

9. The method according to any one of claims 1 to 8, characterized in that, The step of delaying the corresponding links according to their respective delay times, adjusting each link to have the same time from sending a single-edge signal to receiving a single-edge signal returned by the PE chip, so as to align the signals of each link in phase, further includes: Delay compensation is performed on other links based on the reference link in the aforementioned links, so that the phase between each link reaches the preset condition.

10. The method according to claim 9, characterized in that, The delay compensation for other links based on the reference link in the link, so that the phase between the links reaches a preset condition, includes: Choose any link as the reference link, and use the IOdelay delay module and the fine delay module to adjust the delay of the corresponding link so that the remaining links achieve the phase relationship required by the PE chip; wherein, the delay accuracy of the IOdelay delay module is greater than the delay accuracy of the fine delay module.

11. A chip testing machine, characterized in that, It includes a controller and a PE chip, the controller being connected to the PE chip, for performing in-channel calibration according to any one of claims 1 to 10.

12. The chip testing machine according to claim 11, characterized in that, The controller includes a driver module and a comparison module. Each serial generator in the driver module is connected to the PE chip through a corresponding link, and the serial receiver in the comparison module is connected to the PE chip.

13. The chip testing machine according to claim 12, characterized in that, The serial generator includes a data selector, a delay module, and a waveform driver. The data selector is connected to the host computer and the delay module, the waveform driver is connected to the delay module, and is connected to the PE chip through a corresponding link. The delay module includes an IOdelay delay module, a fine delay module, and a coarse delay module arranged in series. The delay accuracy of the IOdelay delay module is greater than that of the fine delay module, and the delay accuracy of the fine delay module is greater than that of the coarse delay module.

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