Super junction structure, preparation method and super junction device

Abstract

This application provides a superjunction structure, a fabrication method, and a superjunction device. The fabrication method includes: providing a substrate, with a first epitaxial layer of a first conductivity type formed on one side of the substrate; etching the first epitaxial layer to form a plurality of deep trenches, the designed width of the deep trenches being w1; forming a second epitaxial layer of a second conductivity type on the surfaces of the first epitaxial layer and the deep trenches, the thickness of the second epitaxial layer being less than w1 / 2-0.25 μm, so as to form an in-trench gap between the second epitaxial layers covering the sidewalls of the deep trenches, and the width of the in-trench gap being greater than 0.5 μm; filling the in-trench gap inside the deep trenches; and performing a planarization process to remove the second epitaxial layer on the surface of the first epitaxial layer. The superjunction structure of this application has lower sensitivity to changes in the width of the deep trenches, and even if the width of the deep trenches is increased, the breakdown voltage remains within a controllable range.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a superjunction structure, its fabrication method, and a superjunction device. Background Technology

[0002] The superjunction structure is a core innovative structure for high-voltage power semiconductor devices. Its core design involves alternating and vertically arranging P-type semiconductor pillars (P pillars) and N-type semiconductor pillars (N pillars) in the device's drift region, achieving the dual advantages of high voltage withstand and low on-resistance through a charge balance mechanism.

[0003] Taking the trench superjunction MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) as an example, the trench superjunction MOSFET is an advanced power semiconductor device. By alternating high-density P-type and N-type semiconductor pillars inside the device, it solves the inherent contradiction between on-resistance and breakdown voltage in traditional MOSFETs. The on-resistance of the MOSFET, which was proportional to the 2.5th power of the rated voltage, is rewritten as being proportional to the 1.32nd power of the rated voltage. Compared with traditional planar MOSFETs, the on-resistance of trench superjunction MOSFETs can be reduced by 30%-50% at high voltage (600-900V). Therefore, it is widely used in high-efficiency power conversion fields, including servers, electric vehicle charging piles, photovoltaic inverters, and industrial motor drives.

[0004] Because superjunction MOSFETs optimize the electric field distribution through a charge balance mechanism, the total doping amount of the P-type and N-type regions must be equal. Therefore, strict requirements are placed on deep trench etching and epitaxy. An imbalance in the total doping amount of the P-type and N-type regions will lead to a decrease in the device's breakdown voltage. In existing superjunction structure manufacturing processes, it is difficult to precisely control the total doping amount of the P-type and N-type regions, making precise control of the breakdown voltage difficult. Furthermore, it is highly sensitive to changes in the width of the deep trench; as the trench width increases, the doping amount of the P-type region changes accordingly, causing the charge balance to be disrupted and resulting in a significant drop in breakdown voltage. Summary of the Invention

[0005] To address the problems in the prior art, the purpose of this application is to provide a superjunction structure, a fabrication method, and a superjunction device. The resulting superjunction structure is less sensitive to changes in the width of the deep trench, and even if the width of the deep trench is increased, the breakdown voltage remains within a controllable range.

[0006] The first aspect of this application provides a method for preparing a superjunction structure, comprising the following steps: A substrate is provided, wherein a first epitaxial layer of a first conductivity type is formed on one side of the substrate; Multiple deep trenches are formed by etching the first epitaxial layer, and the designed width of the deep trenches is w1; A second epitaxial layer of a second conductivity type is formed on the surface of the first epitaxial layer and the deep trench. The thickness of the second epitaxial layer is less than w1 / 2-0.25μm, so that an in-trench gap is formed between the second epitaxial layers covering the two sidewalls of the deep trench, and the width of the in-trench gap is greater than 0.5μm. Fill the gaps inside the deep trench; A planarization process is performed to remove the second epitaxial layer from the surface of the first epitaxial layer.

[0007] In some embodiments, the doping concentration of the second epitaxial layer is P, the thickness is t, and the product of P and t is a constant value.

[0008] In some embodiments, the width of the first epitaxial layer between two adjacent deep trenches is w2, and the constant value is equal to the product of the doping concentration of the first epitaxial layer and w2 / 2.

[0009] In some embodiments, filling the gaps within the deep trench includes: Use undoped silicon epitaxial layers or doping concentrations less than 1e14cm -3 The doped layer fills the gaps inside the deep trench, and the doped layer is a first conductivity type doped layer or a second conductivity type doped layer.

[0010] In some embodiments, filling the gaps within the deep trench includes: An oxide layer is used to fill the gaps inside the deep trench.

[0011] In some embodiments, the bottom of the oxide layer is lower than the surface of the first epitaxial layer, and the distance between the bottom of the oxide layer and the surface of the first epitaxial layer is greater than 3 μm.

[0012] In some embodiments, when performing planarization and removing the second epitaxial layer on the surface of the first epitaxial layer, the oxide layer on the surface of the first epitaxial layer is removed.

[0013] A second aspect of this application provides a superjunction structure, comprising: Substrate; A first epitaxial layer of a first conductivity type, wherein a plurality of deep trenches are formed in the first epitaxial layer, and the design width of the deep trenches is w1; A second epitaxial layer covers the surface of the deep trench, and the thickness of the second epitaxial layer is less than w1 / 2-0.25μm, so that an in-trench gap is formed between the second epitaxial layers covering the two sidewalls of the deep trench, and the width of the in-trench gap is greater than 0.5μm. A filling layer is used to fill the gaps within the deep trenches.

[0014] A third aspect of this application provides a superjunction device, including the superjunction structure of the second aspect.

[0015] In some embodiments, the superjunction device further includes: The gate-source structure is located on the surface of the first epitaxial layer; The first metal layer is located on the side of the gate-source structure opposite to the first epitaxial layer; The second metal layer is located on the side of the substrate opposite to the first epitaxial layer.

[0016] The superjunction structure, fabrication method, and superjunction device provided in this application have the following advantages: By adopting the technical solution of this application, when filling the deep trench in the first epitaxial layer, a second epitaxial layer is first formed, and the thickness of the second epitaxial layer is controlled to be less than w1 / 2-0.25μm, so that a trench gap is formed between the second epitaxial layers covering the two side walls of the deep trench, and the width of the trench gap is greater than 0.5μm. Then the trench gap is filled. By controlling the thickness of the second epitaxial layer and the doping concentration of the second epitaxial layer, the charge balance of the P-type region and the N-type region can be precisely controlled. Furthermore, by reserving the trench gap and filling it, the width of the deep trench is allowed to fluctuate to a certain extent, and the sensitivity to the width change of the deep trench is lower. Even if the width of the deep trench is increased, the breakdown voltage is still within a controllable range. Attached Figure Description

[0017] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

[0018] Figure 1 This is a flowchart of a method for preparing a superjunction structure according to an embodiment of this application; Figure 2 This is a schematic diagram showing the formation of a deep trench in the first epitaxial layer during the fabrication process of a superjunction structure according to an embodiment of this application; Figure 3 This is a schematic diagram showing the formation of the second epitaxial layer during the fabrication process of a superjunction structure according to an embodiment of this application; Figure 4 This is a schematic diagram showing the process of filling the gaps in the trench with a silicon epitaxial layer or doped layer during the fabrication of a superjunction structure according to an embodiment of this application. Figure 5 This is a schematic diagram of the superjunction structure obtained after planarization treatment during the preparation process of a superjunction structure according to an embodiment of this application; Figure 6 This is a schematic diagram of the structure of a superjunction device according to an embodiment of this application; Figure 7 yes Figure 6 Enlarged view of the cell region in the image; Figure 8 This is a schematic diagram showing the process of filling the gaps in the trench with an oxide layer during the fabrication of a superjunction structure according to another embodiment of this application; Figure 9 This is a schematic diagram of the structure of a superjunction device according to another embodiment of this application; Figure 10 This is a comparison of the breakdown voltage curves of the superjunction device of this application and conventional superjunction devices. Detailed Implementation

[0019] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this application will be comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore repeated descriptions of them will be omitted. Although the terms “upper,” “lower,” “between,” etc., may be used in this specification to describe different exemplary features and elements of this application, these terms are used herein only for convenience, such as the orientation of the examples described in the accompanying drawings. Nothing in this specification should be construed as requiring a specific three-dimensional orientation of the structure to fall within the scope of this application. Although “first” or “second,” etc., are used in this specification to denote certain features, they are merely indicative of function and not as a limitation on the number or importance of specific features.

[0020] like Figure 1 As shown in the embodiments of this application, a method for preparing a superjunction structure is provided, comprising the following steps: S100: A substrate is provided, wherein a first epitaxial layer of a first conductivity type is formed on one side of the substrate; In this embodiment, the substrate is doped with a first conductivity type, and a first epitaxial layer of the first conductivity type is formed on the substrate by epitaxial growth. The doping concentration of the first epitaxial layer is, for example, 1e15-1e16 cm⁻¹. -3 Specifically, the doping concentration and thickness of the first epitaxial layer are determined based on the voltage withstand requirements of the superjunction device. S200: The first epitaxial layer is etched to form a plurality of deep trenches, the design width of which is w1; In this embodiment, deep trenches are etched based on a hard mask layer (such as an ONO layer composed of oxide, nitride, and oxide layers). The size of the deep trenches can be determined according to design requirements. Optionally, the angle of the deep trenches is 88-90°, the design width of the deep trenches is 2-4μm, the spacing between the deep trenches is 3-5μm, and the depth is 35μm-100μm. For example, for a 650V voltage-level superjunction MOSFET device, the design width of the deep trenches is 2-4μm, the spacing between the deep trenches is 3-5μm, and the depth is 42μm-45μm. S300: A second epitaxial layer of a second conductivity type is formed on the surface of the first epitaxial layer and the deep trench, the thickness of the second epitaxial layer being less than w1 / 2-0.25μm, so that an in-trench gap is formed between the second epitaxial layers covering the two sidewalls of the deep trench, and the width of the in-trench gap is greater than 0.5μm. In this embodiment, before forming the second epitaxial layer, a sacrificial oxygen deep trench repair with a thickness of 300 Å - 800 Å is also performed; In this embodiment, the formed second epitaxial layer covers the surface of the first epitaxial layer, the two sidewalls of the deep trench, and the bottom surface. Since the thickness of the second epitaxial layer is less than w1 / 2-0.25μm, there are still gaps in the trench between the two sidewalls of the deep trench that are not covered and filled by the second epitaxial layer, and the width of the gaps in the trench is greater than 0.5μm. For example, if the designed width of the deep trench is 4μm, then the thickness of the epitaxial layer is less than 1.75μm, preferably less than or equal to 1.5μm, so as to leave enough space for the gaps in the trench. S400: Fill the gaps inside the deep trench; S500: Perform planarization processing to remove the second epitaxial layer from the surface of the first epitaxial layer; In this process, planarization is performed to remove the portion of the second epitaxial layer covering the surface of the first epitaxial layer until the surface of the first epitaxial layer is exposed.

[0021] By adopting the technical solution of this application, when filling the deep trench in the first epitaxial layer, a second epitaxial layer is first formed, and the thickness of the second epitaxial layer is controlled to be less than w1 / 2-0.25μm, so that a trench gap is formed between the second epitaxial layers covering the two side walls of the deep trench, and the width of the trench gap is greater than 0.5μm. Then the trench gap is filled. By controlling the thickness of the second epitaxial layer and the doping concentration of the second epitaxial layer, the charge balance of the P-type region and the N-type region can be precisely controlled. Furthermore, by reserving the trench gap and filling it, the width of the deep trench is allowed to fluctuate to a certain extent, and the sensitivity to the width change of the deep trench is lower. Even if the width of the deep trench is increased, the breakdown voltage is still within a controllable range.

[0022] The superjunction structure fabricated using the method described in this application is a partial structure in superjunction devices. These superjunction devices include, for example, trench-gate deep trench superjunction MOSFETs, planar-gate deep trench superjunction MOSFETs, deep trench superjunction diodes, and deep trench superjunction insulated-gate transistors. The following description uses the semiconductor structure within a trench-gate deep trench superjunction MOSFET as an example to illustrate the specific implementation of this application.

[0023] In this embodiment, the doping concentration of the second epitaxial layer is P, the thickness is t, and the product of P and t is a constant value. The width of the first epitaxial layer between two adjacent deep trenches is w2, and the constant value is equal to the product of the doping concentration of the first epitaxial layer and w2 / 2. Here, the width w2 of the first epitaxial layer is the designed width of the first epitaxial layer. By making the constant value equal to the product of the doping concentration of the first epitaxial layer and w2 / 2, regardless of changes in the thickness of the second epitaxial layer, the product P of the doping concentration P and the thickness t can always be achieved. t is equal to the product of the doping concentration P' of the first epitaxial layer and w² / 2. w² / 2, i.e., P t=P' w² / 2 allows for charge balance between the first and second epitaxial layers, i.e., charge balance between the P-pillars and N-pillars. The thickness of the second epitaxial layer can be varied as needed, but the charge balance between P-pillars and N-pillars must be maintained. t is a constant value. For example, when the thickness of the second epitaxial layer is t1, the doping concentration is P1; when the thickness of the second epitaxial layer is t2, the doping concentration is P2. Then t1 P1=t2 P2.

[0024] In this embodiment, the first conductivity type and the second conductivity type are different conductivity types. For example, the first conductivity type is N-type and the second conductivity type is P-type; or, the first conductivity type is P-type and the second conductivity type is N-type.

[0025] In one embodiment, step S400, filling the gaps within the deep trench, includes: Use undoped silicon epitaxial layers or silicon doping concentration less than 1e14cm -3 A weakly doped layer is used to fill the gaps within the deep trenches until the gaps are completely filled. The doped layer can be either a first conductivity type doped layer or a second conductivity type doped layer. For example, a doping concentration of less than 1e14cm⁻¹ is used. -3 The effect of the P-type or N-type silicon doped layer on charge balance can be ignored because the doping concentration is much lower than that of the second epitaxial layer.

[0026] In this embodiment, when filling the gaps in the trench in step S400, the formed silicon epitaxial layer or weakly doped layer not only fills the gaps in the trench but also covers the upper surface of the second epitaxial layer. Therefore, in step S500, when performing planarization and removing the second epitaxial layer from the surface of the first epitaxial layer, the silicon epitaxial layer or weakly doped layer covering the upper surface of the second epitaxial layer is also removed.

[0027] In another embodiment, step S400, filling the gaps inside the deep trench, includes: An oxide layer is used to fill the gaps inside the deep trench.

[0028] Optionally, the oxide layer may be, for example, a silicon dioxide layer. The silicon dioxide layer may or may not completely fill the gaps in the trench, but it must satisfy the following conditions: the bottom of the oxide layer is lower than the surface of the first epitaxial layer, and the distance between the bottom of the oxide layer and the surface of the first epitaxial layer is greater than 3 μm. The bottom depth of the oxide layer corresponds to the sealing depth of the oxide layer, ensuring that the oxide layer can still seal the gaps in the trench after planarization.

[0029] In this embodiment, when filling the gaps in the trench in step S400, the oxide layer not only fills the gaps in the trench but also covers the upper surface of the second epitaxial layer. Therefore, in step S500, when performing planarization and removing the second epitaxial layer from the surface of the first epitaxial layer, the oxide layer on the surface of the first epitaxial layer is also removed simultaneously, that is, the oxide layer covering the upper surface of the second epitaxial layer is removed simultaneously.

[0030] The following is combined Figures 2-5 The specific implementation process of the preparation method of the superjunction structure in one embodiment is described in detail. Figures 2-5 The images show cross-sectional morphology of the superjunction structure at different stages of its fabrication. The following example uses N-type as the first conductivity type and P-type as the second conductivity type. However, it is understood that the methods and processes described below can also be used when the first conductivity type is P-type and the second conductivity type is N-type.

[0031] Figure 2 This is a schematic diagram showing the formation of a deep trench in the first epitaxial layer during the fabrication process of a superjunction structure according to an embodiment of this application. Figure 2 As shown, corresponding to S100, an N-type doped substrate 100 is provided, and an N-type first epitaxial layer 200 is formed on one side of the substrate 100. In this embodiment, the doping concentration of the first epitaxial layer is, for example, 1e15-1e16 cm⁻¹. -3Specifically, the doping concentration and thickness of the first epitaxial layer 200 are determined according to the voltage withstand requirements of the superjunction device. Corresponding to step S200, the first epitaxial layer 200 is etched to form a plurality of deep trenches 201, the design width of which is w1.

[0032] In this embodiment, deep trenches are etched based on the hard mask layer 300. The size of the deep trenches can be determined according to design requirements. Optionally, the angle of the deep trenches is 88-90°, the design width of the deep trenches is 2μm-4μm, the spacing of the deep trenches is 3μm-5μm, and the depth is 35μm-100μm. For example, for a 650V voltage level superjunction MOSFET device, the design width of the deep trenches is 2μm-4μm, the spacing of the deep trenches is 3μm-5μm, and the depth is 42μm-45μm.

[0033] Figure 3 This is a schematic diagram showing the formation of the second epitaxial layer during the fabrication process of a superjunction structure according to an embodiment of this application. Figure 3 As shown, after etching to form deep trenches, sacrificial oxygen deep trench repair with a thickness of 300 Å - 800 Å is used. Corresponding to step S300, a P-type second epitaxial layer 400 is formed on the surface of the first epitaxial layer 200 and the deep trench. The thickness of the second epitaxial layer 400 is less than w1 / 2 - 0.25 μm, so that an in-trench gap 202 is formed between the second epitaxial layer 400 covering the two sidewalls of the deep trench, and the width of the in-trench gap 202 is greater than 0.5 μm. In this embodiment, height and depth refer to the dimensions along the Y-axis direction, and width refers to the dimensions along the X-axis direction. Let the thickness of the second epitaxial layer 400 be t, then as... Figure 3 As shown, the width of the gap within the groove is w1-2. t; In this embodiment, the formed second epitaxial layer 400 covers the surface of the first epitaxial layer 200, the two sidewalls of the deep trench, and the bottom surface. Since the thickness of the second epitaxial layer 400 is less than w1 / 2-0.25μm, there are still trench gaps 202 between the two sidewalls of the deep trench that are not covered and filled by the second epitaxial layer 400, and the width of these trench gaps 202 is greater than 0.5μm. For example, if the designed width of the deep trench is 4μm, then the thickness of the epitaxial layer is less than 1.75μm, preferably less than or equal to 1.5μm, to leave sufficient space for the trench gaps. The second epitaxial layer 400 filling the deep trench forms P-pillars, and the first epitaxial layer 200 separated by the deep trench forms N-pillars. Multiple P-pillars form P-type regions, and multiple N-pillars form N-type regions. The doping concentration of the second epitaxial layer 400 is P, and its thickness is t, and the product of P and t is a constant value. The width of the first epitaxial layer between two adjacent deep trenches (i.e., the spacing between the deep trenches) is w2, and the constant value is equal to the product of the doping concentration of the first epitaxial layer and w2 / 2, thereby achieving charge balance between the P-type and N-type regions.

[0034] Figure 4 This is a schematic diagram illustrating the fabrication process of a superjunction structure according to an embodiment of this application, after filling the gaps within the trenches with a silicon epitaxial layer or doped layer. Figure 4 As shown, corresponding to step S400, an undoped silicon epitaxial layer is formed by epitaxy or a silicon doping concentration of less than 1e14cm is used. -3 A P-type or N-type silicon doped layer fills the trench gaps inside the deep trench. Here, 510 is used to denote the filling layer structure that fills the trench gaps.

[0035] Figure 5 This is a schematic diagram of the superjunction structure obtained after planarization treatment during the fabrication process of a superjunction structure according to an embodiment of this application. Corresponding to step S500, a CMP (Chemical Mechanical Polishing) process is used for planarization treatment, removing portions of the second epitaxial layer, silicon filling layer (epitaxy layer or doped layer), and hard mask layer covering the surface of the first epitaxial layer until the surface of the first epitaxial layer is exposed, resulting in the superjunction structure shown below. Figure 5 The superjunction structure shown.

[0036] like Figure 5 As shown in the embodiments of this application, a superjunction structure is also provided, comprising: Substrate 100; the substrate 100 is a silicon substrate doped with a first conductivity type; A first epitaxial layer 200 of a first conductivity type, wherein a plurality of deep trenches are formed in the first epitaxial layer 200, and the design width of the deep trenches is w1; A second epitaxial layer 400 covers the surface of the deep trench, and the thickness of the second epitaxial layer 400 is less than w1 / 2-0.25μm, so that an in-trench gap is formed between the second epitaxial layers 400 covering the two side walls of the deep trench, and the width of the in-trench gap is greater than 0.5μm. The filling layer 510 fills the gaps within the grooves of the deep trench.

[0037] By adopting the superjunction structure of this application, the second epitaxial layer fills the deep trench, and a filling layer is also formed inside the second epitaxial layer. The filling layer is used to fill the gaps in the trench. The thickness of the second epitaxial layer is less than w1 / 2-0.25μm, so that the width of the filling layer is greater than 0.5μm. By controlling the thickness of the second epitaxial layer, combined with the control of the doping concentration of the second epitaxial layer, the charge balance of the P-type region and the N-type region can be precisely controlled. Furthermore, by filling the gaps in the reserved trench with undoped / low-doped silicon or oxide layers, the impact of the width fluctuation of the deep trench within or between wafers caused by the manufacturing process on the breakdown voltage is reduced, and the breakdown voltage is maintained within a controllable range of 10%, thereby increasing the process window and improving the device yield.

[0038] Figure 6 This is a schematic diagram of the structure of a superjunction device according to an embodiment of this application. Figure 6 As shown in the figure, this application embodiment also provides a superjunction device, including the superjunction structure described above. In this embodiment, the superjunction device further includes: a gate-source structure 600 located on the surface of the first epitaxial layer 200; a first metal layer 700 located on the side of the gate-source structure 600 opposite to the first epitaxial layer 200; and a second metal layer 800 located on the side of the substrate 100 opposite to the first epitaxial layer 200. Figure 7 yes Figure 6 A magnified view of the cell region in the image. (See image for example.) Figure 7 As shown, in this embodiment, the gate-source structure 600 includes an interlayer dielectric (ILD) layer 610, a source region 620, a P+ region 630, a body region 640, polysilicon 650, and a gate oxide layer 660. This superjunction device includes the aforementioned superjunction structure; therefore, it possesses the technical effects of the aforementioned superjunction structure, which will not be elaborated upon here.

[0039] In this embodiment, the fabrication method of the superjunction device includes the following steps: The superjunction structure was prepared using the above-described method. The gate trench is etched using conventional processes, with a width of, for example, 0.4-1.2 μm and a depth of, for example, 1-2 μm; then gate oxide growth and gate polysilicon filling and etching are performed to form polysilicon 650 and gate oxide layer 660. Injection and propulsion into the body region are carried out to form a body region of 640. Source region injection and activation are performed to form source region 620, and then interlayer medium deposition is performed to form interlayer medium layer 610; Contact holes are formed by etching and then implanted. The depth of the contact holes is, for example, 0.3-0.5 μm, and the width of the contact holes is 1-3 μm larger than the width of the deep trench. The implantation energy of the contact holes is 40-100 keV, and the dose is 5e13-5e15 cm⁻¹. -3 The contact hole is injected 1-3 times to form the P+ region. Annealing is performed, followed by deposition of the first metal layer 700 on the front side; The entire structure (wafer) is flipped over, the back side of the wafer is thinned, and then a second metal layer 800 is deposited on the back side to obtain... Figure 6 and Figure 7 The superjunction device is shown.

[0040] Figure 8 and Figure 9 This is a schematic diagram of a superknot structure according to another embodiment of this application. The difference between this embodiment and the previous embodiment is that the filling layer used to fill the gaps in the trenches in step S400 is different. For example... Figure 8 As shown, in this embodiment, corresponding to step S400, a silicon dioxide layer 520 is used to fill the gaps inside the deep trench. Corresponding to step S500, a planarization process is performed. When removing the second epitaxial layer 400 on the surface of the first epitaxial layer 200, the silicon dioxide layer on the surface of the first epitaxial layer 200 is also removed, that is, the silicon dioxide layer covering the upper surface of the second epitaxial layer 400 is removed simultaneously. Figure 9 A schematic diagram of a superjunction device using a silicon dioxide layer as the oxide layer is shown. The silicon dioxide layer 520 may or may not completely fill the gaps in the trench, but it must satisfy the following conditions: the bottom of the silicon dioxide layer 520 is lower than the surface of the first epitaxial layer 200, and the distance between the bottom of the silicon dioxide layer 520 and the surface of the first epitaxial layer 200 is greater than 3 μm. The bottom depth of the silicon dioxide layer 520 corresponds to the sealing depth of the silicon dioxide layer 520, ensuring that the silicon dioxide layer 520 can still seal the gaps in the trench after planarization.

[0041] Figure 10 This is a comparison of the breakdown voltage curves of the superjunction device of this application and a conventional superjunction device. The horizontal axis represents Vds / V, indicating the drain-source voltage of the device (in volts); the vertical axis represents Ids / A, indicating the drain-source current of the device (in amperes). By testing the drain-source current (Ids) at different drain-source voltages (Vds), the breakdown voltage of the device (i.e., the Vds value corresponding to when Ids begins to rise sharply) is determined. Figure 10As shown, taking a superjunction MOSFET as an example, the breakdown voltage of the superjunction device in this application is significantly less sensitive to changes in the deep trench width than that of the superjunction device with existing structure. When the deep trench width increases by 0.3μm, the breakdown voltage decreases by only 6%, which can still be controlled within 10%, while the breakdown voltage of the superjunction device with existing structure decreases by 12%, which is beyond the controllable range.

[0042] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications or substitutions should be considered within the scope of protection of this application.

Claims

1. A method for preparing a superjunction structure, characterized in that, include: A substrate is provided, wherein a first epitaxial layer of a first conductivity type is formed on one side of the substrate; Multiple deep trenches are formed by etching the first epitaxial layer, and the designed width of the deep trenches is w1; A second epitaxial layer of a second conductivity type is formed on the surface of the first epitaxial layer and the deep trench. The thickness of the second epitaxial layer is less than w1 / 2-0.25μm, so that an in-trench gap is formed between the second epitaxial layers covering the two sidewalls of the deep trench, and the width of the in-trench gap is greater than 0.5μm. Fill the gaps inside the deep trench; A planarization process is performed to remove the second epitaxial layer from the surface of the first epitaxial layer.

2. The method for preparing the superjunction structure according to claim 1, characterized in that, The second epitaxial layer has a doping concentration of P and a thickness of t, and the product of P and t is a constant value.

3. The method for preparing the superjunction structure according to claim 2, characterized in that, The width of the first epitaxial layer between two adjacent deep trenches is w2, and the constant value is equal to the product of the doping concentration of the first epitaxial layer and w2 / 2.

4. The method for preparing the superjunction structure according to claim 1, characterized in that, Filling the gaps within the deep trench includes: Use undoped silicon epitaxial layers or doping concentrations less than 1e14cm -3 The doped layer fills the gaps inside the deep trench, and the doped layer is a first conductivity type doped layer or a second conductivity type doped layer.

5. The method for preparing the superjunction structure according to claim 1, characterized in that, Filling the gaps within the deep trench includes: An oxide layer is used to fill the gaps inside the deep trench.

6. The method for preparing the superjunction structure according to claim 5, characterized in that, The bottom of the oxide layer is lower than the surface of the first epitaxial layer, and the distance between the bottom of the oxide layer and the surface of the first epitaxial layer is greater than 3 μm.

7. The method for preparing the superjunction structure according to claim 5, characterized in that, When performing planarization and removing the second epitaxial layer on the surface of the first epitaxial layer, the oxide layer on the surface of the first epitaxial layer is also removed.

8. A superjunction structure, characterized in that, include: Substrate; A first epitaxial layer of a first conductivity type, wherein a plurality of deep trenches are formed in the first epitaxial layer, and the design width of the deep trenches is w1; A second epitaxial layer covers the surface of the deep trench, and the thickness of the second epitaxial layer is less than w1 / 2-0.25μm, so that an in-trench gap is formed between the second epitaxial layers covering the two sidewalls of the deep trench, and the width of the in-trench gap is greater than 0.5μm. A filling layer is used to fill the gaps within the deep trenches.

9. A superjunction device, characterized in that, Including the superjunction structure as described in claim 8.

10. The superjunction device according to claim 9, characterized in that, Also includes: The gate-source structure is located on the surface of the first epitaxial layer; The first metal layer is located on the side of the gate-source structure opposite to the first epitaxial layer; The second metal layer is located on the side of the substrate opposite to the first epitaxial layer.

Images