Double-sided SMT (Surface Mount Technology) substrate laminated structure and manufacturing method

Abstract

The invention discloses a double-sided SMT substrate laminated packaging structure and a manufacturing method. The double-sided SMT substrate laminated packaging structure comprises a first substrate; a second substrate; the first chip is mounted on the upper surface of the first substrate; the at least one copper column is electrically connected with the first chip, and the upper surface of the at least one copper column is higher than the upper surface of the first chip; and the first plastic package body is used for carrying out plastic package on the upper surface of the first substrate, the first chip and the at least one copper column, and the upper surface of the first plastic package body is flush with the upper surface of the at least one copper column after being ground. According to the invention, the copper columns are arranged on the first substrate, so that the solder balls are prevented from collapsing, the manufacturing cost is reduced, and the double-sided SMT substrate laminated structure is realized through the routing process. Longitudinal three-dimensional arrangement is adopted, signal transmission between the two substrates is linked through simple bonding of the copper columns and the gold wires, the adopted technology is a conventional packaging process, the method can be achieved without a complex technology, and cost is saved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, particularly to the field of packaging structure research and development technology, specifically to a double-sided SMT substrate stack structure and manufacturing method. Background Technology

[0002] In traditional SMT surface mount technology, solder paste collapse refers to the phenomenon where solder paste, after printing or during reflow soldering, expands and collapses beyond a predetermined range due to abnormal fluidity. This manifests as solder paste pattern deformation, solder paste bridging between adjacent pads, or solder paste covering non-soldered areas. The main causes include: poor thixotropic properties of the solder paste itself, leading to easy flow when stationary; excessively low metal content and excessively high flux ratio; improper printing parameters, such as excessive squeegee pressure, excessively large stencil apertures, or uneven wall thickness; and unreasonable reflow soldering temperature settings, such as excessively rapid temperature rise during preheating, causing premature and excessive flux evaporation, thus damaging the solder paste's shape. Solder paste collapse has significant negative impacts on circuit boards: a dramatically increased risk of short circuits: solder paste bridging between adjacent pads due to collapse forms solder bridges after reflow soldering, causing short circuits, directly leading to component failure, or even chip burnout. Deterioration in soldering quality: Collapse causes uneven solder paste thickness, insufficient solder in some solder joints, which easily leads to cold solder joints and reduces the mechanical strength and electrical connection stability of the solder joints, affecting the service life of the circuit board.

[0003] Currently, some package-on-package (BOP) structures utilize copper core balls in the middle of the substrate to achieve soldering and support between the substrates. Because there are devices and chips between the substrates, the solder balls will collapse during the reflow soldering process of ordinary solder balls, resulting in poor soldering. This method is currently the mainstream method, but the manufacturing cost is higher. It is currently used for high value-added products, and the cost is too high for low value-added conventional consumer electronics. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of existing technologies and provide a double-sided SMT substrate stack-up structure and manufacturing method. This invention is applicable to solving the problem of solder ball collapse and high manufacturing costs in semiconductor packaging.

[0005] To achieve the above objectives, the first technical solution adopted by the present invention is: a double-sided SMT substrate stacked packaging structure, comprising: a first substrate; a second substrate; a first chip, which is mounted on the upper surface of the first substrate; at least one copper pillar, which is electrically connected to the first chip, and the upper surface of the at least one copper pillar is higher than the upper surface of the first chip; a first molding compound, which molds the upper surface of the first substrate, the first chip and the at least one copper pillar, and the upper surface of the first molding compound is ground to be flush with the upper surface of the at least one copper pillar; Optionally, the lower surface of the copper pillar is connected to the pins on the first substrate.

[0006] Optionally, the horizontal distance between the copper pillar and the second substrate is not less than a first predetermined distance.

[0007] Optionally, the upper surface of the copper pillar is connected to the pins on the upper surface of the second substrate via gold wire bonding.

[0008] Optionally, it further includes: a second chip, which is mounted on the lower surface of the second substrate, and the spacing between the second chip and the first chip is not less than a second predetermined distance.

[0009] Optionally, it further includes: a second molding compound that molds the lower surface of the second substrate and the second chip.

[0010] Optionally, it further includes: a fixing adhesive disposed between the first molding compound and the second molding compound to fix the second molding compound and the first molding compound together.

[0011] Optionally, it further includes: a third chip mounted on the upper surface of the second substrate; and a third molding compound that molds the space between the upper surface of the second substrate, the third chip, the first molding compound, and the second molding compound.

[0012] The second technical solution adopted in this invention is: a method for manufacturing a double-sided SMT substrate stack-up structure, applied to any of the double-sided SMT substrate stack-up structures described in the invention, comprising: mounting the first chip onto the upper surface of the first substrate and encapsulating it to form a first encapsulation body; polishing the upper surface of the first encapsulation body until copper pillars are exposed; mounting the second chip onto the lower surface of the second substrate and encapsulating it to form a second encapsulation body; mounting the third chip onto the upper surface of the second substrate to form a single unit; fixing the second encapsulation body and the first encapsulation body with adhesive; and encapsulating the entire assembly after electrical connection.

[0013] Optionally, the overall encapsulation after electrical connection includes: using gold wire bonding to connect the solder joints of the second substrate and the copper pillars of the first substrate through gold wires.

[0014] The beneficial effects of this invention are: This invention prevents solder ball collapse by placing copper pillars on the first substrate, reducing manufacturing costs, and achieves a double-sided SMT substrate stack-up structure through wire bonding. The invention uses a vertical three-dimensional arrangement, connecting the signal transmission between the two substrates via simple copper pillars and gold wire bonding. All processes utilize conventional packaging procedures, eliminating the need for complex processes and saving costs. Attached Figure Description

[0015] Figure 1 This is a side view of the double-sided SMT substrate stack structure of the present invention; Figure 2 This is a schematic diagram of the first substrate packaging structure of the present invention; Figure 3 This is a schematic diagram of the grinding structure of the first substrate after packaging according to the present invention; Figure 4 This is a schematic diagram of the encapsulation structure on the upper surface of the second substrate of the present invention; Figure 5 This is a schematic diagram of the chip mounting structure on the lower surface of the second substrate of the present invention; Figure 6 This is a schematic diagram of the second substrate packaging unit structure of the present invention; Figure 7 This is a schematic diagram of the stacked structure of the first substrate and the second substrate of the present invention; Figure 8 This is a schematic diagram of the first substrate and the second substrate of the present invention being connected by copper pillars and gold wire bonding; Figure 9 This is a schematic diagram of the encapsulation structure of the first substrate and the second substrate of the present invention using a plastic encapsulation body; Figure 10 This is a schematic diagram of the prior art structure in this invention.

[0016] Reference numerals: 1. Copper pillar; 2. Gold wire; 3. First substrate; 31. First chip; 32. First component; 4. Second substrate; 41. Third chip; 42. Third component; 43. Second chip; 44. Second component; 5. Fixing adhesive; 6. First encapsulation; 7. Second encapsulation; 8. Third encapsulation. Detailed Implementation

[0017] The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby providing a clearer and more explicit definition of the scope of protection of the present invention.

[0018] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0019] This invention provides a double-sided SMT substrate stack-up structure achieved through wire bonds and copper pillars. In the electronics manufacturing industry, surface mount technology (SMT) is one of the core technologies of modern electronic assembly. Its high efficiency and precision have greatly promoted the miniaturization, lightweighting, and high performance of electronic products. Different types of PCBs exhibit varying characteristics, advantages, and process requirements during SMT assembly due to their unique structures and designs. Double-sided boards have two conductive pattern layers connected by vias, increasing circuit complexity and component density. In SMT processing, double-sided boards can accommodate more components, improving product integration. Precise control of the via fabrication quality is required during processing to ensure reliable electrical connections. Furthermore, during double-sided assembly, component heights must be rationally planned to avoid obstruction or interference, while appropriate fixtures and process parameters must be used to ensure the accuracy and stability of the assembly.

[0020] In one specific embodiment of this application, the substrate includes: a multilayer substrate, comprising at least a first substrate 3 and a second substrate 4; the second substrate 4 is stacked on top of the first substrate 3, and multiple chips are respectively mounted on the substrates; at least one substrate has chips mounted on both sides, with a first chip 31 mounted on the upper surface of the first substrate 3, and a second chip 43 and a third chip 42 mounted on the lower and upper surfaces of the second substrate 4, respectively. A copper pillar 1 is embedded in a molding compound on the first substrate 3, and the copper pillar 1 is electrically connected to the second substrate 4 via gold wire bonding. Using copper pillars for conductivity achieves both soldering and support between substrates, as well as electrical connection between substrates, and has a lower manufacturing cost.

[0021] In one specific embodiment of this application, the upper surface of the copper pillar 1 is ground to the same height as the upper surface of the first encapsulator 6 on the first substrate 3. In this embodiment, by grinding the first encapsulator 6 to make its height equal to the upper surface of the copper pillar 1, the exposed copper pillar facilitates wire bonding and connection with the second substrate. By first encapsulating the first encapsulator 6 and then grinding to expose the copper pillar, the manufacturing cost is further reduced.

[0022] In one specific embodiment of this application, the lower surface of the copper pillar 1 is connected to pins on the first substrate 3, thereby making the lower surface of the copper pillar electrically connected to the first substrate.

[0023] In one specific embodiment of this application, the horizontal distance between the copper pillar 1 and the second substrate 4 is not less than a first predetermined distance. Positioning the copper pillar outside the edge of the second substrate facilitates the bonding of the upper surface of the copper pillar to the pins on the edge of the second substrate via gold wire 2.

[0024] In one specific embodiment of this application, the upper surface of the copper pillar 1 is connected to the pins on the upper surface of the second substrate 4 via gold wire bonding. Semiconductor bonding wire is a high-purity metallic material, primarily composed of 99.999% gold, and doped with elements such as silver, palladium, and magnesium. It is used in semiconductor packaging processes to connect chips to the substrate, ensuring stable transmission of circuit signals. Its core process is wire bonding technology, a crucial step in chip packaging. In semiconductor packaging, it is also called "wire bonding," or WB for short. This refers to bonding the chip interface to the substrate interface with high-purity gold, copper, or aluminum wire after treating the adhesive between the chip and the substrate to improve adhesion. It is mainly used for chip bonding in semiconductor packaging processes. The material's properties, such as hardness, rigidity, and conductivity, are optimized by adjusting the proportion of doping elements. The production process includes refining and purification, continuous casting, wire drawing, and annealing to adjust the metal crystal structure and balance ductility and strength. Finished products must undergo standardized quality certifications such as visual inspection, tensile testing, and shear testing. The main performance parameters include tensile strength and elongation.

[0025] In one specific embodiment of this application, it further includes: a first chip 31 and a first component 32 soldered to the upper surface of the first substrate 3, wherein the height of the copper pillar 1 is not less than the height of the first chip 31 and the first component 32 on the first substrate 3, and the copper pillar 1, the first chip 31, and the first component 32 are encapsulated in the same plastic package. During the polishing process after the first substrate is plastic-encapsulated, the upper surface of the copper pillar needs to be exposed, and the first chip and the first component must be completely encapsulated in the first plastic package; therefore, the height of the copper pillar cannot exceed the height of the first chip and the first component.

[0026] In one specific embodiment of this application, a second chip 43 and a second component 44 are further included, soldered to the lower surface of the second substrate 4, wherein the second chip 43 and the second component 44 are encapsulated in the same molding compound. Specifically, the second chip and the second component are encapsulated within the second molding compound 7. Furthermore, the distance between the lower surface of the second chip 43 and the upper surface of the first chip 31 is not less than a second predetermined distance.

[0027] In one specific embodiment of this application, a third chip 41 and a third component 42 are soldered to the upper surface of the second substrate, wherein the third chip 41 and the third component 42 are encapsulated in the same molding compound. Specifically, the third chip and the third component are encapsulated in a third molding compound 8, so that the upper and lower surfaces of the second substrate form a single unit cell.

[0028] In one specific embodiment of this application, a fixing adhesive is further included, wherein the upper part of the first substrate and the lower part of the second substrate are connected by the fixing adhesive. In the electronics manufacturing industry, chip bonding adhesives act as invisible "adhesives," tightly bonding the chip to the substrate and directly affecting the product's stability and lifespan. Epoxy resin adhesives are considered evergreen in the chip packaging field. These adhesives use bisphenol A type epoxy resin as a base material, adding curing agents, fillers, and other components, and then curing by heating to form a three-dimensional cross-linked structure. Their advantages include strong adhesion, rapid curing at room or medium temperature, and relatively low cost, making them suitable for large-scale mass production. When selecting chip fixing adhesives, the following factors need to be considered: the material characteristics of the chip and substrate to ensure good compatibility and adhesion between the adhesive and them; the application environment, such as temperature, humidity, and chemical corrosion, to select an adhesive with appropriate resistance; and the bonding requirements and curing time to select the appropriate adhesive type and curing method.

[0029] In one specific embodiment of this application, the unit formed by the second substrate, the second chip, the second component, the third chip, and the third component is arranged on a ring fixture. Chips with rings offer significant advantages. Although the seal ring does not participate in circuit signal processing, it significantly improves the reliability and stability of the chip. Regarding mechanical stress protection, it can absorb more than 90% of the mechanical stress during wafer dicing; the dicing yield of chips without seal rings drops sharply from 98% to 82%, and the risk of edge circuit breakage increases by 60%. In terms of environmental isolation, the multi-layer structure can block moisture intrusion, providing excellent moisture protection. Chips with seal rings have a failure time three times longer than those without seal rings in an 85℃ / 85% RH environment; they can also block contaminants, preventing metal corrosion and leakage. Regarding electrostatic and electromagnetic protection, the P+ diffusion layer provides a low-impedance grounding path, improving ESD protection capability by 40%; the overall grounding forms a shielding layer, which can reduce parasitic noise by more than 20dB in RF chips.

[0030] In one specific embodiment of this application, a manufacturing method for a double-sided SMT substrate stack-up structure using wire bonds and copper pillars is also provided. Step 1: Following normal packaging of the first substrate, chip thinning → dicing → SMT → FCA, including reflow soldering, cleaning → molding, to obtain... Figure 2 As shown.

[0031] Step 2: Use strip grinder to completely remove the molding compound above the copper pillars, exposing the copper pillars but ensuring the chip and components are still encapsulated. Do not expose the chip, as this poses a high risk of die cracking. Figure 3 As shown, Step 3: Continue with encapsulation on the lower surface of the second substrate. Specific steps include: chip thinning → dicing → SMT → FCA (Film Processing and Assembly), including reflow soldering, cleaning → molding, to obtain... Figure 4 As shown.

[0032] Step 4: Continue with the encapsulation process on the second substrate. For this SMT process, a custom platform is needed for solder paste printing. Grooves are cut into the area of ​​the platform that contacts the molding compound on side A of the substrate to allow for solder paste printing. Custom carriers are used for component placement and flip-chip assembly. After completion, the components are cut into individual units, resulting in... Figure 5 The structure shown is used, but the product is still on the ring fixture, without disrupting the overall unit layout, resulting in the following: Figure 6 As shown; Step 5: Apply adhesive to the first substrate using a BESI 2100 pick-and-place machine and place... Figure 6 The unit shown is adsorbed and mounted to obtain the following result: Figure 6 The structure shown.

[0033] Step 6: Continuing with the wire bonding process at the solder joints of the second substrate, gold wires are used to connect the copper pillars of the first substrate, resulting in the following... Figure 8 The structure shown; Step 7: Perform final molding to wrap and protect all structures, then cut into individual pieces to obtain the final product. Figure 9 The invention shown.

[0034] This invention prevents solder ball collapse by placing copper pillars on the first substrate, reducing manufacturing costs, and achieves a double-sided SMT substrate stack-up structure through wire bonding. The invention uses a vertical three-dimensional arrangement, connecting the signal transmission between the two substrates via simple copper pillars and gold wire bonding. All processes utilize conventional packaging procedures, eliminating the need for complex processes and saving costs.

[0035] The above are merely embodiments of the present invention and do not limit the patent scope of the present invention. Any equivalent structural transformations made based on the content of the present invention specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A double-sided SMT substrate laminate package structure, characterized in that, include: First substrate; Second substrate; The first chip is mounted on the upper surface of the first substrate; At least one copper pillar is electrically connected to the first chip, and the upper surface of the at least one copper pillar is higher than the upper surface of the first chip; A first molding compound encapsulates the upper surface of the first substrate, the first chip, and the at least one copper pillar, wherein the upper surface of the first molding compound is ground to be flush with the upper surface of the at least one copper pillar.

2. The double-sided SMT substrate stack-up structure of claim 1, wherein, The lower surface of the copper pillar is connected to the pins on the first substrate.

3. The double-sided SMT substrate stack-up structure of claim 1, wherein, The horizontal distance between the copper pillar and the second substrate is not less than a first predetermined distance.

4. The double-sided SMT substrate stack-up structure of claim 1, wherein, The upper surface of the copper pillar is connected to the pins on the upper surface of the second substrate via gold wire bonding.

5. The double-sided SMT substrate stack-up structure of claim 1, wherein, Also includes: The second chip is mounted on the lower surface of the second substrate, and the distance between the lower surface of the second chip and the upper surface of the first chip is not less than a second predetermined distance.

6. The double-sided SMT substrate stack-up structure of claim 5, wherein, Also includes: The second molding compound encapsulates the lower surface of the second substrate and the second chip.

7. The double-sided SMT substrate stack-up structure of claim 6, wherein, Also includes: A fixing adhesive is applied between the first and second molding bodies to fix and connect them.

8. The double-sided SMT substrate stack-up structure of claim 1, wherein, Also includes: The third chip is mounted on the upper surface of the second substrate; The third molding compound encapsulates the upper surface of the second substrate, the third chip, and the space between the first molding compound and the second molding compound.

9. A method for manufacturing a double-sided SMT substrate stack-up structure, applied to the double-sided SMT substrate stack-up structure according to any one of claims 1-8, characterized in that, The first chip is mounted onto the upper surface of the first substrate and then encapsulated to form the first encapsulated body; Polish the upper surface of the first molding compound until the copper pillar is exposed; The second chip is mounted onto the lower surface of the second substrate and then encapsulated to form a second molding compound; The third chip is mounted onto the upper surface of the second substrate to form a single unit; The second molding compound and the first molding compound are fixed together with adhesive; After electrical connection, the entire assembly is encapsulated.

10. A method for manufacturing a double-sided SMT substrate stack-up structure according to claim 9, characterized in that, The process of making electrical connections followed by overall encapsulation includes: The solder joints on the second substrate are connected to the copper pillars on the first substrate via gold wire bonding using a gold wire bonding process.

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