Laminated ceramic electronic components

Abstract

A multilayer ceramic electronic component, such as a multilayer ceramic capacitor, is provided. The multilayer ceramic electronic component (1) has multiple internal electrode layers, including a first internal electrode layer (6a) exposed from a first end face (E1) and a second internal electrode layer (6b) exposed from a second end face (E2). The multilayer body (2) has an inner layer portion in which the first internal electrode layer (6a) and the second internal electrode layer (6b) are opposed in the stacking direction (T). The particle size of the ceramic contained in the first side face (S1) and the second side face (S2) of the multilayer body (2) is smaller than the particle size of the ceramic contained in the central portion in the width direction (W) of the multilayer body (2). The particle size of the ceramic contained in the ends of the first end face (E1) and the second end face (E2) of the inner layer portion is the same as or larger than the particle size of the ceramic contained in the central portion of the inner layer portion.

Description

Technical Field

[0001] This invention relates to laminated ceramic electronic components. Background Technology

[0002] Multilayer ceramic capacitors and other multilayer ceramic electronic components are manufactured by stacking multiple dielectric sheets. On these dielectric sheets, internal electrode layers for constituting capacitors, resistors, inductors, varistors, filters, etc., are formed according to the multilayer ceramic electronic component. For this multilayer ceramic electronic component, efforts are being made to reduce the thickness and multilayering of the dielectric sheets to achieve miniaturization and high performance. For example, there is Patent Document 1.

[0003] Prior art literature

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2001-267173 Summary of the Invention

[0006] The problem the invention aims to solve

[0007] As shown in Patent Document 1, if the dielectric sheet and the internal electrode layer are alternately stacked and the internal electrode layer is arranged and stacked such that the ends of the internal electrode layer are exposed differently from each other from the two end faces in the longitudinal direction, then a step is generated in an amount corresponding to the thickness of the internal electrode layer.

[0008] When a laminate is pressed in a state where a step corresponding to its thickness is created, the ceramic of the dielectric sheet near the step flows into the step, filling it and thinning the dielectric sheet near the step. Therefore, sometimes the thickness of the dielectric sheet, which has been reduced due to thinning, may become even thinner.

[0009] However, if the dielectric sheet, already thinned by thinning, becomes even thinner, the grain boundaries of the dielectric sheet become very few in the thickness direction, and the resistance becomes very low. As a result, if a voltage is applied to the thinned dielectric sheet, excessive current may flow, leading to electric field concentration and insulation breakdown.

[0010] Furthermore, when current flows through the internal electrode layer, due to the edge effect, the electric field intensity increases at the end of the internal electrode layer near the step compared to other regions of the internal electrode layer. Therefore, electric field concentration is more pronounced at the end of the internal electrode layer near the step, sometimes leading to insulation breakdown.

[0011] Therefore, the objective of this invention is to provide multilayer ceramic electronic components such as multilayer ceramic capacitors with high reliability, and in particular, to provide multilayer ceramic electronic components capable of suppressing the generation of insulation breakdown at the ends of internal electrode layers exposed to strong electric fields.

[0012] Technical solutions for solving the problem

[0013] The laminated ceramic electronic component of the present invention comprises a laminated body including a plurality of stacked dielectric layers and a plurality of internal electrode layers, and having a first main surface and a second main surface opposite to each other in the stacking direction, a first end surface and a second end surface opposite to each other in a length direction intersecting the stacking direction, and a first side surface and a second side surface opposite to each other in a width direction intersecting the stacking direction and the length direction. The plurality of internal electrode layers have a first internal electrode layer exposed from the first end surface and a second internal electrode layer exposed from the second end surface. 2. An inner electrode layer, wherein the laminate has an inner layer portion in which the first inner electrode layer and the second inner electrode layer are opposed in the lamination direction, wherein the particle size of the ceramic contained in the first side surface and the second side surface of the laminate is smaller than the particle size of the ceramic contained in the central portion of the laminate in the width direction, and the particle size of the ceramic contained in the ends of the first end face and the second end face of the inner layer portion is the same as or larger than the particle size of the ceramic contained in the central portion of the inner layer portion.

[0014] Invention Effects

[0015] According to the present invention, it is possible to provide multilayer ceramic electronic components such as multilayer ceramic capacitors with high reliability. Attached Figure Description

[0016] Figure 1 This is a perspective view illustrating a stacked ceramic electronic component according to one embodiment of the present invention.

[0017] Figure 2 yes Figure 1 Sectional view along line II.

[0018] Figure 3 yes Figure 1 Sectional view along line II-II.

[0019] Figure 4 yes Figure 1 Sectional view along line III-III.

[0020] Figure 5 The second embodiment of the present invention illustrates a laminated ceramic electronic component, which is related to... Figure 1 The sectional view corresponding to the II-II line sectional view.

[0021] Figure 6 This is a diagram showing an outline of the core of the laminate.

[0022] Figure 7 This is an explanatory diagram showing the inner layer after grinding.

[0023] Figure 8 This is an explanatory diagram showing the inner layer after grinding.

[0024] Figure 9 This is an LW cross-sectional view showing the particle size distribution of ceramics in a laminate. Detailed Implementation

[0025] (First Embodiment)

[0026] The method of carrying out the invention will be explained using a multilayer ceramic capacitor 1 as an example of a multilayer ceramic electronic component. Figure 1 This is a perspective view of the multilayer ceramic capacitor 1 according to the first embodiment of the present invention.

[0027] (Layered structure)

[0028] The stack 2 comprises multiple stacked dielectric layers and multiple internal electrode layers. The stack 2 has a generally cuboid shape. In the stack 2, the direction in which the dielectric layers and internal electrode layers are stacked is designated as the stacking direction T. Furthermore, the direction orthogonal to the stacking direction T is designated as the width direction W. The direction orthogonal to both the stacking direction T and the width direction W is designated as the length direction L.

[0029] In the laminate 2, two opposing surfaces in the lamination direction T are designated as the first main surface M1 and the second main surface M2, respectively. Furthermore, in the laminate 2, two opposing surfaces in the width direction W are designated as the first side surface S1 and the second side surface, respectively. Additionally, two opposing end surfaces in the length direction L are designated as the first end surface E1 and the second end surface E2. The mounting surface of the laminated ceramic capacitor 1 is designated as the second main surface M2. The mounting surface is the surface facing the wiring substrate when the laminated ceramic capacitor 1 is mounted on the wiring substrate, etc.

[0030] Regarding the cross-section of laminate 2, Figure 1 The II-line section is defined as the LT section. Figure 1 The II-II line section is defined as the WT section. Figure 1 The section along line III-III is defined as the LW section.

[0031] In the laminate 2, it is preferable to round its corners and edges. A corner is the part where three faces of the laminate 2 intersect. An edge is the part where two faces of the laminate 2 intersect. Furthermore, unevenness or protrusion may be formed on part or all of the main face, side face, and end face.

[0032] (Dielectric layer)

[0033] The total number of dielectric layers stacked in the second laminate is preferably 15 or more and 2000 or less. The dielectric layers are mainly formed of ceramic materials. For example, dielectric ceramics containing main components such as BaTiO3, CaTiO3, SrTiO3, and CaZrO3 can be used as such ceramic materials. In addition, dielectric ceramics with secondary components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds added to these main components can also be used as ceramic materials.

[0034] In this embodiment, a multilayer ceramic capacitor 1, which is one type of multilayer ceramic electronic component, will be used as an example to describe the multilayer ceramic electronic component.

[0035] When piezoelectric ceramics are used in the laminate 2 of a multilayer ceramic electronic component, it functions as a ceramic piezoelectric element. Specific examples of piezoelectric ceramic materials include PZT (lead zirconate titanate) based ceramic materials.

[0036] Furthermore, when semiconductor ceramics are used in the laminate 2, the multilayer ceramic electronic component functions as a thermistor element. Specific examples of semiconductor ceramic materials include spinel-based ceramic materials.

[0037] Furthermore, when the laminated ceramic electronic component uses magnetic ceramic in the laminate 2, it functions as an inductor element. Moreover, when the laminated ceramic electronic component functions as an inductor element, the internal electrode layer becomes a coil-shaped conductor. Specific examples of magnetic ceramic materials include ferrite ceramic materials.

[0038] The thickness of the dielectric layer is preferably 0.5 μm or more and 10 μm or less.

[0039] (Division of layered structures)

[0040] based on Figure 2 This is used to illustrate the division along the length direction L of the laminate 2. Figure 2 yes Figure 1 The cross-sectional view along line II. The laminate 2 can be divided in the lamination direction T into an outer layer OL1 on the first main surface side, an inner layer range IL, and an outer layer OL2 on the second main surface side. The outer layer OL1 on the first main surface side, the inner layer range IL, and the outer layer OL2 on the second main surface side are arranged sequentially from the first main surface M1 toward the second main surface M2 in the lamination direction T.

[0041] A line is drawn from the first end face E1 to the second end face E2 along the surface of the inner electrode layer closest to the first main surface M1. The outer layer portion OL1 on the first main surface side is the portion between this line and the first main surface M1. A line is drawn from the first end face E1 to the second end face E2 along the surface of the inner electrode layer closest to the second main surface M2. The outer layer portion OL2 on the second main surface side is the portion between this line and the second main surface M2. The inner layer range IL is the range sandwiched between the outer layer portion OL1 on the first main surface side and the outer layer portion OL2 on the second main surface side. That is, the inner layer range IL is the range between the line drawn from the first end face E1 to the second end face E2 along the surface of the inner electrode layer closest to the first main surface M1 and the line drawn from the second end face E2 towards the first end face E1 along the surface of the inner electrode layer closest to the second main surface M2.

[0042] The outer layer OL1 on the first main surface side is located on the first main surface M1 side of the laminate 2. A line is drawn from the first end face E1 to the second end face E2 along the outermost surface of the inner electrode layer closest to the first main surface M1. The outer layer OL1 on the first main surface side can be configured as an assembly of multiple dielectric layers located between the first main surface M1 and the line.

[0043] The second main surface side outer layer OL2 is located on the second main surface M2 side of the laminate 2. A line is drawn from the first end face E1 to the second end face E2 along the outermost surface of the inner electrode layer closest to the second main surface M2. The second main surface side outer layer OL2 can be configured as an assembly of multiple dielectric layers located between the second main surface M2 and the line and the second main surface M2.

[0044] The outer layer OL1 on the first main surface side is located on the first main surface M1 side and is formed by a plurality of dielectric layers between the outermost surface of the inner layer range IL on the first main surface M1 side and the extension line of the outermost surface.

[0045] The outer layer OL2 on the second main surface side is located on the second main surface M2 side and is formed by a plurality of dielectric layers between the outermost surface of the inner layer range IL on the second main surface M2 side and the extension line of the outermost surface.

[0046] The inner layer range IL is the range sandwiched between the first main surface side outer layer portion OL1 and the second main surface side outer layer portion OL2.

[0047] The dielectric layers disposed on the outer layer portion OL1 on the first main surface side and the outer layer portion OL2 on the second main surface side are designated as outer dielectric layers 3. The dielectric layers disposed in the inner layer range IL are designated as inner dielectric layers 4.

[0048] The dimensions of the laminate 2 are not particularly limited. The dimension L in the length direction of the laminate 2 is defined as dimension L. Dimension L is preferably 0.2 mm or more and 10 mm or less. The dimension W in the width direction of the laminate 2 is defined as dimension W. Dimension W is preferably 0.1 mm or more and 5 mm or less. The dimension T in the lamination direction of the laminate 2 is defined as dimension T. Dimension T is preferably 0.1 mm or more and 5 mm or less.

[0049] (L-gap)

[0050] The division of the laminate 2 along the length direction L will be explained. The laminate 2 can be divided along the length direction L into a first end face side outer layer LG1, an L-opposite layer LF, and a second end face side outer layer LG2. The first end face side outer layer LG1, the L-opposite layer LF, and the second end face side outer layer LG2 are arranged sequentially from the first end face E1 toward the second end face E2 along the length direction L.

[0051] The first end-face side outer layer LG1 is the portion where only the first inner electrode layers 6a oppose each other in the stacking direction T, and it is the portion between the first main-face side outer layer OL1 and the second main-face side outer layer OL2. The second end-face side outer layer LG2 is the portion where only the second inner electrode layers 6b oppose each other in the stacking direction T, and it is the portion between the first main-face side outer layer OL1 and the second main-face side outer layer OL2. The L-opposing portion LF is the region sandwiched between the first end-face side outer layer LG1 and the second end-face side outer layer LG2. That is, the L-opposing portion LF is the portion where the first inner electrode layer 6a and the second inner electrode layer 6b oppose each other in the stacking direction T. The L-opposing portion LF is the portion corresponding to the opposing electrode portion of the inner electrode layers. The first end-face side outer layer LG1 and the second end-face side outer layer LG2 are the portions corresponding to the lead-out electrode portions of the inner electrode layers. The opposing electrode portions and the lead-out electrode portions will be explained later. Furthermore, the outer layer portion LG1 on the first end face side and the outer layer portion LG2 on the second end face side are also referred to as L gaps.

[0052] The outer layer LG1 on the first end face side is located on the first end face E1 side, between the outermost surface on the first end face E1 side and the outermost end surface of the second inner electrode layer 6b that is not connected to the first outer electrode 20a.

[0053] The outer layer LG2 on the second end face side is located on the second end face E2 side, between the outermost surface on the second end face E2 side and the outermost surface of the first inner electrode layer 6a that is not connected to the second outer electrode 20b.

[0054] (W gap)

[0055] based on Figure 3 This is to illustrate the division along the width direction W of the laminate 2. Figure 3 yes Figure 1The cross-sectional view along line II-II. The laminate 2 can be divided in the lamination direction T into a first main surface side outer layer portion OL1, an inner layer range IL, and a second main surface side outer layer portion OL2. A line is drawn from the first side surface S1 to the second side surface S2 along the outermost surface of the inner electrode layer closest to the first main surface M1; the first main surface side outer layer portion OL1 is the portion between this line and the first main surface M1. A line is drawn from the first side surface S1 to the second side surface S2 along the outermost surface of the inner electrode layer closest to the second main surface M2; the second main surface side outer layer portion OL2 is the portion between this line and the second main surface M2. The inner layer range IL is the range enclosed by the first main surface side outer layer portion OL1 and the second main surface side outer layer portion OL2. That is, the inner layer range IL is the range between a line drawn from the first side surface S1 to the second side surface S2 along the outermost surface of the inner electrode layer closest to the first main surface M1, and a line drawn from the second side surface S2 to the first side surface S1 along the outermost surface of the inner electrode layer closest to the second main surface M2. The dielectric layers disposed in the outer layer portion OL1 on the first main surface side and the outer layer portion OL2 on the second main surface side are designated as outer dielectric layers 3. The dielectric layer disposed in the inner layer range IL2 is designated as inner dielectric layers 4.

[0056] The laminate 2 can be divided into a first side outer layer WG1, a W opposing layer WF, and a second side outer layer WG2 in the width direction W. The first side outer layer WG1, the W opposing layer WF, and the second side outer layer WG2 are arranged sequentially from the first side S1 toward the second side S2 in the width direction W.

[0057] The W-opposed portion WF is the portion where the internal electrode layers are opposed to each other in the stacking direction T. The first side outer layer portion WG1 is the portion between the W-opposed portion WF, the first side surface S1, the first main surface outer layer portion OL1, and the second main surface outer layer portion OL2. The second side outer layer portion WG2 is the portion between the W-opposed portion WF, the second side surface S2, the first main surface outer layer portion OL1, and the second main surface outer layer portion OL2. The first side outer layer portion WG1 and the second side outer layer portion WG2 are also referred to as the W gap.

[0058] The first side outer layer WG1 and the second side outer layer WG2 are portions in which no internal electrode layer exists in the stacking direction T. The first side outer layer WG1 is located on the first side S1 side, is a portion in which no internal electrode exists in the stacking direction T, and is sandwiched between the first main surface outer layer OL1 and the second main surface outer layer OL2. That is, the first side outer layer WG1 is located on the first side S1 side and can be formed by multiple dielectric layers located between the first side S1, the first main surface outer layer OL1, the second main surface outer layer OL2, and the outermost surface of the inner layer on the first side S1 side.

[0059] Similarly, the second side outer layer WG2 is located on the second side S2 side, and is a portion in which there are no internal electrodes in the stacking direction T, and is sandwiched between the first main side outer layer OL1 and the second main side outer layer OL2. That is, the second side outer layer WG2 is located on the second side S2 side and can be formed by multiple dielectric layers located between the outermost surfaces of the inner layers on the second side S2, the first main side outer layer OL1, the second main side outer layer OL2, and the second side S2 side.

[0060] (Internal electrode layer)

[0061] The internal electrode layer has multiple first internal electrode layers 6a and multiple second internal electrode layers 6b. The first internal electrode layers 6a are internal electrode layers exposed at the first end face E1. The second internal electrode layers 6b are internal electrode layers exposed at the second end face E2.

[0062] The first internal electrode layer 6a includes a first opposing electrode portion 7a opposite to the second internal electrode layer 6b, and a first lead-out electrode portion 8a extending from the first opposing electrode portion 7a to the first end face E1 of the laminate 2. The end portion of the first lead-out electrode portion 8a on the first end face E1 side is led out to the surface of the first end face E1 of the laminate 2. The end portion of the first lead-out electrode portion 8a led out to the first end face E1 forms an exposed portion in the first end face E1.

[0063] The second inner electrode layer 6b includes a second opposing electrode portion 7b opposite to the first inner electrode layer 6a, and a second lead-out electrode portion 8b extending from the second opposing electrode portion 7b to the second end face E2 of the laminate 2. The end portion of the second lead-out electrode portion 8b on the second end face E2 side is led out to the surface of the second end face E2 of the laminate 2. The end portion of the second lead-out electrode portion 8b led out to the second end face E2 forms an exposed portion in the second end face E2.

[0064] The first opposing electrode portion 7a and the second opposing electrode portion 7b are preferably rectangular, but their shapes are not particularly limited. However, the corners of the first opposing electrode portion 7a and the second opposing electrode portion 7b may also be rounded. Furthermore, the corners of the first opposing electrode portion 7a and the second opposing electrode portion 7b may also be formed at an angle. "Formed at an angle" means formed in a conical shape.

[0065] In the first embodiment, the first lead-out electrode portion 8a and the second lead-out electrode portion 8b are preferably rectangular, but the shape is not particularly limited to that embodiment. While the first lead-out electrode portion 8a and the second lead-out electrode portion 8b are preferably rectangular, the corners of the first lead-out electrode portion 8a and the second lead-out electrode portion 8b may also be rounded. Furthermore, the corners of the first lead-out electrode portion 8a and the second lead-out electrode portion 8b may also be formed at an angle. "Formed at an angle" means formed in a conical shape.

[0066] The width of the first counter electrode portion 7a and the width of the first lead-out electrode portion 8a may also be formed to be the same width. Alternatively, either the width of the first counter electrode portion 7a or the width of the first lead-out electrode portion 8a may be formed to be narrower than the other.

[0067] Similarly, the width of the second counter electrode portion 7b and the width of the second lead-out electrode portion 8b can also be formed to be the same width. Alternatively, either the width of the second counter electrode portion 7b or the width of the second lead-out electrode portion 8b can be formed to be narrower than the other.

[0068] The first internal electrode layer 6a and the second internal electrode layer 6b can be made of suitable conductive materials, such as metals like Ni, Cu, Ag, Pd, Au, or alloys containing at least one of these metals, such as Ag-Pd alloys.

[0069] In the multilayer ceramic capacitor 1 of this embodiment, a capacitor is formed by the first opposing electrode portion 7a and the second opposing electrode portion 7b being opposed to each other through the inner dielectric layer 4. Thus, the multilayer ceramic capacitor 1 exhibits the characteristics of a capacitor.

[0070] The thickness of each of the first internal electrode layer 6a and the second internal electrode layer 6b is preferably 0.2 μm or more and 2.0 μm or less. Furthermore, the total number of the first internal electrode layer 6a and the second internal electrode layer 6b is preferably 15 or more and 2000 or less.

[0071] (Reduce the steps near the end face)

[0072] In the multilayer ceramic capacitor 1 of this embodiment, a second dielectric layer 5b is provided. The second dielectric layer 5b is configured to ensure that the length of the multilayer 2 in the stacking direction T is uniform.

[0073] For stepped levels, refer to Figure 2Let's explain. Regarding the length of the lamination direction T of the laminate 2, it is preferable that the length difference between the L-opposed portion LF and the first end-face side outer layer portion LG1 and the second end-face side outer layer portion LG2 is small. However, in the inner layer range IL, an inner dielectric layer 4 is disposed between the first inner electrode layer 6a and the second inner electrode layer 6b in the L-opposed portion LF, but in the first end-face side outer layer portion LG1 and the second end-face side outer layer portion LG2, there are areas where the first inner electrode layer 6a, the second inner electrode layer 6b, and the inner dielectric layer 4 are not disposed. Therefore, after the lamination and pressing process, the length of the lamination direction T between the L-opposed portion LF and the first end-face side outer layer portion LG1 and the second end-face side outer layer portion LG2 can easily become different.

[0074] Within the inner layer range IL, an inner dielectric layer 4, a first internal electrode layer 6a, and a second internal electrode layer 6b are stacked in the L-opposite portion LF.

[0075] In contrast, in the outer layer portion LG1 on the first end face side, only the inner dielectric layer 4 and the first internal electrode layer 6a are stacked. The second internal electrode layer 6b is not stacked in the outer layer portion LG1 on the first end face side.

[0076] Furthermore, in the outer layer portion LG2 on the second end face side, only the inner dielectric layer 4 and the second internal electrode layer 6b are stacked. The first internal electrode layer 6a is not stacked in the outer layer portion LG2 on the second end face side.

[0077] Therefore, after the lamination process, the length of the lamination direction T between the L-opposite portion LF and the outer layer portion LG1 on the first end face side and the outer layer portion LG2 on the second end face side can easily become different.

[0078] Therefore, in order to reduce the difference in length of the stacking direction T between the L-opposite portion LF and the first end-face side outer layer portion LG1 and the second end-face side outer layer portion LG2, an additional inner dielectric layer 4 is disposed in the first end-face side outer layer portion LG1 and the second end-face side outer layer portion LG2. This additional inner dielectric layer 4 is designated as the second dielectric layer 5b. In contrast, the dielectric layers other than the second dielectric layer 5b included in the laminate 2 are designated as the first dielectric layer 5a.

[0079] The second dielectric layer 5b is disposed between the end of the L opposing portion LF on the first end face E1 side and the end of the outer layer portion LG1 on the first end face E1 side. In addition, the second dielectric layer 5b is disposed between the end of the L opposing portion LF on the second end face E2 side and the end of the outer layer portion LG2 on the second end face E2 side.

[0080] The second dielectric layer 5b preferably has the same main components as the first dielectric layer 5a. However, the composition of the second dielectric layer 5b is not limited thereto.

[0081] (Reduce the number of steps near the side)

[0082] In the multilayer ceramic capacitor 1 of this embodiment, the second dielectric layer 5b is also disposed on the side. Based on Figure 3 The following explanation is provided. Preferably, the length of the lamination direction T of the laminate 2 is uniform not only in the length direction L but also in the width direction W. However, within the inner layer range IL, similarly to the length direction L, the length of the lamination direction T tends to differ between the W-opposite portion WF and the first side outer layer portion WG1 and the second side outer layer portion WG2 in the width direction W.

[0083] Within the inner layer IL, in the W-opposite portion WF, an inner dielectric layer 4, a first internal electrode layer 6a, and a second internal electrode layer 6b are stacked.

[0084] In contrast, in the first side outer layer WG1 and the second side outer layer WG2, the first inner electrode layer 6a and the second inner electrode layer 6b are not stacked. In the first side outer layer WG1 and the second side outer layer WG2, only the inner dielectric layer 4 is stacked.

[0085] Therefore, the length of the stacking direction T can easily become different between the W-opposite portion WF and the first side outer layer portion WG1 and the second side outer layer portion WG2.

[0086] Therefore, in order to reduce the difference in length of the stacking direction T between the W-opposite portion WF and the first side outer layer portion WG1 and the second side outer layer portion WG2, an additional inner dielectric layer 4 is disposed on the first side outer layer portion WG1 and the second side outer layer portion WG2. This additional inner dielectric layer 4 is a second dielectric layer 5b.

[0087] The second dielectric layer 5b is disposed between the end of the first side surface S1 side of the outer layer WG1 on the first side surface and the end of the first side surface S1 side of the opposing WF. Furthermore, the second dielectric layer 5b is disposed between the end of the second side surface S2 side of the outer layer WG1 on the first side surface and the end of the second side surface S2 side of the opposing WF.

[0088] In the multilayer ceramic capacitor 1 of this embodiment, the characteristics lie in the concentration of additives and the particle size of ceramics in the multilayer 2.

[0089] (Inner layer)

[0090] The portion where the first inner electrode layer 6a and the second inner electrode layer 6b face each other is designated as the inner layer portion 10. The inner layer portion 10 is... Figure 2 The L-shaped opposite part LF and shown Figure 3The portion where the opposing W-section WF and the inner layer range IL intersect is shown. The inner layer 10 has a generally cuboid shape. Figure 2 In the diagram, the portion where the L-opposite portion LF and the inner layer range IL intersect is shown as the inner layer portion 10. Furthermore, in... Figure 3 In the diagram, the portion where the opposing WF and the inner layer range IL intersect is shown as the inner layer 10.

[0091] (Concentration of additives (LT profile))

[0092] exist Figure 2 In the LT cross-section shown, the end portion of the inner layer 10 on the first end face E1 side is designated as region R1. The end portion of the inner layer 10 on the second end face E2 side is designated as region R2. The central portion of the inner layer 10 in the length direction L is designated as region R3.

[0093] The concentration of additives in region R1 and region R2 is the same as or lower than the concentration of additives in region R3.

[0094] (Additive concentration (WT profile))

[0095] The WT section differs from the LT section described above. Figure 3 In the WT cross-section shown, the region containing the first side surface S1 of the inner layer 10 is designated as region R4, and the region of the dielectric layer of the outer layer adjacent to it is designated as region R5. The region of the central portion of the inner layer 10 in the width direction W is designated as region R6.

[0096] The concentration of additives in region R4 and region R5 is higher than that in region R6.

[0097] (Example of additive (Ni))

[0098] One example of an additive is Ni. By ensuring that the Ni concentration of the additive is higher on the side surfaces of the inner layer 10 than in the center, the reliability of the multilayer ceramic capacitor 1 can be improved. Specifically, this is because when the Ni concentration of the additive is higher on the side surfaces of the inner layer 10, the ceramic particle size on the side surfaces of the inner layer 10 can be kept small during the firing process, increasing the number of ceramic particles within the dielectric layer. Therefore, by increasing the number of ceramic particles within the dielectric layer, the applied voltage at each grain boundary can be reduced, thereby suppressing insulation degradation and insulation breakdown on the side surfaces of the inner layer 10 where the electric field tends to concentrate.

[0099] (Example of additives (V))

[0100] Another example of an additive is vanadium (V). By increasing the concentration of V on the side surfaces of the inner layer 10 compared to its central portion, the reliability of the multilayer ceramic capacitor 1 can be improved. Specifically, when the concentration of V is higher on the side surfaces of the inner layer 10, sintering the ceramic in the area with the higher concentration allows the solid solution of V to penetrate into the grain boundaries and shells within the dielectric layer. This reduces the resistance of the grain boundaries and shells, suppressing electric field concentration in these areas when voltage is applied. In other words, by suppressing electric field concentration, electrons become less mobile on the side surfaces of the dielectric layer during voltage application, thus suppressing insulation degradation and breakdown.

[0101] (Example of an additive (Sn))

[0102] Another example of an additive is Sn. By increasing the Sn concentration on the side surfaces of the inner layer 10 compared to the central portion of the inner layer 10, the reliability of the multilayer ceramic capacitor 1 can be improved. Specifically, this is because the higher Sn concentration on the side surfaces of the inner layer 10 results in increased withstand voltage. With increased Sn concentration, Sn tends to segregate towards the end surfaces of the inner electrode layers. This segregation of Sn towards the end surfaces increases the size of the depletion layer (the region where no electrons exist) between the dielectric layer and the inner electrodes. If the depletion layer becomes larger, the energy required for electrons to pass through it increases. In other words, since electrons become less likely to move within the depletion layer, electric field concentration can be suppressed. Because electric field concentration can be suppressed, insulation degradation and insulation breakdown on the side surfaces of the inner layer 10, where electric field concentration is prone to occur, can be suppressed. This is because, consequently, insulation degradation and insulation breakdown on the side surfaces of the inner layer 10, where electric field concentration is prone to occur, can be suppressed.

[0103] (V, Sn, and ceramic particle size)

[0104] Furthermore, similarly to Ni, when the concentration of V or Sn additives is high on the side surface of the inner layer 10, the ceramic particle size on the side surface of the inner layer 10 can be kept small during the firing process, thereby increasing the number of ceramic particles in the dielectric layer. Therefore, by increasing the number of ceramic particles in the dielectric layer, the applied voltage at each grain boundary can be reduced, thus suppressing insulation degradation and insulation breakdown on the side surface of the inner layer 10 where the electric field tends to concentrate.

[0105] Furthermore, the types of additives are not limited to Ni, V, and Sn. Examples of additives other than Ni, V, and Sn include Mn and Mg.

[0106] The reliability of the aforementioned multilayer ceramic capacitor 1 is related to the particle size of the ceramic in the dielectric layer. The particle size of the ceramic will be explained below.

[0107] (Particle size of ceramics)

[0108] exist Figure 2 In the LT profile shown, the particle size of the ceramics in region R1 and region R2 is the same as or larger than that of the ceramics in region R3.

[0109] Similarly, in Figure 3 In the WT cross-section shown, the particle size of the ceramics in region R4 and region R5 is smaller than that of the ceramics in region R6.

[0110] (The side of the inner layer)

[0111] The smaller particle size of the ceramic on the side surfaces of the inner layer 10 compared to the particle size of the ceramic in the central portion of the inner layer 10 results in the following effect: By reducing the particle size of the ceramic, the number of ceramic particles in the side surfaces of the inner layer 10 can be increased. This reduces the applied voltage at each grain boundary of the ceramic particles. Consequently, insulation degradation and insulation breakdown in the side surfaces of the inner layer 10, where electric fields tend to concentrate, can be suppressed.

[0112] The particle size of the ceramic on the side of the inner layer 10 is smaller than that of the ceramic in the center of the inner layer 10 because the concentration of the additive on the side of the inner layer 10 is greater than that in the center of the inner layer 10.

[0113] As described above, in this embodiment, the additive is Ni, V, or Sn (hereinafter referred to as Ni, etc.). The presence of Ni, etc., in the first dielectric layer 5a on the side surface of the inner layer 10 produces the following effects: By containing Ni, the particle size of the ceramic on the side surface of the inner layer 10 can be kept small. Therefore, the number of ceramic particles in the first dielectric layer 5a on the side surface of the inner layer 10 can be increased. Furthermore, by increasing the number of ceramic particles in the first dielectric layer 5a on the side surface of the inner layer 10, the applied voltage at each grain boundary can be reduced. As a result, insulation degradation and insulation breakdown in the first dielectric layer 5a on the side surface of the inner layer 10, where the electric field tends to concentrate, can be suppressed.

[0114] (Example of additive concentration)

[0115] In addition, for additives such as Ni, Figure 3The concentration of additives in regions R4 and R5 of the inner layer 10 shown in the WT cross-section is at least 100.1 mol% and less than 103.0 mol% relative to the concentration of additives in region R6 of the inner layer 10. If the concentration ratio is less than 100.1 mol%, the ceramic grain size within the dielectric layer cannot be reduced, the applied voltage at each grain boundary cannot be lowered, and therefore insulation breakdown cannot be suppressed, resulting in no improvement in reliability. Furthermore, if the concentration ratio exceeds 103.0 mol%, there becomes an excess of acceptors within the dielectric layer. This excessive generation of oxygen vacancies accelerates the deterioration of the electric field strength and leads to insulation breakdown, thus also resulting in no improvement in reliability.

[0116] The particle size of the ceramic contained in regions R4 and R5 of the inner layer 10 is more than 10% and less than 40% smaller than the particle size of the ceramic contained in region R6 of the inner layer 10. If the particle size reduction rate is less than 10%, the reliability improvement effect brought about by reducing the particle size of the ceramic cannot be obtained. If the particle size reduction rate exceeds 40%, the particles become smaller, εr decreases, and therefore the desired capacitance cannot be obtained.

[0117] (End face side of the inner layer)

[0118] By ensuring that the particle size of the ceramic on the end face side of the inner layer 10 is the same as or larger than the particle size of the ceramic in the central part of the inner layer 10, the following effect is achieved: That is, by increasing the particle size of the ceramic, the increase in the number of ceramic particles on the end face side of the inner layer 10 can be suppressed. This, in turn, increases the capacitance obtained on the end face side.

[0119] The particle size of the ceramic on the end face side of the inner layer 10 is the same as or larger than the particle size of the ceramic in the central part of the inner layer 10, because the concentration of the additive on the end face side of the inner layer 10 is the same as or smaller than the concentration of the additive in the central part of the inner layer 10.

[0120] (Example of additive concentration)

[0121] For additives such as Ni Figure 2The concentration of additives in regions R1 and R2 of the inner layer 10 shown in the LT cross-section is between 100 mol% and 97.0 mol% or more, relative to the concentration of additives in region R3 of the inner layer 10. If the concentration ratio exceeds 100 mol%, the particle size of the ceramic within the dielectric layer cannot be increased. If the ceramic particle size is small, the dielectric constant of the ceramic will not increase, resulting in a decrease in capacitance. Furthermore, if the concentration ratio is less than 97.0 mol%, the particle size of the ceramic within the dielectric layer becomes too large. If the ceramic particle size is large, the insulation will decrease due to a reduction in the number of grain boundaries within the element, resulting in a lack of improved reliability.

[0122] (Example of particle size)

[0123] The particle size of the ceramic contained in regions R1 and R2 of the inner layer 10 is preferably 0% to 40% larger than that of the ceramic contained in region R3 of the inner layer 10.

[0124] Figure 4 It is shown Figure 1 A diagram of the section along line III-III. Figure 4 The LW cross-section of the multilayer ceramic capacitor 1 is shown. The particle size distribution of the ceramic is explained within the LW plane of the multilayer ceramic capacitor 1.

[0125] (Region R2)

[0126] Figure 4 The line L1 shown is a line indicating a position 80 μm from the end of the inner layer 10 on the second end face E2 side towards the first end face E1. That is, Figure 4 The distance D1 shown is 80 μm. In the inner layer 10, the region between the end of the second end face E2 side of the inner layer 10 and the line L1 is region R2. In addition, the end of the second end face E2 side of the inner layer 10 becomes the interface between the inner layer 10 and the second dielectric layer 5b.

[0127] (Region R5)

[0128] Figure 4 The line L2 shown is a line indicating a position 80 μm from the end of the inner layer 10 on the second side surface S2 towards the first side surface S1. That is, Figure 4 The distance D2 shown is 80 μm. The region R5 includes the area between the end of the second side surface S2 side of the inner layer 10 and the line L2, and the area of ​​the dielectric layer of the outer layer nearby. In addition, the end of the second side surface S2 side of the inner layer 10 forms the interface between the inner layer 10 and the second dielectric layer 5b.

[0129] (Region R2 and Region R5)

[0130] The regions R2 and R5 at the ends of the inner layer 10 have been described above. The same applies to regions R1 and R4. Region R1 extends from the end of the inner layer 10 on the first end face E1 side to a position shown by a line 80 μm in the direction toward the second end face E2. Region R4 includes the region extending from the end of the inner layer 10 on the first side face S1 side to a position shown by a line 80 μm in the direction toward the second side face S2, and the adjacent region of the dielectric layer of the outer layer.

[0131] Figure 4 Line L3 is the center line in the length direction L of the inner layer 10. Line L4 is the center line in the width direction W of the inner layer 10.

[0132] (Region R3)

[0133] In the inner layer 10, the region R3 is a range of 80 μm in length direction L centered on line L3. Figure 4 The distance D3 shown is 80 μm.

[0134] (Region R6)

[0135] Furthermore, in the inner layer 10, the region R6 is a range with a length of 80 μm in the width direction W centered on line L4. Figure 4 The distance D4 shown is 80 μm.

[0136] As described above, in the length direction L, the additive concentration in region R2 is the same as or lower than that in region R3. Furthermore, the particle size of the ceramic in region R2 is the same as or larger than that in region R3. Furthermore, in the width direction W, the additive concentration in region R5 is higher than that in region R6. Furthermore, the particle size of the ceramic in region R5 is smaller than that in region R6.

[0137] Here, the overlapping region of regions R2 and R5 is designated as region R7. The ceramic particle size in region R7 is smaller than that in region R2. In region R7, the number of ceramic particles in the dielectric layer is greater than in region R2, allowing for the formation of more grain boundaries. By increasing the number of ceramic particles in the dielectric layer, the applied voltage at each grain boundary can be reduced, thus suppressing insulation degradation and insulation breakdown at the intersection of the end face and side face of the inner layer 10 where the electric field tends to concentrate.

[0138] The above explanation uses a portion of the inner layer 10 as an example. The same applies to the other portions of the inner layer 10. The particle size of the ceramic, etc., will be explained further later.

[0139] (External electrode)

[0140] Next, the external electrodes will be described. The external electrodes include a first external electrode 20a and a second external electrode 20b. The first external electrode 20a is connected to the first internal electrode layer 6a. The first external electrode 20a is also disposed from the first end face E1 to a portion of the first main face M1, a portion of the second main face M2, a portion of the first side face S1, and a portion of the second side face S2.

[0141] The second external electrode 20b is connected to the second internal electrode layer 6b. The second external electrode 20b is also disposed from the second end face E2 to a portion of the first main face M1 and a portion of the second main face M2, a portion of the first side face S1 and a portion of the second side face S2.

[0142] The first external electrode 20a and the second external electrode 20b preferably have a base electrode layer and a plating layer. Furthermore, the base electrode layer may include at least one selected from a sintered layer, a conductive resin layer, a thin film layer, etc. Additionally, the conductive resin layer may be provided separately from the base electrode layer. In the following description, an example will be given of a structure in which the base electrode layer has a sintered layer and also separately has a conductive resin layer.

[0143] The first external electrode 20a includes a first base electrode layer 21a, a first conductive resin layer 22a, a first lower plating layer 23a, and a first upper plating layer 24a. Furthermore, the second external electrode 20b includes a second base electrode layer 21b, a second conductive resin layer 22b, a second lower plating layer 23b, and a second upper plating layer 24b.

[0144] The first base electrode layer 21a and the second base electrode layer 21b are layers containing conductive metal and glass components. The first conductive resin layer 22a and the second conductive resin layer 22b do not contain metal components and are layers containing thermosetting resin. The first lower plating layer 23a and the second lower plating layer 23b can be, for example, Ni plating layers. The first upper plating layer 24a and the second upper plating layer 24b can be, for example, Sn plating layers. The following description will focus on each layer.

[0145] (Base electrode layer)

[0146] The substrate electrode layer includes a first substrate electrode layer 21a and a second substrate electrode layer 21b. The first substrate electrode layer 21a is disposed from a first end face E1 to a portion of a first main surface M1, a portion of a second main surface M2, a portion of a first side surface S1, and a portion of a second side surface S2. The second substrate electrode layer 21b is disposed from a second end face E2 to a portion of the first main surface M1, a portion of the second main surface M2, a portion of the first side surface S1, and a portion of the second side surface S2.

[0147] The first base electrode layer 21a and the second base electrode layer 21b comprise a conductive metal and a glass component. The conductive metal may include, for example, at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloys, Au, etc. The glass component may include at least one selected from B, Si, Ba, Mg, Al, Li, etc.

[0148] The first base electrode layer 21a and the second base electrode layer 21b can each be formed as multiple layers. Furthermore, the first base electrode layer 21a and the second base electrode layer 21b can also be layers formed by applying a conductive paste containing glass components and metal to the laminate and then sintering it. This sintering can be performed simultaneously with the sintering of the inner electrode layers, or it can be performed after the sintering of the inner electrode layers. When sintering is performed simultaneously with the sintering of the inner electrode layers and the dielectric layer, it is preferable to add a dielectric material instead of glass components to form a sintered base electrode layer. In this way, the first base electrode layer 21a and the second base electrode layer 21b are constructed as sintered layers.

[0149] The thickness of the first base electrode layer 21a located at the center of the stacking direction T of the first base electrode layer 21a on the first end face E1 is preferably, for example, 10 μm or more and 150 μm or less. Similarly, the thickness of the second base electrode layer 21b located at the center of the stacking direction T of the second base electrode layer 21b on the second end face E2 is preferably, for example, 10 μm or more and 150 μm or less.

[0150] When the first base electrode layer 21a and the second base electrode layer 21b are disposed on the first main surface M1 and the second main surface M2, and the first side surface S1 and the second side surface S2, the thickness of the first base electrode layer 21a or the second base electrode layer 21b located at the center of the length direction L of the first base electrode layer 21a or the second base electrode layer 21b on the first main surface M1 and the second main surface M2, and the first side surface S1 and the second side surface S2 is preferably, for example, 5 μm or more and 50 μm or less.

[0151] When the substrate electrode layer is set as a thin film layer, the thin film layer can be formed by thin film formation methods such as sputtering or vapor deposition. The formed thin film layer is a layer with metal particles deposited at a depth of less than 1 μm.

[0152] (Conductive resin layer)

[0153] A conductive resin layer is disposed on top of a substrate electrode layer. The conductive resin layer comprises a resin component and a metal component. The conductive resin layer has a first conductive resin layer 22a and a second conductive resin layer 22b. The first conductive resin layer 22a and the second conductive resin layer 22b comprise a thermosetting resin as the resin component. Therefore, the first conductive resin layer 22a and the second conductive resin layer 22b are more flexible than the substrate electrode layer. This is because the substrate electrode layer comprises, for example, a sintered product of a coating film, a metal component, and a glass component.

[0154] Therefore, even when flexural stress is applied to the mounting substrate, or when a physical impact is applied to the multilayer ceramic capacitor 1, or even when an impact caused by thermal cycling is applied to the multilayer ceramic capacitor 1, cracking in the multilayer ceramic capacitor 1 can be suppressed. This is because the conductive resin layer functions as a buffer layer.

[0155] Specific examples of thermosetting resins included in conductive resin layers include epoxy resins, phenolic resins, polyurethane resins, silicone resins, and polyimide resins, among other well-known thermosetting resins. Epoxy resin is one of the most suitable resins because it possesses excellent heat resistance, moisture resistance, and adhesion.

[0156] A first conductive resin layer 22a is disposed on the first base electrode layer 21a. Furthermore, the first conductive resin layer 22a is configured to cover the first base electrode layer 21a. Moreover, the end of the first conductive resin layer 22a preferably contacts the laminate 2. Similarly, a second conductive resin layer 22b is disposed on the second base electrode layer 21b. Furthermore, the second conductive resin layer 22b is configured to cover the second base electrode layer 21b. Moreover, the end of the second conductive resin layer 22b preferably contacts the laminate 2.

[0157] The metal components contained in the first conductive resin layer 22a and the second conductive resin layer 22b can be Ag, Cu, Ni, Sn, Bi, or alloys thereof. The metal components are preferably formed in the form of metal fillers. When the metal component is metal powder, metal powder coated with Sn, Ni, or Cu can also be used. When using materials coated with Sn, N, or Cu on the surface of metal powder, Ag, Cu, Ni, Sn, Bi, or alloys thereof are preferably used as the metal powder. The metal component particularly preferably contains Ag. Ag can be Ag monomer, an alloy containing Ag, or metal powder coated with Ag.

[0158] When using metal powder coated with Ag, Cu, Ni, Sn, Bi, or alloys thereof are preferred as the metal powder. Using Ag as a metal filler offers the following advantages: Ag has the lowest resistivity among metals. Therefore, electrodes with low resistance can be formed. Ag is a noble metal and is therefore not easily oxidized. Therefore, the resistance of the conductive resin layer can be improved. As described above, by using Ag as a metal filler, it is possible to maintain the properties of Ag while using an inexpensive metal as the base material.

[0159] The shape of the metal filler contained in the first conductive resin layer 22a and the second conductive resin layer 22b is not particularly limited. The shape of the metal filler may also be spherical, flat, etc. The metal filler may also be a material composed of a mixture of spherical metal powder and flat metal powder.

[0160] The average particle size of the metal filler contained in the first conductive resin layer 22a and the second conductive resin layer 22b is not particularly limited. For example, the average particle size of the metal filler can be set to 0.3 μm or more and 10 μm or less. Furthermore, the average particle size of the metal filler contained in the conductive resin layer can be determined by calculation based on laser diffraction particle size analysis (based on ISO 13320). This method for determining the average particle size can be applied regardless of the shape of the filler.

[0161] The metal fillers contained in the first conductive resin layer 22a and the second conductive resin layer 22b primarily bear the responsibility for the electrical conductivity of the conductive resin layers. Specifically, the metal fillers contact each other, thereby forming an electrical path within the conductive resin layers.

[0162] As mentioned above, various known thermosetting resins, such as epoxy resin, phenoxy resin, phenolic resin, polyurethane resin, silicone resin, and polyimide resin, can be used as the resins included in the first conductive resin layer 22a and the second conductive resin layer 22b. Among these, epoxy resin, which has excellent heat resistance, moisture resistance, and adhesion, is one of the most suitable resins.

[0163] The first conductive resin layer 22a and the second conductive resin layer 22b preferably contain a curing agent together with the thermosetting resin. As the curing agent, when using epoxy resin as the base resin, various known compounds such as phenolic, amine, acid anhydride, imidazole, reactive ester, and amide-imide compounds can be used.

[0164] The metal contained in the first conductive resin layer 22a preferably comprises 35 vmol% or more and 75 vmol% or less relative to the total volume of the first conductive resin layer 22a. Similarly, the metal contained in the second conductive resin layer 22b preferably comprises 35 vmol% or more and 75 vmol% or less relative to the total volume of the second conductive resin layer 22b.

[0165] The resin contained in the first conductive resin layer 22a preferably comprises 25 vmol% or more and 65 vmol% or less relative to the total volume of the first conductive resin layer 22a. The resin contained in the second conductive resin layer 22b preferably comprises 25 vmol% or more and 65 vmol% or less relative to the total volume of the second conductive resin layer 22b.

[0166] The thickness of the first conductive resin layer 22a or the second conductive resin layer 22b located at the center of the first end face E1 or the second end face E2 in the lamination direction T is preferably, for example, 10 μm or more and 200 μm or less.

[0167] When a first conductive resin layer 22a and a second conductive resin layer 22b are also provided on the first main surface M1, the second main surface M2, the first side surface S1, and the second side surface S2, the thickness of the conductive resin layer located at the center of the first conductive resin layer 22a or the second conductive resin layer 22b in the longitudinal direction L of the first main surface M1, the second main surface M2, the first side surface S1, and the second side surface S2 is preferably, for example, 10 μm or more and 200 μm or less.

[0168] (Coating)

[0169] The plating layer will be described below. As mentioned above, it includes a lower plating layer and an upper plating layer. That is, the plating layer consists of two layers. However, the plating layer can also be a single layer or multiple layers.

[0170] (Lower plating layer)

[0171] A lower plating layer is disposed on a conductive resin layer. The lower plating layer covers at least a portion of the conductive resin layer. The lower plating layer includes a first lower plating layer 23a and a second lower plating layer 23b. The first lower plating layer 23a is disposed on a first conductive resin layer 22a. The second lower plating layer 23b is disposed on a second conductive resin layer 22b.

[0172] The first lower plating layer 23a and the second lower plating layer 23b can be Ni plating layers. By setting the lower plating layers to Ni plating layers, it is possible to suppress the erosion of the base electrode layer and the like by solder when mounting the multilayer ceramic capacitor 1.

[0173] (Upper coating layer)

[0174] An upper plating layer is disposed on a lower plating layer. The upper plating layer covers at least a portion of the lower plating layer. The upper plating layer includes a first upper plating layer 24a and a second upper plating layer 24b. The first upper plating layer 24a is disposed on a first lower plating layer 23a. The second upper plating layer 24b is disposed on a second lower plating layer 23b.

[0175] The first upper plating layer 24a and the second upper plating layer 24b can be Sn plating layers. Sn plating layers offer good solder wettability. Therefore, by setting the upper plating layers as Sn plating layers, mounting the multilayer ceramic capacitor 1 onto a substrate or similar surface becomes easier.

[0176] Furthermore, the metals used as materials for both the lower and upper plating layers are not limited to the examples described above. The plating layers include both a lower and an upper plating layer, and the plating layer can be configured to include at least one metal selected from Cu, Ni, Ag, Pd, Au, and Sn, and an alloy such as an Ag-Pd alloy.

[0177] Furthermore, the thickness of each coating layer is preferably 2 μm or more and 15 μm or less.

[0178] It is also possible to form an external electrode without a base electrode layer, using only a plating layer. The following describes a structure where only a plating layer is used without a base electrode layer.

[0179] The first external electrode 20a and the second external electrode 20b are each formed directly on the surface of the laminate 2 as a coating layer. That is, the laminated ceramic capacitor 1 may also be constructed to include a coating layer electrically connected to the first internal electrode layer 6a or the second internal electrode layer 6b. In the case of such a construction of the external electrodes, the coating layer may be formed after a catalyst has been disposed on the surface of the laminate 2 as a pretreatment.

[0180] The plating layer preferably comprises a lower plating electrode formed on the surface of the laminate 2 and an upper plating electrode formed on the surface of the lower plating electrode. In this case, the lower plating electrode and the upper plating electrode preferably each comprise, for example, at least one metal selected from Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi or Zn, or an alloy containing such metal.

[0181] The lower plating electrode is preferably formed using Ni, which has solder barrier properties. The upper plating electrode is preferably formed using Sn or Au, which have good solder wettability.

[0182] Furthermore, for example, when the first inner electrode layer and the second inner electrode layer are formed using Ni, the lower plating electrode is preferably formed using Cu, which has good adhesion to Ni. Additionally, the upper plating electrode can be formed as needed, and the first outer electrode 20a and the second outer electrode 20b may each be composed solely of the lower plating electrode.

[0183] The plating layer may have the upper plating electrode as the outermost layer, or other plating electrodes may be further formed on the surface of the upper plating electrode. When the plating layer is configured without a base electrode layer, the thickness of each layer of the plating layer is preferably 1 μm or more and 15 μm or less. Furthermore, the plating layer preferably does not contain glass. The metal content per unit volume of the plating layer is preferably 99% by volume or more.

[0184] The dimensions of the multilayer ceramic capacitor 1 are not particularly limited. The length L of the multilayer ceramic capacitor 1, including the laminate 2 and external electrodes, is defined as dimension L. Dimension L is preferably 0.2 mm or more and 10 mm or less. The lamination direction T of the multilayer ceramic capacitor 1, including the laminate 2 and external electrodes, is defined as dimension T. Dimension T is preferably 0.1 mm or more and 0.5 mm or less. The width W of the multilayer ceramic capacitor 1, including the laminate 2 and external electrodes, is defined as dimension W. Dimension W is preferably 0.1 mm or more and 10 mm or less.

[0185] (Method for manufacturing a multilayer ceramic capacitor according to the first embodiment)

[0186] The manufacturing method of the multilayer ceramic capacitor 1 will be described.

[0187] (1) Prepare conductive paste for dielectric sheets and internal electrode layers. The conductive paste for dielectric sheets and internal electrode layers contains adhesives and solvents. Among these adhesives and solvents, known organic adhesives and organic solvents can be used.

[0188] (2) A conductive paste for the internal electrode layer is printed on the dielectric sheet in a given pattern to form the internal electrode layer pattern. The printing can be performed, for example, by screen printing or gravure printing.

[0189] (3) A given number of dielectric sheets for the outer layer are stacked. The inner electrode layer pattern is not printed on the dielectric sheets for the outer layer. Dielectric sheets with the inner electrode layer pattern printed on them are stacked sequentially. And, a given number of dielectric sheets for the outer layer are stacked on them. Thus, a laminated sheet is manufactured.

[0190] The second dielectric layer 5b used to reduce steps will be described below. The dielectric paste that will become the second dielectric layer 5b is called a step-reducing paste.

[0191] The step-reducing paste is applied to the area surrounding the pattern of the internal electrode layer in a dielectric sheet that has an internal electrode layer pattern formed by printing a conductive paste for the internal electrode layer. That is, the step-reducing paste is applied to the areas where the internal electrode layer pattern is not formed. This is because the step-reducing paste is used to eliminate steps between the internal electrode layer pattern and its surrounding area. Furthermore, the step-reducing paste can also be applied to partially overlap the area surrounding the internal electrode layer pattern. In this case, the overlap width can be set to, for example, 50 μm. Additionally, the step-reducing paste can also be applied to form a gap between itself and the internal electrode layer pattern. In this case, the gap width can be set to, for example, 50 μm.

[0192] The printing steps reduce the amount of paste covering the internal electrode layer, i.e., the overlap. Examples include setting it to -30μm in the length direction L, +20μm in the width direction W, and setting the thickness to the thickness of the pattern used for the internal electrode layer or about 50% of the Ni thickness.

[0193] Furthermore, when printing the step reduction paste onto the dielectric sheet first and then printing the internal electrode layer paste, the amount of overlap covering the second dielectric layer 5b can be, for example, set to -30 μm in the length direction L, +20 μm in the width direction W, and the thickness can be set to the thickness of the pattern used for the internal electrode layer or about 50% of the Ni thickness.

[0194] The step reduction paste can use the ceramic paste used in the manufacture of dielectric wafers, or it can use a different paste. The amount of Ni, etc., added to the step reduction paste differs from that of the ceramic paste used in the manufacture of dielectric wafers. The step reduction paste applied to the area surrounding the pattern along the length direction of the inner electrode layer has a higher amount of Ni, etc. On the other hand, the step reduction paste applied to the area surrounding the pattern along the width direction of the inner electrode layer has a lower amount of Ni, etc. When the amount of Ni added to the step reduction paste is higher, Ni diffusion into the dielectric wafer occurs. Ni can be added by adding Ni powder to the paste during the manufacture of the step reduction paste. In addition, Ni powder can also be added by increasing the amount of Ni added during the preparation of the raw materials. Furthermore, it can also be done by, for example, further printing Ni paste on top of the step reduction paste after printing the step reduction paste onto the dielectric wafer.

[0195] (4) Laminated blocks are made by pressing laminated sheets in the lamination direction. Pressing is carried out by means such as isostatic pressing.

[0196] (5) Cut the stacked block to a given size. This produces stacked chips. At this point, the corners and edges of the stacked chips can also be rounded. This rounding can be done by tumbling or grinding.

[0197] (6) Firing the stacked sheets. Thus, a stacked body is produced. The firing temperature is preferably 900°C or higher and 1200°C. The firing temperature can be changed depending on the dielectric and the material of the internal electrode layer. In this way, by sequentially performing stacking, high-temperature degreasing, firing, and annealing, the grain growth of the particles can be promoted. However, the grain growth of the particles on the side of the inner layer 10 is suppressed because of the large amount of Ni solid solution.

[0198] Next, external electrodes are placed on the laminate.

[0199] (7) A conductive paste, serving as a base electrode, is applied to both ends of the laminate to form a base electrode layer. In this embodiment, a sintered layer is formed as the base electrode layer. When forming the sintered layer, the conductive paste is applied to a given location on the laminate. The conductive paste contains glass components and metals. Furthermore, the application can be performed, for example, by impregnation. After application, a sintering process is performed to form the base electrode layer. The sintering temperature is preferably 700°C or higher and 900°C or lower.

[0200] (8) Forming a conductive resin layer on the substrate electrode layer. As a method for forming the conductive resin layer, firstly, a conductive resin paste containing resin and metal components is prepared. This conductive resin paste is then applied to the substrate electrode layer. This application can be performed by an impregnation process. After application, a heat treatment is performed at a temperature of 200°C or higher and 550°C or lower. This heat treatment thermally cures the resin. Thus, a conductive electrode layer is formed. The atmosphere used during heat treatment is preferably a nitrogen atmosphere. Furthermore, to prevent resin scattering and oxidation of various metal components, the oxygen concentration is preferably suppressed to 100 ppm or lower.

[0201] (9) After forming the conductive resin layer, a Ni plating layer is formed on the surface of the conductive resin layer as the first lower plating layer and the second lower plating layer. Electrolytic plating can be used as a method for forming the first Ni plating layer and the second Ni plating layer. In addition, as a plating process, roller plating is preferred.

[0202] (10) In this embodiment, a Sn plating layer is further formed on the Ni plating layer. That is, a first Sn plating layer is formed on the first Ni plating layer, and a second Sn plating layer is formed on the second Ni plating layer. As a result, the wettability of the solder used in mounting the multilayer ceramic capacitor 1 to a substrate or the like can be improved. As a result, the multilayer ceramic capacitor 1 can be easily mounted to a substrate or the like. As a method for forming the Sn plating layer, electrolytic plating can be used. Furthermore, as a plating process, roller plating is preferred.

[0203] As described above, in this embodiment, by using a material with a high amount of Ni added to the step reduction paste, the concentration of the additive at the end of the side surface of the inner layer 10 is higher than the concentration of the additive in the central part of the inner layer 10.

[0204] (Modified example)

[0205] However, the method of making the concentration of additive at the side end of the inner layer 10 higher than the concentration of additive at the center of the inner layer 10 is not limited to the method of using step-reducing paste. Even without using step-reducing paste, it is possible to make the concentration of additive at the side end of the inner layer 10 higher than the concentration of additive at the center of the inner layer 10. In addition, the case of not using step-reducing paste corresponds to the case where the second dielectric layer 5b is not provided.

[0206] Without providing a second dielectric layer 5b, for example, it is possible to apply an additive or a material containing an additive to the area of ​​the dielectric sheet where step-reducing paste has been printed. By applying an additive or a material containing an additive to the area surrounding the pattern of the inner electrode layer in the dielectric sheet, the concentration of the additive at the end of the side surface of the inner layer 10 can be higher than the concentration of the additive at the center of the inner layer 10.

[0207] Furthermore, the second dielectric layer 5b is not limited to being disposed near either the end face or the side face. The second dielectric layer 5b can be disposed either near the end face or the side face. In this case, for the portion where the second dielectric layer 5b is not disposed, an additive or a material containing an additive is coated onto the corresponding portion of the dielectric sheet. This allows the additive concentration at the end of the inner layer 10 on the side face to be higher than the additive concentration at the center of the inner layer 10.

[0208] (Second Implementation)

[0209] A second embodiment of the multilayer ceramic capacitor 1 will be described. In the following description, the differences from the first embodiment will be primarily explained. The difference between the multilayer ceramic capacitor 1 of the second embodiment and the multilayer ceramic capacitor 1 of the first embodiment is that the side outer layer is formed of a dielectric sheet for the side outer layer. To distinguish it from the side outer layer of the first embodiment, in the second embodiment, the first side outer layer WG1 is designated as the first side outer layer 30a, and the second side outer layer WG2 is designated as the second side outer layer 30b.

[0210] Figure 5 It is the same as in the second embodiment. Figure 1 The diagram corresponding to the section view along line II-II. For example... Figure 5 As shown, the laminate 2 includes a laminate core 40, a first side outer layer 30a, and a second side outer layer 30b. The laminate core 40 is the portion in the laminate 2 corresponding to the opposing portion WF. The first side outer layer 30a and the second side outer layer 30b are provided in the width direction W, such that the laminate core 40 is sandwiched between them.

[0211] Figure 6 This is a schematic diagram showing the core 40 of the laminate. The first internal electrode layer 6a and the second internal electrode layer 6b are exposed from two end faces in the width direction W of the core 40 of the laminate.

[0212] The first side outer layer 30a and the second side outer layer 30b are composed of a plurality of dielectric layers used for side outer layers. Specifically, as Figure 5As shown, the first side outer layer 30a includes a first outer layer 32a located on the first side S1 side and a first inner layer 31a located on the laminate core 40 side. Furthermore, the second side outer layer 30b includes a second outer layer 32b located on the second side S2 side and a second inner layer 31b located on the laminate core 40 side.

[0213] Due to the difference in sinterability between the first outer layer 32a and the first inner layer 31a, it is sometimes possible to confirm a two-layer structure and the interface between the layers by observing under a dark field using an optical microscope. Furthermore, due to the difference in sinterability between the second outer layer 32b and the second inner layer 31b, it is sometimes possible to confirm a two-layer structure and the interface between the layers by observing under a dark field using an optical microscope.

[0214] Furthermore, even when observing under a dark field using an optical microscope, it is sometimes impossible to confirm whether it is a two-layer structure and the interface between the layers. In this case, the outer 80% region of the first side outer layer 30a is designated as the first outer layer 32a, and the area outside the first outer layer 32a is designated as the first inner layer 31a. Similarly, the outer 80% region of the second side outer layer 30b is designated as the second outer layer 32b, and the area outside the second outer layer 32b is designated as the second inner layer 31b.

[0215] The outer side layer can be made of a dielectric material with a perovskite structure, for example, containing BaTiO3 as the main component. Furthermore, the ratio of the number of moles of Si to the number of moles of Ti in the outer side layer is preferably 1.0 or more and 7.0 or less.

[0216] The dimension W along the width direction of the outer side layer is preferably 5 μm or more and 40 μm or less.

[0217] In the inner layer of the side outer layer, the additive is contained at a higher concentration than that in the outer layer. Furthermore, the Si content in the outer layer of the side outer layer is preferably higher than the Si content in the inner layer. Additionally, the Ni content in the outer layer of the side outer layer is preferably lower than the Ni content in the inner layer.

[0218] In this embodiment, the positional deviations of the ends of the internal electrode layers on the first side S1 and the second side S2 of the inner layer 10 are small. For example, regarding the positions of the ends of the first internal electrode layer 6a and the second internal electrode layer 6b on the first side S1 side in the width direction W, the difference between the position closest to the first side S1 and the position furthest from the first side S1 of the internal electrode layer is 5 μm or less. Similarly, the difference between the distance closest to the second side S2 and the distance furthest from the second side S2 is 5 μm or less.

[0219] (Method for manufacturing a multilayer ceramic capacitor according to the second embodiment)

[0220] Regarding the manufacturing method of the multilayer ceramic capacitor 1 according to the second embodiment, the differences from the manufacturing method of the first embodiment will be mainly explained.

[0221] The same method can be used for (1) to (4) in the manufacturing method of the first embodiment.

[0222] (5) When cutting the laminated blocks, cut them so that the conductive paste corresponding to the inner electrode layer is exposed on both sides in the width direction W. In addition, before lamination, the conductive paste for the inner electrode layer is pre-printed on the dielectric sheet in a pattern that allows for such cutting.

[0223] (6) Fabrication of a dielectric sheet for the outer side layer. Specifically, a perovskite-type compound containing Ba and Ti is prepared as the dielectric material. At least one of Si, Ni, V, Sn, Mn, Mg, and Ba is added as an additive to the dielectric powder obtained from this dielectric material. Furthermore, a binder resin, an organic solvent, a plasticizer, and a dispersant are mixed into the dielectric powder in a given proportion. Thus, a ceramic slurry is prepared.

[0224] The solvent contained in the ceramic slurry that forms the inner layer of the outer side layer is selected optimally to prevent dissolution of the dielectric sheet used in the outer layer. Furthermore, the dielectric sheet used in the inner layer serves to bond with the laminated sheets.

[0225] The content of Ni and other additives in the inner layer is preferably greater than that in the outer layer.

[0226] (7) The ceramic slurry, which is made to form the outer layer, is coated on the surface of the resin film and then dried. Thus, a dielectric sheet for the outer layer is obtained.

[0227] (8) A ceramic slurry, which forms the inner layer, is coated onto the surface of the dielectric sheet used for the outer layer and then dried. This forms the dielectric sheet used for the inner layer. Thus, a dielectric sheet for the outer side layer with a two-layer structure is obtained.

[0228] (9) For a two-layer dielectric sheet for the outer side layer, a method has been described that involves coating the surface of the outer layer dielectric sheet with the inner layer dielectric sheet and then drying it. However, it is also possible to form it using methods other than those described above. For example, the outer layer dielectric sheet and the inner layer dielectric sheet can be formed separately in advance. Then, by bonding them separately, a two-layer dielectric sheet for the outer side layer can also be obtained. Furthermore, the dielectric sheet for the outer side layer is not limited to two layers, but can also be three or more layers.

[0229] (10) Next, a dielectric sheet for the outer side layer is peeled off from a resin film such as a PET film. Then, the dielectric sheet for the inner layer of the peeled outer side layer is pressed onto a laminated sheet. At this time, the dielectric sheet is pressed onto one side of the laminated sheet in the width direction W. Then, by stamping, a layer forming the outer side layer is formed. Next, on the other side of the laminated sheet where a layer forming the outer side layer is not formed, the inner layer dielectric sheet is also placed opposite and pressed. Then, by stamping, a layer forming the outer side layer is formed. At this time, an organic solvent, preferably a binder, is pre-coated onto the side surface of the laminated sheet.

[0230] (11) The laminated pieces having layers forming the outer side layer are degreased under given conditions in a nitrogen atmosphere. Then, the laminated pieces are sintered at a given temperature in a nitrogen-hydrogen-water vapor mixed atmosphere to obtain a sintered laminate.

[0231] (12) External electrodes are formed on the two end faces of the sintered laminate. As described above, the laminated ceramic capacitor 1 is manufactured.

[0232] Furthermore, in the second embodiment, a second dielectric layer 5b for step reduction can be disposed near the end face of the laminate, similar to that in the first embodiment. Also, similar to the first embodiment, the material constituting the second dielectric layer 5b can contain fewer additives, or none at all.

[0233] Alternatively, in the second embodiment, the second dielectric layer 5b may not be disposed near the end face of the laminate. In this case, the concentration of the additive at the end face side of the inner layer 10 can be the same as the concentration of the additive at the center of the inner layer 10.

[0234] In the second embodiment, similarly to the first embodiment, the concentration of the additive at the end of the side surface of the inner layer 10 can be higher than the concentration of the additive at the center of the inner layer 10. This is because the additives contained in the outer side surface layer, especially the additives contained in the first inner layer 31a and the second inner layer 31b, diffuse into the dielectric layer of the inner layer 10.

[0235] (Determination Method)

[0236] The method for determining the particle size of ceramics is explained.

[0237] (WT side)

[0238] based on Figure 7 This is to illustrate the measurement on the WT surface. Figure 7This is a perspective view showing the inner layer 10 after grinding. First, the grinding of the inner layer 10 will be explained.

[0239] The laminate 2 is ground starting from the first end face E1, and grinding continues until a position 80 μm from the end of the inner layer 10 in the length direction L is reached. This position is shown by line L11. The WT section at line L11 is designated as the first section 11a.

[0240] Similarly, the laminate 2 is ground starting from the second end face E2, and grinding continues until a position 80 μm from the end of the inner layer 10 in the length direction L is reached. This position is shown by line L12. The WT section at line L12 is designated as the second section 11b.

[0241] The measurement portion in the width direction W is the width of the inner layer 10 extending 30 μm in one direction and 30 μm in the other direction from the center position in the width direction W, i.e., 80 μm in the width direction W with the center position as the center, and the width of the inner layer 10 extending 80 μm from each end in the width direction W. The width of the inner layer 10 extending 80 μm in the width direction W with the center position in the width direction W as the center portion in the width direction W is defined as the central portion in the width direction W.

[0242] The measurement area in the lamination direction T is the width of the inner layer 10 extending 30 μm from the center position in the lamination direction T in one direction and 30 μm in the other direction, i.e., 80 μm in the lamination direction T with the center position as the center, and the width of the inner layer 10 extending 80 μm from each end of the lamination direction T. The 80 μm width of the inner layer 10 in the lamination direction T with the center position of the lamination direction T as the central part in the lamination direction T is defined.

[0243] The inner layer 10 is further ground starting from either the first section 11a or the second section 11b. Grinding continues until half the length of the inner layer 10 in the length direction L is reached. This position is indicated by line L13. The WT section at line L13 is designated as the third section 11c.

[0244] In the third section 11c, the same locations as in the first section 11a and the second section 11b are also designated as measurement locations.

[0245] The measurement sites determined as described above are shown as measurement sites PW. Nine measurement sites PW are arranged in each of the first section 11a, the second section 11b, and the third section 11c, for a total of 27.

[0246] The measurement area at each measurement site is 80 μm in both the width direction (W) and the stacking direction (T). That is, the length of one side of the quadrilateral frame shown at the measurement site PW is 80 μm.

[0247] (LT side)

[0248] based on Figure 8 This is to illustrate the measurement on the LT plane. Figure 8 This is a perspective view showing the inner layer 10 after grinding. For the LT surface, the measurement area is determined in the same way as the WT surface described previously.

[0249] The laminate 2 is ground starting from the first side surface S1, and grinding continues until a position 80 μm from the end of the inner layer 10 in the width direction W is reached. This position is shown by line L21. The LT section at line L21 is designated as the fourth section 12a.

[0250] Similarly, the laminate 2 is ground from the second side surface S2 until a position 80 μm from the end of the inner layer 10 in the width direction W is reached. This position is shown by line L22. The LT section at line L22 is designated as the fifth section 12b.

[0251] The measurement points in the length direction L are the width of 80 μm at the center of the inner layer 10 in the length direction L, and the width of the inner layer 10 from each end in the length direction L of each other.

[0252] The measurement location in the stacking direction T is the width of 80 μm at the center of the inner layer 10 in the stacking direction T, and the width of the inner layer 10 from the end of the stacking direction T in the 80 μm direction T.

[0253] The inner layer 10 is further ground starting from either section 4 12a or section 5 12b. Grinding continues until half the length of the inner layer 10 in the width direction W is reached. This position is indicated by line L23. The LT section at line L23 is designated as section 6 12c.

[0254] In section 6 12c, measurements will also be performed at the same locations as in section 4 12a and section 5 12b.

[0255] The measurement points PL are shown as defined above. Nine measurement points PL are set in each of the fourth section 12a, the fifth section 12b, and the sixth section 12c, for a total of 27.

[0256] The measurement range at each measurement site shown by measurement site PL is the same as that of measurement site PW. That is, the measurement range is 80 μm in both the length direction L and the stacking direction T. In other words, the length of one side of the quadrilateral frame shown by measurement site PL is 80 μm.

[0257] The above has explained the WT and LT planes. However, the same measurement can be performed in the LW plane.

[0258] Furthermore, the measurement can be set up, for example, to measure the WT surface of 15 laminates 2 manufactured under the same conditions in a batch as described above, and to measure the LT surface of 15 laminates 2 manufactured under the same conditions in a batch as described above.

[0259] When measuring the concentration of the additive and the particle size of the ceramic at the measurement sites described above, it was confirmed that, as mentioned above, the concentration of the additive at the side end of the inner layer 10 is higher than the concentration of the additive at the center of the inner layer 10. Furthermore, it was confirmed that the particle size of the ceramic at the side end of the inner layer 10 is smaller than the particle size of the ceramic at the side end of the inner layer 10.

[0260] Furthermore, it was confirmed that the concentration of the additive at the end face of the inner layer 10 is the same as or lower than the concentration of the additive at the center of the inner layer 10. Furthermore, it was confirmed that the particle size of the ceramic at the end face of the inner layer 10 is the same as or larger than the particle size of the ceramic at the end face of the inner layer 10.

[0261] The particle size of the ceramic is determined as follows: A cross-section of an 80 μm × 80 μm area at the aforementioned measurement site is observed using an electron microscope. The particle sizes of the ceramic particles observed are averaged. This averaged particle size is set as the particle size of the ceramic.

[0262] based on Figure 9 Here is an example to illustrate the measurement results. Figure 9 This is a diagram showing the particle size distribution of the ceramics corresponding to the LW cross-sectional view of the laminate.

[0263] Figure 9 The multilayer ceramic capacitor 1 according to the second embodiment is shown. Furthermore... Figure 9 The portion near the second end face E2 and the second side face S2 of the multilayer ceramic capacitor 1 are shown. Additionally, in Figure 9 In the stacked ceramic capacitor 1 shown, the second dielectric layer 5b is not provided.

[0264] exist Figure 9 In the example shown, the second dielectric layer 5b is not provided. Therefore, the particle size of region R2 becomes the same as that of region R6. This is because there is no diffusion of additives from the second dielectric layer 5b.

[0265] Specifically, the particle size in the outer region of the inner layer 10 is approximately 160 nm in the outer layer LG2 on the second end face side. This is equal to the particle size in region R6. This is because, in Figure 9In the example shown, since the second dielectric layer 5b is not provided, the concentration of the additive is the same in the inner layer 10 and the outer layer LG2 on the second end face side.

[0266] On the other hand, the particle size in region R5 becomes smaller than that in region R6. This is due to the diffusion of additives contained in the outer layer 30b of the second side.

[0267] In the multilayer ceramic capacitor 1 of the present invention, the content of additives in the end portion of the inner layer 10 and the particle size of the ceramic in the end portion of the inner layer 10 are optimized. Therefore, compared with the conventional multilayer ceramic capacitor 1 that uses a step-reduction ceramic paste layer with unadjusted additive concentration, the insulation resistance in the end portion of the inner layer 10 is increased. As a result, a multilayer ceramic capacitor 1 with high reliability can be provided. Furthermore, by varying the particle size of the ceramic in the end portion of the inner layer 10, the reliability of the multilayer ceramic capacitor 1 can be improved.

[0268] The reasons for increasing insulation resistance by optimizing the concentration of additives and the particle size of ceramics are as follows. By adding, for example, Ni as an additive, the particle size of the ceramics within the dielectric layer can be kept small during the firing of the laminated wafers. This increases the number of ceramic particles within the dielectric layer. By increasing the number of ceramic particles within the dielectric layer, the applied voltage at each grain boundary can be reduced. As a result, insulation degradation and insulation breakdown at the ends where electric fields tend to concentrate can be suppressed.

[0269] In the multilayer ceramic capacitor 1 of this embodiment, the concentration of additives on the side surfaces of the inner layer 10 is higher than the concentration of additives in the central portion of the inner layer 10. Furthermore, the particle size of the ceramics contained at the ends of the inner layer 10 is smaller than the particle size of the ceramics contained in the central portion of the inner layer 10. Therefore, insulation degradation and insulation breakdown at the ends of the inner layer 10 can be further suppressed.

[0270] The embodiments of the present invention have been described above, but the present invention is not limited to the foregoing embodiments and various changes and modifications are possible.

[0271] <1> A laminated ceramic electronic component, comprising a laminate,

[0272] The laminate includes multiple stacked dielectric layers and multiple internal electrode layers, and has a first main surface and a second main surface opposite each other in the stacking direction, a first end surface and a second end surface opposite each other in the length direction intersecting the stacking direction, and a first side surface and a second side surface opposite each other in the width direction intersecting the stacking direction and the length direction.

[0273] The plurality of internal electrode layers have a first internal electrode layer exposed from the first end face and a second internal electrode layer exposed from the second end face.

[0274] The laminate has inner layers in which the first inner electrode layer and the second inner electrode layer face each other in the lamination direction.

[0275] The ceramic particles contained on the first and second side surfaces of the laminate are smaller than the ceramic particles contained in the central portion of the laminate in the width direction.

[0276] The particle size of the ceramic contained in the first end face and the second end face of the inner layer is the same as or larger than the particle size of the ceramic contained in the central part of the inner layer.

[0277] <2> according to <1> The described laminated ceramic electronic components, among which,

[0278] The plurality of dielectric layers include: a first dielectric layer disposed between the first inner electrode layer and the second inner electrode layer opposite each other in the stacking direction; and a second dielectric layer disposed on the inner layer portion.

[0279] The ceramic particles contained in the first and second side surfaces of the first dielectric layer are smaller than the ceramic particles contained in the central portion of the laminate in the width direction.

[0280] The particle size of the ceramic contained in the second dielectric layer disposed on the first and second side surfaces is smaller than the particle size of the ceramic contained in the central portion of the laminate in the width direction.

[0281] <3> A laminated ceramic electronic component, comprising a laminate,

[0282] The laminate includes multiple stacked dielectric layers and multiple internal electrode layers, and has a first main surface and a second main surface opposite each other in the stacking direction, a first end surface and a second end surface opposite each other in the length direction intersecting the stacking direction, and a first side surface and a second side surface opposite each other in the width direction intersecting the stacking direction and the length direction.

[0283] The plurality of internal electrode layers have a first internal electrode layer exposed from the first end face and a second internal electrode layer exposed from the second end face.

[0284] The laminate has inner layers in which the first inner electrode layer and the second inner electrode layer face each other in the lamination direction.

[0285] The concentration of additives contained on the first and second side surfaces of the laminate is higher than the concentration of additives contained in the central portion of the laminate in the width direction.

[0286] The concentration of the additive contained in the first end face and the second end face of the inner layer is the same as or lower than the concentration of the additive contained in the central part of the inner layer.

[0287] <4> according to <3> The described laminated ceramic electronic components, among which,

[0288] The additive contains at least one of Ni, V, Sn, Mn, and Mg.

[0289] <5> according to <1> to <4> Among the laminated ceramic electronic components described in any one of them,

[0290] The particle size of the ceramics contained on the first and second side surfaces of the laminate is 10% to 40% smaller than the particle size of the ceramics contained in the central portion of the laminate in the width direction.

[0291] The particle size of the ceramic contained in the first end face and the second end face of the inner layer is 10% to 40% larger than the particle size of the ceramic contained in the central part of the inner layer.

[0292] <6> according to <3> or <4> The described laminated ceramic electronic components, among which,

[0293] The concentration of the additive contained in the first and second side surfaces of the laminate is 100.1 mol% or more and 103.0 mol% or less of the concentration of the additive contained in the central portion of the laminate in the width direction.

[0294] The concentration of the additive contained in the first end face and the second end face of the inner layer is less than 100 mol% and more than 97.0 mol% of the concentration of the additive contained in the central part of the inner layer.

[0295] <7> according to <3> , <4> as well as <6> Among the laminated ceramic electronic components described in any one of them,

[0296] The high concentration range of the additive is from the end of the first side surface of the inner layer towards the center in the width direction, which is 0 μm or more and 80 μm or less.

[0297] The concentration of the additive is high in the range of 0 μm or more and 80 μm or less from the end of the second side of the inner layer toward the center in the width direction.

[0298] <8> according to <1> to <7> Among the laminated ceramic electronic components described in any one of them,

[0299] The laminate has an outer layer made of a dielectric material.

[0300] The outer layer includes:

[0301] The first main surface side outer layer is disposed between the first main surface side surface and the first main surface of the inner layer;

[0302] The second main surface side outer layer is disposed between the second main surface side surface and the second main surface of the inner layer;

[0303] The first side outer layer is disposed between the first side side surface and the first side surface of the inner layer;

[0304] The second side outer layer is disposed between the second side side surface and the second side surface of the inner layer;

[0305] The outer layer portion on the first end face side is disposed between the first end face side surface and the first end face of the inner layer portion; and

[0306] The outer layer portion on the second end face side is disposed between the second end face side surface and the second end face of the inner layer portion.

[0307] The outer layer of the side surface has an inner layer disposed on the inner layer side, and an outer layer disposed on the first side surface and the second side surface relative to the inner layer.

[0308] The outer layer contains more Si than the inner layer.

[0309] The outer layer contains less of at least one of the additives selected from Ni, V, Sn, Mn, and Mg than the inner layer contains of the same additive.

[0310] <9> according to <8> The described laminated ceramic electronic components, among which,

[0311] The ratio of the number of mol of Si to the number of mol of Ti in the outer side layer is greater than 1.0 and less than 7.0.

[0312] <10> according to <8> or <9> The described laminated ceramic electronic components, among which,

[0313] The dimension of the outer side layer along the width direction is more than 5 μm and less than 40 μm.

[0314] Explanation of reference numerals in the attached figures

[0315] 1: Multilayer ceramic capacitors (multilayer ceramic electronic components)

[0316] 2: Layered body

[0317] 3: Outer dielectric layer

[0318] 4: Inner dielectric layer

[0319] 6a: First inner electrode layer

[0320] 6b: Second inner electrode layer

[0321] 10: Inner layer

[0322] 40: Core of the laminated body

[0323] IL: Inner Scope

[0324] OL1: Outer layer of the first main surface

[0325] OL2: Outer layer of the second main surface

[0326] LF: L Opposite Part

[0327] LG1: Outer layer on the first end face

[0328] LG2: Outer layer on the second end face

[0329] WF: W Opposite Part

[0330] WG1: First side outer layer

[0331] WG2: Second side outer layer

[0332] E1: First end face

[0333] E2: Second end face

[0334] S1: First side

[0335] S2: Second side

[0336] T: Stacking direction

[0337] W: Width direction.

Claims

1. A laminated ceramic electronic component, comprising a laminate, The laminate includes multiple stacked dielectric layers and multiple internal electrode layers, and has a first main surface and a second main surface opposite each other in the stacking direction, a first end surface and a second end surface opposite each other in the length direction intersecting the stacking direction, and a first side surface and a second side surface opposite each other in the width direction intersecting the stacking direction and the length direction. The plurality of internal electrode layers have a first internal electrode layer exposed from the first end face and a second internal electrode layer exposed from the second end face. The laminate has inner layers in which the first inner electrode layer and the second inner electrode layer are opposed to each other in the lamination direction. The ceramic particles contained on the first and second side surfaces of the laminate are smaller than the ceramic particles contained in the central portion of the laminate in the width direction. The particle size of the ceramic contained in the first end face and the second end face of the inner layer is the same as or larger than the particle size of the ceramic contained in the central part of the inner layer.

2. The laminated ceramic electronic component according to claim 1, wherein, The plurality of dielectric layers include: a first dielectric layer disposed between the first inner electrode layer and the second inner electrode layer opposite each other in the stacking direction; and a second dielectric layer disposed on the inner layer portion. The ceramic particles contained in the first and second side surfaces of the first dielectric layer are smaller than the ceramic particles contained in the central portion of the laminate in the width direction. The particle size of the ceramic contained in the second dielectric layer disposed on the first and second side surfaces is smaller than the particle size of the ceramic contained in the central portion of the laminate in the width direction.

3. A laminated ceramic electronic component, comprising a laminate, The laminate includes multiple stacked dielectric layers and multiple internal electrode layers, and has a first main surface and a second main surface opposite each other in the stacking direction, a first end surface and a second end surface opposite each other in the length direction intersecting the stacking direction, and a first side surface and a second side surface opposite each other in the width direction intersecting the stacking direction and the length direction. The plurality of internal electrode layers have a first internal electrode layer exposed from the first end face and a second internal electrode layer exposed from the second end face. The laminate has inner layers in which the first inner electrode layer and the second inner electrode layer are opposed to each other in the lamination direction. The concentration of additives contained on the first and second side surfaces of the laminate is higher than the concentration of additives contained in the central portion of the laminate in the width direction. The concentration of the additive contained in the first end face and the second end face of the inner layer is the same as or lower than the concentration of the additive contained in the central part of the inner layer.

4. The laminated ceramic electronic component according to claim 3, wherein, The additive contains at least one of Ni, V, Sn, Mn, and Mg.

5. The laminated ceramic electronic component according to any one of claims 1 to 4, wherein, The particle size of the ceramics contained on the first and second side surfaces of the laminate is 10% to 40% smaller than the particle size of the ceramics contained in the central portion of the laminate in the width direction. The particle size of the ceramic contained in the first end face and the second end face of the inner layer is 10% to 40% larger than the particle size of the ceramic contained in the central part of the inner layer.

6. The laminated ceramic electronic component according to claim 3 or 4, wherein, The concentration of the additive contained in the first and second side surfaces of the laminate is 100.1 mol% or more and 103.0 mol% or less of the concentration of the additive contained in the central portion of the laminate in the width direction. The concentration of the additive contained in the first end face and the second end face of the inner layer is less than 100 mol% and more than 97.0 mol% of the concentration of the additive contained in the central part of the inner layer.

7. The laminated ceramic electronic component according to any one of claims 3, 4, and 6, wherein, The high concentration range of the additive is from the end of the first side surface of the inner layer towards the center in the width direction, which is 0 μm or more and 80 μm or less. The concentration of the additive is high in the range of 0 μm or more and 80 μm or less from the end of the second side of the inner layer toward the center in the width direction.

8. The laminated ceramic electronic component according to any one of claims 1 to 7, wherein, The laminate has an outer layer made of a dielectric material. The outer layer includes: The first main surface side outer layer is disposed between the first main surface side surface and the first main surface of the inner layer; The second main surface side outer layer is disposed between the second main surface side surface and the second main surface of the inner layer; The first side outer layer is disposed between the first side side surface and the first side surface of the inner layer; The second side outer layer is disposed between the second side side surface and the second side surface of the inner layer; The outer layer portion on the first end face side is disposed between the first end face side surface and the first end face of the inner layer portion; and The outer layer portion on the second end face side is disposed between the second end face side surface and the second end face of the inner layer portion. The outer layer of the side surface has an inner layer disposed on the inner layer side, and an outer layer disposed on the first side surface and the second side surface relative to the inner layer. The outer layer contains more Si than the inner layer. The outer layer contains less of at least one of the additives selected from Ni, V, Sn, Mn, and Mg than the inner layer contains of the same additive.

9. The laminated ceramic electronic component according to claim 8, wherein, The ratio of the number of mol of Si to the number of mol of Ti in the outer side layer is greater than 1.0 and less than 7.

0.

10. The laminated ceramic electronic component according to claim 8 or 9, wherein, The dimension of the outer side layer along the width direction is more than 5 μm and less than 40 μm.

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