Multilayer ceramic capacitors
By designing specific dimensions and recessed structures in the central part of the laminated ceramic capacitor, the problem of insufficient flux cleaning was solved, achieving effective flux cleaning and reducing the occurrence of undesirable conditions.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- MURATA MFG CO LTD
- Filing Date
- 2024-11-06
- Publication Date
- 2026-05-26
AI Technical Summary
In existing multilayer ceramic capacitors, insufficient flux cleaning after mounting on a substrate can lead to defects such as poor appearance and short circuits.
In the design of multilayer ceramic capacitors, the stacked dimension between the main face and the end face in the central part of the width direction is smaller than that at both ends, and a recess is formed on the end face to increase the space for flux cleaning fluid to enter.
It improves the cleaning effect of flux, reduces residues, and lowers the probability of appearance defects and short circuits.
Smart Images
Figure CN122095449A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to multilayer ceramic capacitors. Background Technology
[0002] A multilayer ceramic capacitor, comprising alternating layers of dielectric layers and internal electrodes, and external electrodes electrically connected to the internal electrodes, is mounted on a substrate for use. In this case, the multilayer ceramic capacitor is mounted to the substrate using solder; however, due to the flux components contained in the solder paste, the function of the multilayer ceramic capacitor may be compromised. To reduce the possibility of this compromise, the flux is removed from the multilayer ceramic capacitor using a flux cleaning solution after mounting it to the substrate (see Patent Document 1).
[0003] Prior art literature
[0004] Patent documents
[0005] Patent Document 1: Japanese Patent Application Publication No. 2020-202335 Summary of the Invention
[0006] The problem the invention aims to solve
[0007] However, in conventional multilayer ceramic capacitors, the space between the substrate and the laminate is narrow, making it difficult for flux cleaning fluid to penetrate. Therefore, the removal of flux using flux cleaning fluid is sometimes insufficient.
[0008] The objective of this invention is to provide a multilayer ceramic capacitor in which flux can be easily removed using a flux cleaning solution.
[0009] Technical solutions for solving the problem
[0010] To address the aforementioned problems, the present invention provides a multilayer ceramic capacitor comprising a multilayer body, a first external electrode, and a second external electrode. The multilayer body includes: a plurality of dielectric layers alternately stacked and a plurality of internal electrodes; a first main surface and a second main surface opposite to each other in the stacking direction; a first side surface and a second side surface opposite to each other in the width direction orthogonal to the stacking direction; and a first end surface and a second end surface opposite to each other in the length direction orthogonal to the stacking direction and the width direction. The plurality of internal electrodes have a first internal electrode leading to the first end surface and a second internal electrode leading to the second end surface. The first external electrode is disposed on the first end surface, and the second external electrode is disposed on the second end surface. In a cross-section of the multilayer body at its central portion in the width direction along the length direction and the stacking direction, the dimension of the stacking direction between the first main surface and the second main surface in the central portion of the length direction is smaller than the dimension of the stacking direction between the first main surface and the second main surface at both ends of the length direction.
[0011] Invention Effects
[0012] According to the present invention, a multilayer ceramic capacitor is provided in which flux can be easily removed using a flux cleaning solution. Attached Figure Description
[0013] Figure 1 This is a schematic three-dimensional view of the multilayer ceramic capacitor 1.
[0014] Figure 2 It is along Figure 1 A sectional view of WT at the center of line II-II, along the length direction L.
[0015] Figure 3 It is along Figure 1 LT section view at the center of line III-III, in the width direction W.
[0016] Figure 4 This is a table showing the results of investigating the occurrence of appearance defects and short-circuit defects in multilayer ceramic capacitors for different implementation methods and comparative methods.
[0017] Figure 5 This is a diagram illustrating a multilayer ceramic capacitor 1A according to a first modified embodiment of the present invention.
[0018] Figure 6 This is a diagram illustrating a multilayer ceramic capacitor 1B of the second variant of the present invention.
[0019] Figure 7 This is a diagram illustrating a multilayer ceramic capacitor 1C according to a third variation of the present invention.
[0020] Figure 8 This is a diagram illustrating a stacked ceramic capacitor 1D of the fourth variant of the present invention. Detailed Implementation
[0021] Hereinafter, the laminated ceramic capacitor 1 according to the embodiments of the present invention will be described. Figure 1 This is a schematic three-dimensional view of the multilayer ceramic capacitor 1.
[0022] (Laminated ceramic capacitor 1)
[0023] The multilayer ceramic capacitor 1 is generally rectangular parallelepiped and includes a multilayer body 2 and a pair of external electrodes 3 disposed at both ends of the multilayer body 2. The multilayer body 2 includes an inner layer 11 consisting of multiple dielectric layers 14 and multiple internal electrodes 15, and an outer layer 12.
[0024] In the following description, as a term indicating the orientation of the multilayer ceramic capacitor 1, the direction in which a pair of external electrodes 3 are disposed is designated as the length direction L. The direction in which the dielectric layer 14 and the internal electrode 15 are stacked is designated as the stacking direction T. The direction that intersects both the length direction L and the stacking direction T is designated as the width direction W. Furthermore, in the embodiment, the width direction W is orthogonal to both the length direction L and the stacking direction T.
[0025] Figure 2 It is along Figure 1 A cross-sectional view along the width direction W and the stacking direction T at the center of line II-II in the length direction L. This section will be referred to as the WT section below. Figure 3 It is along Figure 1 A cross-sectional view along the length direction L and the stacking direction at the center of line III-III in the width direction W. This section will be referred to as the LT section below.
[0026] Furthermore, in the following explanation, in Figure 2 Of the six outer peripheral surfaces of the stacked body 2 shown, one pair of peripheral surfaces opposite each other in the stacking direction T is designated as the first main surface A1 and the second main surface A2. Unless otherwise specified, they will be uniformly referred to as main surface A. Another pair of peripheral surfaces opposite each other in the width direction W is designated as the first side surface B1 and the second side surface B2. Unless otherwise specified, they will be uniformly referred to as side surface B. Finally, one pair of peripheral surfaces opposite each other in the length direction L is designated as the first end surface C1 and the second end surface C2. Unless otherwise specified, they will be uniformly referred to as end surface C.
[0027] The size of the multilayer ceramic capacitor 1 in the length direction L is shorter than the size in the width direction W. Regarding the size of the multilayer ceramic capacitor 1 of the embodiment, for example, the length direction L is 0.2 mm or more and 0.6 mm or less, the width direction W is 0.4 mm or more and 1 mm or less, and the stacking direction T is 0.1 mm or more and 0.9 mm or less, but it is not limited to these.
[0028] (Stacked body 2)
[0029] The stacked body 2 preferably has rounded corners at the corner portions and the ridge line portions. The corner portion is the portion where three faces of the stacked body 2 intersect, and the ridge line portion is the portion where two faces of the stacked body 2 intersect. In addition, fine irregularities different from the concave portion 20 described below may be formed on a part or all of the main surface A, the side surface B, and the end surface C.
[0030] As Figure 3 shown, the stacked body 2 of the embodiment is substantially a rectangular parallelepiped, but in the LT cross-section, the dimension T1 in the stacking direction T between the first main surface A1 and the second main surface A2 in the central portion of the length direction L is smaller than the dimension T2 in the stacking direction T between the first main surface A1 and the second main surface A2 at both ends of the length direction L.
[0031] In other words, in the LT cross-section of the stacked body 2 of the embodiment, the dimension T1 in the stacking direction T between the first main surface A1 and the second main surface A2 in the central portion of the length direction L is smaller than either the dimension T2 in the stacking direction T between the first main surface A1 and the second main surface A2 in the first end surface C1 or the dimension T2 in the stacking direction T between the first main surface A1 and the second main surface A2 in the second end surface C2.
[0032] Here, the central portion of the length direction L of the stacked body 2 is the central portion between the first end surface C1 and the second end surface C2 of the stacked body 2. That is, it is the position at 1 / 2 of the distance between the first end surface C1 and the second end surface C2 in the length direction L starting from one end surface C.
[0033] Similarly, the central portion of the width direction W of the stacked body 2 is the central portion between the first side surface B1 and the second side surface B2 of the stacked body 2. That is, it is the position at 1 / 2 of the distance between the first side surface B1 and the second side surface B2 in the width direction W starting from one side surface B. However, it is not limited to the position at 1 / 2 of the size in the width direction W, and it may be any position from the position at 1 / 3 of the size in the width direction W to the position at 2 / 3 of the size in the width direction W.
[0034] In the embodiment, since the first main surface A1 of the stacked body 2 is flat, a concave portion 20 is formed on the second main surface A2 of the stacked body 2 so that the central portion is recessed in the stacking direction T, resulting in T1 < T2. However, in Figure 2 In the WT cross-section shown, the contour of the second major surface A2 of the laminate 2 along the width direction W is a straight line.
[0035] The recess 20 on the side of the second major surface A2 is formed by Figure 3 In the LT cross-section shown, in at least a part from the central portion in the length direction L to both end portions in the length direction L, the dimension from the first major surface A1 to the second major surface A2 gradually increases. In the embodiment, the dimension from the first major surface A1 to the second major surface A2 gradually increases over the entire length between the central portion in the length direction L and the position of the end portion of the external electrode 3 on the major surface side.
[0036] In addition, T2 / T1 is preferably 1.01 or more, more preferably 1.033 or more and 1.201 or less.
[0037] Furthermore, T2 - T1 is preferably greater than the sum ΣTE of the dimensions (thickness of the internal electrode 15) TE in the stacking direction T of the first internal electrode 15A or the second internal electrode 15B ((T2 - T1) > ΣTE).
[0038] In addition, in the laminate 2, as Figure 1 shown, in the first side surface B1 and the second side surface B2, the dimension t1 in the stacking direction T between the first major surface A1 and the second major surface A2 at the central portion in the length direction L is smaller than the dimension t2 in the stacking direction T between the first major surface A1 and the second major surface A2 at both end portions in the length direction L. t2 / t1 is also preferably 1.01 or more, more preferably 1.033 or more and 1.201 or less.
[0039] (Observation method)
[0040] <Measurement method of T1 and T2>
[0041] The measurement of T1 and T2 can be carried out as follows.
[0042] (1) Grind the multilayer ceramic capacitor 1 along the LT cross-section to expose the LT cross-section at the 1 / 2 of the dimension in the width direction W. Then, observe the exposed LT cross-section using a microscope.
[0043] (2) In this LT cross-section, measure the shortest dimension in the stacking direction T between the first major surface A1 and the second major surface A2, and set it as T1.
[0044] (3) In this LT section, the dimension of the stacking direction T between the first main surface A1 and the second main surface A2 in the first end face C1 and the second end face C2 is measured. Then, the average value of the dimension of the stacking direction T between the first main surface A1 and the second main surface A2 in the first end face C1 and the second end face C2 is set as T2.
[0045] For the determination of t2 and t1, the side surface can be exposed by grinding, and then the same operation as for T1 and T2 can be performed to obtain them in the same way.
[0046] (Dielectric layer 14)
[0047] The dielectric layer 14 is primarily composed of a ceramic material containing at least one of Ca, Sr, Zr, and Ti. Specifically, for example, it is primarily composed of a ceramic material with a perovskite structure represented by the general formula ABO3, containing both Ca and Zr. Examples of such perovskite-structured ceramic materials include, but are not limited to, CaZrO3 (calcium zirconate) and TiO2 (titanium oxide). Furthermore, the main component of the ceramic material forming the dielectric layer 14 may include all of Ca, Zr, and Ti. In addition, in CaZrO3, Ca(Zr0.9Ti0.1)O3, in which a portion of ZrO3 or Zr is replaced with Ti, may also be used.
[0048] In addition, as the ceramic material forming the dielectric layer 14, (Ca1-xy, Srx, Bay)m(Zr1-z-α, Tiz, Hfα)O3 (where x is 0 or more and 1 or less, y is 0 or more and 0.4 or less, m is 1.0 or more and 1.1 or less, z is 0 or more and 0.2 or less, and α is 0 or more and 0.3 or less) can also be used.
[0049] Additives are added to the ceramic material forming the dielectric layer 14, depending on the purpose. Examples of such additives include oxides of rare earth elements such as Mn, Mg, Dy, Cr, V, Sm, Eu, Gd, Tb, Ho, Er, Tm, Yb, Y, or oxides of Co, Ni, Li, B, Na, K, and Si, or glass.
[0050] The thickness of the dielectric layer 14 can be determined by measuring the distance between two adjacent first internal electrodes 15A or the distance between two adjacent second internal electrodes 15B, and is, for example, more than 1 μm and less than 100 μm.
[0051] (Internal electrode 15)
[0052] The plurality of internal electrodes 15 have a first internal electrode 15A extending to a first end face C1 and a second internal electrode 15B extending to a second end face C2. The number of the first internal electrode 15A and the second internal electrode 15B is, for example, more than 1 and less than 50, but is not limited thereto.
[0053] In the implementation method, such as Figure 3 As shown, the first internal electrode 15A and the second internal electrode 15B do not overlap each other in the stacking direction T, and the total length direction L of the first internal electrode 15A and the second internal electrode 15B is less than the length direction L of the laminate 2.
[0054] Furthermore, the first internal electrode 15A and the second internal electrode 15B exist on the same surface. That is, both the first internal electrode 15A and the second internal electrode 15B have a length direction L that is less than half the length direction L of the laminate 2, and are arranged side by side in a plane (within the LW cross section) along both the length direction L and the width direction W. In other words, the laminated ceramic capacitor 1 of the embodiment has a so-called mating structure with a gap between the first internal electrode 15A and the second internal electrode 15B in the length direction L.
[0055] Furthermore, the dimension L15 of the internal electrode 15 in the length direction can also be shorter than the average dimension L3 of the external electrode 3 (folded-back portion) disposed on the main surface A in the length direction. Specifically, in the LT cross section, the dimension L15A of the first internal electrode 15A in the length direction can also be smaller than the average dimension L3A of the first external electrode 3A disposed on the first main surface A1 and the second main surface A2 in the length direction. Moreover, the dimension L15B of the second internal electrode 15B in the length direction can also be smaller than the average dimension L3B of the second external electrode 3B disposed on the first main surface A1 and the second main surface A2 in the length direction.
[0056] By making the length L of the internal electrode 15 shorter than the average length L of the external electrode 3 disposed on the main surface A, the possibility of the first internal electrode 15A contacting the second external electrode 3B, and the second internal electrode 15B contacting the first external electrode 3A, can be greatly reduced. This reduces the likelihood of short-circuit failure.
[0057] exist Figure 3 In the LT cross-section shown, the distance L1 between the second end face C2 side end of the first internal electrode 15A and the first end face C1 side end of the second internal electrode 15B is preferably 5 μm or more and 400 μm or less.
[0058] The internal electrode 15 is a conductive thin film comprising at least one of Ni, Cu, Ag, Pd, an alloy of Ag and Pd, and metals such as Au. To improve the frequency characteristics of the multilayer ceramic capacitor 1, Cu is preferably used as the internal electrode 15. The internal electrode 15 may also further comprise dielectric particles of the same composition as the ceramic contained in the dielectric layer 14.
[0059] More specifically, the internal electrode 15 may contain Cu, and the base electrode of the external electrode 3 described later may contain Cu; alternatively, the internal electrode 15 may contain Ni, and the base electrode of the external electrode 3 described later may contain Ni.
[0060] The thickness of each of the internal electrodes 15 is preferably 0.5 μm or more and 10 μm or less.
[0061] (Outer layer 12)
[0062] The outer layer 12 is an assembly of multiple dielectric layers 14 made of the same dielectric ceramic material as the dielectric layer 14 of the inner layer 11. However, it is not limited to this, and the outer layer 12 may also use a different dielectric ceramic material than the dielectric layers 14.
[0063] (External electrode 3)
[0064] The external electrode 3 includes a first external electrode 3A and a second external electrode 3B. The first external electrode 3A is configured to cover the first end face C1 of the laminate 2 and is connected to the first internal electrode 15A that extends to the first end face C1. The first external electrode 3A is preferably configured to reach a portion of the first main surface A1 and the second main surface A2, and a portion of the first side surface B1 and the second side surface B2. However, it may also be disposed only on the first end face C1.
[0065] The second external electrode 3B is configured to cover the second end face C2 of the laminate 2 and is connected to the second internal electrode 15B that extends to the second end face C2. The second external electrode 3B is preferably configured to reach a portion of the first main surface A1 and the second main surface A2, and a portion of the first side surface B1 and the second side surface B2. However, it may also be configured only on the second end face C2.
[0066] Hereinafter, without specifically distinguishing between the first external electrode 3A and the second external electrode 3B, they will be uniformly referred to as external electrode 3. External electrode 3 includes a base electrode layer 31 and a plating layer 32.
[0067] (Base electrode layer 31)
[0068] The substrate electrode layer 31 includes at least one selected from the sintered layer, resin layer, thin film layer, etc. The substrate electrode layer 31 is configured to cover the end face C of the laminate 2 and is connected to the internal electrode 15 led out to the end face C.
[0069] (The case where the substrate electrode layer 31 includes a sintered layer)
[0070] The sintered layer comprises a glass component and a metal. The glass component includes at least one selected from B, Si, Ba, Mg, Al, Li, etc. The metal used as the sintered layer includes, for example, at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The sintered layer can also be multilayered. The sintered layer is formed by applying a conductive paste containing glass and metal to the laminate 2 and then sintering it. It can also be a sintered layer that is sintered simultaneously with the internal electrode 15 and the dielectric layer 14, or it can be sintered after the internal electrode 15 is sintered. In the case of sintering simultaneously with the internal electrode 15 and the dielectric layer 14, it is preferable to add a dielectric material instead of a glass component to form the sintered layer. The thickness of the thickest part of the sintered layer is preferably, for example, 5 μm or more and 50 μm or less.
[0071] (In the case where the substrate electrode layer 31 includes a resin layer)
[0072] The resin layer can also be multilayered. For example, the resin layer may contain conductive particles and a thermosetting resin. When forming the resin layer, it may be formed directly on the laminate 2 without forming a sintered electrode layer, or the resin layer may be formed as a coated sintered layer. The resin layer may be formed on the surface of the sintered layer, or it may be formed directly on the surface of end face C without forming a sintered layer. The thickness of the resin layer (thickest part) is preferably 5 μm or more and 150 μm or less.
[0073] (The case where the substrate electrode layer 31 includes a thin film layer)
[0074] The thin film layer is formed by thin film formation methods such as sputtering or vapor deposition, and is a layer with metal particles deposited at a depth of less than 1 μm.
[0075] (Coating layer 32)
[0076] The plating layer 32 is configured to cover the substrate electrode layer 31. The plating layer 32 may, for example, comprise at least one selected from Cu, Ni, Sn, Ag, Pd, Ag-Pd alloys, Au, etc. The plating layer 32 may also be formed in multiple layers.
[0077] Preferably, it has a two-layer structure of Ni plating 321 and Sn plating 322. Ni plating layer 321 can prevent the base electrode layer 31 from being eroded by solder when mounting ceramic electronic components, and Sn plating layer 322 can improve the wettability of solder when mounting ceramic electronic components, making it easier to mount. The thickness of each plating layer 32 is preferably 0.5 μm or more and 10 μm or less.
[0078] (Manufacturing method of multilayer ceramic capacitor 1)
[0079] As an example, the multilayer ceramic capacitor 1 of the embodiment can be manufactured through the following process.
[0080] (1) Ceramic green slab preparation process
[0081] First, a conductive material such as conductive paste, which becomes the internal electrode 15, is printed onto a ceramic green sheet or other ceramic material that becomes the dielectric layer 14, in order to form a ceramic green sheet with an internal electrode pattern.
[0082] (2) Lamination process
[0083] A ceramic green sheet with an internal electrode pattern is stacked and then further stacked on top of it to form a ceramic green sheet without an internal electrode pattern in the outer layer 12 to form a master block.
[0084] (3) Pressing process
[0085] Next, the master block is pressed. During pressing, rubber or the like is used to press from the surface that becomes the second master surface A2 toward the first master surface A1. At this time, by making the pressure near the center of the laminate 2 in the length direction L greater than the pressure at the end of the length direction L, a recess 20 can be formed on the second master surface A2.
[0086] Here, the internal electrodes 15 of the laminated ceramic capacitor 1 in this embodiment have a butt joint structure. Therefore, the number of internal electrodes 15 and dielectric layers 14 laminated in the central portion along the length direction L is less than the number of laminated sheets of internal electrodes 15 and dielectric layers 14 in the end faces C where the first internal electrode 15A and the second internal electrode 15B are led out. Furthermore, in the pressing process, the pressure near the central portion along the length direction L of the laminate 2 is made greater than the pressure at the ends along the length direction L.
[0087] Therefore, in this pressing process, the dimension of the stacking direction T in the central part of the length direction L of the laminate 2 is smaller than the dimension of the stacking direction T in the end face C, making it easier to form a recess 20 in the central part of the length direction L of the second main face A2.
[0088] In addition to this manufacturing method, the recess 20 can also be formed by thinning the thickness of the dielectric layer 14 in the portion forming the recess 20, or by removing the portion of the dielectric layer 14 used for the outer layer of the unprinted internal electrode 15.
[0089] (4) Cutting process
[0090] The pressed master block is cut to a given size to obtain an unfired laminate 2.
[0091] (5) Firing process
[0092] Next, the laminate 2 is fired.
[0093] (6) External electrode formation process
[0094] Next, the external electrode 3 is formed by sintering, plating, etc. Alternatively, the external electrode 3 can also be formed by sintering part or all of it simultaneously with the sintering of the laminate 2, in addition to plating.
[0095] Through the above processes, the multilayer ceramic capacitor 1 of the embodiment is manufactured.
[0096] (Installation of multilayer ceramic capacitor 1)
[0097] Regarding the multilayer ceramic capacitor 1, one external electrode 3 (first external electrode 3A) is connected to one pad 51 via solder 52, and another external electrode 3 (second external electrode 3B) is connected to another pad 51 via solder 52. Thus, the multilayer ceramic capacitor 1 of this embodiment is mounted on a substrate. Furthermore, the surface of the substrate 50, except for the pads 51, is covered with an insulating film formed of solder resist, leaving a given mounting area.
[0098] Here, flux is used to promote soldering when the multilayer ceramic capacitor 1 is soldered to the substrate 50. Then, after being mounted on the substrate, the multilayer ceramic capacitor 1 is cleaned to remove the flux.
[0099] However, sometimes flux residue remains due to insufficient cleaning. If residual flux is present, when a voltage is applied between the electrodes of the multilayer ceramic capacitor 1, the anolyte metal is ionized and transferred to the cathode. If electrons are received at the cathode, an electrochemical phenomenon of metal deposition / growth, i.e., migration, occurs, which may cause poor appearance and short circuit problems.
[0100] (Effect of the stacked ceramic capacitor 1 in the embodiment)
[0101] like Figure 3As shown, in the LT cross-section of the stacked ceramic capacitor 1 of the embodiment, the dimension T1 of the stacking direction T between the first main surface A1 and the second main surface A2 in the central part of the length direction L is smaller than the dimension T2 of the stacking direction T between the first main surface A1 and the second main surface A2 at both ends of the length direction L. Furthermore, since the first main surface A1 of the stacked body 2 is flat, a recess 20 is formed on the second main surface A2 of the stacked body 2, with its central part recessed in the stacking direction T, such that T1... <T2。
[0102] Therefore, the space S between the portion of the laminate 2 on the second main surface A2 side (which serves as the substrate mounting side) where the external electrode 3 is not formed and the substrate 50 becomes larger. As a result, flux cleaning solution can more easily penetrate between the laminated ceramic capacitor 1 and the substrate, reducing residue caused by insufficient cleaning. Consequently, undesirable conditions arising from residual flux can be suppressed.
[0103] At this point, if T2 / T1 is 1.01 or higher, the cleaning performance of the cleaning solution becomes good; if it is 1.033 or higher and 1.201 or lower, it becomes even better.
[0104] Furthermore, such as Figure 1 As shown, in the first side surface B1 and the second side surface B2, the dimension t1 of the stacking direction T between the first main surface A1 and the second main surface A2 in the central part of the length direction L of the laminate 2 is smaller than the dimension t2 of the stacking direction T between the first main surface A1 and the second main surface A2 in the two ends of the length direction L.
[0105] Therefore, the inlet and outlet of flux cleaning fluid into space S in the first side B1 and the second side B2 become larger. Consequently, flux cleaning fluid from the outside becomes easier to flow into / out of space S, improving the cleaning effect on flux. As a result, undesirable conditions caused by residual flux can be further suppressed.
[0106] In the above-described embodiment of the multilayer ceramic capacitor 1, the flux cleaning solution easily penetrates between the multilayer ceramic capacitor 1 and the substrate, thus reducing residue caused by insufficient cleaning. As a result, undesirable conditions arising from residual flux can be suppressed.
[0107] (Verification of the cleaning effect of the stacked ceramic capacitor 1 according to the embodiment)
[0108] To verify the above effects, the occurrence of appearance defects and short circuit defects caused by migration defects was investigated in the prepared multilayer ceramic capacitor 1 of the embodiment and the comparative multilayer ceramic capacitor.
[0109] (Verification method)
[0110] (1) The following were manufactured according to the above manufacturing method: Figure 3 As shown, in the LT cross-section at the center of the width direction W, the dimension T1 of the stacking direction T between the first main surface A1 and the second main surface A2 at the center of the length direction L is smaller than the dimension T2 of the stacking direction T between the first main surface A1 and the second main surface A2 at both ends of the length direction L, and T2 / T1 is 1.01 or higher. This relates to the stacked ceramic capacitor 1 of Embodiments 1, 2, 3, 4, 5, 6, and 7, and the stacked ceramic capacitor of Comparative Example 1, where T1 is slightly larger than T2 and T2 / T1 is 0.998. The dimensions of T1, T2, and T2 / T1 of each are shown in the figure. Figure 4 The table.
[0111] However, in the multilayer ceramic capacitor 1 of Comparative Example 1, the ceramic green sheets are stacked such that the internal electrodes 15 adjacent to each other in the stacking direction T at the center of the length direction L overlap each other, and the stacked sheets are uniformly pressed during pressing.
[0112] (2) 72 stacked ceramic capacitors were randomly selected from Comparative Example 1 and from Examples 1, 2, 3, 4, 5, 6, and 7, and their appearance and structural defects were observed using an optical microscope. The stacked ceramic capacitors with structural defects were counted, and the total number of stacked ceramic capacitors used for verification was used as the denominator to calculate the structural defect rate. The results are shown below. Figure 4 The "construction defect rate".
[0113] In Example 7, where the T2 / T1 ratio is 1.53, the defect rate is 2 / 72, but in Comparative Example 1 and Examples 1, 2, 3, 4, 5, and 6, the defect rate is 0 / 72. It can be assumed that the defect rate in Example 7 is higher than in other examples because the dielectric layer 14 is excessively stretched during the pressing process, resulting in cracks and fissures due to firing in this state.
[0114] (3) Next, the 72 multilayer ceramic capacitors used in (2) were mounted on the substrate and subjected to a moisture resistance test. The moisture resistance test was conducted by applying a voltage of 25V to the substrate on which the multilayer ceramic capacitors were mounted for 200 hours at a humidity of 95% and a temperature of 120°C.
[0115] (4) The appearance of the multilayer ceramic capacitors mounted on the substrate of (3) is observed using an optical microscope. Multilayer ceramic capacitors on the surface of the multilayer 2 where metal has been deposited without the formation of the first external electrode 3A and the second external electrode 3B are counted as migration defects. The migration defect rate is calculated by using the total number of multilayer ceramic capacitors used for verification as the denominator. The results are shown in Figure 4 The "migration failure rate".
[0116] The migration defect rate in Comparative Example 1 was as high as 32 / 72. The migration defect rate in Example 1 was 9 / 72. The migration defect rates in Examples 2, 3, 4, 5, 6, and 7 were 0 / 72.
[0117] The judgment result based on the above verification results is shown below. Figure 4 .exist Figure 4 In the diagram, the judgment result of a migration defect rate of 0 / 72 and a construction defect rate of 0 / 72 is indicated by a double circle (◎), the judgment result of a migration defect rate or a construction defect rate of 0 / 72 and a defect rate of 10 / 72 or less is indicated by a single circle (〇), and the judgment result of a migration defect rate or a construction defect rate of more than 10 / 72 is indicated by a cross (×).
[0118] like Figure 4 As shown, if the value of T2 / T1 is less than 1.0, as in Comparative Example 1, poor migration is likely to occur. However, in the embodiment, a T2 / T1 value of 1.010 or higher, which is a preferred range, was found to have a good effect in suppressing poor migration. Furthermore, in the embodiment, a T2 / T1 value of 1.033 or higher and 1.201 or lower, which is a more preferred range, was found to have a good effect in suppressing defects in construction.
[0119] (Deformation method)
[0120] The embodiments of the multilayer ceramic capacitor 1 have been described above, but the present invention is not limited to the above, and various modifications as described below are also within the scope of the present invention.
[0121] (First type of transformation)
[0122] In the implementation method, such as Figure 2 As shown, in the WT section at the center of the length direction L, the dimension of the stacking direction T between the first main surface A1 and the second main surface A2 is fixed from the position at 1 / 2 of the dimension of the width direction W to the two ends of the width direction W (the first and second side surfaces B2).
[0123] However, it is not limited to this. Figure 5 This diagram illustrates a multilayer ceramic capacitor 1A according to a first variation of the present invention. As shown, it can also be constructed in which the dimension of the stacking direction T between the first main surface A1 and the second main surface A2 gradually decreases from the center of the width direction W to both ends of the width direction W (the first side surface B1 and the second side surface B2). In this case, the center of the width direction W of both the first main surface A1 and the second main surface A2 can also be convex.
[0124] In the first modified version of the multilayer ceramic capacitor 1A, the same effect as in the embodiment can be obtained. Furthermore, according to the first modified version of the multilayer ceramic capacitor 1A, the ratio of the flux cleaning liquid inlet to the outlet of the space S is... Figure 2 The multilayer ceramic capacitor 1 shown is large. Therefore, flux cleaning fluid becomes easier to flow in / out through space S, further improving cleaning performance.
[0125] Furthermore, in the first deformation mode, the first main surface A1 and the second main surface A2 have the same shape. Therefore, either the first or the second main surface A2 can be selected as the mounting surface.
[0126] (Second variation)
[0127] In the implementation method, such as Figure 3 As shown, in the LT section, the outline of the recess 20 formed on the side of the second main surface A2 is a circular arc or an elliptical arc shape.
[0128] However, it is not limited to this. Figure 6 This is a diagram illustrating a multilayer ceramic capacitor 1B according to a second variation of the present invention. As shown, the outline of the recess 20 formed on the second main surface A2 side can also be the shape of a triangle with the center of the width direction W as the vertex, i.e., two straight lines. In the multilayer ceramic capacitor 1B of the second variation, the same effect as in the embodiment can also be obtained.
[0129] (Third variation)
[0130] In the implementation method, such as Figure 3 As shown, the first main surface A1 is flat, and the second main surface A2, which serves as the mounting side of the substrate, is recessed in the lamination direction T to form a recess 20, but is not limited to this.
[0131] Figure 7 This diagram illustrates a third modified version of the multilayer ceramic capacitor 1C. In this third modified version, both the first main surface A1 and the second main surface A2, which serves as the substrate mounting side, are recessed in the lamination direction T. This third modified version of the multilayer ceramic capacitor 1C also exhibits the same effects as the embodiment.
[0132] (4th transformation method)
[0133] In the implementation method, such as Figure 3 As shown, the first main surface A1 is flat, and the second main surface A2, which serves as the mounting side of the substrate, is recessed in the lamination direction T to form a recess 20. The outline of the recess 20 is a smooth arc or elliptical arc shape, but is not limited to this.
[0134] Figure 8This diagram illustrates a stacked ceramic capacitor 1D with a fourth deformation. The stacked ceramic capacitor 1D with the fourth deformation may also have both the first main surface A1 and the second main surface A2, which serves as a substrate mounting side, recessed in the stacking direction T. Furthermore, the outline of the recess 20 in the fourth deformation is... Figure 8 In the cross-section shown, the outline of the recess 20 can also be the shape of two sides of a triangle with the center of the width direction W as the vertex, i.e., two straight lines. The same effect is achieved in the fourth modified version of the multilayer ceramic capacitor 1D as in the embodiment.
[0135] The embodiments of the present invention have been described above. The present invention is not limited to the aforementioned embodiments and various modifications and variations are possible.
[0136] <1> A multilayer ceramic capacitor includes a multilayer body, a first external electrode, and a second external electrode.
[0137] The laminate has:
[0138] Multiple dielectric layers and multiple internal electrodes are stacked alternately.
[0139] The first and second principal faces are opposite each other in the stacking direction;
[0140] The first and second side surfaces, which are opposite each other in the width direction orthogonal to the stacking direction; and
[0141] The first end face and the second end face are opposite each other in the length direction orthogonal to the stacking direction and the width direction.
[0142] The plurality of internal electrodes have a first internal electrode led out to the first end face and a second internal electrode led out to the second end face.
[0143] The first external electrode is disposed on the first end face.
[0144] The second external electrode is disposed on the second end face.
[0145] in,
[0146] In a cross-section along the length direction and the stacking direction at the central portion of the laminate in the width direction, the dimension of the stacking direction between the first main surface and the second main surface in the central portion of the length direction is smaller than the dimension of the stacking direction between the first main surface and the second main surface at both ends of the length direction.
[0147] <2> according to <1> The described multilayer ceramic capacitors, among which,
[0148] The dimension of the laminate in the length direction is shorter than the dimension in the width direction.
[0149] <3> according to <1> or <2> The described multilayer ceramic capacitors, among which,
[0150] The dimension of the laminate in the central portion of the length direction between the first main surface and the second main surface in the first and second side surfaces is smaller than the dimension of the laminate in the length direction between the first main surface and the second main surface at both ends.
[0151] <4> according to <1> to <3> Among the multilayer ceramic capacitors described in any one of the following,
[0152] In a cross-section along the length direction and the stacking direction at the central portion of the laminate in the width direction, the dimension between the first main surface and the second main surface gradually increases in at least a portion from the central portion of the length direction to both ends of the length direction.
[0153] <5> according to <1> to <4> Among the multilayer ceramic capacitors described in any one of the following,
[0154] The first internal electrode and the second internal electrode do not overlap each other in the stacking direction.
[0155] <6> according to <1> to <5> Among the multilayer ceramic capacitors described in any one of the following,
[0156] The combined length dimension of the first internal electrode and the second internal electrode is less than the length dimension of the laminate.
[0157] <7> according to <1> to <6> Among the multilayer ceramic capacitors described in any one of the following,
[0158] The first external electrode is configured to extend from the first end face to a portion of the first main face and a portion of the second end face.
[0159] The second external electrode is configured to extend from the second end face to a portion of the first main face and a portion of the second end face.
[0160] The length dimension of the first inner electrode is shorter than the average length dimension of the first outer electrode disposed on the first main surface and the second main surface.
[0161] The length dimension of the second inner electrode is shorter than the average length dimension of the second outer electrode disposed on the first main surface and the second main surface.
[0162] <8> according to <1> to <7> Among the multilayer ceramic capacitors described in any one of the following,
[0163] The first internal electrode and the second internal electrode exist on the same surface along the width direction and the length direction.
[0164] <9> according to <1> to <8> Among the multilayer ceramic capacitors described in any one of the following,
[0165] The dielectric layer comprises at least one of Ca, Sr, Zr, and Ti.
[0166] <10> according to <1> to <9> Among the multilayer ceramic capacitors described in any one of the following,
[0167] The first internal electrode, the second internal electrode, the first external electrode, and the second external electrode comprise at least one of Ni, Cu, Ag, Pd, an alloy of Ag and Pd, and Au.
[0168] <11> according to <1> to <10> Among the multilayer ceramic capacitors described in any one of the following,
[0169] The first internal electrode and the second internal electrode contain Cu.
[0170] <12> according to <1> to <11> Among the multilayer ceramic capacitors described in any one of the following,
[0171] The first external electrode and the second external electrode comprise Cu and glass.
[0172] <13> according to <1> to <12> Among the multilayer ceramic capacitors described in any one of the following,
[0173] The first internal electrode and the second internal electrode contain Ni.
[0174] <14> according to <1> to <13> Among the multilayer ceramic capacitors described in any one of the following,
[0175] The first external electrode and the second external electrode contain Ni and ceramic components.
[0176] <15> according to <1> to <14> Among the multilayer ceramic capacitors described in any one of the following,
[0177] T2 / T1 is above 1.033 and below 1.201.
[0178] Explanation of reference numerals in the attached figures
[0179] A main surface
[0180] A1 1st main side
[0181] A2 Second Main Side
[0182] B Side
[0183] B1 First Side
[0184] B2 Second Side
[0185] C end face
[0186] C1 First end face
[0187] C2 Second end face
[0188] T stacking direction
[0189] W width direction
[0190] S Space
[0191] 1. Multilayer ceramic capacitor
[0192] 3 External Electrodes
[0193] 3A First External Electrode
[0194] 3B Second External Electrode
[0195] 11 Inner layer
[0196] 12 Outer layer
[0197] 14 Dielectric layer
[0198] 15 Internal Electrodes
[0199] 15A First Internal Electrode
[0200] 15B Second Internal Electrode
[0201] 20 concavity
[0202] 50 substrates
[0203] 51 pads
[0204] 52 Solder.
Claims
1. A multilayer ceramic capacitor comprising a laminate, a first external electrode, and a second external electrode. The laminate has: Multiple dielectric layers and multiple internal electrodes are stacked alternately. The first and second principal faces are opposite each other in the stacking direction; The first and second side surfaces, which are opposite each other in the width direction orthogonal to the stacking direction; and The first end face and the second end face are opposite each other in the length direction orthogonal to the stacking direction and the width direction. The plurality of internal electrodes have a first internal electrode led out to the first end face and a second internal electrode led out to the second end face. The first external electrode is disposed on the first end face. The second external electrode is disposed on the second end face. in, In a cross-section along the length direction and the stacking direction at the central portion of the laminate in the width direction, the dimension of the stacking direction between the first main surface and the second main surface in the central portion of the length direction is smaller than the dimension of the stacking direction between the first main surface and the second main surface at both ends of the length direction.
2. The multilayer ceramic capacitor according to claim 1, wherein, The dimension of the laminate in the length direction is shorter than the dimension in the width direction.
3. The multilayer ceramic capacitor according to claim 1 or 2, wherein, The dimension of the laminate in the central portion of the length direction between the first main surface and the second main surface in the first and second side surfaces is smaller than the dimension of the laminate in the length direction between the first main surface and the second main surface at both ends.
4. The multilayer ceramic capacitor according to any one of claims 1 to 3, wherein, In a cross-section along the length direction and the stacking direction at the central portion of the laminate in the width direction, the dimension between the first main surface and the second main surface gradually increases in at least a portion from the central portion of the length direction to both ends of the length direction.
5. The multilayer ceramic capacitor according to any one of claims 1 to 4, wherein, The first internal electrode and the second internal electrode do not overlap each other in the stacking direction.
6. The multilayer ceramic capacitor according to any one of claims 1 to 5, wherein, The combined length dimension of the first internal electrode and the second internal electrode is less than the length dimension of the laminate.
7. The multilayer ceramic capacitor according to any one of claims 1 to 6, wherein, The first external electrode is configured to extend from the first end face to a portion of the first main face and a portion of the second end face. The second external electrode is configured to extend from the second end face to a portion of the first main face and a portion of the second end face. The length dimension of the first inner electrode is shorter than the average length dimension of the first outer electrode disposed on the first main surface and the second main surface. The length dimension of the second inner electrode is shorter than the average length dimension of the second outer electrode disposed on the first main surface and the second main surface.
8. The multilayer ceramic capacitor according to any one of claims 1 to 7, wherein, The first internal electrode and the second internal electrode exist on the same surface along the width direction and the length direction.
9. The multilayer ceramic capacitor according to any one of claims 1 to 8, wherein, The dielectric layer comprises at least one of Ca, Sr, Zr, and Ti.
10. The multilayer ceramic capacitor according to any one of claims 1 to 9, wherein, The first internal electrode, the second internal electrode, the first external electrode, and the second external electrode comprise at least one of Ni, Cu, Ag, Pd, an alloy of Ag and Pd, and Au.
11. The multilayer ceramic capacitor according to any one of claims 1 to 10, wherein, The first internal electrode and the second internal electrode contain Cu.
12. The multilayer ceramic capacitor according to any one of claims 1 to 11, wherein, The first external electrode and the second external electrode comprise Cu and glass.
13. The multilayer ceramic capacitor according to any one of claims 1 to 12, wherein, The first internal electrode and the second internal electrode contain Ni.
14. The multilayer ceramic capacitor according to any one of claims 1 to 13, wherein, The first external electrode and the second external electrode contain Ni and ceramic components.
15. The multilayer ceramic capacitor according to any one of claims 1 to 14, wherein, T2 / T1 is above 1.033 and below 1.201.