Design method for code-based adjustable resolution and generalizable process SAR ADC
By dividing the entire SAR ADC circuit into four core models through code-based and parameterized design, rapid migration and parameterized design across process nodes are achieved, solving the problems of flexibility and process adaptability of SAR ADC, and improving circuit reuse rate and R&D efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- TSINGHUA UNIVERSITY
- Filing Date
- 2026-01-26
- Publication Date
- 2026-05-29
Smart Images
Figure CN122113804A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit design automation technology, and in particular to a design method and apparatus for a SAR ADC with adjustable resolution and generalizable process based on code implementation. Background Technology
[0002] With the rapid development of China's integrated circuit industry and the surge in chip design demand, successive approximation (SAR) ADCs, based on the core principle of bit-by-bit comparison, realize the conversion of analog signals to digital signals. With their significant advantages of simple structure, low power consumption, and small area, they dominate in low-to-medium speed (1M-10M) and low-to-medium precision (8bit-12bit) application scenarios such as industrial control, portable medical devices, and smart homes.
[0003] However, current mainstream SAR ADCs are generally hard-core products with fixed resolution and conversion rate, and the core module adopts an integrated design, which has three prominent drawbacks. First, the flexibility of resolution and conversion rate is insufficient. The bit depth and conversion rate of the capacitor DAC are hard-coded, which cannot flexibly adapt to the differentiated needs of different scenarios for 6-12 bit resolution and high and low data rates. Adjusting parameters requires redesigning the core circuit, with a development cycle of 3-6 months. Second, the process adaptability is poor. The product is deeply tied to a specific process node. As domestic chip processes upgrade from 180nm to 55nm and 12nm, the device characteristics of different process nodes are significantly different. Cross-process migration requires recalculating device parameters, adjusting the topology, and carrying out circuit simulation and timing optimization. The migration cost accounts for more than 50% of the cost of the new design, and the workload accounts for more than 60% of the workload of the new design. Third, the circuit reuse rate is low. The core module interface has no standardized definition. Adjusting the resolution requires simultaneous modification of multiple module circuits, which cannot adapt to the "small batch, multiple varieties" needs of domestic chip design companies.
[0004] The aforementioned shortcomings directly lead to a large amount of repetitive development work. When some domestic companies develop SAR ADCs of different resolutions, the amount of repetitive design work accounts for up to 70%, increasing the R&D cost of a single project by more than 200,000 yuan and extending the R&D cycle by 2-3 months. Ultimately, this results in the chip design industry generally facing the pain points of high costs and long R&D cycles, which seriously restricts the product iteration efficiency and market competitiveness of domestic electronic equipment manufacturers. As a result, SAR ADC soft core IPs with process generalization capabilities and high reusability have become an urgent market demand. Summary of the Invention
[0005] The main objective of this invention is to provide a design method for a SAR ADC with adjustable resolution and generalizable process based on code implementation.
[0006] Another objective of this invention is to provide a design device for a SARADC with adjustable resolution and generalizable process based on code implementation.
[0007] To achieve the above objectives, a first aspect of the present invention proposes a design method for a SAR ADC with adjustable resolution and generalizable process based on code implementation, comprising: S1 describes the entire SAR ADC circuit through coding and divides it into four core models. It defines process parameters and performance parameters as independent configurable parameters, so that the core logic of the circuit is completely decoupled from the parameters. S2 conducts targeted design for the four core models, optimizing the circuit from the dimensions of linearity improvement, noise suppression, multi-structure adaptation, and timing control, so that the parameters of each model can dynamically respond to the target process and performance requirements. S3 adopts a layout strategy with fixed topology variable spacing to keep the core model positional relationship unchanged, defines the model spacing as a configurable variable, and calls the routing rules of the corresponding process to achieve rapid generation of layout across process nodes; S4 constructs a general simulation verification platform. It reads process parameters and performance parameters from the configuration file through parameterized test vector generation model, automatically generates excitation signals and calls a standardized verification test case library. Combined with a unified data comparison model, it generates a verification report and completes the full-process simulation.
[0008] Optionally, the four core models include the adaptive capacitor DAC model, the adaptive comparator model, the parameterized successive approximation register model, and the process generalization clock model.
[0009] Optional, the adaptive capacitor DAC model, which optimizes the circuit from the perspective of linearity improvement, is also used for: The process mismatch is adapted by using a lookup table method. The mismatch rate-capacitance value corresponding data of multiple process nodes are pre-stored. The unit capacitance is matched according to the three-dimensional correlation between process node, resolution and mismatch threshold, so as to control the mismatch rate within the preset range. The layout design of the capacitor DAC model adopts a symmetrical topology to take into account the effects of process deviation, interconnect parasitics and mechanical stress, ensure photolithography uniformity, and reduce parasitic parameters by layered wiring and coplanar grounding, thereby controlling the INL index of SARADC within the preset range.
[0010] Optionally, the adaptive comparator model, which optimizes the circuit from the perspective of noise suppression, is also used for: It adopts a two-stage structure of preamplifier and latch, and integrates offset storage technology. During the calibration stage, the preamplifier offset voltage is stored in the sampling capacitor. During the operation stage, the offset is canceled by feedback. At the same time, the noise averaging effect is used to reduce the impact of flicker noise. The GM / ID method is used to optimize the transistor size of the preamplifier, balance the performance indicators of power consumption, noise and bandwidth, and a machine learning scheme is used to match the circuit performance requirements of different application scenarios to achieve multi-scenario adaptation. A dynamic latch structure is adopted, and by adjusting the clock frequency and transistor width-to-length ratio, the performance indicators of the latch are optimized to ensure the stable operation of the comparator.
[0011] Optionally, parameterized successive approximation register models, which optimize circuits from multiple structural adaptation dimensions, are also used for: The current comparison result is stored and the control signal for the next comparison is generated. Independent control logic is designed for CDAC and RDAC. The timing synchronization unit ensures that the two work together and avoids charge interference to improve conversion linearity. The register bit depth and logic step count are dynamically adjusted by configuring the bit count signal. The corresponding shift register level is enabled under different bit counts, and the clock cycle is automatically matched to ensure timing stability under multiple conversion rates.
[0012] Optionally, the process generalization clock model, which optimizes the circuit from a timing control perspective, is also used for: By using a built-in process load detection unit, clock load parameters for multiple process nodes are pre-stored, and the width-to-length ratio of the clock drive stage transistor is automatically adjusted through the load configuration signal to ensure stable clock amplitude and response time. An edge calibration unit is designed to meet the clock edge requirements of the sampling switch. By fine-tuning the rise and fall slopes of the clock through the delay chain, the turn-on and turn-off timing of the sampling switch is matched with the charging and discharging rhythms of the CDAC and RDAC, and the clock edge jitter is locked within a preset range.
[0013] Optionally, a layout strategy using fixed topology variable spacing is adopted to maintain the positional relationship of the core model, defining the model spacing as a configurable variable, and calling the routing rules of the corresponding process to achieve rapid layout generation across process nodes. This also includes: The layout strategy of the core model is defined as a cross-symmetric structure, in which the capacitor DAC model is located on the left, the comparator model is located in the middle right, and the register model is located in the lower right. By using automatic routing tools to call the routing rules corresponding to the process nodes, including metal layer selection, line width setting, and parasitic capacitance compensation algorithm, the parasitic capacitance deviation of routing under different processes is kept at a low level.
[0014] To achieve the above objectives, a second aspect of the present invention provides a design apparatus for a SAR ADC with adjustable resolution and generalizable process based on code implementation, comprising: The parameter decoupling module is used to describe the entire SAR ADC circuit in a coded manner and divide it into four core models. The process parameters and performance parameters are defined as independent configurable parameters, so that the core logic of the circuit is completely decoupled from the parameters. The dimension optimization module is used to carry out targeted design for the four core models, optimizing the circuit from the dimensions of linearity improvement, noise suppression, multi-structure adaptation, and timing control, so that the parameters of each model can dynamically respond to the target process and performance requirements. The cross-process layout module is used to adopt a layout strategy with fixed topology variable spacing, keeping the positional relationship of the core model unchanged, defining the model spacing as a configurable variable, and calling the routing rules of the corresponding process to achieve rapid generation of layout across process nodes; The parameterized verification module is used to build a general simulation verification platform. It reads process parameters and performance parameters from the configuration file through parameterized test vector generation model, automatically generates excitation signals and calls a standardized verification test case library. It combines a unified data comparison model to generate a verification report and complete the full-process simulation.
[0015] The embodiments of the present invention have the following beneficial effects: First, it has significant advantages in general process technology, enabling rapid migration between different process nodes such as 180nm to 55nm and then to 12nm under the same architecture, effectively addressing the R&D challenges brought about by the upgrading of advanced process technologies.
[0016] Secondly, by relying on parametric design, the core logic and variable parameters are decoupled. There is no need to redraw the circuit. By simply updating the parameter configuration, it can adapt to the differentiated needs of different application scenarios, which greatly improves the circuit reuse rate and shortens the R&D cycle.
[0017] Third, it can achieve fast and accurate automatic generation of layout through unique algorithms and automated processes, which solves the problems of time-consuming and error-prone traditional manual layout drawing, avoids risks such as unreasonable routing and violation of design rules, reduces design costs while ensuring stable chip performance, and provides key support for multi-scenario applications. Attached Figure Description
[0018] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein: Figure 1 A flowchart illustrating a design method for an adjustable resolution and generalizable process SAR ADC based on code implementation, provided in this embodiment of the invention; Figure 2 This is a top-level model diagram of the SAR ADC code implementation provided in the embodiments of the present invention; Figure 3 A flowchart of the SAR ADC process provided in this embodiment of the invention; Figure 4 This is an example diagram of module layout using the TED platform provided in an embodiment of the present invention; Figure 5 This is a structural diagram of a design device for a SAR ADC with adjustable resolution and generalizable process based on code implementation, provided in an embodiment of the present invention. Detailed Implementation
[0019] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.
[0020] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.
[0021] The following describes, with reference to the accompanying drawings, a design method and apparatus for a code-based SAR ADC with adjustable resolution and generalizable process according to an embodiment of the present invention.
[0022] Example 1 This invention provides a design method for an adjustable resolution and generalizable process SAR ADC based on code implementation. Figure 1 This is a flowchart illustrating a design method for an adjustable resolution and generalizable process SAR ADC based on code implementation, as provided in an embodiment of the present invention. Figure 1 As shown, the method includes the following steps: Step S1: The entire SAR ADC circuit is described in a coded manner and divided into four core models. The process parameters and performance parameters are defined as independent configurable parameters, so that the core logic of the circuit is completely decoupled from the parameters.
[0023] In this embodiment, the entire SAR ADC circuit is described in code abstraction on the TED platform. The SAR ADC implementation adopts a "modeling + parameterization" architecture, dividing the entire circuit into four core models: a configurable capacitor DAC model, an adaptive comparator model, a parameterized successive approximation register model, and a process generalization clock model, such as... Figure 2 As shown.
[0024] The SAR ADC of this application supports adjustable 6-12 bit resolution, a maximum conversion rate of 3M, and is compatible with mainstream process nodes from 180nm to 12nm. This application defines process-related parameters such as unit capacitance and transistor aspect ratio, as well as performance parameters such as resolution and conversion rate, as configurable parameter variables. This completely decouples the core circuit logic from the parameters. Based on this design, no modification to the underlying circuit code is required; only parameter adjustments are needed to adapt the circuit to different process nodes and performance requirements. Figure 3 As shown.
[0025] Step S2 involves targeted design for the four core models, optimizing the circuits from the dimensions of linearity improvement, noise suppression, multi-structure adaptation, and timing control, so that the parameters of each model can dynamically respond to the target process and performance requirements.
[0026] Specifically, in this application embodiment, for the configurable capacitor DAC model, which is the core of the SAR ADC to achieve high-precision conversion, its linearity directly determines the ADC's INL / DNL index. This application optimizes from the perspective of improving linearity. In terms of capacitor size design, a lookup table method is used to adapt to process mismatch. Mismatch rate-capacitance value data of 180nm-12nm process are pre-stored, and the unit capacitor is matched according to the three dimensions of "process node-resolution-mismatch threshold". For example, in the 55nm / 12bit scenario, the unit capacitor is selected as 16fF, and the mismatch rate can be ≤0.2% without manual iteration. In terms of layout mismatch design, process deviation, interconnect parasitics, and mechanical stress are taken into account. A symmetrical topology structure is adopted to ensure photolithography uniformity. At the same time, the parasitic effects are reduced by layered wiring and coplanar grounding, and INL≤0.3LSB is achieved in 12bit.
[0027] For the adaptive comparator model, this application optimizes it from the dimensions of noise suppression and multi-structure adaptation. The model adopts a two-stage structure of "preamplifier + latch". In terms of offset and flicker noise suppression, offset storage technology is integrated. During the calibration stage, the offset voltage of the preamplifier is stored in the sampling capacitor. During the operation stage, the offset is canceled by feedback. At the same time, the noise averaging effect is used to reduce the impact of flicker noise. In the design of the preamplifier, the transistor size is optimized by the gm / id method to balance power consumption, noise and bandwidth. For different circuit performance requirements corresponding to different application scenarios, the circuit performance required for the corresponding scenario is achieved by machine learning scheme to achieve multi-scenario adaptation. In the design of the latch, a dynamic latch structure is adopted, and various indicators are balanced by adjusting the clock frequency and transistor width-to-length ratio.
[0028] For the parameterized successive approximation register model, this application optimizes it from the perspective of multi-structure adaptation. The core function of this model is to store the current comparison result and generate the control signal for the next comparison. It adapts to the C+RDAC structure and multi-bit resolution requirements. Independent control logic is designed for CDAC (capacitor DAC) and RDAC (resistor DAC). After storing the comparison result, the CDAC outputs a capacitor array configuration signal, which is the high-order capacitor charging and discharging control signal, and the RDAC outputs a resistor divider voltage adjustment signal, which is the low-order resistor network switching signal. The timing synchronization unit ensures that the two work together to avoid charge interference and improve conversion linearity. At the same time, the number of register bits and the number of logic steps are dynamically adjusted through the bit number configuration signal. When it is 6-bit, a 6-level shift register is enabled, and only 1 bit comparison is processed in each step. When it is 12-bit, it is expanded to 12 levels. The clock cycle is automatically adjusted to ensure timing stability at a conversion rate of 1-3M.
[0029] For the process generalization clock model, this application optimizes it from the perspective of timing control. The core of this model is to solve the differences in clock load and sampling switch timing requirements of different processes. In terms of adaptive adjustment of process load, a process load detection unit is built in, and clock load parameters of 180nm-12nm processes are pre-stored. The aspect ratio of the clock driver stage transistor is automatically adjusted through the load configuration signal. For example, when facing a high load process, the size of the driver transistor is increased and the output impedance is reduced to ensure the stability of clock amplitude and response time and avoid timing offset caused by load differences. In terms of precise control of sampling switch timing, an edge calibration unit is designed to meet the requirements of the sampling switch for clock edge. The rise / fall slope of the clock is finely adjusted through the delay chain to ensure that the switch turn-on / turn-off timing matches the charging and discharging rhythm of CDAC / RDAC. At the same time, the edge jitter is locked to ≤50ps to prevent charge injection error caused by excessively slow edges or noise caused by excessively steep edges, and to ensure sampling accuracy at 1-3M conversion rate.
[0030] It is clear that through targeted optimization design of the above four core models, the parameters of each model can dynamically respond to the target process and performance requirements.
[0031] Step S3: A layout strategy with fixed topology variable spacing is adopted to keep the core model positional relationship unchanged. The model spacing is defined as a configurable variable, and the routing rules of the corresponding process are called to realize the rapid generation of layout across process nodes.
[0032] In this embodiment, a "fixed topology + variable spacing" layout strategy is adopted for the layout design of the entire SAR ADC circuit. The four core models—configurable capacitor DAC model, adaptive comparator model, parameterized successive approximation register model, and process generalization clock model—maintain the same positional relationship under 180nm-12nm processes and 6-12bit resolution. For example, a cross-symmetrical layout is adopted with the capacitor DAC on the left, the comparator on the right center, and the register on the lower right. Only the spacing between models is defined as a configurable variable, and the spacing parameter is automatically called according to the process. During the routing stage, a uniformly configured automatic routing tool is used, calling the routing rules corresponding to the process based on the fixed topology, including metal layer selection and line width settings, to ensure that the parasitic capacitance deviation of routing is small under different parameters. The entire layout generation process requires only minimal manual intervention. Based on the above strategy, rapid layout generation across process nodes can be achieved. Figure 4 As shown.
[0033] Step S4: Construct a general simulation verification platform. The platform reads process parameters and performance parameters from the configuration file by generating a model through parameterized test vectors, automatically generates excitation signals and calls a standardized verification test case library. It then combines a unified data comparison model to generate a verification report and completes the full-process simulation.
[0034] In this embodiment, a general simulation verification framework is built on the TED platform to construct a general simulation verification platform for the entire SAR ADC circuit. This platform is equipped with a parameterized test vector generation model. By reading the process parameters and performance parameters in the configuration file, including key parameters such as resolution (6-12 bits), conversion rate (1-3M), and process node (180nm-12nm), it automatically generates suitable excitation signals, such as analog input voltage range and sampling clock frequency. At the same time, the platform has a built-in standardized verification test case library covering core indicators such as linearity (INL / DNL), power consumption, and noise. It can adapt to different performance circuits without modifying the test case logic. In addition, the platform designs a unified data comparison model, automatically receives the digital code output by the circuit, performs deviation analysis with the theoretical value, and generates a verification report.
[0035] Based on the above design, SAR ADC circuits with different performance only need to update the configuration file parameters to call the same verification platform to complete the whole process simulation. There is no need to repeatedly build stimulus, test cases and comparison models, which ensures verification efficiency and verification consistency.
[0036] Example 2 This invention provides a design apparatus for a SAR ADC with adjustable resolution and generalizable process based on code implementation. Figure 5 This is a flowchart illustrating a design apparatus for a code-based SAR ADC with adjustable resolution and generalizable process, provided as an embodiment of the present invention. Figure 5As shown, the device includes: The parameter decoupling module 100 is used to describe the entire circuit of the SAR ADC in a coded manner and divide it into four core models. The process parameters and performance parameters are defined as independent configurable parameters, so that the core logic of the circuit is completely decoupled from the parameters. The Dimension Optimization Module 200 is used to carry out targeted design for the four core models, optimizing the circuit from the dimensions of linearity improvement, noise suppression, multi-structure adaptation, and timing control, so that the parameters of each model can dynamically respond to the target process and performance requirements. The cross-process layout module 300 is used to adopt a layout strategy with fixed topology variable spacing, keep the positional relationship of the core model unchanged, define the model spacing as a configurable variable, and call the routing rules of the corresponding process to realize the rapid generation of layout across process nodes. The parameterized verification module 400 is used to build a general simulation verification platform. It reads process parameters and performance parameters from the configuration file through the parameterized test vector generation model, automatically generates excitation signals and calls the standardized verification test case library, and generates a verification report by combining the unified data comparison model to complete the full-process simulation.
[0037] Regarding the apparatus in the above embodiments, the specific manner in which each module performs its operation has been described in detail in the embodiments related to the method, and will not be elaborated upon here.
[0038] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
[0039] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.
[0040] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.
Claims
1. A design method for a SAR ADC with adjustable resolution and generalizable process based on code implementation, characterized in that, include: S1 describes the entire SAR ADC circuit through coding and divides it into four core models. It defines process parameters and performance parameters as independent configurable parameters, so that the core logic of the circuit is completely decoupled from the parameters. S2 conducts targeted design for the four core models, optimizing the circuit from the dimensions of linearity improvement, noise suppression, multi-structure adaptation, and timing control, so that the parameters of each model can dynamically respond to the target process and performance requirements. S3 adopts a layout strategy with fixed topology variable spacing to keep the core model positional relationship unchanged, defines the model spacing as a configurable variable, and calls the routing rules of the corresponding process to achieve rapid generation of layout across process nodes; S4 constructs a general simulation verification platform. It reads process parameters and performance parameters from the configuration file through parameterized test vector generation model, automatically generates excitation signals and calls a standardized verification test case library. Combined with a unified data comparison model, it generates a verification report and completes the full-process simulation.
2. The method according to claim 1, characterized in that, The four core models include the adaptive capacitor DAC model, the adaptive comparator model, the parameterized successive approximation register model, and the process generalization clock model.
3. The method according to claim 2, characterized in that, The adaptive capacitor DAC model optimizes the circuit from the perspective of linearity improvement and is also used for: The process mismatch is adapted by using a lookup table method. The mismatch rate-capacitance value corresponding data of multiple process nodes are pre-stored. The unit capacitance is matched according to the three-dimensional correlation between process node, resolution and mismatch threshold, so as to control the mismatch rate within the preset range. The layout design of the capacitor DAC model adopts a symmetrical topology to take into account the effects of process deviation, interconnect parasitics and mechanical stress, ensure photolithography uniformity, and reduce parasitic parameters by layered wiring and coplanar grounding, thereby controlling the INL index of the SAR ADC within the preset range.
4. The method according to claim 3, characterized in that, The adaptive comparator model, which optimizes the circuit from the perspective of noise suppression, is also used for: It adopts a two-stage structure of preamplifier and latch, and integrates offset storage technology. During the calibration stage, the preamplifier offset voltage is stored in the sampling capacitor. During the operation stage, the offset is canceled by feedback. At the same time, the noise averaging effect is used to reduce the impact of flicker noise. The GM / ID method is used to optimize the transistor size of the preamplifier, balance the performance indicators of power consumption, noise and bandwidth, and a machine learning scheme is used to match the circuit performance requirements of different application scenarios to achieve multi-scenario adaptation. A dynamic latch structure is adopted, and by adjusting the clock frequency and transistor width-to-length ratio, the performance indicators of the latch are optimized to ensure the stable operation of the comparator.
5. The method according to claim 4, characterized in that, The parameterized successive approximation register model optimizes circuits from multiple structural adaptation dimensions and is also used for: The current comparison result is stored and the control signal for the next comparison is generated. Independent control logic is designed for CDAC and RDAC. The timing synchronization unit ensures that the two work together and avoids charge interference to improve conversion linearity. The register bit depth and logic step count are dynamically adjusted by configuring the bit count signal. The corresponding shift register level is enabled under different bit counts, and the clock cycle is automatically matched to ensure timing stability under multiple conversion rates.
6. The method according to claim 5, characterized in that, The process generalization clock model optimizes circuits from a timing control perspective and is also used for: By using a built-in process load detection unit, clock load parameters for multiple process nodes are pre-stored, and the width-to-length ratio of the clock drive stage transistor is automatically adjusted through the load configuration signal to ensure stable clock amplitude and response time. An edge calibration unit is designed to meet the clock edge requirements of the sampling switch. By fine-tuning the rise and fall slopes of the clock through the delay chain, the turn-on and turn-off timing of the sampling switch is matched with the charging and discharging rhythms of the CDAC and RDAC, and the clock edge jitter is locked within a preset range.
7. The method according to claim 6, characterized in that, A layout strategy employing fixed topology variable spacing maintains the positional relationships of the core models, defines the model spacing as a configurable variable, and calls the routing rules of the corresponding process to achieve rapid layout generation across process nodes. It also includes: The layout strategy of the core model is defined as a cross-symmetric structure, in which the capacitor DAC model is located on the left, the comparator model is located in the middle right, and the register model is located in the lower right. By using automatic routing tools to call the routing rules corresponding to the process nodes, including metal layer selection, line width setting, and parasitic capacitance compensation algorithm, the parasitic capacitance deviation of routing under different processes is kept at a low level.
8. A design device for a code-based SAR ADC with adjustable resolution and generalizable process, characterized in that, include: The parameter decoupling module is used to describe the entire SAR ADC circuit in a coded manner and divide it into four core models. The process parameters and performance parameters are defined as independent configurable parameters, so that the core logic of the circuit is completely decoupled from the parameters. The dimension optimization module is used to carry out targeted design for the four core models, optimizing the circuit from the dimensions of linearity improvement, noise suppression, multi-structure adaptation, and timing control, so that the parameters of each model can dynamically respond to the target process and performance requirements. The cross-process layout module is used to adopt a layout strategy with fixed topology variable spacing, keeping the positional relationship of the core model unchanged, defining the model spacing as a configurable variable, and calling the routing rules of the corresponding process to achieve rapid generation of layout across process nodes; The parameterized verification module is used to build a general simulation verification platform. It reads process parameters and performance parameters from the configuration file through parameterized test vector generation model, automatically generates excitation signals and calls a standardized verification test case library. It combines a unified data comparison model to generate a verification report and complete the full-process simulation.
9. The apparatus according to claim 8, characterized in that, The cross-process layout module is also used for: The layout strategy of the core model is defined as a cross-symmetric structure, in which the capacitor DAC model is located on the left, the comparator model is located in the middle right, and the register model is located in the lower right. By using automatic routing tools to call the routing rules corresponding to the process nodes, including metal layer selection, line width setting, and parasitic capacitance compensation algorithm, the parasitic capacitance deviation of routing under different processes is kept at a low level.