Deposition mask, method for manufacturing the same, and electronic device manufactured using the mask.

Abstract

A deposition mask is provided, as well as a method for manufacturing the same and an electronic device manufactured using the mask. The deposition mask includes: a mask substrate having cell openings; an intermediate inorganic film disposed on the mask substrate and having an intermediate opening communicating with the cell openings; a mask alignment key disposed on the intermediate inorganic film; and a film disposed on the intermediate inorganic film and having a plurality of pixel openings communicating with the intermediate openings and a key opening exposing the mask alignment key.

Description

Technical Field

[0001] This invention relates to a deposition mask, a method for manufacturing the same, and an electronic device manufactured using the same mask. Background Technology

[0002] Wearable devices, in the form of glasses or helmets, are being developed to focus on the user's near field of vision. For example, the wearable device could be a head-mounted display (HMD) or AR glasses. Such wearable devices can provide users with augmented reality (AR) or virtual reality (VR) visuals.

[0003] For wearable devices such as HMD devices or AR glasses, a display specification of approximately 3000 PPI (pixels per inch) or higher is required to enable users to use them for extended periods without experiencing dizziness. Therefore, Organic Light Emitting Diode on Silicon (OLEDoS) technology is emerging for use in high-resolution, small-scale organic light-emitting display devices. OLEDoS technology involves placing organic light-emitting diodes (OLEDs) on a semiconductor substrate on which complementary metal-oxide-semiconductor (CMOS) elements are arranged.

[0004] To manufacture high-resolution display panels with a resolution of approximately 3000 PPI or higher, high-resolution deposition masks are required. For example, deposition masks can be manufactured by forming a membrane with multiple pixel openings on a mask substrate such as a silicon wafer and partially removing the mask substrate to form cell openings that expose the pixel openings.

[0005] In the deposition process for forming the light-emitting layer of a display panel, a backplane substrate can be disposed on a deposition mask, and vapor-phase deposited material provided from a deposition source can be deposited on the backplane substrate through pixel openings in the deposition mask. Substrate alignment keys can be disposed on the backplane substrate, and mask alignment keys can be disposed on the deposition mask. The positional information of the substrate alignment keys and mask alignment keys can be obtained by a camera, and the backplane substrate can be aligned with the deposition mask based on the positional information. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a deposition mask including a mask alignment key with improved recognition rate, a method for manufacturing the same, and an electronic device manufactured using the mask.

[0007] The technical problem of the present invention is not limited to the technical problems mentioned above. Those skilled in the art can clearly understand another technical problem not mentioned from the following description.

[0008] A deposition mask according to an embodiment of the present invention may include: a mask substrate having a cell opening; an intermediate inorganic film disposed on the mask substrate and having an intermediate opening communicating with the cell opening; a mask alignment key disposed on the intermediate inorganic film; and a film disposed on the intermediate inorganic film and having a plurality of pixel openings communicating with the intermediate opening and a key opening for exposing the mask alignment key.

[0009] According to one embodiment of the present invention, the intermediate inorganic membrane may have a groove located below the key opening, and the mask alignment key may be arranged on the bottom surface of the groove.

[0010] According to one embodiment of the present invention, the mask alignment key may have a thickness smaller than the depth of the groove.

[0011] According to one embodiment of the present invention, the groove may have a width wider than the key opening.

[0012] According to one embodiment of the present invention, the mask alignment key may include: a plurality of inner key patterns extending parallel to each other; and a ring-shaped outer key pattern surrounding the inner key patterns.

[0013] According to one embodiment of the present invention, the mask alignment key may include: a plurality of first inner key patterns extending parallel to each other along a first direction; a plurality of second inner key patterns extending parallel to each other along a second direction perpendicular to the first direction and intersecting with the first inner key patterns; and a ring-shaped outer key pattern surrounding the first inner key patterns and the second inner key patterns.

[0014] According to one embodiment of the present invention, the deposition mask may further include: a second mask alignment bond, disposed on the film, and having a ring shape surrounding the bond opening.

[0015] According to one embodiment of the present invention, the mask alignment key may include metal.

[0016] According to one embodiment of the present invention, the mask alignment key may include aluminum (Al), nickel (Ni), tungsten (W), molybdenum (Mo), gold (Au), silver (Ag), platinum (Pt), or copper (Cu).

[0017] A method for manufacturing a deposition mask according to an embodiment of the present invention may include the following steps: forming an intermediate inorganic film on a mask substrate; forming a film on the intermediate inorganic film; forming pixel openings and bond openings that expose the intermediate inorganic film by partially removing the film; forming mask alignment bonds at the locations of the intermediate inorganic film exposed through the bond openings; and forming cell openings and intermediate openings that expose the pixel openings by partially removing the mask substrate and the intermediate inorganic film.

[0018] According to one embodiment of the present invention, the mask alignment key may be formed as including: a plurality of inner key patterns extending parallel to each other; and an outer key pattern in a ring shape surrounding the inner key patterns.

[0019] According to one embodiment of the present invention, the method for manufacturing the deposition mask may further include the step of forming a groove by removing portions of the intermediate inorganic film exposed through the key openings. In this case, the mask alignment key may be formed on the bottom surface of the groove.

[0020] According to one embodiment of the present invention, the key opening can be formed by an anisotropic etching process, which can be performed by forming a groove by partially removing the surface portion of the intermediate inorganic film, and the mask alignment key can be formed on the bottom surface of the groove.

[0021] According to one embodiment of the present invention, the mask alignment key may be formed to have a thickness smaller than the depth of the groove.

[0022] According to one embodiment of the present invention, the key opening may include: a plurality of inner opening patterns extending parallel to each other; and an outer opening pattern in the form of a ring surrounding the inner opening patterns, wherein the groove includes: an inner groove pattern formed below the inner opening patterns; and an outer groove pattern in the form of a ring formed below the outer opening patterns.

[0023] According to one embodiment of the present invention, during the formation of the key opening, an island pattern may be formed between the inner opening pattern and the outer opening pattern, and during the formation of the mask alignment key, a dummy key pattern may be formed on the island pattern.

[0024] According to an embodiment of the present invention, the method for manufacturing the deposition mask may further include the following steps: removing the island pattern and the dummy bond pattern.

[0025] According to an embodiment of the present invention, the method for manufacturing the deposition mask may further include the step of forming a second mask alignment key in a ring shape surrounding the key opening on the film.

[0026] According to one embodiment of the present invention, the mask alignment key can be formed by an electron beam evaporation process or a thermal evaporation process using a shadow mask that exposes the portion of the intermediate inorganic film to which the mask alignment key will be formed.

[0027] According to an embodiment of the present invention, in an electronic device including a display panel, the display panel may include a backplane substrate and a plurality of light-emitting layers formed on the backplane substrate using a deposition mask. The deposition mask may include: a mask substrate having cell openings; an intermediate inorganic film disposed on the mask substrate and having an intermediate opening communicating with the cell openings; a mask alignment bond disposed on the intermediate inorganic film; and a film disposed on the intermediate inorganic film and having a plurality of pixel openings communicating with the intermediate openings and a bond opening exposing the mask alignment bond. The plurality of light-emitting layers may be formed by a deposition process in which a vapor phase of a deposited material is provided on the backplane substrate through the cell openings, the intermediate openings, and the pixel openings.

[0028] Specific details of other embodiments are included in the detailed description and accompanying drawings.

[0029] According to embodiments of the present invention as described above, a deposition mask may include: a mask substrate; an intermediate inorganic film disposed on the mask substrate; a mask alignment bond disposed on the intermediate inorganic film; and a film disposed on the intermediate inorganic film, having bond openings that expose the mask alignment bond. The mask alignment bond may include a metal with high light reflectivity, thereby improving the recognition rate of the mask alignment bond.

[0030] The effects of the embodiments described are not limited to those illustrated above, and more diverse effects are included in this specification. Attached Figure Description

[0031] Figure 1 This is a block diagram illustrating an electronic device according to an embodiment.

[0032] Figure 2 It is used for explanation Figure 1 A schematic diagram of an example of an electronic device.

[0033] Figure 3 This is an exploded perspective view illustrating an example of a display device according to an embodiment of the present invention.

[0034] Figure 4 It is used for explanation Figure 3 Block diagram of the display device shown.

[0035] Figure 5 It is used for explanation Figure 4The equivalent circuit diagram of an example of the first sub-pixel is shown.

[0036] Figure 6 It is used for explanation Figure 3 A schematic floor plan of an example display panel is shown.

[0037] Figure 7 It is used for explanation Figure 6 A schematic enlarged plan view of an example of the display area shown.

[0038] Figure 8 It is used for explanation Figure 6 A schematic enlarged plan view of another example of the display area shown.

[0039] Figure 9 It is used to explain along Figure 7 A schematic cross-sectional view of an example display panel obtained by the I1-I1' line shown.

[0040] Figure 10 It is used to explain along Figure 7 A schematic cross-sectional view of another example of a display panel obtained by the I1-I1' line shown.

[0041] Figure 11 This is a schematic perspective view used to illustrate an example of a head-mounted display device.

[0042] Figure 12 It is used for explanation Figure 11 A schematic exploded perspective view of the head-mounted display device shown.

[0043] Figure 13 This is a schematic perspective view used to illustrate another example of a head-mounted display device.

[0044] Figure 14 This is a schematic diagram illustrating a deposition mask and a deposition apparatus including the deposition mask according to an embodiment of the present invention.

[0045] Figure 15 It is used for explanation Figure 14 A schematic bottom view of the backplate substrate shown.

[0046] Figure 16 It is used for explanation Figure 14 The diagram shows a schematic plan view of the deposition mask.

[0047] Figure 17 It is used for explanation Figure 16 A schematic plan view of the mask unit area shown.

[0048] Figure 18 It is along Figure 17A schematic cross-sectional view obtained from the I2-I2' line shown.

[0049] Figure 19 It is used for explanation Figure 16 A schematic cross-sectional view of the mask alignment key is shown.

[0050] Figure 20 It is used for explanation Figure 19 A schematic enlarged cross-sectional view of the mask alignment key shown.

[0051] Figure 21 It is used for explanation Figure 19 A schematic enlarged plan view of the mask alignment key shown.

[0052] Figure 22 It is used for explanation Figure 21 A schematic enlarged plan view of another example of a mask alignment key.

[0053] Figure 23 It is used for explanation Figure 14 A schematic enlarged cross-sectional view of the camera shown.

[0054] Figures 24 to 39 This is a schematic diagram illustrating a method for manufacturing a deposition mask according to another embodiment of the present invention.

[0055] Figure 24 It is a schematic cross-sectional view used to illustrate the formation of the intermediate inorganic membrane and the second intermediate inorganic membrane.

[0056] Figure 25 It is a schematic cross-sectional view used to illustrate the formation of the membrane and the inorganic membrane on the back surface.

[0057] Figure 26 It is a schematic cross-sectional view used to illustrate the formation of the first photoresist pattern.

[0058] Figure 27 It is a schematic cross-sectional view used to illustrate the formation of pixel openings and key openings.

[0059] Figure 28 It is used for explanation Figure 27 A schematic enlarged cross-sectional view of the key opening shown.

[0060] Figure 29 It is used for explanation Figure 27 A schematic enlarged plan view of the key opening shown.

[0061] Figure 30 It is used for explanation Figure 29 A schematic enlarged plan view of another example of a key opening shown.

[0062] Figure 31 It is a schematic cross-sectional view used to illustrate the formation of the mask alignment key, the second mask alignment key, and the dummy key pattern.

[0063] Figure 32 It is used for explanation Figure 31 A schematic enlarged cross-sectional view of the mask alignment key, the second mask alignment key, and the dummy key pattern shown.

[0064] Figure 33 It is used to explain the formation Figure 31 The diagram shows an electron beam evaporator with a mask alignment key, a second mask alignment key, and a dummy key pattern.

[0065] Figure 34 It is used for explanation Figure 33 A schematic enlarged cross-sectional view of the shadow mask shown.

[0066] Figure 35 It is a schematic cross-sectional view used to illustrate the formation of the second photoresist pattern.

[0067] Figure 36 It is a schematic cross-sectional view used to illustrate the formation of the rear surface opening and the second intermediate opening.

[0068] Figure 37 It is a schematic cross-sectional view used to illustrate the formation of the unit opening.

[0069] Figure 38 It is a schematic cross-sectional view used to illustrate the formation of the central opening.

[0070] Figure 39 It is a schematic enlarged cross-sectional view used to illustrate the removal of island patterns and dummy key patterns.

[0071] Explanation of reference numerals in the attached figures Detailed Implementation

[0072] The advantages and features of the present invention, as well as the methods for achieving them, will become clear from the detailed embodiments described below in conjunction with the accompanying drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments disclosed below. These embodiments are provided only to complete the disclosure of the invention and to fully inform those skilled in the art of the invention's scope, which is defined only by the scope of the claims.

[0073] The reference to elements or layers being "on" other elements or layers includes situations where they are immediately above or adjacent to other elements or layers, or where other layers or elements are sandwiched in between. Throughout this specification, the same reference numerals refer to the same constituent elements. The shapes, dimensions, ratios, angles, quantities, etc., disclosed in the drawings used to illustrate embodiments are exemplary, and therefore the invention is not limited to the matters shown.

[0074] Although terms such as "first," "second," etc., are used to describe multiple constituent elements, these constituent elements are clearly not limited to these terms. These terms are only used to distinguish one constituent element from another. Therefore, the "first constituent element" mentioned below can obviously also be a "second constituent element" within the technical concept of this invention.

[0075] The various features of the multiple embodiments of the present invention can be partially or wholly combined or integrated with each other, and can be linked and driven in various ways in terms of technology. Each embodiment can be implemented independently of each other, or can be implemented together in a related relationship.

[0076] The specific embodiments will now be described with reference to the accompanying drawings.

[0077] The display device according to one embodiment can be applied to a variety of electronic devices. The electronic device according to one embodiment may include the display device, and in addition to the display device, may also include modules or devices with other additional functions.

[0078] Figure 1 This is a block diagram illustrating an electronic device according to an embodiment.

[0079] Reference Figure 1 According to one embodiment, the electronic device 10 may include a display module 11, a processor 12, a memory 13, and a power module 14.

[0080] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0081] The memory 13 may store the data information required for the operation of the processor 12 or the display module 11. If the processor 12 executes the application stored in the memory 13, the image data signal and / or input control signal can be transmitted to the display module 11, and the display module 11 can process the received signal and output image information through the display screen.

[0082] The power module 14 may include a power supply module such as a power adapter or battery device and a power conversion module that generates the power required for the operation of the electronic device 10 by converting the power supplied by the power supply module.

[0083] At least one of the various configurations of the electronic device 10 described above may be included in the display device 20 according to the embodiments described later (see reference). Figure 3 Furthermore, a portion of an individual module that is functionally included within a module may also be included within the display device 20, while another portion may be separately disposed from the display device 20. For example, the display device 20 may include a display module 11, and the processor 12, memory 13, and power module 14 may be configured as other non-display device 20 components within the electronic device 10.

[0084] Figure 2 It is used for explanation Figure 1 A schematic diagram of an example of an electronic device.

[0085] Reference Figure 2 The application uses the display device 20 according to the embodiment (see reference 20). Figure 3 The various electronic devices 10 can include image display electronic devices such as smartphones 10_1a, tablet computers 10_1b, laptop computers 10_1c, televisions (TVs) 10_1d, and desktop monitors 10_1e. The electronic devices 10 using the display device 20 according to the embodiments can be applied to wearable electronic devices including display modules 11, such as smart glasses 10_2a, head-mounted displays 10_2b, and smartwatches 10_2c. Furthermore, the electronic devices 10 using the display device 20 according to the embodiments can include vehicle electronic devices 10_3 including display modules 11, such as vehicle dashboards, center consoles, central information displays (CIDs) arranged on instrument panels, and room mirror displays.

[0086] Figure 3 This is an exploded perspective view illustrating an example of a display device according to an embodiment of the present invention. Figure 4 It is used for explanation Figure 3 Block diagram of the display device shown.

[0087] Reference Figure 3 and Figure 4 According to one embodiment, the display device 20 is a device for displaying moving or still images. According to one embodiment, the display device 20 can be used as an electronic device 10 or a display module 11 of an electronic device 10. For example, according to one embodiment, the display device 20 can be applied to portable electronic devices such as mobile phones, smartphones, tablet personal computers, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigators, and ultra-mobile PCs (UMPCs). According to one embodiment, the display device 20 can be used as a display unit for electronic devices such as televisions, laptops, monitors, billboards, or Internet of Things (IoT) devices. According to one embodiment, the display device 20 can be applied to electronic devices such as smartwatches, watch phones, and head-mounted displays (HMDs) for realizing virtual and augmented reality.

[0088] According to one embodiment, the display device 20 may include a display panel 100, a heat dissipation layer 200, a circuit board 300, a timing control circuit 400, and a power supply circuit 500.

[0089] The display panel 100 can be formed in a planar shape similar to a quadrilateral. For example, the display panel 100 can have a planar shape similar to a quadrilateral having a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. In the display panel 100, the corners where the short side in the first direction DR1 and the long side in the second direction DR2 intersect can be smoothly formed with a predetermined curvature, or they can be formed as right angles. The planar shape of the display panel 100 is not limited to a quadrilateral and can be formed similarly to other polygons, circles, or ellipses. The planar shape of the display device 20 can follow the planar shape of the display panel 100, but the embodiments described in this specification are not limited thereto.

[0090] The display panel 100 may include multiple pixels PX, multiple scan lines SL, multiple light emission control lines EL, multiple data lines DL, a scan driver unit 610, a light emission driver unit 620, and a data driver unit 700. For example... Figure 4 As shown, the display panel 100 can be divided into a display area DAA for displaying images and a non-display area NDA for not displaying images.

[0091] Multiple pixels (PX) are arranged in the display area (DAA). These pixels (PX) can be arranged in a matrix along a first direction (DR1) and a second direction (DR2). Multiple scan lines (SL) and multiple light emission control lines (EL) can extend along the first direction (DR1) and be arranged along the second direction (DR2). Multiple data lines (DL) can extend along the second direction (DR2) and be arranged along the first direction (DR1).

[0092] Multiple scan lines SL can include multiple write scan lines GWL, multiple control scan lines GCL, and multiple bias scan lines GBL. Multiple emission control lines EL include multiple first emission control lines ECL1 and multiple second emission control lines ECL2.

[0093] Multiple pixels PX can include multiple sub-pixels SP1, SP2, SP3. For example... Figure 5 As shown, the multiple sub-pixels SP1, SP2, and SP3 may include multiple pixel transistors, and the multiple pixel transistors can be formed and arranged on a semiconductor substrate SSUB using semiconductor processes. Figure 9 For example, multiple pixel transistors can be formed using complementary metal-oxide-semiconductor (CMOS), but the embodiments described in this specification are not limited thereto.

[0094] Each of the multiple sub-pixels SP1, SP2, and SP3 can be connected to a write scan line GWL, a control scan line GCL, a bias scan line GBL, a first emission control line ECL1, a second emission control line ECL2, and a data line DL. Each of the multiple sub-pixels SP1, SP2, and SP3 can receive the data voltage of the data line DL according to the write scan signal of the write scan line GWL, and can cause the light-emitting element to emit light according to the data voltage.

[0095] The scanning drive unit 610, the light emission drive unit 620, and the data drive unit 700 can be arranged in the non-display area NDA.

[0096] The scan driving unit 610 includes multiple scan transistors, and the light-emitting driving unit 620 includes multiple light-emitting transistors. The multiple scan transistors and multiple light-emitting transistors can be formed using semiconductor processes and can be formed on a semiconductor substrate SSUB (Semiconductor Substrate Base). Figure 9 For example, multiple scanning transistors and multiple light-emitting transistors can be formed using complementary metal-oxide-semiconductor (CMOS), but the embodiments described herein are not limited thereto.

[0097] The scan drive unit 610 may include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 may receive a scan timing control signal SCS from the timing control circuit 400. The write scan signal output unit 611 may generate a write scan signal based on the scan timing control signal SCS from the timing control circuit 400, and thereby output the write scan signal sequentially to the write scan line GWL. The control scan signal output unit 612 may generate a control scan signal based on the scan timing control signal SCS, and thereby output the control scan signal sequentially to the control scan line GCL. The bias scan signal output unit 613 may generate a bias scan signal based on the scan timing control signal SCS, and thereby output the bias scan signal sequentially to the bias scan line GBL.

[0098] The light-emitting driver unit 620 may include a first light-emitting control driver unit 621 and a second light-emitting control driver unit 622. Each of the first light-emitting control driver unit 621 and the second light-emitting control driver unit 622 may receive a light-emitting timing control signal ECS from the timing control circuit 400. The first light-emitting control driver unit 621 may generate a first light-emitting control signal based on the light-emitting timing control signal ECS, and then sequentially output the first light-emitting control signal to the first light-emitting control line ECL1. The second light-emitting control driver unit 622 may generate a second light-emitting control signal based on the light-emitting timing control signal ECS, and then sequentially output the second light-emitting control signal to the second light-emitting control line ECL2.

[0099] The data drive unit 700 may include multiple data transistors, which can be formed by semiconductor processes and can be formed on a semiconductor substrate SSUB (Semiconductor Substrate Surface Mount Technology). Figure 9 For example, multiple data transistors can be formed using complementary metal-oxide-semiconductor (CMOS), but the embodiments described in this specification are not limited thereto.

[0100] The data driver unit 700 can receive digital video data DATA and data timing control signal DCS from the timing control circuit 400. The data driver unit 700 converts the digital video data DATA into analog data voltage according to the data timing control signal DCS and outputs the analog data voltage to the data line DL. In this case, sub-pixels SP1, SP2, and SP3 can be selected by the write scan signal of the scan driver unit 610, and data voltage can be supplied to the selected sub-pixels SP1, SP2, and SP3.

[0101] The heat dissipation layer 200 may overlap with the display panel 100 on a third direction DR3, which is the thickness direction of the display panel 100. The heat dissipation layer 200 may be disposed on a surface (e.g., the rear surface) of the display panel 100. The heat dissipation layer 200 serves to release heat generated from the display panel 100. The heat dissipation layer 200 may include graphite or metals such as silver (Ag), copper (Cu), and aluminum (Al) that have high thermal conductivity.

[0102] The circuit board 300 can be bonded to the first pad portion PDA1 of the display panel 100 using conductive adhesive components such as anisotropic conductive film. Figure 6 Multiple first pads PD1 () Figure 6 Electrical connection. Circuit board 300 can be a flexible printed circuit board or a flexible film made of a flexible material. Although in Figure 3 The illustration shows the circuit board 300 unfolded, but the circuit board 300 can be bent. In this case, one end of the circuit board 300 can be disposed on the rear surface of the display panel 100 and / or the rear surface of the heat dissipation layer 200. The other end of the circuit board 300 can be attached to the first pad portion PDA1 of the display panel 100 using a conductive adhesive component. Figure 6 Multiple first pads PD1 () Figure 6 (Connection). One end of circuit board 300 can be the opposite end of the other end of circuit board 300.

[0103] The timing control circuit 400 can receive digital video data DATA and timing signals from an external source. Based on the timing signals, the timing control circuit 400 generates a scan timing control signal SCS, a light emission timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100. The timing control circuit 400 can output the scan timing control signal SCS to the scan driver unit 610 and the light emission timing control signal ECS to the light emission driver unit 620. The timing control circuit 400 can also output digital video data DATA and the data timing control signal DCS to the data driver unit 700.

[0104] The power supply circuit 500 can generate multiple panel driving voltages based on an external power supply voltage. For example, the power supply circuit 500 can generate a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT and supply them to the display panel 100. A description of the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT will be provided in conjunction with... Figure 5 This will be discussed later.

[0105] Each of the timing control circuit 400 and the power supply circuit 500 can be formed as an integrated circuit (IC) and can be attached to one surface of the circuit board 300. In this case, the scan timing control signal SCS, the light emission timing control signal ECS, the digital video data DATA, and the data timing control signal DCS of the timing control circuit 400 can be supplied to the display panel 100 through the circuit board 300. Furthermore, the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT of the power supply circuit 500 can be supplied to the display panel 100 through the circuit board 300.

[0106] Alternatively, each of the timing control circuit 400 and the power supply circuit 500 may be arranged in the non-display area NDA of the display panel 100 in a similar manner to the scan drive unit 610, the light emission drive unit 620, and the data drive unit 700. In this case, the timing control circuit 400 may include a plurality of timing transistors, and the power supply circuit 500 may include a plurality of power transistors. The plurality of timing transistors and the plurality of power transistors may be formed by semiconductor processes and may be formed on a semiconductor substrate SSUB (Semiconductor Substrate Base). Figure 9 For example, multiple timing transistors and multiple power transistors can be formed using complementary metal-oxide-semiconductor (CMOS), but the embodiments described herein are not limited thereto. Each of the timing control circuit 400 and the power supply circuit 500 can be arranged between the data drive section 700 and the first pad section PDA1. Figure 6 )between.

[0107] Figure 5 It is used for explanation Figure 4 The equivalent circuit diagram of an example of the first sub-pixel is shown.

[0108] Reference Figure 5 The first sub-pixel SP1 can be connected to the write scan line GWL, the control scan line GCL, the bias scan line GBL, the first emission control line ECL1, the second emission control line ECL2, and the data line DL. Furthermore, the first sub-pixel SP1 can be connected to the first driving voltage line VSL, which is applied with a first driving voltage VSS equivalent to a low potential voltage; the second driving voltage line VDL, which is applied with a second driving voltage VDD equivalent to a high potential voltage; and the third driving voltage line VIL, which is applied with a third driving voltage VINT equivalent to an initialization voltage.

[0109] The first sub-pixel SP1 may include multiple transistors T1~T6, a light-emitting element LE, a first capacitor CP1, and a second capacitor CP2.

[0110] The light-emitting element LE emits light according to the driving current flowing in the channel of the first transistor T1. The amount of light emitted by the light-emitting element LE is proportional to the driving current. The first electrode of the light-emitting element LE can be an anode electrode, and the second electrode of the light-emitting element LE can be a cathode electrode. The light-emitting element LE can be an organic light-emitting diode including a first electrode, a second electrode, and an organic light-emitting layer disposed between the first electrode and the second electrode, but the embodiments in this specification are not limited thereto. For example, the light-emitting element LE can be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode. In this case, the light-emitting element LE can be a micro light-emitting diode.

[0111] The first transistor T1 may be a drive transistor that controls the source-drain current (hereinafter referred to as "drive current") flowing between the source and drain electrodes according to the voltage applied to the gate electrode.

[0112] The second transistor T2 can be disposed between one electrode of the first capacitor CP1 and the data line DL. The second transistor T2 is turned on by the write scan signal of the write scan line GWL to connect one electrode of the first capacitor CP1 to the data line DL. Thus, the data voltage of the data line DL can be applied to one electrode of the first capacitor CP1.

[0113] The third transistor T3 can be arranged between the first node N1 and the second node N2. The third transistor T3 is turned on by the control scan signal of the control scan line GCL to connect the first node N1 to the second node N2. Thus, with the gate electrode and drain electrode of the first transistor T1 connected, the first transistor T1 can operate like a diode.

[0114] A fourth transistor T4 can be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by the first light-emitting control signal of the first light-emitting control line ECL1 to connect the second node N2 to the third node N3. Thus, the drive current of the first transistor T1 can be supplied to the light-emitting element LE. A fifth transistor T5 can be arranged between the third node N3 and the third drive voltage line VIL. The fifth transistor T5 is turned on by the bias scan signal of the bias scan line GBL to connect the third node N3 to the third drive voltage line VIL. Thus, the third drive voltage VINT of the third drive voltage line VIL can be applied to the first electrode of the light-emitting element LE.

[0115] A sixth transistor T6 can be disposed between the source electrode of the first transistor T1 and the second driving voltage line VDL. The sixth transistor T6 is turned on by a second light-emitting control signal of the second light-emitting control line ECL2 to connect the source electrode of the first transistor T1 to the second driving voltage line VDL. Thus, a second driving voltage VDD of the second driving voltage line VDL can be applied to the source electrode of the first transistor T1.

[0116] A first capacitor CP1 is formed between the first node N1 and the drain electrode of the second transistor T2. A second capacitor CP2 is formed between the gate electrode of the first transistor T1 and the second drive voltage line VDL.

[0117] Each of the first transistors T1 to the sixth transistor T6 can be a metal-oxide-semiconductor field-effect transistor (MOSFET). For example, each of the first transistors T1 to the sixth transistor T6 can be a p-type MOSFET, but the embodiments in this specification are not limited thereto. Each of the first transistors T1 to the sixth transistor T6 can be an n-type MOSFET. Alternatively, some of the first transistors T1 to the sixth transistor T6 can be p-type MOSFETs, and the remaining transistors can be n-type MOSFETs.

[0118] Although Figure 5 The example illustrates the first sub-pixel SP1 comprising six transistors T1~T6 and two capacitors CP1 and CP2. However, it should be noted that the equivalent circuit diagram of the first sub-pixel SP1 is not limited to this. Figure 5 The situation is illustrated. For example, the number of transistors and capacitors in the first sub-pixel SP1 is not limited to... Figure 5 The situation shown.

[0119] Furthermore, the equivalent circuit diagrams of the second sub-pixel SP2 and the third sub-pixel SP3 can be combined with... Figure 5 The equivalent circuit diagram for the first sub-pixel SP1 is substantially the same. Therefore, the description of the equivalent circuit diagrams for the second sub-pixel SP2 and the third sub-pixel SP3 is omitted in this specification.

[0120] Figure 6 It is used for explanation Figure 3 A schematic floor plan of an example display panel is shown.

[0121] Reference Figure 6According to one embodiment, the display area DAA of the display panel 100 includes a plurality of pixels PX arranged in a matrix. According to one embodiment, the non-display area NDA of the display panel 100 includes a scan driving unit 610, a light-emitting driving unit 620, a data driving unit 700, a first distribution circuit 710, a second distribution circuit 720, a first pad PDA1, and a second pad PDA2.

[0122] The scan driving unit 610 can be arranged on the first side of the display area DAA, and the light-emitting driving unit 620 can be arranged on the second side of the display area DAA. For example, the scan driving unit 610 can be arranged on one side of the display area DAA in the first direction DR1, and the light-emitting driving unit 620 can be arranged on the other side of the display area DAA in the first direction DR1. However, the embodiments of this specification are not limited to this, and the scan driving unit 610 and the light-emitting driving unit 620 can be arranged on both the first side and the second side of the display area DAA.

[0123] The first pad portion PDA1 may include a plurality of first pads PD1 connected to pads or bumps of the circuit board 300 by conductive adhesive members. The first pad portion PDA1 may be disposed on the third side of the display area DAA. For example, the first pad portion PDA1 may be disposed on one side of the display area DAA in the second direction DR2. The first pad portion PDA1 may be disposed on the outside of the data drive unit 700 in the second direction DR2.

[0124] The second pad PDA2 may include multiple second pads PD2, which are equivalent to inspection pads used to check whether the display panel 100 is operating normally. The multiple second pads PD2 may be connected to a fixture or probe during the inspection process, or they may be connected to an inspection circuit board. The inspection circuit board may be a rigid printed circuit board made of a hard material or a flexible printed circuit board made of a soft material.

[0125] The second pad PDA2 can be arranged on the fourth side of the display area DAA. For example, the second pad PDA2 can be arranged on the other side of the display area DAA in the second direction DR2. The second pad PDA2 can be arranged on the outside of the second distribution circuit 720 in the second direction DR2.

[0126] The first distribution circuit 710 distributes the data voltage applied through the first pad PDA1 to multiple data lines DL. For example, the first distribution circuit 710 can distribute the data voltage applied through one first pad PD1 of the first pad PDA1 to P data lines DL (P is a positive integer greater than or equal to 2), thereby reducing the number of multiple first pads PD1. The first distribution circuit 710 can be arranged on the third side of the display area DAA of the display panel 100. For example, the first distribution circuit 710 can be arranged on one side of the second direction DR2 of the display area DAA.

[0127] The second distribution circuit 720 distributes the signal applied through the second pad PDA2 to the scan drive unit 610, the light emission drive unit 620, and the data line DL. The second pad PDA2 and the second distribution circuit 720 can be configured to check the operation of each pixel PX in the display area DAA. The second distribution circuit 720 can be arranged on the fourth side of the display area DAA of the display panel 100. For example, the second distribution circuit 720 can be arranged on the other side of the display area DAA in the second direction DR2.

[0128] The cathode connection CCA can be a display element layer EML ( Figure 9 The second electrode CAT () Figure 9 The region connected to the first driving voltage line VSL of the non-display area NDA. The cathode connection portion CCA can be arranged on the outer side of at least one side of the display area DAA. For example, the cathode connection portion CCA can be arranged on the outer side of at least one of the left, right, upper, and lower sides of the display area DAA. Alternatively, the cathode connection portion CCA can be arranged as follows: Figure 6 The diagram shows the arrangement around the display area DAA to minimize the deviation of the first drive voltage VSS in the display area DAA caused by the voltage drop (IR drop) or voltage rise (IR rising) of the second electrode CAT.

[0129] Figure 7 It is used for explanation Figure 6 A schematic enlarged plan view of an example of the display area shown. Figure 8 It is used for explanation Figure 6 A schematic enlarged plan view of another example of the display area shown.

[0130] Reference Figure 7 and Figure 8 Each of the multiple pixels PX includes a first light-emitting region EA1 as the light-emitting region of the first sub-pixel SP1, a second light-emitting region EA2 as the light-emitting region of the second sub-pixel SP2, and a third light-emitting region EA3 as the light-emitting region of the third sub-pixel SP3.

[0131] The first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 can have the following characteristics: Figure 7 and Figure 8 The planar shape shown is a quadrilateral or hexagon, but the embodiments in this specification are not limited to this. The first light-emitting area EA1, the second light-emitting area EA2, and the third light-emitting area EA3 may have other polygonal, circular, elliptical, or irregular planar shapes other than quadrilaterals and hexagons.

[0132] like Figure 7 As shown, in each of the plurality of pixels PX, the first light-emitting region EA1 and the second light-emitting region EA2 can be adjacent in the first direction DR1. Furthermore, the first light-emitting region EA1 and the third light-emitting region EA3 can be adjacent in the first direction DR1. Furthermore, the second light-emitting region EA2 and the third light-emitting region EA3 can be adjacent in the second direction DR2. The areas of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 can be different.

[0133] Or, such as Figure 8 As shown, the light-emitting regions EA1, EA2, EA3, and EA4 can have a hexagonal planar shape. In this case, the first light-emitting region EA1 and the third light-emitting region EA3 can be adjacent in the first direction DR1, and the second light-emitting region EA2 and the fourth light-emitting region EA4 can be adjacent in the second direction DR2. Furthermore, the first light-emitting region EA1 and the second light-emitting region EA2 can be adjacent in the first oblique direction DD1, and the second light-emitting region EA2 and the third light-emitting region EA3 can be adjacent in the second oblique direction DD2. Also, the first light-emitting region EA1 and the fourth light-emitting region EA4 can be adjacent in the second oblique direction DD2, and the third light-emitting region EA3 and the fourth light-emitting region EA4 can be adjacent in the first oblique direction DD1. The first oblique direction DD1 is the direction between the first direction DR1 and the second direction DR2, and can indicate a direction inclined at 45° relative to the first direction DR1 and the second direction DR2. The second oblique direction DD2 can be a direction orthogonal to the first oblique direction DD1.

[0134] The first sub-pixel SP1 can emit light of a first color, the second sub-pixel SP2 can emit light of a second color, and the third sub-pixel SP3 can emit light of a third color. Here, the first color can be light in the blue wavelength band, the second color can be light in the green wavelength band, and the third color can be light in the red wavelength band. For example, the blue wavelength band can represent light whose peak wavelength is contained in the wavelength band of approximately 370nm to 460nm, the green wavelength band can represent light whose peak wavelength is contained in the wavelength band of approximately 480nm to 560nm, and the red wavelength band can represent light whose peak wavelength is contained in the wavelength band of approximately 600nm to 750nm.

[0135] like Figure 7 As shown, each of the multiple pixels PX can include three luminous regions EA1, EA2, and EA3, or as... Figure 8 As shown, it may also include four light-emitting regions EA1, EA2, EA3, and EA4. In this case, the fourth light-emitting region EA4 can emit light of the same second color as the second light-emitting region EA2, but the embodiments in this specification are not limited to this.

[0136] The light-emitting areas of multiple pixels PX can be arranged as a stripe structure with the light-emitting areas aligned along the first direction DR1, such as... Figure 8 The luminescent regions EA1, EA2, EA3, and EA4 shown are arranged in a diamond shape by the PENTILE. ® A hexagonal structure is a structure or luminescent region that has a hexagonal arrangement.

[0137] Figure 9 It is used to explain along Figure 7 A schematic cross-sectional view of an example display panel obtained by the I1-I1' line shown.

[0138] Reference Figure 9 The display panel 100 includes a semiconductor backplane (SBP), a light-emitting element backplane (EBP), a display element layer (EML), a packaging layer (TFE), an adhesive layer (ADL), an optical layer (OPL), a cover layer (CVL), and a polarizing plate (POL).

[0139] The semiconductor backplane (SBP) includes a semiconductor substrate (SSUB) containing multiple pixel transistors (PTRs), multiple semiconductor insulating films covering the multiple pixel transistors (PTRs), and multiple contact terminals (CTEs) electrically connected to the multiple pixel transistors (PTRs). The multiple pixel transistors (PTRs) can be combined... Figure 6 The first transistor T1 to the sixth transistor T6 are described.

[0140] The semiconductor substrate SSUB can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB can be a substrate doped with a type I impurity. Multiple well regions WA can be arranged on the upper surface of the semiconductor substrate SSUB. The multiple well regions WA can be regions doped with a type II impurity. The type II impurity can be different from the aforementioned type I impurity. For example, if the type I impurity is a p-type impurity, the type II impurity can be an n-type impurity. Alternatively, if the type I impurity is an n-type impurity, the type II impurity can be a p-type impurity.

[0141] Each of the multiple well regions WA includes a source region SA corresponding to the source electrode of the pixel transistor PTR, a drain region DA corresponding to the drain electrode, and a channel region CH disposed between the source region SA and the drain region DA.

[0142] A lower insulating film (BINS) can be disposed between the gate electrode GE and the well region WA. A side insulating film (SINS) can be disposed on the side surface of the gate electrode GE. The side insulating film (SINS) can be disposed on the lower insulating film (BINS).

[0143] Each of the source region SA and drain region DA can be a region doped with a type I impurity. The gate electrode GE of the pixel transistor PTR can overlap with the well region WA on the third direction DR3, which is the thickness direction of the semiconductor substrate SSUB. The channel region CH can overlap with the gate electrode GE on the third direction DR3. The source region SA can be disposed on one side of the gate electrode GE, and the drain region DA can be disposed on the other side of the gate electrode GE.

[0144] Each of the multiple well regions WA also includes a first low-concentration impurity region LDD1 disposed between the channel region CH and the source region SA, and a second low-concentration impurity region LDD2 disposed between the channel region CH and the drain region DA. The first low-concentration impurity region LDD1 may be a region having a lower impurity concentration than the source region SA due to the lower insulating film BINS. The second low-concentration impurity region LDD2 may be a region having a lower impurity concentration than the drain region DA due to the lower insulating film BINS. Through the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2, the distance between the source region SA and the drain region DA can be increased, thereby increasing the length of the channel region CH of each of the pixel transistors PTR.

[0145] The first semiconductor insulating film SINS1 can be disposed on the semiconductor substrate SSUB. The second semiconductor insulating film SINS2 can be disposed on the first semiconductor insulating film SINS1.

[0146] Multiple contact terminals (CTEs) can be arranged on the second semiconductor insulating film (SINS2). The multiple contact terminals (CTEs) can be connected to one of the gate electrode (GE), source region (SA), and drain region (DA) of each pixel transistor (PTR) through holes penetrating the first semiconductor insulating film (SINS1) and the second semiconductor insulating film (SINS2), respectively. The multiple contact terminals (CTEs) can be formed using one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing one of these materials.

[0147] A third semiconductor insulating film (SINS3) may be disposed on the side surface of each of the plurality of contact terminals (CTEs). The upper surface of each of the plurality of contact terminals (CTEs) may be exposed without being covered by the third semiconductor insulating film (SINS3).

[0148] Each of the first semiconductor insulating film SINS1, the second semiconductor insulating film SINS2, and the third semiconductor insulating film SINS3 can be made of silicon carbon nitride (SiCN) or silicon oxide (SiO2). x The inorganic membranes formed are of the series ), but the embodiments in this specification are not limited thereto.

[0149] The semiconductor substrate SSUB can be replaced by a glass substrate or a polymer resin substrate such as a polyimide substrate. In this case, thin film transistors can be arranged on the glass substrate or the polymer resin substrate. The glass substrate can be a rigid substrate that cannot be bent, while the polymer resin substrate can be a flexible substrate that can be bent or folded.

[0150] The backplane EBP of the light-emitting element includes multiple conductive layers ML1~ML8, multiple vias VA1~VA9, and multiple insulating films INS1~INS9. Furthermore, the backplane EBP includes a first conductive layer ML1 to an eighth conductive layer ML8 disposed between the multiple insulating films INS1~INS9.

[0151] The first insulating film INS1 to the ninth insulating film INS9 serves to insulate the first conductive layer ML1 to the eighth conductive layer ML8. The first conductive layer ML1 to the eighth conductive layer ML8 are connected to multiple contact terminals CTE exposed in the semiconductor backplane SBP. Figure 6 The function of the circuit for the first sub-pixel SP1 shown.

[0152] For example, only the first transistor T1 to the sixth transistor T6 are formed on the semiconductor backplane SBP. The connection between the first transistor T1 to the sixth transistor T6, as well as the first capacitor CP1 and the second capacitor CP2, are realized through the first conductive layer ML1 to the eighth conductive layer ML8. Furthermore, the connection between the drain region corresponding to the drain electrode of the fourth transistor T4, the source region corresponding to the source electrode of the fifth transistor T5, and the first electrode AND of the light-emitting element LE can also be realized through the first conductive layer ML1 to the eighth conductive layer ML8.

[0153] The first conductive layers ML1 to ML8 and the first vias VA1 to VA8 can be formed using substantially the same material. The first conductive layers ML1 to ML8 and the first vias VA1 to VA8 can be formed using one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing one of these. The first vias VA1 to VA8 can be formed using substantially the same material. The first insulating film INS1 to INS8 can be made using silicon oxide (SiO2). x The inorganic membranes formed are of the series ), but the embodiments in this specification are not limited thereto.

[0154] The ninth insulating film INS9 can be disposed on the eighth insulating film INS8 and the eighth conductive layer ML8. The ninth insulating film INS9 can be made of silicon oxide (SiO2). x The inorganic membranes formed are of the series ), but the embodiments in this specification are not limited thereto.

[0155] Each of the ninth vias VA9 can be connected to the exposed eighth conductive layer ML8 by passing through the ninth insulating film INS9. The ninth vias VA9 can be formed using one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing one of them.

[0156] The display element layer (EML) can be arranged on the backplane (EBP) of the light-emitting element. The display element layer (EML) may include a tenth insulating film (INS10), an eleventh insulating film (INS11), a reflective electrode (RL), a first electrode (AND), a light-emitting stack (IL), a second electrode (CAT), a pixel definition film (PDL), and multiple trenches (TRC).

[0157] A reflective electrode RL can be arranged on the ninth insulating film INS9. The reflective electrode RL may include one or more reflective electrodes RL1, RL2, RL3, and RL4. For example, the reflective electrode RL may be as follows: Figure 9The area shown includes a first reflective electrode RL1, a second reflective electrode RL2, a third reflective electrode RL3, and a fourth reflective electrode RL4.

[0158] The first reflective electrode RL1 can be disposed on the ninth insulating film INS9 and can be connected to the ninth via VA9. Each of the second reflective electrodes RL2 can be disposed on its corresponding first reflective electrode RL1. Each of the third reflective electrodes RL3 can be disposed on its corresponding second reflective electrode RL2. Each of the fourth reflective electrodes RL4 can be disposed on its corresponding third reflective electrode RL3.

[0159] Since the second reflective electrode RL2 is an electrode that substantially reflects light from the light-emitting element LE, the thickness of the second reflective electrode RL2 can be greater than the thickness of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4.

[0160] The first reflective electrode RL1 can be formed using one or an alloy of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). For example, the first reflective electrode RL1 may include titanium nitride (TiN), the second reflective electrode RL2 may include aluminum (Al), the third reflective electrode RL3 may include titanium nitride (TiN), and the fourth reflective electrode RL4 may include titanium (Ti).

[0161] The tenth insulating film INS10 can be disposed on the ninth insulating film INS9. The tenth insulating film INS10 can be disposed between adjacent reflective electrodes RL. The tenth insulating film INS10 can be a film used to flatten the step difference caused by the reflective electrode RL. The eleventh insulating film INS11 can be disposed on the tenth insulating film INS10 and the reflective electrode RL.

[0162] The tenth insulating film INS10 and the eleventh insulating film INS11 can utilize silicon dioxide (SiO2). x The inorganic membranes formed are of the series ), but the embodiments in this specification are not limited thereto.

[0163] The eleventh insulating film INS11 can be an optical auxiliary layer used to match the resonant distance of light emitted from the light-emitting stack IL in at least one of the first sub-pixels SP1, SP2, and SP3. The thickness of the eleventh insulating film INS11 can be different in the first sub-pixels SP1, SP2, and SP3. That is, in order to adjust the distance from the reflective electrode RL to the first electrode AND according to the main peak wavelength of the light emitted from each of the first sub-pixels SP1, SP2, and SP3, the thickness of the eleventh insulating film INS11 can be set in each of the first sub-pixels SP1, SP2, and SP3.

[0164] For example, such as Figure 9 As shown, the thickness of the eleventh insulating film INS11 in the first sub-pixel SP1 can be greater than the thickness of the eleventh insulating film INS11 in the second sub-pixel SP2, and the thickness of the eleventh insulating film INS11 in the second sub-pixel SP2 can be greater than the thickness of the eleventh insulating film INS11 in the third sub-pixel SP3. In this case, the distance between the first electrode AND and the reflective electrode RL in the first sub-pixel SP1 can be greater than the distance between the first electrode AND and the reflective electrode RL in the second sub-pixel SP2. Furthermore, the distance between the first electrode AND and the reflective electrode RL in the second sub-pixel SP2 can be greater than the distance between the first electrode AND and the reflective electrode RL in the third sub-pixel SP3.

[0165] Each of the tenth vias VA10 can be connected to the exposed fourth reflective electrode RL4 through the eleventh insulating film INS11. The tenth vias VA10 can be formed using one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing one of these. The thickness of the tenth via VA10 in the first sub-pixel SP1 can be greater than the thickness of the tenth via VA10 in the second sub-pixel SP2, and the thickness of the tenth via VA10 in the second sub-pixel SP2 can be greater than the thickness of the tenth via VA10 in the third sub-pixel SP3.

[0166] The first electrode AND of each of the light-emitting elements LE can be disposed on the eleventh insulating film INS11 and can be connected to the tenth via VA10. The first electrode AND of each of the light-emitting elements LE can be connected to the drain region DA or source region SA of the pixel transistor PTR through the tenth via VA10, the reflective electrode RL, the first vias VA1 to the ninth via VA9, the first conductive layers ML1 to the eighth conductive layers ML8, and the contact terminal CTE. The first electrode AND of each of the light-emitting elements LE can be formed using one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing one of them. For example, the first electrode AND of each of the light-emitting elements LE can be titanium nitride (TiN).

[0167] A pixel definition film (PDL) can be disposed on a portion of the first electrode AND of each of the light-emitting elements (LEs). The PDL can cover the edge of the first electrode AND of each of the light-emitting elements (LEs). The PDL can divide a first light-emitting region EA1, a second light-emitting region EA2, and a third light-emitting region EA3. Each of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 can be a region of the light-emitting element LE on which the first electrode AND, the light-emitting stack IL, and the second electrode CAT are disposed.

[0168] The first light-emitting region EA1 can be defined as the region in the first sub-pixel SP1 where a first electrode AND, a light-emitting stack IL, and a second electrode CAT are stacked sequentially and emit light. The second light-emitting region EA2 can be defined as the region in the second sub-pixel SP2 where a first electrode AND, a light-emitting stack IL, and a second electrode CAT are stacked sequentially and emit light. The third light-emitting region EA3 can be defined as the region in the third sub-pixel SP3 where a first electrode AND, a light-emitting stack IL, and a second electrode CAT are stacked sequentially and emit light.

[0169] A pixel definition film (PDL) may include a first pixel definition film (PDL1), a second pixel definition film (PDL2), and a third pixel definition film (PDL3). The first pixel definition film (PDL1) may be disposed on the edge of the first electrode AND of each of the light-emitting elements (LEs). The second pixel definition film (PDL2) may be disposed on the first pixel definition film (PDL1), and the third pixel definition film (PDL3) may be disposed on the second pixel definition film (PDL2). The first pixel definition film (PDL1), the second pixel definition film (PDL2), and the third pixel definition film (PDL3) may be made of silicon oxide (SiO2). xInorganic films of the series ( ) are formed. Alternatively, compared to the first pixel defining film PDL1 and the third pixel defining film PDL3, silicon nitride (SiN) is used. x The inorganic film formation of the series, the second pixel defining film PDL2 can utilize silicon oxide (SiO2) x The inorganic film is formed in a series of ( ) series. The thickness of each of the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 can be approximately 500 Å.

[0170] To prevent the first encapsulated inorganic film TFE1 from breaking due to step coverage (step coverage), the first pixel definition film PDL1, the second pixel definition film PDL2, and the third pixel definition film PDL3 can have a stepped profile with a stepped morphology. Step coverage refers to the ratio of the thickness of the film formed on the inclined portion to the thickness of the film formed on the flat portion. The lower the step coverage, the higher the probability that the film will break on the inclined portion.

[0171] Each of the plurality of trench TRCs may extend through the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3. Each of the plurality of trench TRCs may have a morphology in which at least a portion of the eleventh insulating film INS11 is recessed.

[0172] At least one trench TRC can be arranged between adjacent sub-pixels SP1, SP2, and SP3. Figure 9 The example shown illustrates a scenario where two trench TRCs are arranged between adjacent sub-pixels SP1, SP2, and SP3, but the embodiments described in this specification are not limited to this.

[0173] The light-emitting stack IL can include multiple stacked layers IL1, IL2, and IL3. Figure 9 The example shown illustrates a case where the light-emitting stack IL has a three-tandem structure including a first stacked layer IL1, a second stacked layer IL2, and a third stacked layer IL3; however, the embodiments described in this specification are not limited to this. For example, as... Figure 10 As shown, the light-emitting stack IL can have a dual-tandem structure comprising two stacked layers.

[0174] In a three-stage cascade structure, the light-emitting stack IL can have a cascade structure comprising multiple stacked layers IL1, IL2, and IL3 that emit different colors of light. For example, the light-emitting stack IL may include a first stacked layer IL1 that emits light of a first color, a second stacked layer IL2 that emits light of a second color, and a third stacked layer IL3 that emits light of a third color. The first stacked layer IL1, the second stacked layer IL2, and the third stacked layer IL3 may be stacked sequentially.

[0175] The first stacked layer IL1 may have a structure in which a first hole transport layer, a first light-emitting layer emitting light of a first color, and a first electron transport layer are stacked sequentially. The second stacked layer IL2 may have a structure in which a second hole transport layer, a second light-emitting layer emitting light of a second color, and a second electron transport layer are stacked sequentially. The third stacked layer IL3 may have a structure in which a third hole transport layer, a third light-emitting layer emitting light of a third color, and a third electron transport layer are stacked sequentially.

[0176] A first charge generation layer for supplying charge to the second stacked layer IL2 and electrons to the first stacked layer IL1 may be disposed between the first stacked layer IL1 and the second stacked layer IL2. The first charge generation layer may include an n-type charge generation layer that supplies electrons to the first stacked layer IL1 and a p-type charge generation layer that supplies holes to the second stacked layer IL2. The n-type charge generation layer may include a dopant of metallic material.

[0177] A second charge generation layer for supplying charge to the third stacked layer IL3 and electrons to the second stacked layer IL2 may be disposed between the second stacked layer IL2 and the third stacked layer IL3. The second charge generation layer may include an n-type charge generation layer that supplies electrons to the second stacked layer IL2 and a p-type charge generation layer that supplies holes to the third stacked layer IL3.

[0178] A first stacked layer IL1 can be disposed on the first electrode AND and the pixel defining film PDL, and a residual film RIL disposed on the bottom surface of the trench TRC in each trench TRC can be formed using the same material as the first stacked layer IL1. Due to the trench TRC, the first stacked layer IL1 can be disconnected between adjacent sub-pixels SP1, SP2, SP3. A second stacked layer IL2 can be disposed on the first stacked layer IL1. Due to the trench TRC, the second stacked layer IL2 can be disconnected between adjacent sub-pixels SP1, SP2, SP3. In the trench TRC, a void ESS or an empty space can be disposed between the residual film RIL and the second stacked layer IL2. A third stacked layer IL3 can be disposed on the second stacked layer IL2. The third stacked layer IL3 can be not disconnected by the trench TRC and can be arranged to cover the second stacked layer IL2 in each trench TRC.

[0179] In a three-series structure, each of the multiple trench TRCs can be a structure for disconnecting the first, second, and third hole transport layers, the first charge generation layer, and the second charge generation layer of the display feature layer EML between adjacent sub-pixels SP1, SP2, and SP3. Furthermore, in a two-series structure, each of the multiple trench TRCs can be a structure for disconnecting the charge generation layer and the lower stacked layer disposed between the lower and upper stacked layers.

[0180] To stably disconnect the first stacked layer IL1 to the second stacked layer IL2 of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3, the height of each of the plurality of trench TRCs can be greater than the height of the pixel definition film PDL. The height of each of the plurality of trench TRCs refers to the length of each of the plurality of trench TRCs on the third-direction DR3. The height of the pixel definition film PDL refers to the length of the pixel definition film PDL on the third-direction DR3. To disconnect the hole transport layer and charge generation layer of the light-emitting stack IL of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3, other structures can be used instead of trench TRCs. For example, inverted cone-shaped partition walls can be arranged on the pixel definition film PDL instead of trench TRCs.

[0181] Furthermore, in Figure 9 The example shown illustrates a case where light-emitting stacked elements IL are arranged in the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3. However, the embodiments described in this specification are not limited to this. For example, the first light-emitting layer may be arranged in place of the light-emitting stacked elements IL in the first light-emitting region EA1, and may not be arranged in the second light-emitting region EA2 and the third light-emitting region EA3. Furthermore, the second light-emitting layer may be arranged in the second light-emitting region EA2, and may not be arranged in the first light-emitting region EA1 and the third light-emitting region EA3. Furthermore, the third light-emitting layer may be arranged in the third light-emitting region EA3, and may not be arranged in the first light-emitting region EA1 and the second light-emitting region EA2. In this case, the first color filter CF1, the second color filter CF2, and the third color filter CF3 of the optical layer OPL can be omitted.

[0182] The second electrode CAT can be disposed on the light-emitting stack IL. That is, the second electrode CAT can be disposed on the third stack layer IL3. The second electrode CAT can be formed using a transparent conductive oxide (TCO) such as ITO or IZO that can transmit light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the second electrode CAT is formed using a semi-transmissive conductive material, the light extraction efficiency of each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be improved due to the microcavity.

[0183] The encapsulation layer TFE can be disposed on the display element layer EML. The encapsulation layer TFE may include at least one inorganic film TFE1 and TFE3 to prevent oxygen or moisture from penetrating into the display element layer EML. The first encapsulation inorganic film TFE1 can be disposed on the second electrode CAT, and the second encapsulation inorganic film TFE3 can be disposed on the first encapsulation inorganic film TFE1. The first encapsulation inorganic film TFE1 and the second encapsulation inorganic film TFE3 can be made of silicon nitride (SiN). x ), silicon oxynitride (SiON), silicon oxide (SiO) x Titanium oxide (TiO) x ) and aluminum oxide (AlO x Multilayer films are formed by alternating stacking of two or more inorganic membranes.

[0184] Furthermore, the encapsulation layer TFE may include at least one encapsulation organic film TFE2 to protect the display element layer EML from foreign matter such as dust. The encapsulation organic film TFE2 may be disposed between the first encapsulation inorganic film TFE1 and the second encapsulation inorganic film TFE3. The encapsulation organic film TFE2 may be a monomer. Alternatively, the encapsulation organic film TFE2 may be an organic film made of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0185] The adhesive layer ADL can be a layer used to bond the encapsulation layer TFE and the optical layer OPL. The adhesive layer ADL can be a double-sided adhesive component. Furthermore, the adhesive layer ADL can be a transparent adhesive component such as a transparent adhesive or a transparent adhesive resin.

[0186] The optical layer OPL may include multiple color filters CF1, CF2, CF3, multiple lenses LNS, and a filler layer FIL. The multiple color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1, the second color filter CF2, and the third color filter CF3 may be arranged on the adhesive layer ADL.

[0187] The first color filter CF1 can overlap with the first emitting region EA1 of the first sub-pixel SP1. The first color filter CF1 can transmit light of a first color (i.e., light in the blue wavelength band). The blue wavelength band can be approximately 370 nm to 460 nm. Therefore, the first color filter CF1 can transmit light of the first color emitted from the first emitting region EA1.

[0188] The second color filter CF2 can overlap with the second emitting region EA2 of the second sub-pixel SP2. The second color filter CF2 can transmit light of a second color (i.e., light in the green wavelength band). The green wavelength band can be approximately 480 nm to 560 nm. Therefore, the second color filter CF2 can transmit light of the second color emitted from the second emitting region EA2.

[0189] The third color filter CF3 can overlap with the third emitting region EA3 of the third sub-pixel SP3. The third color filter CF3 can transmit light of the third color (i.e., light in the red wavelength band). The red wavelength band can be approximately 600 nm to 750 nm. Therefore, the third color filter CF3 can transmit light of the third color emitted from the third emitting region EA3.

[0190] Each of the plurality of lenses LNS can be arranged on each of the first color filter CF1, the second color filter CF2, and the third color filter CF3. Each of the plurality of lenses LNS can be a structure for improving the ratio of light directed toward the front of the display device 20. Each of the plurality of lenses LNS can have a cross-sectional shape that convexes in the upward direction.

[0191] The filler layer (FIL) can be disposed on multiple lens lenses (LNS). The filler layer (FIL) can have a predetermined refractive index so that light travels in the third direction (DR3) at the interface between the multiple lens lenses (LNS) and the filler layer (FIL). Furthermore, the filler layer (FIL) can be a planarization layer. The filler layer (FIL) can be an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0192] A capping layer CVL can be disposed on a filler layer FIL. The capping layer CVL can be a glass substrate or a polymer resin such as a resin. When the capping layer CVL is a glass substrate, it can be attached to the filler layer FIL. In this case, the filler layer FIL can function as an adhesive for the capping layer CVL. When the capping layer CVL is a glass substrate, it can function as an encapsulation substrate. When the capping layer CVL is a polymer resin such as a resin, it can be directly coated onto the filler layer FIL.

[0193] The polarizing plate (POL) can be disposed on one surface of the CVL cover layer. The polarizing plate (POL) can be a structure used to prevent reduced visibility caused by external light reflection. The polarizing plate (POL) can include a linear polarizing plate and a phase retardation film. For example, the phase retardation film can be a λ / 4 plate (quarter-wave plate), but the embodiments in this specification are not limited thereto. However, the polarizing plate (POL) can be omitted if visibility caused by external light reflection is sufficiently improved by the first color filter CF1, the second color filter CF2, and the third color filter CF3.

[0194] Figure 10 It is used to explain along Figure 7 A schematic cross-sectional view of another example of a display panel obtained by the I1-I1' line shown.

[0195] Figure 10 Implementation examples and Figure 9 The difference in this embodiment is that the first electrode AND of each of the light-emitting elements LE is in contact with and electrically connected to the side surface of the connection electrode ANC connected to the eighth conductive layer ML8. Furthermore, Figure 10 Implementation examples and Figure 9 The difference in this embodiment is that the trench TRC is omitted, and instead, the third pixel defining film PDL3 and the fourth pixel defining film PDL4 have a roof-shaped or mushroom-shaped cross-sectional structure. Figure 10 In the embodiments, the terms "and" are omitted. Figure 9 The embodiments are described repeatedly.

[0196] Reference Figure 10Multiple connecting electrodes ANC can be respectively arranged on the first portion AA1 of the ninth insulating film INS9. The multiple connecting electrodes ANC can be respectively arranged on their corresponding first portions AA1 of the ninth insulating film INS9. The multiple connecting electrodes ANC can be formed using one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), alloys containing one of them, or transparent conductive oxides. For example, the multiple connecting electrodes ANC may include titanium (Ti), titanium nitride (TiN), indium tin oxide (ITO), or indium zinc oxide (IZO), but the embodiments in this specification are not limited thereto.

[0197] Multiple reflective electrodes RL can be arranged on multiple connecting electrodes ANC. The multiple reflective electrodes RL can be formed using one or an alloy containing one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). For example, each of the multiple reflective electrodes RL may include aluminum (Al), which has high reflectivity.

[0198] Multiple optical auxiliary films (OALs) can be respectively arranged on multiple reflective electrodes (RLs). Multiple optical auxiliary films (OALs) can be respectively arranged on their corresponding reflective electrodes (RLs). Multiple optical auxiliary films (OALs) can utilize silicon oxide (SiO2). x The inorganic membranes formed are of the series ), but the embodiments in this specification are not limited thereto.

[0199] The stepped layer STPL can be disposed on the reflective electrode RL in each of the first light-emitting region EA1 and the third light-emitting region EA3, and an optical auxiliary film OAL can be disposed on the stepped layer STPL. In the second light-emitting region EA2, only the optical auxiliary film OAL can be disposed on the reflective electrode RL. The thickness of the optical auxiliary film OAL can be substantially the same in the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3.

[0200] Due to the stepped layer STPL, the distance between the reflective electrode RL and the first electrode AND in the first light-emitting region EA1 and the third light-emitting region EA3 can be greater than the distance between the reflective electrode RL and the first electrode AND in the second light-emitting region EA2. The thickness of the stepped layer STPL and the thickness of the optical auxiliary film OAL can be determined by considering the wavelength and resonant distance of the light emitted from the first stacked layer IL1 of the light-emitting stack IL and the wavelength and resonant distance of the light emitted from the second stacked layer IL2.

[0201] Each of the light-emitting elements LE may include a first electrode AND, a light-emitting stack IL, and a second electrode CAT.

[0202] The first electrode AND of each of the light-emitting elements LE can be disposed on its corresponding optical auxiliary film OAL. Since the connecting electrode ANC, the reflective electrode RL, and the optical auxiliary film OAL are stacked sequentially, the first electrode AND of each of the light-emitting elements LE can be disposed on the upper and side surfaces of the optical auxiliary film OAL, the side surface of the reflective electrode RL, and the side surface of the connecting electrode ANC. Thus, the first electrode AND of each of the light-emitting elements LE can contact and be electrically connected to the side surfaces of the reflective electrode RL and the connecting electrode ANC. Therefore, compared to connecting the first electrode AND of each of the light-emitting elements LE to the reflective electrode RL, which is exposed through a through-hole in the optical auxiliary film OAL, masking processes can be reduced, thus offering the advantages of reduced manufacturing costs and increased manufacturing efficiency.

[0203] The first electrode AND of each of the light-emitting elements LE can be connected to the drain region DA or source region SA of the pixel transistor PTR through the connecting electrode ANC, the first via VA1 to the ninth via VA9, the first conductive layer ML1 to the eighth conductive layer ML8 and the contact terminal CTE.

[0204] The ninth insulating film INS9 may include a first portion AA1 that overlaps with the connecting electrode ANC on the third-direction DR3 and a second portion AA2 that does not overlap with the connecting electrode ANC on the third-direction DR3. The thickness of the first portion AA1 and the thickness of the second portion AA2 of the ninth insulating film INS9 may be substantially the same.

[0205] Alternatively, the thickness of the first portion AA1 of the ninth insulating film INS9 can be greater than the thickness of the second portion AA2. In this case, the side surface of the first portion AA1 of the ninth insulating film INS9 can be exposed, and the first electrode AND of each of the light-emitting elements LE can be arranged on the exposed side surface of the first portion AA1 of the ninth insulating film INS9.

[0206] The first electrode AND of each of the light-emitting elements LE can be formed using one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or transparent conductive oxide containing one of these. For example, the first electrode AND of each of the light-emitting elements LE may include titanium nitride (TiN), indium tin oxide (ITO), or indium zinc oxide (IZO), but the embodiments described in this specification are not limited thereto.

[0207] A pixel definition film (PDL) can be disposed on a portion of the first electrode AND of each of the light-emitting elements (LEs). The PDL can cover the edge of the first electrode AND of each of the light-emitting elements (LEs). The PDL can divide a first light-emitting region EA1, a second light-emitting region EA2, and a third light-emitting region EA3.

[0208] The pixel definition film (PDL) may include a first pixel definition film (PDL1), a second pixel definition film (PDL2), a third pixel definition film (PDL3), and a fourth pixel definition film (PDL4).

[0209] The first pixel defining film PDL1 can be disposed on the first electrode AND of each of the light-emitting elements LE. Specifically, the first pixel defining film PDL1 can cover a portion of the upper surface of the first electrode AND disposed on the optical auxiliary film OAL. Furthermore, the first pixel defining film PDL1 can cover the first electrode AND disposed on the side surface of the connecting electrode ANC, the side surface of the reflective electrode RL, and the side surface of the optical auxiliary film OAL. The first pixel defining film PDL1 can be disposed on the upper surface of the second portion AA2 of the ninth insulating film INS9.

[0210] The planarization film PNS is a film used to planarize the step difference caused by the connecting electrode ANC, the reflective electrode RL and the optical auxiliary film OAL.

[0211] The planarization film PNS can be disposed on the first pixel definition film PDL1 covering the first electrode AND, wherein the first electrode AND is disposed on the side surface of the connecting electrode ANC, the side surface of the reflective electrode RL, and the side surface of the optical auxiliary film OAL. The planarization film PNS can be disposed on the first pixel definition film PDL1 disposed on the second part AA2 of the ninth insulating film INS9.

[0212] The planarization film PNS can be disposed between adjacent connecting electrodes ANC in the first direction DR1 or the second direction DR2. The planarization film PNS can be disposed between adjacent reflecting electrodes RL in the first direction DR1 or the second direction DR2. The planarization film PNS can be disposed between adjacent optical auxiliary films OAL in the first direction DR1 or the second direction DR2.

[0213] In the second light-emitting region EA2, there is no step layer STPL; conversely, in each of the first light-emitting region EA1 and the third light-emitting region EA3, there is a step layer STPL. Therefore, the height of the connecting electrode ANC, the reflective electrode RL, and the optical auxiliary film OAL in the second light-emitting region EA2 can be less than the height of the connecting electrode ANC, the reflective electrode RL, the step layer STPL, and the optical auxiliary film OAL in each of the first light-emitting region EA1 and the third light-emitting region EA3. Therefore, the planarization film PNS can cover the upper surface of the first pixel definition film PDL1, which is a first pixel definition film PDL1 disposed on the upper surface of the first electrode AND disposed in the second light-emitting region EA2.

[0214] In contrast, the upper surface of the planarization film PNS can be in flat contact with the upper surface of the first electrode AND disposed in the first light-emitting region EA1 and the third light-emitting region EA3. That is, the planarization film PNS may not cover the upper surface of the first pixel definition film PDL1, which is the first pixel definition film PDL1 disposed on the upper surface of the first electrode AND disposed in each of the first light-emitting regions EA1 and the third light-emitting region EA3.

[0215] The second pixel definition film PDL2 can be disposed on the first pixel definition film PDL1 and the planarization film PNS, the third pixel definition film PDL3 can be disposed on the second pixel definition film PDL2, and the fourth pixel definition film PDL4 can be disposed on the third pixel definition film PDL3. The first pixel definition film PDL1 and the third pixel definition film PDL3 can be made of silicon nitride (SiN). x In contrast to the inorganic film formation of the series, the second pixel defining film PDL2, the fourth pixel defining film PDL4, and the planarization film PNS can utilize silicon oxide (SiO2) to form the inorganic film. x The inorganic film formation of the first pixel definition film PDL1 is performed using a different material than the planarization film PNS. Therefore, it can act as a stopper in the chemical mechanical polishing process of the planarization film PNS.

[0216] Silicon oxide (SiO2) is used in the planarization film PNS and the second pixel definition film PDL2. x When inorganic films of the same series are formed in the same way, the planarization film PNS and the second pixel definition film PDL2 can be formed into a single film.

[0217] Since the length of the third pixel defining film PDL3 in one direction is less than the length of the fourth pixel defining film PDL4 in one direction, the lower surface of the fourth pixel defining film PDL4 can be exposed without being covered by the third pixel defining film PDL3. That is, the third pixel defining film PDL3 and the fourth pixel defining film PDL4 can have a roof-shaped or mushroom-shaped cross-sectional structure.

[0218] The light-emitting stack IL can be disposed on the first electrode AND and the pixel definition film PDL. The light-emitting stack IL can include a first stacked layer IL1 and a second stacked layer IL2 that emit different colors of light. In the case that the light-emitting stack IL has a dual-series structure, one of the first stacked layer IL1 and the second stacked layer IL2 can emit light in a wavelength range including one of the following colors: a first color, a second color, and a third color, while the other can emit light in a wavelength range including the other two colors. For example, the first stacked layer IL1 can emit light in a wavelength range including both the first color and the third color, and the second stacked layer IL2 can emit light in a wavelength range including the second color. Here, the first color of light can be light in the blue wavelength band, the second color of light can be light in the green wavelength band, and the third color of light can be light in the red wavelength band.

[0219] A charge generation layer for supplying charge to the second stacked layer IL2 and electrons to the first stacked layer IL1 may be disposed between the first stacked layer IL1 and the second stacked layer IL2. The charge generation layer may include an n-type charge generation layer that supplies electrons to the first stacked layer IL1 and a p-type charge generation layer that supplies holes to the second stacked layer IL2. The n-type charge generation layer may include a dopant of metallic material.

[0220] Since the first stacked layer IL1 cannot be formed on the lower surface of the fourth pixel-defining film PDL4, which is exposed and not covered by the third pixel-defining film PDL3, it can be broken by the roof-shaped or mushroom-shaped cross-sectional structure caused by the third pixel-defining film PDL3 and the fourth pixel-defining film PDL4. In this case, the first hole transport layer of the first stacked layer IL1 and the charge generation layer disposed between the first stacked layer IL1 and the second stacked layer IL2 can also be broken. Furthermore, in Figure 10The example illustrates a scenario where the second stacked layer IL2 is connected without being disconnected. However, the second hole transport layer of the second stacked layer IL2 can be disconnected, and the second electron transport layer of the second stacked layer IL2 can be connected without being disconnected. Therefore, leakage current can be prevented from flowing between adjacent light-emitting regions EA1, EA2, and EA3 through the first hole transport layer of the first stacked layer IL1, the second hole transport layer of the second stacked layer IL2, and the charge generation layer. Thus, it can be prevented that the light-emitting stacks IL in adjacent light-emitting regions EA1, EA2, and EA3 emit light other than the originally intended light due to the influence of the aforementioned current.

[0221] exist Figure 10 The example shown is a dual-tandem structure of a light-emitting stack IL comprising two stacked layers IL1 and IL2, but the embodiments described in this specification are not limited thereto. For example, as Figure 9 As shown, the light-emitting stack IL can have a three-tandem structure comprising three stacked layers. In this case, the charge generation layer between the first stacked layer IL1 and the second stacked layer IL2, and between the second stacked layer IL2 and the third stacked layer IL3, can be designed to be disconnected by adjusting the height of the third pixel defining film PDL3. Alternatively, as Figure 9 As shown, a trench TRC can be added that penetrates the first pixel definition film PDL1, the planarization film PNS, the second pixel definition film PDL2, and the third pixel definition film PDL3. In this case, the trench TRC can penetrate at least a portion of the eleventh insulating film INS11, but the embodiments in this specification are not limited thereto.

[0222] Figure 11 This is a schematic perspective view used to illustrate an example of a head-mounted display device. Figure 12 It is used for explanation Figure 11 A schematic exploded perspective view of the head-mounted display device shown.

[0223] Reference Figure 11 and Figure 12 According to one embodiment, a head-mounted display device 1000 includes a first display device 20_1, a second display device 20_2, a display device storage part 1100, a storage part cover 1200, a first eyepiece 1210, a second eyepiece 1220, a headband 1300, a middle frame 1400, a first optical component 1510, a second optical component 1520, and a control circuit board 1600.

[0224] The first display device 20_1 provides an image to the user's left eye, and the second display device 20_2 provides an image to the user's right eye. Because each of the first display device 20_1 and the second display device 20_2 is combined with... Figures 3 to 10The display devices 20 described are substantially the same, therefore the description of the first display device 20_1 and the second display device 20_2 is omitted.

[0225] The first optical component 1510 may be disposed between the first display device 20_1 and the first eyepiece 1210. The second optical component 1520 may be disposed between the second display device 20_2 and the second eyepiece 1220. Each of the first optical component 1510 and the second optical component 1520 may include at least one convex lens.

[0226] The intermediate frame 1400 can be arranged between the first display device 20_1 and the control circuit board 1600, and can also be arranged between the second display device 20_2 and the control circuit board 1600. The intermediate frame 1400 can support and fix the first display device 20_1, the second display device 20_2, and the control circuit board 1600.

[0227] The control circuit board 1600 can be arranged between the intermediate frame 1400 and the display device housing 1100. The control circuit board 1600 can be connected to the first display device 20_1 and the second display device 20_2 via connectors. The control circuit board 1600 can convert externally input image sources into digital video data DATA, and can transmit the digital video data DATA to the first display device 20_1 and the second display device 20_2 via connectors.

[0228] The control circuit board 1600 can transmit digital video data DATA corresponding to a left-eye image optimized for the user's left eye to the first display device 20_1, and can transmit digital video data DATA corresponding to a right-eye image optimized for the user's right eye to the second display device 20_2. Alternatively, the control circuit board 1600 can transmit the same digital video data DATA to both the first display device 20_1 and the second display device 20_2.

[0229] The display device housing 1100 serves to house the first display device 20_1, the second display device 20_2, the intermediate frame 1400, the first optical component 1510, the second optical component 1520, and the control circuit board 1600. The housing cover 1200 is arranged to cover the open side of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 for the user's left eye and a second eyepiece 1220 for the user's right eye. Figure 11 and Figure 12 The example shown illustrates a configuration where the first eyepiece 1210 and the second eyepiece 1220 are arranged separately, but the embodiments described herein are not limited to this. The first eyepiece 1210 and the second eyepiece 1220 may be combined into one.

[0230] The first eyepiece 1210 can be aligned with the first display device 20_1 and the first optical component 1510, and the second eyepiece 1220 can be aligned with the second display device 20_2 and the second optical component 1520. Therefore, the user can see the image of the first display device 20_1 magnified into a virtual image by the first optical component 1510 through the first eyepiece 1210, and can see the image of the second display device 20_2 magnified into a virtual image by the second optical component 1520 through the second eyepiece 1220.

[0231] The headband 1300 serves to secure the display device storage unit 1100 to the user's head, allowing the first eyepiece 1210 and the second eyepiece 1220 of the storage unit cover 1200 to remain positioned in the user's left and right eyes, respectively. When the display device storage unit 1100 is made lightweight and compact, the head-mounted display device 1000 can be equipped with, for example... Figure 13 The eyeglasses frame shown is used to replace the headband 1300.

[0232] Figure 13 This is a schematic perspective view used to illustrate another example of a head-mounted display device.

[0233] Reference Figure 13 According to one embodiment, the head-mounted display device 1000_1 may be a display device in which the display device storage unit 1200_1 is implemented as a lightweight and compact eyeglasses-shaped display device. According to one embodiment, the head-mounted display device 1000_1 may be equipped with a display device 20_3, a left eye lens 1010, a right eye lens 1020, a support frame 1030, eyeglass temples 1040 and 1050, optical components 1060, an optical path conversion component 1070, and a display device storage unit 1200_1.

[0234] The display device housing 1200_1 can house the display device 20_3, the optical component 1060, and the light path conversion component 1070. The image displayed on the display device 20_3 can be magnified by the optical component 1060, the light path can be converted by the light path conversion component 1070, and the image can be provided to the user's right eye through the right eye lens 1020. Thus, the user can view an augmented reality image—a combination of the virtual image displayed on the display device 20_3 and the real image seen through the right eye lens 1020—through their right eye.

[0235] exist Figure 13The example shown illustrates a display device storage unit 1200_1 positioned at the right end of the support frame 1030, but the embodiments described herein are not limited to this. For example, the display device storage unit 1200_1 may be positioned at the left end of the support frame 1030, in which case the image displayed on the display device 20_3 can be provided to the user's left eye. Alternatively, the display device storage unit 1200_1 may be positioned at both the left and right ends of the support frame 1030, in which case the user can view the image displayed on the display device 20_3 through both their left and right eyes.

[0236] Figure 14 This is a schematic diagram illustrating a deposition mask and a deposition apparatus including the deposition mask according to an embodiment of the present invention.

[0237] Reference Figure 14 The deposition apparatus 2000 can be used on the display panel 100 (see reference). Figure 3 In the manufacturing process of [the material], a light-emitting layer is formed on the backplane substrate 3000. For example, such as... Figure 9 As shown, a semiconductor backplane SBP and a light-emitting element backplane EBP can be arranged on the backplane substrate 3000, and a reflective electrode RL and insulating films INS10 and INS11 can be arranged on the light-emitting element backplane EBP. An electrode pattern can be arranged on the insulating film INS11; for example, a first electrode AND functioning as an anode electrode and a pixel definition film PDL exposing the first electrode AND can be arranged, and the first electrode AND can be electrically connected to the reflective electrode RL through a tenth via VA10. As an example, the deposition apparatus 2000 can form a first light-emitting layer on the first electrode AND of the first light-emitting region EA1. As another example, the deposition apparatus 2000 can form a second light-emitting layer on the first electrode AND of the second light-emitting region EA2. As yet another example, the deposition apparatus 2000 can form a third light-emitting layer on the first electrode AND of the third light-emitting region EA3.

[0238] The deposition apparatus 2000 may include a deposition source 2200 for providing a vapor phase deposition material on a backplane substrate 3000, a substrate chuck 2300 supporting the backplane substrate 3000 toward the deposition source 2200, and a mask chuck 2400 disposed between the deposition source 2200 and the substrate chuck 2300 and supporting a deposition mask 4000 toward the backplane substrate 3000. The deposition source 2200, the substrate chuck 2300, and the mask chuck 2400 may be disposed within a process chamber (or evaporation chamber) 2100.

[0239] The process chamber 2100 may be equipped with an internal space in which a deposition process for forming a deposited material layer on the backplane substrate 3000 can be performed. The process chamber 2100 may be connected to a vacuum pump (not shown), and the internal space of the process chamber 2100 may be created into a vacuum atmosphere by means of the vacuum pump. An opening (not shown) for entry and exit of the backplane substrate 3000 and the deposition mask 4000 may be provided on one side wall of the process chamber 2100, and the opening may be opened and closed by means of a gate valve (not shown).

[0240] The deposition source 2200 can be arranged inside the process chamber 2100, and the deposition material can be contained inside the deposition source 2200. The deposition source 2200 can cause the deposition material, such as organic material, inorganic material, conductive material, etc., to evaporate toward the backplane substrate 3000, and the evaporated deposition material can be deposited onto the backplane substrate 3000 through a deposition mask 4000. For example, the deposition source 2200 can cause the organic material used to form a light-emitting layer on the backplane substrate 3000 to evaporate, and can be equipped with a heater (not shown) for evaporating the organic material. The evaporated organic material can be deposited onto the electrode pattern on the backplane substrate 3000 through the deposition mask 4000. Figure 14 As shown, the deposition source 2200 is arranged on the central part of the bottom surface of the process chamber 2100. However, unlike this, the deposition source 2200 can also be configured to be able to move horizontally by means of a separate drive unit (not shown).

[0241] The substrate chuck 2300 can be disposed above the deposition source 2200 and supports the backplane substrate 3000 such that it faces the deposition source 2200. For example, the substrate chuck 2300 can be an electrostatic chuck that uses electrostatic force to hold the rear surface of the backplane substrate 3000. Specifically, an electrode pattern (e.g., a first electrode AND) can be disposed on the front surface of the backplane substrate 3000, and the substrate chuck 2300 can hold the rear surface of the backplane substrate 3000 such that the front surface of the backplane substrate 3000 faces downward (i.e., towards the deposition source 2200).

[0242] Multiple lifting fingers 2350 for loading the backplane substrate 3000 onto the substrate chuck 2300 can be arranged within the process chamber 2100. The lifting fingers 2350 can be arranged around the substrate chuck 2300 and the mask chuck 2400, and can be moved vertically by the finger drive unit 2360. For example, three or four lifting fingers 2350 can be arranged around the substrate chuck 2300 and the mask chuck 2400.

[0243] The backplate substrate 3000 can be moved into the process chamber 2100 by a transfer robot (not shown), and can be transferred from below the substrate suction cup 2300 to the lifting fingers 2350 by the transfer robot. At this time, the rear surface of the backplate substrate 3000 can face the lower surface of the substrate suction cup 2300, and the multiple lifting fingers 2350 can support the edge of the front surface of the backplate substrate 3000. The finger drive unit 2360 can raise the lifting fingers 2350, so that the backplate substrate 3000 is adjacent to the lower surface of the substrate suction cup 2300, and the rear surface of the backplate substrate 3000 can be held on the lower surface of the substrate suction cup 2300 by electrostatic force.

[0244] Each of the finger drive units 2360 can be arranged on the upper cover (lid) of the process chamber 2100 and can be connected to the lifting finger 2350 via a drive shaft 2362 extending vertically through the upper cover of the process chamber 2100. The finger drive unit 2360 can move the lifting finger 2350 vertically to load or unload the backplane substrate 3000. Furthermore, the finger drive unit 2360 can rotate the lifting finger 2350 about the drive shaft 2362. For example, the finger drive unit 2360 can rotate the lifting finger 2350 so that the end of the lifting finger 2350 does not overlap with the substrate suction cup 2300 and the mask suction cup 2400, thereby enabling the lifting finger 2350 to move vertically. Furthermore, the finger drive unit 2360 can rotate the lifting finger 2350 so that the end of the lifting finger 2350 overlaps with the edge of the back plate substrate 3000 to support the edge of the back plate substrate 3000.

[0245] The deposition mask 4000 can be moved into the process chamber 2100 by a transfer robot and transferred from the top of the mask chuck 2400 to the lifting finger 2350. The edge of the deposition mask 4000 can be placed on the end of the lifting finger 2350, and the finger drive 2360 can lower the lifting finger 2350 to load the deposition mask 4000 onto the mask chuck 2400. In this case, a groove (not shown) for the end of the lifting finger 2350 to be inserted can be provided on the upper edge of the mask chuck 2400. After the deposition mask 4000 is loaded onto the mask chuck 2400, the finger drive 2360 can rotate the lifting finger 2350 so that the lifting finger 2350 does not overlap with the mask chuck 2400.

[0246] The mask chuck 2400 can support the edge portion of the deposition mask 4000. For example, the mask chuck 2400 can be an electrostatic chuck that uses electrostatic force to hold the edge portion of the deposition mask 4000. In particular, the mask chuck 2400 can have a circular opening, so that the deposition mask 4000 is exposed towards the deposition source 2200. For example, the mask chuck 2400 can have a disk shape with a circular opening or a square plate shape.

[0247] The deposition apparatus 2000 may include a substrate chuck drive unit 2500 for moving a substrate chuck 2300 and a mask chuck drive unit 2600 for moving a mask chuck 2400. For example, the substrate chuck drive unit 2500 may move the substrate chuck 2300 along a first direction DR1, a second direction DR2, and a third direction DR3 to adjust the position of the backplane substrate 3000. In this case, the first direction DR1 may be a first horizontal direction, the second direction DR2 may be a second horizontal direction perpendicular to the first direction DR1, and the third direction DR3 may be a vertical direction. That is, the first direction DR1, the second direction DR2, and the third direction DR3 may be the X-axis direction, the Y-axis direction, and the Z-axis direction, respectively.

[0248] The substrate suction cup drive unit 2500 can rotate the substrate suction cup 2300 around the Z-axis to adjust the azimuth angle of the backplate substrate 3000. Furthermore, to adjust the tilt rate of the backplate substrate 3000, the substrate suction cup drive unit 2500 can rotate the substrate suction cup 2300 around the X-axis and also around the Y-axis. For example, the substrate suction cup drive unit 2500 may include a hexapod actuator 2510 that provides six degrees of freedom (X, Y, Z, θx, θy, and θz) motion.

[0249] The substrate chuck drive unit 2500 may include a substrate stage 2520 on which a hexapod actuator 2510 is mounted, and a second actuator 2530 connected to the substrate stage 2520. The substrate stage 2520 may be arranged horizontally within the process chamber 2100, and the second actuator 2530 may be arranged on the upper part of the process chamber 2100. The second actuator 2530 may be connected to the substrate stage 2520 by a plurality of drive shafts 2532 extending in a third direction DR3 (i.e., the vertical direction (Z direction)) through the upper cover (lid) of the process chamber 2100, and may move the substrate stage 2520 in the direction of the central axis (i.e., the vertical direction) of the hexapod actuator 2510. For example, the second actuator 2530 may be constructed using a brushless DC motor, a linear motor, a direct drive motor, etc., and the height of the substrate chuck 2300 may be adjusted for loading or unloading the backplane substrate 3000.

[0250] The hexa-legged actuator 2510 may include a first platform connected to the substrate chuck 2300, a second platform mounted on the substrate stage 2520, and six sub-actuators arranged between the first and second platforms. For example, the six sub-actuators may be constructed using brushless DC motors, voice coil linear motors, stepper motors, direct drive motors, servo motors, etc. In order to adjust the horizontal position, vertical position, azimuth angle, and tilt rate of the backplane substrate 3000, the first platform can be moved and rotated.

[0251] The mask chuck drive unit 2600 can move and rotate the mask chuck 2400 to adjust the horizontal position and azimuth angle of the deposition mask 4000. The mask chuck drive unit 2600 can move the mask chuck 2400 in a direction parallel to the deposition mask 4000, and can rotate the mask chuck 2400 about its central axis. For example, the mask chuck drive unit 2600 can move the mask chuck 2400 in a first direction DR1 (X-axis) and a second direction DR2 (Y-axis), and can rotate the mask chuck 2400 about a third direction DR3 (Z-axis).

[0252] As an example, the mask chuck drive unit 2600 may include a piezo actuator 2610 that provides three degrees of freedom (X, Y, and θz) motion. The piezo actuator 2610 may have an opening communicating with a circular opening of the mask chuck 2400. The mask chuck 2400 may be arranged at predetermined intervals upward from the piezo actuator 2610. For example, a plurality of support members 2612 may be arranged on the piezo actuator 2610, and the mask chuck 2400 may be arranged on the plurality of support members 2612.

[0253] The mask chuck drive unit 2600 may include a mask stage 2620 arranged horizontally within the process chamber 2100 and supporting the piezoelectric actuator 2610. For example, the mask stage 2620 may have an opening communicating with the opening of the piezoelectric actuator 2610 and may be supported by a plurality of pillars 2622 connected to the upper cover of the process chamber 2100.

[0254] After the backplane substrate 3000 and the deposition mask 4000 are respectively mounted onto the substrate chuck 2300 and the mask chuck 2400, the second actuator 2530 can lower the substrate chuck 2300 so that the backplane substrate 3000 is adjacent to the deposition mask 4000. The hexapod actuator 2510 can adjust the gap between the backplane substrate 3000 and the deposition mask 4000, and can adjust the tilt rate of the substrate chuck 2300 to adjust the parallelism between the substrate chuck 2300 and the mask chuck 2400. For example, although not shown, multiple gap sensors (not shown) for measuring the gap between the substrate chuck 2300 and the mask chuck 2400 can be mounted on the substrate chuck 2300, and the hexapod actuator 2510 can adjust the parallelism between the substrate chuck 2300 and the mask chuck 2400 based on the measurements of the gap sensors.

[0255] The deposition apparatus 2000 may include a camera 2700 for acquiring positional information of the backplane substrate 3000 and the deposition mask 4000, for alignment between the backplane substrate 3000 and the deposition mask 4000. For example, a substrate alignment key 3030 may be arranged on the edge of the backplane substrate 3000 (see reference). Figure 15 Furthermore, mask alignment keys 4600 can be arranged on the edge of the deposition mask 4000 (see reference). Figure 16 The deposition apparatus 2000 may include a camera 2700 for detecting the substrate alignment key 3030 and the mask alignment key 4600. The substrate chuck drive unit 2500 or the mask chuck drive unit 2600 may align the backplane substrate 3000 and the deposition mask 4000 with each other based on the position information of the substrate alignment key 3030 and the mask alignment key 4600 obtained by the camera 2700.

[0256] As described above, after adjusting the parallelism between the substrate chuck 2300 and the mask chuck 2400 and aligning the backplate substrate 3000 with the deposition mask 4000, the backplate substrate 3000 can be positioned on the deposition mask 4000. For example, the hexapod actuator 2510 can adjust the height of the substrate chuck 2300 so that the gap between the backplate substrate 3000 and the deposition mask 4000 becomes a predetermined gap (e.g., a gap of several micrometers). As another example, the hexapod actuator 2510 can adjust the height of the substrate chuck 2300 so that the backplate substrate 3000 contacts the deposition mask 4000.

[0257] After the backplane substrate 3000 is placed on the deposition mask 4000, the deposition source 2200 can provide a vapor-phase deposited material onto the backplane substrate 3000 through the deposition mask 4000, thereby forming a deposited material layer on the backplane substrate 3000. For example, the deposition source 2200 can evaporate the organic material used to form a light-emitting layer on the backplane substrate 3000, and the evaporated organic material can pass through the pixel opening 4312 of the deposition mask 4000 (see reference). Figure 17 Electrode patterns are deposited on the backplane substrate 3000.

[0258] Figure 15 It is used for explanation Figure 14 A schematic bottom view of the backplate substrate shown.

[0259] Reference Figure 15 The backplane substrate 3000 may include multiple display unit regions 3010 and scribe lane regions 3020 arranged between the display unit regions 3010. Figure 15 As shown, the display unit area 3010 can be arranged in a row and column configuration along the first direction DR1 and the second direction DR2, and after the display manufacturing process is completed, it is individually processed into a display panel 100 through a cutting process (see reference). Figure 3 For example, the first direction DR1 can be a first horizontal direction, and the second direction DR2 can be a second horizontal direction perpendicular to the first direction DR1. Furthermore, as an example, each of the display cell regions 3010 can have a quadrilateral shape as shown in the figure.

[0260] For example, such as Figure 9 As shown, each of the display unit regions 3010 may include a semiconductor backplane SBP, a light-emitting element backplane EBP disposed on the semiconductor backplane SBP, a reflective electrode RL disposed on the light-emitting element backplane EBP, and an eleventh insulating film INS11 disposed on the reflective electrode RL. Furthermore, each of the display unit regions 3010 may include multiple electrode patterns (e.g., multiple first electrodes AND) disposed on the insulating film INS11, and the first electrodes AND can be connected to the reflective electrode RL through multiple tenth vias VA10. In this case, the electrode patterns of the display unit regions 3010 can be disposed on the front surface of the backplane substrate 3000, and the substrate chuck 2300 can hold the rear surface of the backplane substrate 3000, such that the electrode pattern surface of the display unit regions 3010 faces downwards (i.e., towards the deposition source 2200).

[0261] Substrate alignment keys 3030 for alignment with the deposition mask 4000 may be arranged on the edge of the backplate substrate 3000. As shown in the figure, four substrate alignment keys 3030 may be arranged on the backplate substrate 3000, but the number of substrate alignment keys 3030 may vary, and the scope of the present invention is not limited by the number of substrate alignment keys 3030.

[0262] Figure 16 It is used for explanation Figure 14 The diagram shows a schematic plan view of the deposition mask. Figure 17 It is used for explanation Figure 16 A schematic plan view of the mask unit area shown. Figure 18 It is along Figure 17 A schematic cross-sectional view obtained from the I2-I2' line shown. Figure 19 It is used for explanation Figure 16 A schematic cross-sectional view of the mask alignment key is shown.

[0263] Reference Figures 16 to 19 The deposition mask 4000 may include mask unit regions 4310 corresponding to display unit regions 3010 of the backplane substrate 3000. Each mask unit region 4310 may have a plurality of pixel openings 4312 that expose the electrode pattern (e.g., first electrode AND) of the backplane substrate 3000 during the deposition process. For example, the deposition mask 4000 may include a mask substrate 4100, an intermediate inorganic film 4200 disposed on the mask substrate 4100, and a film 4300 disposed on the intermediate inorganic film 4200. In this case, the film 4300 may include a plurality of mask unit regions 4310, and each mask unit region 4310 may have a plurality of pixel openings 4312. Furthermore, the film 4300 may include a grid region 4320 disposed between the mask unit regions 4310, and the grid region 4320 may correspond to the scribe line region 3020 of the backplane substrate 3000.

[0264] The mask substrate 4100 may have cell openings 4110 corresponding to the mask cell regions 4310, and the intermediate inorganic film 4200 may have intermediate openings 4210 respectively disposed on the cell openings 4110. In this case, the mask cell regions 4310 of the film 4300 may be disposed on the intermediate openings 4210, and the pixel openings 4312 of the film 4300 may be connected to the cell openings 4110 through the intermediate openings 4210. That is, the mask cell regions 4310 of the film 4300 may be exposed to the deposition source 2200 through the cell openings 4110 of the mask substrate 4100 and the intermediate openings 4210 of the intermediate inorganic film 4200, and the pixel openings 4312 may be formed to penetrate the mask cell regions 4310.

[0265] like Figure 16 As shown, the mask unit regions 4310 can be arranged in a row and column configuration along the first direction DR1 and the second direction DR2. For example, the first direction DR1 can be a first horizontal direction, and the second direction DR2 can be a second horizontal direction perpendicular to the first horizontal direction. In particular, the mask unit regions 4310 can be arranged to correspond to the display unit regions 3010 of the backplane substrate 3000, respectively. As an example, each of the mask unit regions 4310 can have a quadrilateral shape as shown in the figure.

[0266] Intermediate inorganic films 4200 and 4300 can be disposed on the front surface of mask substrate 4100, and a second intermediate inorganic film 4400 and a rear surface inorganic film 4500 can be disposed on the rear surface of mask substrate 4100. For example, the second intermediate inorganic film 4400 can be disposed on the rear surface of mask substrate 4100, and the rear surface inorganic film 4500 can be disposed on the second intermediate inorganic film 4400. The second intermediate inorganic film 4400 and the rear surface inorganic film 4500 can each have a second intermediate opening 4410 and a rear surface opening 4510 respectively communicating with the cell opening 4110, and the rear surface inorganic film 4500 can function as an etching mask in the etching process used to form the cell opening 4110. In this case, the mask cell region 4310 can be exposed to the deposition source 2200 through the intermediate opening 4210, the cell opening 4110, the second intermediate opening 4410, and the rear surface opening 4510. Furthermore, in the deposition process for forming a light-emitting layer on the backplane substrate 3000, the vapor-phase deposition material provided from the deposition source 2200 can be deposited on the backplane substrate 3000 through the rear surface opening 4510, the second intermediate opening 4410, the unit opening 4110, the intermediate opening 4210 and the pixel opening 4312.

[0267] For example, the intermediate inorganic film 4200 can be formed using the same material as the second intermediate inorganic film 4400, and film 4300 can be formed using the same material as the back surface inorganic film 4500. In particular, film 4300 can be formed using a material having an etch selectivity ratio relative to the intermediate inorganic film 4200 and the mask substrate 4100. For example, the mask substrate 4100 can be formed using silicon (Si), and the intermediate inorganic film 4200 and the second intermediate inorganic film 4400 can be formed using silicon oxide (SiO2). x The film 4300 and the back surface inorganic film 4500 can be formed using silicon nitride (SiN). xIn this case, the intermediate inorganic film 4200 and the second intermediate inorganic film 4400 can be formed simultaneously by thermal oxidation, and the film 4300 and the back surface inorganic film 4500 can be formed simultaneously by chemical vapor deposition (CVD).

[0268] The pixel opening 4312 of the film 4300 can be formed by an anisotropic etching process (e.g., reactive ion etching). For example, after forming a photoresist pattern on the film 4300 that exposes the area where the pixel opening 4312 will be formed, the pixel opening 4312 that exposes the intermediate inorganic film 4200 is formed by performing a RIE process that uses the photoresist pattern as an etching mask. In this case, the pixel opening 4312 can be formed as a through-film 4300, and the intermediate inorganic film 4200 can be used as an etching barrier film in the RIE process.

[0269] The second intermediate opening 4410 and the rear surface opening 4510 can be formed by an anisotropic etching process (e.g., RIE process). For example, after forming a photoresist pattern on the rear surface inorganic film 4500 that exposes the portion where the rear surface opening 4510 will be formed, the second intermediate opening 4410 and the rear surface opening 4510 that expose the rear surface of the mask substrate 4100 are formed by performing a RIE process that uses the photoresist pattern as an etching mask.

[0270] The cell openings 4110 of the mask substrate 4100 can be formed by an anisotropic etching process that uses the back surface inorganic film 4500 and the second intermediate inorganic film 4400 as an etching mask, thereby exposing the intermediate inorganic film 4200. For example, the mask substrate 4100 can use a single-crystal silicon substrate, and the cell openings 4110 can be formed by a wet etching process using a first etchant such as a tetramethylammonium hydroxide (TMAH) solution. In this case, the single-crystal silicon substrate used as the mask substrate 4100... <100> The crystallization direction can be a third direction DR3 perpendicular to the first direction DR1 and the second direction DR2. Accordingly, through the wet etching process, the unit opening 4110 can be formed with a width that gradually decreases from the rear surface of the mask substrate 4100 toward the front surface of the mask substrate 4100. For example, the inner surface of the unit opening 4110 can have a slope of approximately 54.74° relative to the rear surface of the mask substrate 4100.

[0271] The intermediate opening 4210 of the intermediate inorganic film 4200 can be formed by a wet etching process after the unit opening 4110 of the mask substrate 4100 is formed. For example, the intermediate inorganic film 4200 utilizes silicon oxide (SiO2). x In the case of the formation of the intermediate inorganic film 4200, the intermediate opening 4210 can be formed by a wet etching process using a second etchant such as buffered oxide etchant (BOE) or diluted hydrofluoric acid (HF). Accordingly, the pixel opening 4312 of the film 4300 can be connected to the unit opening 4110 of the mask substrate 4100 through the intermediate opening 4210 of the intermediate inorganic film 4200.

[0272] As another example, the second intermediate inorganic film 4400 can be omitted. In this case, the rear surface inorganic film 4500 can be disposed on the rear surface of the mask substrate 4100, and the intermediate inorganic film 4200 can be formed by a thermal oxidation process or a CVD process.

[0273] The deposition mask 4000 may include mask alignment keys 4600 for alignment with the backplane substrate 3000. For example, the mask alignment keys 4600 may be arranged at the edge of the deposition mask 4000 to correspond to the substrate alignment keys 3030 of the backplane substrate 3000. Figure 16 As shown, the deposition mask 4000 includes four mask alignment keys 4600, but the number of mask alignment keys 4600 can be varied in various ways, and the scope of the present invention is not limited by the number of mask alignment keys 4600.

[0274] According to an embodiment of the present invention, such as Figure 19 As shown, each mask alignment key 4600 can be arranged on the intermediate inorganic membrane 4200, and the membrane 4300 can have key openings 4330 that expose the mask alignment keys 4600 respectively.

[0275] Figure 20 It is used for explanation Figure 19 A schematic enlarged cross-sectional view of the mask alignment key shown. Figure 21 It is used for explanation Figure 19 A schematic enlarged plan view of the mask alignment key shown. Figure 22 It is used for explanation Figure 21 A schematic enlarged plan view of another example of a mask alignment key.

[0276] Reference Figures 20 to 22The intermediate inorganic membrane 4200 may have a groove 4220 located below the bond opening 4330, and a mask alignment key 4600 may be disposed on the bottom surface of the groove 4220. The mask alignment key 4600 may have a thickness smaller than the depth of the groove 4220, thereby allowing the mask alignment key 4600 to be arranged at a predetermined interval from the membrane 4300. Further, the groove 4220 of the intermediate inorganic membrane 4200 may have a width wider than the bond opening 4330. Accordingly, as... Figure 20 As shown, the bond opening 4330 of the membrane 4300 and the groove 4220 of the intermediate inorganic membrane 4200 can have an under-cut structure.

[0277] For example, such as Figure 21 As shown, the mask alignment key 4600 may have a generally quadrilateral shape and may include an inner key pattern 4610 arranged along a first direction DR1 and extending parallel to each other in a second direction DR2, and an outer key pattern 4620 in a ring shape surrounding the inner key pattern 4610. That is, the inner key pattern 4610 may be arranged in a stripe pattern, and the bottom surface portion of the groove 4220 may be exposed between the inner key pattern 4610 and the outer key pattern 4620. The outer key pattern 4620 may have a generally quadrangular ring shape, and the two ends of the inner key pattern 4610 may be connected to the outer key pattern 4620.

[0278] As another example, such as Figure 22 As shown, the mask alignment key 4600 may include a first inner key pattern 4612 extending parallel to each other along a first direction DR1, a second inner key pattern 4614 extending parallel to each other along a second direction DR2 perpendicular to the first direction DR1 and intersecting with the first inner key pattern 4612, and an outer key pattern 4620 in a ring shape surrounding the first inner key pattern 4612 and the second inner key pattern 4614. That is, the first inner key pattern 4612 and the second inner key pattern 4614 may be arranged in a mesh pattern, and the bottom surface portion of the groove 4220 may be exposed between the first inner key pattern 4612, the second inner key pattern 4614, and the outer key pattern 4620. The outer key pattern 4620 may have a generally quadrangular ring shape, and the two ends of the first inner key pattern 4612 and the second inner key pattern 4614 may be connected to the outer key pattern 4620.

[0279] The deposition mask 4000 may include a second mask alignment key 4630 disposed on the film 4300 and having a ring shape surrounding the bond opening 4330. For example, the second mask alignment key 4630 may have a generally square ring shape, and the inner surface of the second mask alignment key 4630 may coincide with the outer surface of the outer bond pattern 4620 on the third direction DR3.

[0280] Mask alignment key 4600 and second mask alignment key 4630 can be formed using metal. Specifically, mask alignment key 4600 and second mask alignment key 4630 can be formed using metal with low light transmittance and high light reflectance. In particular, mask alignment key 4600 and second mask alignment key 4630 can be formed using metal with high light reflectance for infrared radiation. For example, mask alignment key 4600 and second mask alignment key 4630 can be formed using aluminum (Al), nickel (Ni), tungsten (W), molybdenum (Mo), gold (Au), silver (Ag), platinum (Pt), or copper (Cu).

[0281] Figure 23 It is used for explanation Figure 14 A schematic enlarged cross-sectional view of the camera shown.

[0282] Reference Figure 14 and Figure 23 A camera 2700 for detecting the substrate alignment keys 3030 and the mask alignment keys 4600 can be arranged on one side of the mask chuck 2400. Furthermore, the deposition apparatus 2000 may include an illumination unit 2800 that provides light capable of transmitting through the backplane substrate 3000 and the deposition mask 4000, and the camera 2700 can be arranged to detect the light transmitted through the backplane substrate 3000 and the deposition mask 4000. For example, light provided from the illumination unit 2800 can transmit through the portion of the backplane substrate 3000 where the substrate alignment keys 3030 are arranged and the portion of the deposition mask 4000 where the mask alignment keys 4600 are arranged.

[0283] For example, the illumination unit 2800 can be arranged within the edge portion of the lower surface of the substrate chuck 2300 and can provide infrared light capable of transmitting through the backplane substrate 3000 and the deposition mask 4000. As an example, the illumination unit 2800 may include an infrared lamp mounted on the substrate chuck 2300, and a through-hole 2410 may be provided at the edge portion of the mask chuck 2400 to allow light transmitted through the backplane substrate 3000 and the deposition mask 4000 to pass through. The infrared lamp can provide near-infrared (NIR) light or short-wave infrared (SWIR) light, and the light transmitted through the backplane substrate 3000 and the deposition mask 4000 can be guided to the camera 2700 via an optical unit 2810 arranged below the mask chuck 2400. For example, the infrared lamp can provide infrared light with a wavelength of approximately 1000 nm to approximately 1200 nm.

[0284] The optical unit 2810 may include mirrors 2812 and 2814 for guiding light transmitted through the backplane substrate 3000 and the deposition mask 4000 to the camera 2700. The camera 2700 can acquire image information of the substrate alignment key 3030 and the mask alignment key 4600 from the light guided by the optical unit 2810. The image information may include position information of the substrate alignment key 3030 and the mask alignment key 4600. The substrate chuck drive unit 2500 or the mask chuck drive unit 2600 may move and / or rotate the substrate chuck 2300 or the mask chuck 2400 based on the image information acquired by the camera 2700, so that the backplane substrate 3000 and the deposition mask 4000 are aligned with each other.

[0285] For example, the hexapod actuator 2510 can move the substrate chuck 2300 in the first direction DR1 and the second direction DR2 based on the image information, and rotate the substrate chuck 2300 with reference to the third direction DR3. As another example, the piezoelectric actuator 2610 can move the mask chuck 2400 in the first direction DR1 and the second direction DR2 based on the image information, and rotate the mask chuck 2400 with reference to the third direction DR3.

[0286] According to one embodiment of the present invention, the mask alignment key 4600 can be formed using a metal with low light transmittance and high light reflectance, thereby allowing the camera 2700 to acquire a clearer image of the mask alignment key 4600. As a result, the recognition rate of the mask alignment key 4600 can be improved, thereby enabling more precise alignment between the backplane substrate 3000 and the deposition mask 4000.

[0287] Figures 24 to 39 This is a schematic diagram illustrating a method for manufacturing a deposition mask according to another embodiment of the present invention.

[0288] Figure 24 It is a schematic cross-sectional view used to illustrate the formation of the intermediate inorganic membrane and the second intermediate inorganic membrane.

[0289] Reference Figure 24 An intermediate inorganic film 4200 can be formed on a mask substrate 4100. The mask substrate 4100 can be formed using monocrystalline silicon. For example, a monocrystalline silicon substrate having a thickness of about 700 μm to about 800 μm (e.g., a thickness of about 775 μm) can be used as the mask substrate 4100.

[0290] As an example, the intermediate inorganic film 4200 can utilize silicon oxide (SiO2). xThe intermediate inorganic film 4400 is formed on the front surface of the mask substrate 4100 and can be formed with a thickness of about 0.5 μm to about 3 μm by a thermal oxidation process. Furthermore, the second intermediate inorganic film 4400 can be formed on the rear surface of the mask substrate 4100. For example, the second intermediate inorganic film 4400 can be formed simultaneously with the intermediate inorganic film 4200 by a thermal oxidation process. Therefore, the second intermediate inorganic film 4400 can be formed using the same material as the intermediate inorganic film 4200 and can have the same thickness as the intermediate inorganic film 4200.

[0291] Figure 25 It is a schematic cross-sectional view used to illustrate the formation of the membrane and the inorganic membrane on the back surface.

[0292] Reference Figure 25 Film 4300 can be formed on the intermediate inorganic film 4200. For example, film 4300 may include silicon nitride (SiN). x Furthermore, it can be formed through a CVD process. Specifically, silicon source gases such as silane (SiH4), disilane (Si2H6), and dichlorosilane (DCS) (SiH2Cl2) and nitrogen source gases such as N2 and NH3 can be supplied onto the intermediate inorganic membrane 4200, and the membrane 4300 can be formed to a thickness of approximately 0.5 μm to approximately 3 μm through the reaction between the silicon source gas and the nitrogen source gas.

[0293] A back surface inorganic film 4500 can be formed on the second intermediate inorganic film 4400. The back surface inorganic film 4500 can be made of silicon nitride (SiN). x The inorganic film 4300 and the back surface inorganic film 4500 can be formed simultaneously using a CVD process. Therefore, the back surface inorganic film 4500 can be formed using the same material as film 4300 and can have the same thickness as film 4300.

[0294] Figure 26 It is a schematic cross-sectional view used to illustrate the formation of the first photoresist pattern. Figure 27 It is a schematic cross-sectional view used to illustrate the formation of pixel openings and key openings. Figure 28 It is used for explanation Figure 27 A schematic enlarged cross-sectional view of the key opening shown. Figure 29 It is used for explanation Figure 27 A schematic enlarged plan view of the key opening shown. Figure 30 It is used for explanation Figure 29 A schematic enlarged plan view of another example of a key opening shown.

[0295] Reference Figures 26 to 30Pixel openings 4312 and bond openings 4330 are formed by patterning the film 4300. For example, as... Figure 26 As shown, a first photoresist pattern 4010 for forming pixel openings 4312 and bond openings 4330 can be formed on the film 4300. The first photoresist pattern 4010 can have openings 4012, 4014 that expose the portions of the film 4300 where the pixel openings 4312 and bond openings 4330 will be formed.

[0296] Pixel openings 4312 and bond openings 4330 can be formed by an anisotropic etching process (e.g., RIE process) using a first photoresist pattern 4010 as an etching mask. For example, the RIE process can be performed using a first reactive gas containing fluorine, such as CF4, C2F4, C2F6, C3F6, C3F8, C4F6, C4F8, CH3F, CH2F2, C2HF5, CHF3, NF3, SF6, etc.; a second reactive gas containing oxygen, such as O2, NO, NO2, etc.; and sputtering gases such as He, Ne, Ar, Xe, etc., accordingly. Figure 27 As shown, pixel openings 4312 and bond openings 4330 can be formed in the through-film 4300. The first photoresist pattern 4010 can be removed by ashing and / or stripping processes after the pixel openings 4312 and bond openings 4330 are formed.

[0297] The pixel opening 4312 can be formed to correspond to the electrode pattern (e.g., the first electrode AND) on the backplane substrate 3000. The bond opening 4330 can be formed as a through-edge portion of the film 4300, such as... Figure 28 and Figure 29 As shown, each of the bond openings 4330 may include an inner opening pattern 4332 arranged along a first direction DR1 and extending parallel to each other in a second direction DR2, and an outer opening pattern 4338 in a ring shape surrounding the inner opening pattern 4332. That is, the inner opening pattern 4332 may be formed in a striped shape. The outer opening pattern 4338 may have a generally quadrangular ring shape, and the two ends of the inner opening pattern 4332 may be connected to the outer opening pattern 4338. In this case, the portion of the membrane 4300 located between the inner opening pattern 4332 and the outer opening pattern 4338 may be isolated. That is, an island pattern 4340 separated from the membrane 4300 may be formed between the inner opening pattern 4332 and the outer opening pattern 4338.

[0298] As another example, such as Figure 30As shown, the key opening 4330 may include a first inner opening pattern 4334 extending parallel to each other along a first direction DR1, a second inner opening pattern 4336 extending parallel to each other along a second direction DR2 perpendicular to the first direction DR1 and intersecting the first inner opening pattern 4334, and an outer opening pattern 4338 in a ring shape surrounding the first inner opening pattern 4334 and the second inner opening pattern 4336. That is, the first inner opening pattern 4334 and the second inner opening pattern 4336 may be formed in a grid shape. The outer opening pattern 4338 may have a generally quadrangular ring shape, and the two ends of the first inner opening pattern 4334 and the second inner opening pattern 4336 may be connected to the outer opening pattern 4338. In this case, the portion of the membrane 4300 located between the first inner opening pattern 4334 and the second inner opening pattern 4336 and the outer opening pattern 4338 may be isolated. That is, an island pattern 4342, which is separated from the membrane 4300, can be formed between the first inner opening pattern 4334, the second inner opening pattern 4336, and the outer opening pattern 4338.

[0299] According to an embodiment of the present invention, the RIE process can be performed by partially removing the intermediate inorganic film 4200. Therefore, grooves 4220 can be formed in the surface portion of the intermediate inorganic film 4200 by the RIE process. Specifically, the grooves 4220 can be formed below the bond openings 4330, and each of the grooves 4220 can have a depth less than about half the thickness of the intermediate inorganic film 4200. For example, the groove 4220 formed below the bond openings 4330 can have a depth of about 0.3 μm to about 1 μm, and can include an inner groove pattern 4222 formed below the inner opening pattern 4332 and an outer groove pattern 4228 formed below the outer opening pattern 4338. In this case, the island pattern 4340 can be supported by the portion 4230 of the intermediate inorganic film 4200 located between the inner groove pattern 4222 and the outer groove pattern 4228. Additionally, silicon oxide (SiO2) x The etching rate of fluorine-based etching gases can be relatively higher than that of silicon nitrides (SiN). x Relative to the etching rate of the fluorine-based etching gas, the width of the groove 4220 can be greater than the width of the bond opening 4330. Furthermore, grooves are also formed below the pixel opening 4312 using the RIE process.

[0300] As another example, although not shown, each of the grooves 4220 may include a first inner groove pattern formed below the first inner opening pattern 4334, a second inner groove pattern formed below the second inner opening pattern 4336, and an outer groove pattern formed below the outer opening pattern 4338. In this case, the island pattern 4342 may be supported by a portion of the intermediate inorganic film 4200 located between the first inner groove pattern, the second inner groove pattern, and the outer groove pattern.

[0301] Figure 31 It is a schematic cross-sectional view used to illustrate the formation of the mask alignment key, the second mask alignment key, and the dummy key pattern. Figure 32 It is used for explanation Figure 31 A schematic enlarged cross-sectional view of the mask alignment key, the second mask alignment key, and the dummy key pattern shown.

[0302] Reference Figure 31 and Figure 32 The mask alignment key 4600 can be formed on the portion of the intermediate inorganic film 4200 exposed by the key opening 4330 of the film 4300. That is, the mask alignment key 4600 can be formed within the groove 4220 of the intermediate inorganic film 4200. Specifically, the mask alignment key 4600 can have approximately 500 approximately 2000 Degree of thickness (e.g., approximately 1000) The thickness of the mask alignment key 4600 is formed on the bottom surface of the groove 4220. The mask alignment key 4600 may include an inner key pattern 4610 formed within the inner groove pattern 4222 and an outer key pattern 4620 formed within the outer groove pattern 4228. In this case, as... Figure 21 As shown, the inner key patterns 4610 can extend parallel to each other, and the outer key patterns 4620 can have a ring shape surrounding the inner key patterns 4610.

[0303] As another example, the mask alignment key 4600 may include a first inner key pattern 4612 formed within a first inner groove pattern, a second inner key pattern 4614 formed within a second inner groove pattern, and an outer key pattern 4620 formed within an outer groove pattern. In this case, as Figure 22 As shown, the first inner key pattern 4612 may extend parallel to each other along the first direction DR1, and the second inner key pattern 4614 may extend parallel to each other along the second direction DR2. The first inner key pattern 4612 and the second inner key pattern 4614 may intersect each other, and the outer key pattern 4620 may have a ring shape surrounding the first inner key pattern 4612 and the second inner key pattern 4614.

[0304] The mask alignment key 4600 can be formed using a metal. Specifically, the mask alignment key 4600 can be formed using a metal with low light transmittance and high light reflectance. In particular, the mask alignment key 4600 can be formed using a metal with high light reflectance for infrared radiation. For example, the mask alignment key 4600 can be formed using aluminum (Al), nickel (Ni), tungsten (W), molybdenum (Mo), gold (Au), silver (Ag), platinum (Pt), or copper (Cu).

[0305] Furthermore, a second mask alignment key 4630 with a ring shape surrounding the bond opening 4330 can be formed on the film 4300, and a dummy bond pattern 4640 can be formed on the island pattern 4340 located within the bond opening 4330. In this case, the mask alignment key 4600, the second mask alignment key 4630, and the dummy bond pattern 4640 can be formed simultaneously. Therefore, the mask alignment key 4600, the second mask alignment key 4630, and the dummy bond pattern 4640 can be formed using the same material and can have the same thickness.

[0306] Figure 33 It is used to explain the formation Figure 31 The diagram shows an electron beam evaporator with a mask alignment key, a second mask alignment key, and a dummy key pattern. Figure 34 It is used for explanation Figure 33 A schematic enlarged cross-sectional view of the shadow mask shown.

[0307] Reference Figure 33 and Figure 34 The mask alignment bond 4600, the second mask alignment bond 4630, and the dummy bond pattern 4640 can be formed by a physical vapor deposition process. For example, the mask alignment bond 4600, the second mask alignment bond 4630, and the dummy bond pattern 4640 can be formed simultaneously by an electron beam evaporation process or a thermal evaporation process using a shadow mask 5002.

[0308] As an example, the electron beam evaporator 5000 used to perform the electron beam evaporation process may include a vacuum chamber 5100, a crucible 5200 disposed in the vacuum chamber 5100 and containing an evaporation source such as a metallic material, a substrate support 5300 disposed on the upper part of the crucible 5200 and used to support a mask substrate 4100, and a mask stage 5400 used to support a shadow mask 5002, etc.

[0309] An electron gun 5210 for providing an electron beam can be arranged on one side of the crucible 5200. A permanent magnet 5220 or electromagnet can be arranged between the crucible 5200 and the electron gun 5210 to guide the electron beam irradiated by the electron gun 5210 to the evaporation source using a magnetic field. The evaporation source contained in the crucible 5200 can be heated and melted by the electron beam, and the material evaporated from the evaporation source can move upward and be deposited on the mask substrate 4100.

[0310] The substrate support 5300 can hold the mask substrate 4100 with the film 4300 facing downwards, and a shadow mask 5002 with an opening 5004 exposing the areas where the mask alignment key 4600, the second mask alignment key 4630, and the dummy key pattern 4640 will be formed can be arranged below the substrate support 5300. In this case, as Figure 34 As shown, metal particles evaporated from the evaporation source can be deposited on intermediate inorganic films 4200 and 4300 through openings 5004 of the shadow mask 5002. Accordingly, mask alignment keys 4600, second mask alignment keys 4630, and dummy key patterns 4640 can be formed on intermediate inorganic films 4200, 4300, and island patterns 4340.

[0311] The configuration of the electron beam evaporator 5000 used to form the mask alignment key 4600, the second mask alignment key 4630, and the dummy key pattern 4640 has been described as an example. Since the configuration of the electron beam evaporator 5000 can be varied, the scope of the present invention is not limited thereto. Furthermore, as described above, the mask alignment key 4600 and the second mask alignment key 4630 can be formed using the electron beam evaporator 5000. However, as another example, the mask alignment key 4600 and the second mask alignment key 4630 can also be formed using a thermal evaporator (not shown) utilizing the shadow mask 5002.

[0312] Figure 35 It is a schematic cross-sectional view used to illustrate the formation of the second photoresist pattern. Figure 36 It is a schematic cross-sectional view used to illustrate the formation of the rear surface opening and the second intermediate opening. Figure 37 It is a schematic cross-sectional view used to illustrate the formation of the unit opening.

[0313] Reference Figures 35 to 37 The cell opening 4110 can be formed by patterning the mask substrate 4100. For example, a second intermediate opening 4410 and a rear surface opening 4510 can be formed to expose the rear surface portion of the mask substrate 4100 where the cell opening 4110 is to be formed. Specifically, as Figure 35As shown, a second photoresist pattern 4020 with an opening 4022 that exposes the portion where the rear surface opening 4510 will be formed can be formed on the inorganic film 4500 on the rear surface.

[0314] After forming the second photoresist pattern 4020, as Figure 36 As shown, an anisotropic etching process (e.g., RIE process) can be performed using the second photoresist pattern 4020 as an etching mask. The anisotropic etching process can be performed until the rear surface portion of the mask substrate 4100 (i.e., the portion where the cell opening 4110 will be formed) is exposed, thereby forming a second intermediate opening 4410 and a rear surface opening 4510 penetrating the second intermediate inorganic film 4400 and the rear surface inorganic film 4500. After forming the second intermediate opening 4410 and the rear surface opening 4510, the second photoresist pattern 4020 can be removed by an ashing and / or stripping process.

[0315] The unit opening 4110 can be formed using a wet etching process. For example, as... Figure 37 As shown, the mask substrate 4100 can be partially removed by a wet etching process using the second intermediate inorganic film 4400 and the back surface inorganic film 4500 as an etching mask, thereby exposing the intermediate inorganic film 4200 and forming a cell opening 4110 penetrating the mask substrate 4100. For example, the wet etching process for forming the cell opening 4110 can be performed using a first etchant such as a TMAH solution. In this case, the single-crystal silicon substrate used as the mask substrate 4100... <100> The crystallization direction can be a third direction DR3, thereby the cell opening 4110 can be formed with a width that gradually decreases from the rear surface of the mask substrate 4100 toward the front surface of the mask substrate 4100. For example, the inner surface of the cell opening 4110 can be formed with a slope of about 54.74° relative to the rear surface of the mask substrate 4100.

[0316] In the wet etching process used to form the unit opening 4110, the intermediate inorganic film 4200 can be used as an etching barrier film. Specifically, if the intermediate inorganic film 4200 is omitted, the first etchant can be provided to the front surface of the mask substrate 4100 through the pixel opening 4312. Due to the reaction between the first etchant and the mask substrate 4100, hydrogen (H2) bubbles may be generated within the pixel opening 4312. In this case, the mask unit region 4310 of the film 4300 may be damaged by the hydrogen bubbles, and the intermediate inorganic film 4200 can be used to prevent the first etchant from being provided to the front surface of the mask substrate 4100 through the pixel opening 4312.

[0317] Figure 38It is a schematic cross-sectional view used to illustrate the formation of the central opening. Figure 39 It is a schematic enlarged cross-sectional view used to illustrate the removal of island patterns and dummy key patterns.

[0318] Reference Figure 38 and Figure 39 An intermediate opening 4210 connecting the pixel opening 4312 and the unit opening 4110 can be formed by patterning the intermediate inorganic film 4200. The intermediate opening 4210 can be formed such that the mask unit region 4310 of the film 4300 is exposed through the unit opening 4110. The intermediate opening 4210 can be formed by a wet etching process. For example, the intermediate inorganic film 4200 can be formed using silicon oxide (SiO2). x In the case of formation, the central opening 4210 can be formed by a wet etching process using a second etchant such as BOE or diluted hydrofluoric acid.

[0319] Furthermore, during the formation of the intermediate opening 4210, such as Figure 39 As shown, the island pattern 4340 located within the bond opening 4330 and the dummy bond pattern 4640 formed on the island pattern 4340 can be removed. Specifically, the second etching solution can be provided into the groove 4220 of the intermediate inorganic film 4200 through the bond opening 4330, and the inner surface portion of the groove 4220 can be removed by the second etching solution. In particular, the portion 4230 of the intermediate inorganic film 4200 supporting the island pattern 4340 (see reference) can be removed by the second etching solution. Figure 28 and Figure 32 Accordingly, the island pattern 4340 and the dummy bond pattern 4640 can be removed from the intermediate inorganic film 4200 and film 4300. Furthermore, the width of the groove 4220 can be increased by a second etching solution, thereby allowing the bond opening 4330 of film 4300 and the groove 4220 of intermediate inorganic film 4200 to have an under-cut structure.

[0320] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, those skilled in the art will understand that the invention can be implemented in other specific forms without altering its technical concept or essential features. Therefore, the embodiments described above should be understood as exemplary in all respects, and not limiting.

Claims

1. A deposition mask, comprising: Mask substrate, having unit openings; An intermediate inorganic film is disposed on the mask substrate and has an intermediate opening that communicates with the unit opening. A mask alignment key is arranged on the intermediate inorganic membrane; as well as A membrane is disposed on the intermediate inorganic membrane and has a plurality of pixel openings communicating with the intermediate opening and a key opening that exposes the mask alignment key.

2. The deposition mask as described in claim 1, wherein, The intermediate inorganic membrane has a groove located below the bond opening. The mask alignment key is arranged on the bottom surface of the groove.

3. The deposition mask as described in claim 2, wherein, The mask alignment key has a thickness smaller than the depth of the groove.

4. The deposition mask as described in claim 2, wherein, The groove has a width that is wider than the key opening.

5. The deposition mask as described in claim 1, wherein, The mask alignment key includes: Multiple inner key patterns extend parallel to each other; and The outer key pattern is in the shape of a ring, surrounding the inner key pattern.

6. The deposition mask as claimed in claim 1, wherein, The mask alignment key includes: Multiple first inner key patterns extend parallel to each other along a first direction; A plurality of second inner key patterns extend parallel to each other along a second direction perpendicular to the first direction and intersect with the first inner key pattern; and The outer key pattern in a ring shape surrounds the first inner key pattern and the second inner key pattern.

7. The deposition mask as claimed in claim 1, further comprising: The second mask is aligned with the key, arranged on the membrane, and has a ring shape surrounding the key opening.

8. The deposition mask as claimed in claim 1, wherein, The mask alignment key comprises metal.

9. The deposition mask as described in claim 8, wherein, The mask alignment key includes aluminum, nickel, tungsten, molybdenum, gold, silver, platinum, or copper.

10. A method for manufacturing a deposition mask, comprising the following steps: An intermediate inorganic film is formed on a mask substrate; A membrane is formed on the intermediate inorganic membrane; Pixel openings and bond openings that expose the intermediate inorganic film are formed by partially removing the film; A mask alignment key is formed at the portion of the intermediate inorganic membrane exposed through the key opening; as well as The cell opening and intermediate opening that expose the pixel opening are formed by partially removing the mask substrate and the intermediate inorganic film.

11. The method for manufacturing a deposition mask as described in claim 10, wherein, The mask alignment key is formed to include: Multiple inner key patterns extend parallel to each other; and The outer key pattern is in the shape of a ring, surrounding the inner key pattern.

12. The method for manufacturing a deposition mask as described in claim 10, further comprising the following steps: A groove is formed below the bond opening by partially removing the intermediate inorganic film. in, The mask alignment key is formed on the bottom surface of the groove.

13. The method for manufacturing a deposition mask as described in claim 10, wherein, The key opening is formed by an anisotropic etching process. The anisotropic etching process is performed to form grooves by partially removing surface portions of the intermediate inorganic film. The mask alignment key is formed on the bottom surface of the groove.

14. The method for manufacturing a deposition mask as described in claim 13, wherein, The mask alignment key is formed to have a thickness that is smaller than the depth of the groove.

15. The method for manufacturing a deposition mask as described in claim 13, wherein, The key opening includes: Multiple inner opening patterns extend parallel to each other; and The outer opening pattern, in the shape of a ring, surrounds the inner opening pattern. The groove includes: An inner groove pattern is formed below the inner opening pattern; and A ring-shaped outer groove pattern is formed below the outer opening pattern.

16. The method for manufacturing a deposition mask as described in claim 15, wherein, During the formation of the key opening, an island pattern is formed between the inner opening pattern and the outer opening pattern. During the formation of the mask alignment key, a dummy key pattern is formed on the island pattern.

17. The method for manufacturing a deposition mask as described in claim 16, further comprising the following steps: Remove the island pattern and the dummy key pattern.

18. The method for manufacturing a deposition mask as described in claim 10, further comprising the following steps: A second mask alignment key is formed on the membrane in the shape of a ring surrounding the key opening.

19. The method for manufacturing a deposition mask as described in claim 10, wherein, The mask alignment key is formed by an electron beam evaporation process or a thermal evaporation process using a shadow mask that exposes the portion of the intermediate inorganic film to which the mask alignment key will be formed.

20. An electronic device, comprising an electronic device with a display panel, The display panel includes a backplane substrate and a plurality of light-emitting layers formed on the backplane substrate using a deposition mask. The deposition mask includes: Mask substrate, having unit openings; An intermediate inorganic film is disposed on the mask substrate and has an intermediate opening that communicates with the unit opening. A mask alignment key is arranged on the intermediate inorganic membrane; as well as A membrane, disposed on the intermediate inorganic membrane, has a plurality of pixel openings communicating with the intermediate opening and a key opening for exposing the mask alignment keys. The plurality of light-emitting layers are formed by a deposition process in which vapor-phase deposited material is provided on the backplane substrate through the unit opening, the intermediate opening and the pixel opening.

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