A ternary logic circuit combination equivalence verification method based on semi-tensor product

Abstract

The application discloses a kind of based on semi-tensor product three-value logic circuit combination equivalence verification method, comprising the following steps: obtaining two circuits to be verified, respectively converted into structural matrix representation and normalized, then construct the three-value miter of output logic, judge whether its structural matrix is constant corresponding three-value zero output;Switching network in two circuits is converted into Boolean expression form, and value detection projection matrix is constructed to three-value input variable, to generate the Boolean indication signal satisfying constraint;Construct Boolean miter, and judge whether the switching network of two circuits is equivalent;When the output logic of two circuits is equivalent and the switching network is equivalent, determine that two circuit combinations are equivalent.The method avoids the exhaustive enumeration of three-value input space 3 n , converts equivalence determination problem into structural matrix identity determination problem, significantly reduces verification complexity and improves scalability, improves verification efficiency and universality and guarantees the soundness of verification result.

Description

Technical Field

[0001] This invention relates to the field of logic synthesis in electronic design automation, and specifically to a method for verifying the combinatorial equivalence of ternary logic circuits based on half-tensor products. Background Technology

[0002] Multi-valued logic (MVL) extends the traditional Boolean logic system by introducing more than two discrete logic values. As the most representative form of MVL, ternary logic offers a good trade-off between information representation capability and circuit implementation complexity, and has therefore regained widespread attention driven by the development of new device technologies and circuit structures. Researchers have proposed various optimization methods for the technology-independent synthesis process of ternary logic circuits, such as structural rewriting, logic balancing, and the sum-of-products (SOP) minimization technique based on pull-up / pull-down networks. These synthesis optimization methods typically generate functionally equivalent circuit implementations with significantly different structures while maintaining functional consistency.

[0003] Existing verification methods for ternary logic circuits typically rely on the input space The exhaustive enumeration has a computational complexity of O(n log n). (in (This refers to the number of circuit inputs). As the input size increases, the computational cost of this method grows exponentially, making it difficult to scale to larger-scale circuits. Furthermore, it cannot effectively utilize the structural information introduced during the synthesis transformation process.

[0004] Furthermore, in static ternary standard operating procedure (SOP) synthesis, each ternary variable is often expanded into a Boolean value-detection predicate, for example... , , They represent , and Then, Boolean SOP simplification and logical rewriting are performed on these predicates. However, during the equivalence check, if these predicates are treated as independent Boolean inputs, unreachable Boolean assignment combinations will be introduced, for example... or These unreachable states do not exist in actual ternary semantics, but they may lead to spurious counterexamples, thereby undermining the integrity of the verification results.

[0005] Therefore, it is necessary to develop a new verification method that can avoid The computational bottleneck caused by enumeration can be overcome by correctly applying ternary semantic constraints in the value detection SOP network and completing the equivalence verification of ternary logic circuits under a unified computational framework. Summary of the Invention

[0006] To address the problems existing in the prior art, this invention proposes a method for verifying the combinatorial equivalence of ternary logic circuits based on semi-tensor products. This method converts the ternary logic circuit into a structure matrix representation through semi-tensor products and performs normalization processing. Then, it combines the ternary miter with the Boolean miter of the switching network for algebraic evaluation, avoiding the need to modify the ternary input space. The exhaustive enumeration transforms the equivalence determination problem into the structural matrix identity determination problem, significantly reducing the verification complexity and improving scalability. At the same time, the semantically preserved value detection projection mechanism excludes unreachable Boolean assignments to ensure the integrity of the verification results. Furthermore, the combinational equivalence verification of the three-valued output logic and the value detection SOP network is realized under a unified semi-tensor product calculation framework, thereby improving verification efficiency and universality and ensuring the integrity of the verification results.

[0007] The technical solution adopted by this invention to solve the above-mentioned technical problems is as follows: a method for verifying the combinational equivalence of ternary logic circuits based on semi-tensor products, comprising the following steps: S1. Obtain the ternary logic circuit before optimization and the ternary logic circuit after optimization as two circuits to be verified. S2. Convert the two circuits into structural matrix representations based on semi-tensor products (STP), and normalize the matrix chain representations of their structural matrices under a fixed main input order. S3. Construct the three-valued miter of the output logic of two circuits based on the inequality comparator in the three-valued logic domain. Determine whether the structure matrix always corresponds to the three-valued zero output by the matrix half-tensor product operation to determine whether the output logic of the two circuits is equivalent. S4. Convert the switching networks in the two circuits into Boolean expressions based on value detection predicates, and construct value detection projection matrices for the three-valued input variables of the two circuits to generate Boolean indication signals that satisfy mutual exclusion and completeness constraints; construct a Boolean miter based on the Boolean indication signals, and determine whether the switching networks of the two circuits are equivalent through matrix semi-tensor product operations. S5. When the output logic of two circuits is equivalent and the switching networks are equivalent, the combination of the two circuits is determined to be equivalent.

[0008] Preferably, in step S1, the two circuits are described using the BLIF (Berkeley Logic InterchangeFormat) format, and their node type is LUT (Look-Up Table) nodes. Using the BLIF format to describe the circuits and the node type as LUT nodes allows the method of this invention to directly read and process standardized digital logic network description files, facilitating integration with existing logic synthesis toolchains and improving the practicality and compatibility of the method.

[0009] Preferably, in step S2, the three-valued input variables in the two circuits are encoded into three-dimensional standard basis vectors, and a structure matrix expression based on the semi-tensor product of the two circuits is constructed. This structure matrix expression is represented by a three-valued logic function. ,in Let be the input vectors of the two circuits. This represents the structure matrix corresponding to the input vector. By constructing the above structure matrix expression, an algebraic unified representation is provided for ternary logic circuits, enabling subsequent matrix semi-tensor product operations to be performed strictly under ternary semantics, thus avoiding information loss or semantic deviation caused by improper encoding methods.

[0010] Preferably, in step S2, the normalization process includes: adjusting the order of input variables using a commutation matrix, eliminating duplicate input variables using a power-reduction matrix, and unifying the matrix chain expression of the structure matrix to a fixed main input order using the commutative property of matrices and input variables. Through this normalization process, the influence of inconsistent input variable order in different circuit implementations on the structure matrix can be eliminated, ensuring that functionally equivalent networks obtain a consistent structure matrix representation under the same input order, thereby making the equivalence determination result unaffected by differences in circuit structure.

[0011] Preferably, in step S3, the inequality comparator is defined in the ternary logic domain as follows: when the two inputs are equal, the output is 0; when the two inputs are unequal, the output is 1. This definition directly corresponds to the equivalence judgment requirement in the ternary logic domain, ensuring that a Miter output of 0 uniquely represents that the outputs of the two circuits are equal under all input conditions, providing a clear algebraic basis for subsequent equivalence determination by ensuring the structure matrix is ​​always zero.

[0012] Preferably, in step S3, a replication matrix is ​​constructed. (Duplication Matrix) will Transform into about Linear mapping: This transforms the three-valued miter into information about... Linear form: ,in, Let be the input vectors of the two circuits. For tensor product, The output vector of the three-valued miter. Let be the structure matrix of the ternary miter; when When all columns correspond to three-valued zero outputs, the output logic of the two circuits is determined to be equivalent. This is achieved by constructing a replication matrix. Will Transform into about A linear mapping, thus expressing the output of the ternary miter as... The linear form of the expression simplifies Miter's equivalence check to a simple check. The process of checking whether all columns correspond to three-valued zero outputs avoids recursive expansion of input combinations and achieves direct algebraic evaluation of the miter output, thus improving verification efficiency.

[0013] Preferably, in step S4, any three-valued input variable Construct three value detection projection matrices, and generate three corresponding Boolean indication signals respectively. This ensures that each value of the three-valued variable is uniquely mapped to a Boolean predicate, providing a semantically preserved encoding basis for subsequent processing of switch networks within the semi-tensor product framework.

[0014] Preferably, the three Boolean indicator signals satisfy the following condition: for any three-valued input assignment, exactly one and at least one of the generated three Boolean indicator signals are true. This ensures that the value detection predicates satisfy mutual exclusion and completeness constraints, eliminates unreachable Boolean assignment combinations, avoids false counterexamples in the equivalence verification of switch networks, and ensures the integrity of the verification results.

[0015] Compared with existing technologies, the present invention has the following advantages: The present invention converts the ternary logic circuit into a structure matrix representation and normalizes it through a semi-tensor product, and then performs algebraic evaluation by combining the ternary miter and the Boolean miter of the switching network, thereby realizing the reuse and cached computation of the intermediate matrix, improving the efficiency of equivalence verification, and avoiding the need for processing the ternary input space. The exhaustive enumeration transforms the equivalence determination problem into a structural matrix identity determination problem, significantly reducing verification complexity and improving scalability. Simultaneously, addressing the unreachable Boolean assignment problem introduced by the predicate extension of value detection in the switch network, a semantically preserved value detection projection mechanism eliminates unreachable Boolean assignments. Specifically, by constructing a value detection projection matrix that satisfies mutual exclusion and completeness constraints to generate Boolean indicator signals, false counterexamples are eliminated, ensuring the soundness of the verification results. Furthermore, the entire method achieves combinatorial equivalence verification of the three-valued output logic and the value detection SOP network within a unified semi-tensor product calculation framework, thereby improving verification efficiency and generality while ensuring the soundness of the verification results. Attached Figure Description

[0016] Figure 1 This is a flowchart of the verification method in the embodiment; Figure 2 This is a flowchart of step S4 in the embodiment; Figure 3 This is a schematic diagram illustrating the construction of a value detection projection matrix for a three-valued input variable in the embodiment. Figure 4 This is a schematic diagram of the Boolean miter verification process for the switch network in the embodiment. Detailed Implementation

[0017] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be noted that the following embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit the scope of protection of the present invention.

[0018] 1. Example: A method for verifying the combinational equivalence of ternary logic circuits based on half-tensor products, comprising the following 5 steps S1 to S5, the flowchart of which is shown below. Figure 1 Steps S1 to S3 determine whether the output logic of the two circuits is equivalent; step S4 determines whether the switching networks of the two circuits are equivalent. The flowchart for this step is shown below. Figure 2 The method includes the following steps: S1. Obtain the ternary logic circuit before optimization. and the optimized ternary logic circuit The BLIF file is used to parse the circuit, obtain the main input set, main output set, and topology of LUT nodes, and construct a directed acyclic graph (DAG) representation of the circuit based on this.

[0019] Specifically, the input port declarations, output port declarations, and logical definitions of each LUT node are first read from the circuit files before and after optimization. For each LUT node, its input nodes, output nodes, and corresponding three-valued truth tables are obtained. For the main input node, it is treated as the source node in the directed acyclic graph (DAG). For the main output node, its corresponding output connection relationships are determined. After parsing, directed edges are established based on the connection relationships between nodes, so that each directed edge represents the signal transmission relationship between the output of one node and the input of another node. Since there are no feedback loops in combinational logic circuits, the constructed circuit diagram is a DAG. Through this DAG representation, the predecessor and successor relationships between each LUT node can be clearly defined, thus providing a foundation for the subsequent construction of the semi-tensor product structure matrix according to the topological order.

[0020] When analyzing two circuits to be verified, a consistency check is performed on the main input sets and main output sets of the two circuits. If the number of main inputs or main outputs of the two circuits are different, it can be directly determined that they do not meet the basic conditions for combinatorial equivalence verification; if the number of main inputs and main outputs are the same, a correspondence is established according to a fixed main input order. In one implementation, the correspondence is established according to the main input names; in another implementation, the correspondence can also be established according to the input declaration order in the BLIF file. Through the above processing, it is ensured that the circuit before optimization and the circuit after optimization use the same order of three-valued input variables in the subsequent verification process, thereby ensuring the consistency of the structure matrix representation.

[0021] S2. In the process of converting the two circuits into structural matrix representations based on half-tensor products, the three-valued input variables in the two circuits are encoded into three-dimensional standard basis vectors:

[0022] in The third unit vector in three dimensions The nth standard basis vector (i.e., the nth standard basis vector in a three-dimensional column vector) One position is 1, and the rest are 0.

[0023] For each Given a 3-valued LUT node, construct the corresponding structure matrix based on its truth table:

[0024] in Enter a number for this node.

[0025] Subsequently, with the main input order fixed, the node structure matrix is ​​recursively expanded using semi-tensor product operations to obtain the structure matrix expression of the entire circuit:

[0026] in, and These represent the circuits before optimization. Compared with the optimized circuit The output vector, This represents the input vectors of the two circuits. and These represent the structure matrices corresponding to the input vectors of the two circuits, respectively.

[0027] Since the semi-tensor product operation does not satisfy the commutative law, different structural implementations may lead to different variable orders. Therefore, this invention normalizes the matrix chain expression of the structure matrix under a fixed main input order. The normalization process includes: adjusting the order of input variables using a commutative matrix, eliminating duplicate input variables using a power-reduction matrix, and unifying the matrix chain expression of the structure matrix to a fixed main input order using the commutative property of the matrix and input variables. This ensures that functionally equivalent networks obtain a consistent structure matrix representation under the same input order.

[0028] In practice, the DAG is first topologically sorted so that each LUT node is processed only after all its input nodes have completed their structure matrix representations. For the main input node, the corresponding three-dimensional standard basis vector is used directly. For the LUT node, a node structure matrix is ​​generated based on the number of its inputs and its three-value truth table. If a LUT node has k inputs, its truth table contains the output results corresponding to the three-value input combinations. The number of columns in the node structure matrix corresponds to the number of all possible input combinations for that LUT node, and each column represents the output standard basis vector under one input combination.

[0029] During the recursive expansion process, if the input of a node comes from other intermediate nodes, the structure matrix representation of the predecessor node is first substituted into the input position of the current node, and then the structure matrix representation of the current node relative to the main input vector is formed using the semi-tensor product operation. For multiple fan-out shared intermediate nodes, their structure matrix representations can be reused to avoid repeated expansion calculations in different successor nodes.

[0030] When evaluating under the same main input order, if the same main input variable appears repeatedly in the matrix chain expression, the repeated variables are merged using a power-reducing matrix; if the variable order is different, the variable order is adjusted using a swap matrix so that the final expression is arranged according to the fixed main input order.

[0031] Through the above method, although the circuit before and after optimization may have different LUT partitioning methods, different intermediate node names, and different topologies, both are ultimately converted into a structure matrix representation with respect to the same main input vector. This normalization process ensures that subsequent equivalence judgments do not depend on the specific circuit structure, but only on the input-output mapping relationship between the two circuits in the three-valued input space.

[0032] S3. Construct an inequality comparator based on a ternary logic domain. Its function is: when The output is 0 if the condition is met, and 1 otherwise. This relates to the circuit before optimization. Compared with the optimized circuit The output of the circuit is connected to the inequality comparator, thus constructing a ternary miter for the output logic of the two circuits.

[0033] Based on the algebraic expansion of the semi-tensor product, the output vector of the ternary miter is obtained as follows:

[0034] in, For tensor product, This is the output vector of the ternary miter.

[0035] By constructing a replication matrix ,Will Transform into about Linear mapping:

[0036] This transforms the ternary miter into a value about Linear form:

[0037] in, This is the output vector of the three-valued miter. The structure matrix of the ternary miter; when All columns correspond to three-valued zero output (i.e. When the output logic of the two circuits is equal, it is determined that the output logic of the two circuits is equivalent.

[0038] In the specific judgment process, a three-valued inequality comparator is constructed based on the output structure matrix of the circuit before and after optimization. For a single-output circuit, only one inequality comparator needs to be constructed; for a multi-output circuit, an inequality comparator is constructed for each pair of corresponding outputs, and the outputs of each inequality comparator are combined. When any pair of corresponding outputs is unequal under a certain three-valued input condition, the combined miter output does not correspond to a three-valued zero; only when all corresponding outputs are equal under all three-valued input conditions does the combined miter output always correspond to a three-valued zero.

[0039] Therefore, each column of the ternary miter corresponds to a ternary input state under a fixed main input order. If all columns in the ternary miter structure matrix are standard basis vectors corresponding to ternary zeros, it means that no input state can cause a difference in the outputs of the two circuits before and after optimization; if at least one column is not a standard basis vector corresponding to ternary zeros, then the input state corresponding to that column is a counterexample that causes the outputs of the two circuits to be inconsistent. Therefore, this step can not only provide the result of determining whether they are equivalent or not, but also provide a counterexample input basis for subsequent error localization when they are not equivalent.

[0040] Unlike directly enumerating and evaluating all three-valued input combinations, this step performs the constant-zero determination of the miter output at the structure matrix level. Since the structure matrix representation of intermediate nodes can be reused during topology expansion, and different circuits are ultimately unified under the same input order for comparison, this method can reduce redundant calculations and improve the efficiency of equivalence verification.

[0041] S4. In the static three-valued SOP synthesis process, the three-valued variables... It is usually expanded into multiple value-detection predicates, for example:

[0042] Representing three-valued variables respectively Values If these predicates are treated as independent Boolean variables during equivalence verification, unreachable Boolean assignment combinations may be introduced, for example:

[0043] in: :when It is a Boolean logic 1 if it is true, otherwise it is 0; :when It is a Boolean logic 1 if it is true, otherwise it is 0; :when It is a Boolean logic 1 if it is true, otherwise it is 0; The above combination does not exist under true ternary semantics, which will lead to false counterexamples during the verification process, thereby undermining the integrity of the verification results.

[0044] To avoid the aforementioned problems, this invention constructs a semantically preserved value detection projection mechanism using a semi-tensor product framework. This invention converts the switching networks in two circuits into Boolean expressions based on value detection predicates, and constructs value detection projection matrices for the three-valued input variables of the two circuits to generate Boolean indication signals that satisfy mutual exclusion and completeness constraints. Based on the Boolean indication signals, a Boolean miter is constructed, and the equivalence of the switching networks of the two circuits is determined through matrix semi-tensor product operations. Specifically: Figure 3 This is a schematic diagram illustrating the construction of a value detection projection matrix for a three-valued input variable in the embodiment. For example... Figure 3 As shown, this invention provides each three-valued input variable Construct a three-value detection projection matrix:

[0045] Used to generate the corresponding three Boolean indicator signals .

[0046] In one exemplary embodiment, the projection matrix is ​​specifically in the form of:

[0047] For three-valued input variables The corresponding value detection signal is represented by the half-tensor product as follows:

[0048]

[0049]

[0050] The above projection matrix guarantees that the three-value detection signals satisfy the following conditions under any three-value input assignment: (1) Mutual exclusion constraint: That is, exactly one predicate is true; (2) Completeness constraint: There exists at least one value for the detection signal to be true.

[0051] Therefore, all Boolean assignments correspond to real three-valued input states, thus eliminating unreachable Boolean states. Furthermore, when constructing the Boolean representation of the switch network, each value detection predicate is not treated as an independent Boolean variable, but rather generated from the corresponding three-valued input variable through a value detection projection matrix. For the same three-valued variable, its three value detection signals originate from the same input vector; therefore, the value relationships between the three are subject to three-valued semantic constraints, thus satisfying mutual exclusion and completeness constraints. In this way, all Boolean indicator signals involved in the calculation correspond to real reachable three-valued input states, preventing situations where multiple value detection signals are simultaneously true or all are false.

[0052] When constructing the Boolean miter, a Boolean XOR comparison structure is built based on the outputs of the switch networks before and after optimization. When the two outputs are the same, the XOR output corresponds to Boolean 0; when the two outputs are different, the XOR output corresponds to Boolean 1. If the Boolean miter corresponds to Boolean 0 in all reachable Boolean states obtained by projecting from the three-valued input, the two switch networks are considered equivalent; if there is an output corresponding to Boolean 1, it means that the two switch networks are not equivalent in a certain real three-valued input state. Since unreachable Boolean states have been excluded by the value detection projection mechanism, this determination will not be affected by false negatives.

[0053] Based on this, all value detection signals are combined through a semi-tensor product to form an indicator vector. ,in:

[0054] Then switch network It can be represented as:

[0055] in Let be the Boolean structure matrix of the switching network.

[0056] Figure 4 This is a schematic diagram of the Boolean miter verification process for the switching network in the embodiment. For the switching networks of the circuit before and after optimization, the structure matrices before and after optimization are obtained respectively. .

[0057] Construct a boolean XOR (exclusive OR) miter:

[0058] in This represents the element-wise XOR operation on a matrix. This represents the miter circuit structure matrix of the switching network. Under semantically preserving projection constraints, the value of the semi-tensor product structure matrix is ​​used to determine whether the miter is always Boolean 0.

[0059] when When the switching network is deemed equivalent, it is determined that the switching network is equivalent.

[0060] S5. The following two conditions must be met: (1) Output logic miter (Logical output) is always 0; (2) Switch network miter (Switch network output) is always 0; The circuit before optimization can be determined. Compared with the optimized circuit Compositional equivalence is required under ternary semantics. In the final determination, both output logic equivalence and switching network equivalence are necessary conditions for compositional equivalence. If the output logic miter is always zero, but the switching network miter is not always zero, it indicates that although the two circuits may have the same output under some ternary input states, their switching network implementations still differ under ternary semantics, and therefore cannot be determined as compositional equivalence. If the switching network miter is always zero, but the output logic miter is not always zero, it indicates that the two circuits produce different outputs under at least one ternary input state, and similarly, cannot be determined as compositional equivalence. Only when both miters are always zero can it be said that the circuit before optimization and the circuit after optimization are consistent at both the ternary output logic and switching network implementation levels.

[0061] Therefore, the final determination result of this invention includes two cases: equivalence and inequivalence. When both the output logic miter and the switch network miter are always zero, the two circuits are determined to be equivalent; when either miter has an output that does not correspond to zero, the two circuits are determined to be inequivalent, and the input state causing the inequivalence can be determined based on the column index of the corresponding structure matrix. This determination process is completed within a unified semi-tensor product calculation framework, avoiding inconsistencies caused by using different semantic models for output logic verification and switch network verification.

[0062] 2. Experimental verification To verify the technical effect of the present invention, a typical existing three-valued reference circuit was used for testing. The running time of the exhaustive enumeration method and the method of the present invention were compared. The experimental results are shown in Table 1.

[0063] Table 1

[0064] As shown in Table 1, the method of the present invention has an average speedup of 3.23 times, and can achieve a performance improvement of more than 5 times in some structurally regular circuits. This verifies that the method of the present invention has good scalability while improving verification efficiency and versatility and ensuring verification integrity.

Claims

1. A method for verifying the combinational equivalence of ternary logic circuits based on semi-tensor products, characterized in that, Includes the following steps: S1. Obtain the ternary logic circuit before optimization and the ternary logic circuit after optimization as two circuits to be verified. S2. Convert the two circuits into structural matrix representations based on half-tensor products, and normalize the matrix chain representations of their structural matrices under a fixed main input order. S3. Construct the three-valued miter of the output logic of two circuits based on the inequality comparator in the three-valued logic domain. Determine whether the structure matrix always corresponds to the three-valued zero output by the matrix half-tensor product operation to determine whether the output logic of the two circuits is equivalent. S4. Convert the switching networks in the two circuits into Boolean expressions based on value detection predicates, and construct value detection projection matrices for the three-valued input variables of the two circuits to generate Boolean indication signals that satisfy mutual exclusion and completeness constraints; construct a Boolean miter based on the Boolean indication signals, and determine whether the switching networks of the two circuits are equivalent through matrix semi-tensor product operations. S5. When the output logic of two circuits is equivalent and the switching networks are equivalent, the two circuits are considered to be combined equally.

2. The method for verifying the combinational equivalence of ternary logic circuits based on semi-tensor products according to claim 1, characterized in that, In step S1, the two circuits are described in BLIF format and their node type is LUT node.

3. The method for verifying the combinational equivalence of ternary logic circuits based on semi-tensor products according to claim 1, characterized in that, In step S2, the three-valued input variables in the two circuits are encoded into three-dimensional standard basis vectors, and a structure matrix expression based on the semi-tensor product of the two circuits is constructed. This structure matrix expression is represented by a three-valued logic function. ,in Let be the input vectors of the two circuits. This is the structure matrix corresponding to the input vector.

4. The method for verifying the combinational equivalence of ternary logic circuits based on semi-tensor products according to claim 1, characterized in that, In step S2, the normalization process includes: adjusting the order of input variables using a commutation matrix, eliminating duplicate input variables using a power-reduction matrix, and unifying the matrix chain expression of the structure matrix to a fixed main input order using the commutation property of the matrix and the input variables.

5. The method for verifying the combinational equivalence of ternary logic circuits based on semi-tensor products according to claim 1, characterized in that, In step S3, the inequality comparator is defined in the ternary logic domain as follows: when the two inputs are equal, the output is 0; when the two inputs are unequal, the output is 1.

6. The method for verifying the combinational equivalence of ternary logic circuits based on semi-tensor products according to claim 1, characterized in that, In step S3, a replication matrix is ​​constructed. Will Transform into about Linear mapping: This transforms the three-valued miter into information about... Linear form: ,in, Let be the input vectors of the two circuits. For tensor product, The output vector of the three-valued miter. Let be the structure matrix of the ternary miter; when When all columns correspond to three-value zero outputs, the output logic of the two circuits is determined to be equivalent.

7. The method for verifying the combinational equivalence of ternary logic circuits based on semi-tensor products according to claim 1, characterized in that, In step S4, for any three-valued input variable Construct three value detection projection matrices, and generate three corresponding Boolean indication signals respectively. .

8. The method for verifying the combinational equivalence of ternary logic circuits based on semi-tensor products according to claim 7, characterized in that, The three Boolean indicator signals satisfy the following condition: for any three-valued input assignment, exactly one of the three generated Boolean indicator signals is true and at least one is true.

Images