Voltage reduction circuit, chip, and electronic device

Abstract

This application provides a step-down circuit, chip, and electronic device. By setting a light load detection module, which is used to compare the load current with a preset threshold current, a valid detection signal is generated when the load current is less than the preset threshold current. This allows the current detection unit to increase the on-resistance of the current detection unit according to the valid detection signal, which is equivalent to the load current increasing, thereby reducing the ripple of the step-down circuit under light load conditions.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, specifically to a step-down circuit, chip, and electronic device. Background Technology

[0002] In the field of integrated circuit technology, it is generally necessary to step down the power supply voltage to power various circuits. For example, in low-power MCU applications, the voltage after stepping down the power supply voltage is relatively small, such as 0.9V, while maintaining low ripple under light load conditions.

[0003] In the traditional peak current mode architecture, the acceptable delay of the loop is already very limited. Under light load conditions, since the load current is very small, the turn-on time required by the transistor in the buck circuit will be even smaller, thus resulting in a large ripple problem. Summary of the Invention

[0004] In view of the above problems, embodiments of this application provide a step-down circuit, a chip, and an electronic device to solve the above technical problems.

[0005] In a first aspect, embodiments of this application provide a step-down circuit, including: A DC-DC module is used to step down an input voltage to generate an output voltage. The DC-DC module includes a current sensing unit for detecting load current. The light load detection module is used to compare the load current with a preset threshold current. When the load current is less than the preset threshold current, a valid detection signal is generated. The current detection unit is used to increase the on-resistance of the current detection unit based on the valid detection signal.

[0006] Secondly, embodiments of this application also provide a chip including the aforementioned step-down circuit.

[0007] Thirdly, embodiments of this application also provide an electronic device, including a device body and a step-down circuit as described above disposed on the device body, or including a device body and a chip as described above disposed on the device body.

[0008] The buck circuit, chip, and electronic device provided in this application embodiment, by setting a light load detection module, since the light load detection module is used to compare the load current and the preset threshold current, when the load current is less than the preset threshold current, an effective detection signal is generated, so that the current detection unit can increase the on-resistance value of the current detection unit according to the effective detection signal, which is equivalent to the load current increasing, thereby reducing the ripple of the buck circuit under light load conditions.

[0009] These or other aspects of this application will become more apparent in the following description of the embodiments. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 A schematic diagram of a step-down circuit provided in an embodiment of this application is shown.

[0012] Figure 2 Another schematic diagram of the step-down circuit provided in the embodiments of this application is shown.

[0013] Figure 3 Another schematic diagram of the step-down circuit provided in the embodiments of this application is shown.

[0014] Figure 4 Another schematic diagram of the step-down circuit provided in the embodiments of this application is shown.

[0015] Figure 5 Another schematic diagram of the step-down circuit provided in the embodiments of this application is shown.

[0016] Figure 6 Another schematic diagram of the step-down circuit provided in the embodiments of this application is shown.

[0017] Figure 7 A schematic diagram of a feedback unit 112 provided in an embodiment of this application is shown.

[0018] Figure 8 Another schematic diagram of the feedback unit 112 provided in an embodiment of this application is shown.

[0019] Figure 9 Another schematic diagram of the step-down circuit provided in the embodiments of this application is shown.

[0020] Figure 10 Another schematic diagram of the step-down circuit provided in the embodiments of this application is shown.

[0021] Figure 11 A schematic diagram of a delay control subunit 1131 provided in an embodiment of this application is shown.

[0022] Figure 12 A schematic diagram of a delay control subunit 1131 provided in an embodiment of this application is shown.

[0023] Figure 13A schematic diagram of a portion of the structure of the DC-DC module 110 provided in an embodiment of this application is shown.

[0024] Figure 14 A schematic diagram of a high-side driving unit 114 provided in an embodiment of this application is shown.

[0025] Figure 15 Another schematic diagram of the high-side driving unit 114 provided in an embodiment of this application is shown.

[0026] Figure 16 Another schematic diagram of the step-down circuit provided in the embodiments of this application is shown. Detailed Implementation

[0027] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0028] To enable those skilled in the art to better understand the solutions of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0029] In the embodiments of this application, it should be noted that, in this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0030] Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0031] In the description of the embodiments of this application, the words "example" or "for example" are used to indicate exemplification, illustration, or description. Any embodiment or design described as "example" or "for example" in the embodiments of this application is not to be construed as being more preferred or having more advantages than another embodiment or design. The use of the words "example" or "for example" is intended to present relative concepts in a clear manner.

[0032] Furthermore, in the embodiments of this application, "multiple" refers to two or more. Therefore, in the embodiments of this application, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, such as one, two, or more. For example, including at least one means including one, two, or more, and is not limited to which ones are included. For example, including at least one of A, B, and C, then it could include A, B, C, A and B, A and C, B and C, or A and B and C.

[0033] It should be noted that in the embodiments of this application, "connection" can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.

[0034] In the embodiments of this application, the first terminal / first end of each transistor is one of the source and the drain, and the second terminal / second end of each transistor is the other of the source and the drain. Since the source and drain of a transistor can be structurally symmetrical, they can be structurally indistinguishable. That is, the first terminal / first end and the second terminal / second end of the transistor in the embodiments of this application can be structurally indistinguishable. For example, when the transistor is a P-type transistor, the first terminal / first end is the source, and the second terminal / second end is the drain; for example, when the transistor is an N-type transistor, the first terminal / first end is the drain, and the second terminal / second end is the source.

[0035] In the circuit structure provided by the embodiments of this application, nodes such as the first node and the second node do not represent actual existing components, but rather represent the junction points of related couplings in the circuit diagram. In other words, these nodes are equivalent to the junction points of related couplings in the circuit diagram.

[0036] In the field of integrated circuit technology, it is generally necessary to step down the power supply voltage to power various circuits. Taking the power supply system of an airbag as an example, the power supply voltage is boosted to a high voltage of approximately 33V, which then powers the first-stage buck circuit. The first-stage buck circuit generates a medium voltage of approximately 6.7V, which powers the sensors and the second-stage buck circuit, producing the voltage required by the MCU. In low-power MCU applications, the voltage after stepping down the power supply voltage is relatively small, such as 0.9V, while maintaining low ripple even under light load conditions.

[0037] Since the conversion rate from 6.7V to 0.9V is already very small, the acceptable delay of the loop is already very limited under the traditional peak current mode architecture. Under light load conditions, the turn-on time required by the transistor in the buck circuit will be even smaller due to the small load current, which will result in a large ripple problem.

[0038] In related technologies, PFM, skip mode, and other modes are often used to skip multiple cycles after detecting that the buck circuit is in a light load state and directly determine the on / off state of the high-side power transistor and the low-side power transistor by detecting the output voltage. Although the above methods can ensure high efficiency under light load conditions, they usually have large ripple.

[0039] Therefore, this application provides a step-down circuit, a chip, and an electronic device, which will be described in detail below.

[0040] First, refer to Figure 1 , Figure 1 A schematic diagram of a step-down circuit provided in an embodiment of this application is shown. The step-down circuit includes a DC-DC module 110 and a light load detection module 120.

[0041] The DC-DC module 110 is used to step down the input voltage VIN to generate the output voltage VOUT. The DC-DC module 110 includes a current detection unit 111 for detecting the load current Iload.

[0042] For example, the DC-DC module 110 can implement a step-down function through a high-side power transistor, and the load current Iload is the current output from the second terminal of the high-side power transistor. The current detection unit 111 can be connected to the control terminal of the high-side power transistor to detect the load current Iload.

[0043] The light load detection module 120 is used to compare the load current Iload with the preset threshold current IR. When the load current Iload is less than the preset threshold current IR, a valid detection signal Lightload is generated.

[0044] When a valid detection signal Lightload is generated, it indicates that the current load current Iload is small, meaning the buck circuit is in a light-load state. For example, the valid detection signal Lightload can be a high-level signal. Conversely, when the load current Iload exceeds a preset threshold current IR, the light-load detection module 120 can generate an invalid detection signal, which can be a low-level signal, indicating that the buck circuit is in a heavy-load state.

[0045] It is understandable that the preset threshold current IR can be set to a small current value. For example, the preset threshold current can be 100mA. When the load current IloadIload is less than 100mA, it can be determined that the buck circuit is in a light load state.

[0046] In some embodiments, refer to Figure 2 , Figure 2 Another schematic diagram of the step-down circuit provided in the embodiment of this application is shown. The DC-DC module 110 further includes at least a feedback unit 112, a drive control signal generation unit 113, a high-side drive unit 114, and a high-side power transistor MHS; the feedback unit 112 is connected to the current detection unit 111 and the drive control signal generation unit 113.

[0047] The feedback unit 112 is used to generate an error detection signal based on the output voltage VOUT and the reference signal, and to generate a detection current Isens based on the error detection signal; the drive control signal generation unit 113 is used to perform logic processing based on the detection current Isens and the load current Iload to generate a first control signal CTRL1; the high-side drive unit 114 is used to output a high-side drive signal HS to the high-side power transistor MHS based on the first control signal CTRL1 and the valid detection signal Lightload, so that the DC-DC module 110 generates an output voltage VOUT.

[0048] The high-side drive signal HS is used to control the high-side power transistor MHS to turn on or off. During the generation of the high-side drive signal HS, the high-side drive unit 114 can utilize the effective detection signal Lightload to enhance its driving capability. Specifically, the processing delay of the high-side drive unit 114 can be shortened based on the effective detection signal Lightload to increase the slew rate and improve its driving capability.

[0049] In some embodiments, refer to Figure 3 , Figure 3This illustration shows another schematic diagram of the buck circuit provided in an embodiment of this application. The DC-DC module 110 may further include a low-side drive unit 115, a low-side power transistor MLS, and an energy storage unit. The drive control signal generation unit 113 is further configured to perform logic processing based on the detected current Isens and the load current Iload to generate a second control signal CTRL2. The low-side drive unit 115 is configured to output a low-side drive signal LS to the low-side power transistor MLS based on the second control signal CTRL2. The low-side drive signal LS is used to control the low-side power transistor MLS to turn on or off. The DC-DC module 110 can control the charging and discharging of the energy storage unit by controlling the high-side power transistor MHS and the low-side power transistor MLS, thereby achieving a buck effect.

[0050] The current detection unit 111 is used to increase the on-resistance of the current detection unit 111 according to the valid detection signal Lightload.

[0051] For example, the current detection unit 111 may include multiple detection transistors Msens. The first terminals of the multiple detection transistors Msens are interconnected, the control terminals of the multiple detection transistors Msens are interconnected, and the second terminals of the multiple detection transistors Msens are respectively connected to the first terminal of their respective selection switches. The second terminals of the selection switches are interconnected. The energy storage unit may include an inductor L. The high-side power transistor MHS and the detection transistors Msens may be PMOS transistors. The selection switches corresponding to the detection transistors Msens may be PMOS transistors. The low-side power transistor MLS may be an NMOS transistor. The first terminal of the high-side power transistor MHS is connected to the power supply terminal to receive the input voltage VIN. The control terminal of the high-side power transistor MHS is connected to the control terminal of each detection transistor Msens. The second terminal of the high-side power transistor MHS is connected to the first terminal of the inductor L through a switch SW. The first terminal of each detection transistor Msens is connected to the power supply terminal to receive the input voltage VIN. The control terminal of the high-side power transistor MHS is used to receive the high-side drive signal HS. It can be seen that the detection transistors Msens and the high-side power transistor MHS form a current mirror structure to realize current detection. The first terminal of the low-side power transistor MLS is connected to the first terminal of the inductor L, and the second terminal of the low-side power transistor MLS is connected to the ground terminal. The control terminal of the low-side power transistor MLS is used to input the low-side drive signal LS, and the second terminal of the inductor L is used to generate the output voltage VOUT. When the high-side power transistor MHS is turned on and the switch SW is turned on, the input voltage VIN charges the inductor L. When the low-side power transistor MLS is turned on and the switch SW is turned off and the high-side power transistor MHS is turned off, the inductor L discharges to the ground terminal, thereby achieving the voltage reduction effect.

[0052] The current detection unit 111 can control the number of conducting transistors Msens via a switch selection signal, thereby controlling the current mirror ratio. For example, the current detection unit 111 can control the multiple selection switches by receiving a switch selection signal. Figure 3 Taking the switch selection signal <2:0> as an example, <2:0> is a 3-bit switch selection signal. Correspondingly, the number of detection transistors Msens and the number of selection switches can be 3 each. Assuming the switch selection signal is 001, the actions of the 3 selection switches are, in sequence, off, off, and on.

[0053] Understandable, Figure 3 The switch selection signals in the example are for illustrative purposes only. The embodiments of this application do not limit the specific number of selection switches. That is, the number of detection transistors Msens in the current detection unit 111 can be set according to actual needs.

[0054] In addition, the DC-DC module 110 may also include an overvoltage protection unit 116 and a discontinuous conduction mode detection unit 117. The overvoltage protection unit 116 is connected to the second terminal of the inductor L to receive the output voltage VOUT. The overvoltage protection unit 116 is also connected to a reference signal REF. By comparing the magnitude of the output voltage VOUT and the reference signal REF, it is determined whether the output voltage VOUT is too large, and an overvoltage signal OV is output, thereby using the overvoltage signal OV to achieve overvoltage protection. The discontinuous conduction mode detection unit 117 is connected to the first terminal of the inductor L and the ground terminal PGND respectively. The discontinuous conduction mode detection unit 117 is used to detect whether the current of the inductor L drops to zero, and then outputs a discontinuous conduction mode detection signal DMD, thereby indicating whether the buck circuit has entered the discontinuous conduction mode. The high-side drive unit 114 can also receive the discontinuous conduction mode detection signal DMD when generating the high-side drive signal HS.

[0055] The light load detection module 120 can be connected to the second terminal of the high-side power transistor MHS to generate a valid detection signal Lightload based on the load current Iload of the high-side power transistor MHS.

[0056] In some embodiments, when the current detection unit 111 includes multiple detection transistors Msens, the current detection unit 111 reduces the number of activated detection transistors Msens when it receives a valid detection signal Lightload. Since the control terminals of the multiple detection transistors Msens are interconnected, the first terminals of the multiple detection transistors Msens are interconnected, and the second terminals of the multiple detection transistors Msens are respectively connected to the first terminals of their respective selection switches, and the second terminals of each selection switch are interconnected, reducing the number of activated detection transistors Msens is equivalent to increasing the on-resistance of the current detection unit 111.

[0057] Specifically, one or more of the switching selection signals of the multiple detection transistors Msens can be controlled by the valid detection signal Lightload. When the current detection unit 111 receives the valid detection signal Lightload, the corresponding switching selection signal is set to a low level (for example, it can be implemented using a logic gate, inverter, etc.), thereby turning off the corresponding selection switch and reducing the number of detection transistors Msens that are turned on.

[0058] By setting up a light load detection module 120, which is used to compare the load current Iload with the preset threshold current IR, a valid detection signal Lightload is generated when the load current Iload is less than the preset threshold current IR. This allows the current detection unit 111 to increase its on-resistance value according to the valid detection signal Lightload, which is equivalent to the load current Iload increasing. This enables the buck circuit to always operate in continuous conduction mode (CCM), thereby reducing the ripple of the buck circuit under light load conditions.

[0059] In some embodiments, refer to Figure 4 , Figure 4 The diagram shows another schematic of the step-down circuit provided in the embodiment of this application. The light load detection module 120 includes a first transistor M1, a first comparator CP1 and a current source IREF. For example, the type of the first transistor M1 is the same as the type of the detection transistor Msens, that is, the first transistor M1 can also be a PMOS transistor.

[0060] In this circuit, the first terminal of the first transistor M1 is connected to the power supply terminal, the second terminal of the first transistor M1 is connected to the first terminal of the current source IREF, and the control terminal of the first transistor M1 is connected to the ground terminal. The current source IREF is used to generate a preset threshold current IR, and the second terminal of the current source IREF is connected to the ground terminal HS_GND. The first input terminal of the first comparator CP1 is connected to the first terminal of the current source IREF, the second input terminal of the first comparator CP1 is connected to the high-side power transistor MHS to connect to the load current Iload, and the output terminal of the first comparator CP1 is used to output a valid detection signal Lightload. The first input terminal of the first comparator CP1 is a non-inverting input terminal, and the second input terminal of the first comparator CP1 is an inverting input terminal.

[0061] Specifically, the second input terminal of the first comparator CP1 can be connected to the second terminal of the high-side power transistor MHS. The second terminal of the high-side power transistor MHS reflects the voltage drop across the load current Iload. Furthermore, since the control terminal of the first transistor M1 is connected to the ground terminal HS_GND, meaning the first transistor M1 is always in the on state, it can be used to simulate the voltage drop generated when a preset threshold current passes through a transistor of a certain size. Therefore, by comparing the voltage between the second terminal of the high-side power transistor MHS and the second terminal of the first transistor M1, it is possible to determine whether the load current Iload is greater than the preset threshold current, achieving a comparison effect between the load current Iload and the preset threshold current. Correspondingly, the preset threshold current is matched to the size of the first transistor M1.

[0062] By using the structure of the first transistor M1, the first comparator CP1, and the current source IEF, the relationship between the load current Iload and the preset threshold current can be accurately detected.

[0063] In some embodiments, there are multiple light load detection modules 120, each light load detection module 120 corresponds to a different preset threshold current IR, and each light load detection module 120 outputs its own corresponding valid detection signal Lightload.

[0064] Each light load detection module 120 can generate different preset threshold currents IR through different current sources IREF. Since there are multiple light load detection modules 120, they can output multiple valid detection signals Lightload. When any of the multiple valid detection signals Lightload indicates that the load current Iload is less than the current threshold, the buck circuit is determined to be in a light load state.

[0065] For example, refer to Figure 5 , Figure 5Another schematic diagram of the buck circuit provided in this application embodiment is shown, taking two light load detection modules 120 as an example. The two light load detection modules 120 respectively output valid detection signals LightloadA and LightloadB. When the valid detection signal LightloadA or the valid detection signal LightloadB indicates that the load current Iload is less than the current threshold, it is determined that the buck circuit is in a light load state. Accordingly, the valid detection signals LightloadA and LightloadB are input to the high-side drive unit 114 and the current detection unit 111.

[0066] Accordingly, when there are multiple valid detection signals Lightload, the switching selection signals of multiple detection transistors Msens can be controlled simultaneously by multiple valid detection signals Lightload. Each valid detection signal Lightload controls the switching selection signal of the corresponding bit, thereby controlling the number of detection transistors Msens turned on more accurately and precisely.

[0067] It is understood that the number of light load detection modules 120 can be increased according to actual needs, and this application embodiment does not limit it.

[0068] In some embodiments, each of the light load detection modules 120 can adopt Figure 4 The structure shown is referenced. Figure 6 , Figure 6 This illustration shows another schematic diagram of the step-down circuit provided in an embodiment of this application. Taking two light-load detection modules 120 as an example, both light-load detection modules 120 may include a first transistor M1, a first comparator CP1, and a current source IREF. The difference is that the current source IREF in the two light-load detection modules 120 is used to provide different preset threshold currents IR. Figure 6 In the example shown, the current sources IREF in the two light load detection modules 120 are used to provide a preset threshold current of 100mA and a preset threshold current of 200mA, respectively.

[0069] By setting up multiple light load detection modules 120, multiple different preset threshold currents can be used to detect the light load state of the step-down circuit, thereby improving the flexibility and precision of the light load state detection.

[0070] In some embodiments, refer to Figure 7 , Figure 7A schematic diagram of a feedback unit 112 provided in an embodiment of this application is shown. The feedback unit 112 may include a voltage divider subunit 1121, an error amplification subunit 1122, a slope compensation subunit 1123, a voltage compensation subunit 1124, and a voltage-to-current conversion subunit 1125. The voltage divider subunit 1121 is used to receive the output voltage VOUT and divide it to obtain a feedback voltage FB. The error amplification subunit 1122 is connected to the voltage divider subunit 1121 to receive the feedback voltage FB. The error amplification subunit 1122 also receives a reference signal REF to compare the feedback voltage FB with the reference signal REF to generate an error detection signal VC. The voltage compensation subunit 1124 is connected to the error amplification subunit 1122 to receive the error detection signal VC. The voltage compensation subunit 1124 is used to compensate the error detection signal VC to improve its stability. The slope compensation subunit 1123 is used to generate a slope compensation signal I_slope. The voltage-to-current subunit 1125 is connected to the slope compensation subunit 1123 and the error amplification subunit 1122 respectively to receive the slope compensation signal I_slope and the error detection signal VC. At the same time, the voltage-to-current subunit 1125 is connected to the current detection unit 111, thereby generating the detection current Isens of the current detection unit 111 based on the slope compensation signal I_slope and the error detection signal VC.

[0071] When the current detection unit 111 includes multiple detection transistors Msens, the voltage-to-current subunit 1125 is connected to the second terminal of the gating switch, and the detection current Isens flows to the reference ground inside the voltage-to-current subunit 1125.

[0072] For example, refer to Figure 8 , Figure 8 Another schematic diagram of the feedback unit 112 provided in this application embodiment is shown. The error amplification subunit 1122 may include a soft-start subunit 11221 and an error amplifier 11222. The soft-start subunit 11221 generates a soft-start signal SS. The first input terminal of the error amplifier 11222 is connected to a reference signal REF, the second input terminal of the error amplifier 11222 is connected to the soft-start signal SS, the third input terminal of the error amplifier 11222 is connected to a feedback voltage FB, and the fourth input terminal of the error amplifier 11222 is connected to a disable signal Disable. The disable signal Disable is used to control whether the error amplifier 11222 operates. When the soft-start signal SS indicates that the soft-start is complete, the error amplifier 11222 compares the feedback voltage FB with the reference signal REF to generate an error detection signal VC.

[0073] The voltage compensation subunit 1124 includes a first capacitor C1, a second capacitor C2, and a first resistor R1. The first plate of the first capacitor C1 is connected to the error detection signal VC, and the second plate of the first capacitor C1 is connected to the ground terminal. The first end of the first resistor R1 is connected to the error detection signal VC, and the second end of the first resistor R1 is connected to the first plate of the second capacitor C2. The second plate of the second capacitor C2 is connected to the ground terminal. The first capacitor C1, the second capacitor C2, and the first resistor R1 form an RC compensation network to improve the stability of the error detection signal VC.

[0074] The voltage divider unit 1121 includes a second resistor R2 and a third resistor R3. The first end of the second resistor R2 is used to connect to the output voltage VOUT. The second end of the second resistor R2 is connected to the first end of the third resistor R3. The second end of the third resistor R3 is connected to the ground terminal. The first end of the third resistor R3 is connected to the error amplifier 11222 to provide the feedback voltage FB to the error amplifier 11222.

[0075] In some embodiments, refer to Figure 9 , Figure 9 This paper shows another schematic diagram of the step-down circuit provided in an embodiment of the present application. The drive control signal generation unit 113 includes a second comparator CP2, a delay control subunit 1131, and a logic subunit 1132.

[0076] The delay control subunit 1131 generates a delay control signal Blanking based on the valid detection signal Lightload and the high-side drive signal HS. The second comparator CP2 compares the load current Iload with the detected current Isens based on the delay control signal Blanking to generate a comparison signal COMP. The second comparator CP2 can also be connected to a disable signal Disable to control whether the second comparator CP2 is working. The logic subunit 1132 performs logic processing based on the comparison signal COMP to generate a first control signal CTRL1 and a second control signal CTRL2.

[0077] Specifically, the delay control subunit 1131 is connected to the high-side drive unit 114 and the light-load detection module 120 respectively to receive the high-side drive signal HS and the valid detection signal Lightload. The second comparator CP2 is connected to the delay control subunit 1131 to receive the delay control signal Blanking. The delay control signal Blanking is used to enable or disable the second comparator CP2. The delay control subunit 1131 can internally delay for a certain period of time before outputting the delay control signal Blanking to ensure the accuracy of feedback adjustment. For example, the second comparator CP2 can be disabled when the delay control signal Blanking is high, and enabled when the delay control signal Blanking is low. When the valid detection signal Lightload indicates that the buck circuit is in a light-load state, the delay duration provided by the delay control subunit 1131 can be shortened. Shortening the delay duration provided by the delay control subunit 1131 can be done by shortening the delay duration to a smaller value, or the delay duration can be removed directly.

[0078] For example, the delay control subunit 1131 can use an RC delay network to provide a delay duration for the second comparator CP2. The delay control subunit 1131 can include a short-circuit switch connected in parallel with the RC delay network, which is controlled to turn on or off based on the valid detection signal Lightload. When the valid detection signal Lightload indicates that the buck circuit is in a light-load state, the short-circuit switch can be turned on, thereby skipping the RC delay network and achieving the effect of eliminating the delay duration.

[0079] In addition, RC delay networks can use resistor arrays or capacitor arrays. The number of resistors selected in the resistor array, and thus the resistance value, can be controlled based on the effective detection signal "Lightload," or the number of capacitors selected in the capacitor array, and thus the capacitance value. The resistor array can be connected in series or in parallel, with each resistor connected to its corresponding selector switch. Similarly, the capacitor array can be connected in series or in parallel, with each capacitor connected to its corresponding selector switch. When the effective detection signal "Lightload" indicates that the buck circuit is under light load, the resistance or capacitance value of either the resistor array or the capacitor array can be reduced by controlling the turn-on or turn-off of the selector switches, thus shortening the delay time. It can be understood that when the effective detection signal "Lightload" indicates that the buck circuit is under light load, the resistance of the resistor array can be reduced individually, or the capacitance value of the capacitor array can be reduced individually, or both the resistance and capacitance values ​​can be reduced simultaneously.

[0080] It can be seen that by shortening the delay duration provided by the delay control subunit 1131 when the valid detection signal Lightload indicates that the buck circuit is in a light load state, the logic delay of the buck circuit can be reduced and the slew rate of the high-side drive unit 114 can be improved.

[0081] In some embodiments, refer to Figure 10 , Figure 10 This paper shows another schematic diagram of the step-down circuit provided in the embodiment of this application. When there are multiple light load detection modules 120, there are multiple valid detection signals Lightload. The drive control signal generation unit 113 also includes a first OR gate 1133.

[0082] Specifically, the first OR gate 1133 is used to generate a light load enable signal Lightload_EN based on multiple valid detection signals Lightload; the delay control subunit 1131 is used to generate a delay control signal Blanking based on the light load enable signal Lightload_EN and the high-side drive signal HS. The first logic unit 142 is connected to each light load detection module 120 to receive multiple valid detection signals Lightload, the first logic unit 142 is connected to the high-side drive unit 114 to receive the high-side drive signal HS, and the first logic unit 142 is connected to the delay control subunit 1131 to provide the light load enable signal Lightload_EN to the delay control subunit 1131.

[0083] For example, there can be two valid detection signals Lightload. When the first OR gate 1133 receives at least one of the valid detection signals Lightload100mA or Lightload200mA, the light load enable signal Lightload_EN is high, thereby indicating that the buck circuit is in a light load state.

[0084] It is understandable that the function of the light load enable signal Lightload_EN is similar to that of the effective detection signal Lightload, which has one phase. When the light load enable signal Lightload_EN indicates that the buck circuit is in a light load state, the delay duration provided by the delay control subunit 1131 can be shortened. The specific principle is similar to that described above and will not be repeated here.

[0085] In some embodiments, in addition to using the aforementioned short-circuit switch to remove the delay duration, refer to Figure 11 , Figure 11The diagram shows a delay control subunit 1131 provided in an embodiment of this application. The delay control subunit 1131 includes a first inverter 11311, a first delay unit 11312, a second inverter 11313, a first NOR gate 11314, and a second OR gate 11315.

[0086] Specifically, the first inverter 11311 is used to invert the high-side drive signal HS to obtain the first inverted signal HS_N; the first delay unit 11312 is used to generate the first delay signal HS_DE based on the first inverted signal HS_N; the second inverter 11313 is used to invert the first delay signal HS_DE to obtain the second inverted signal HS_DE_N; the first NOR gate 11314 is used to generate the first logic signal LOG1 based on the second inverted signal HS_DE_N and the light load enable signal Lightload_EN; and the second OR gate 11315 is used to generate the delay control signal Blanking based on the first logic signal LOG1 and the first inverted signal HS_N.

[0087] Specifically, the first inverter 11311 is connected to the high-side drive unit 114 to receive the high-side drive signal HS, the first delay unit 11312 is connected to the first inverter 11311 to receive the first inverted signal HS_N, the second inverter 11313 is connected to the first delay unit 11312 to receive the first delayed signal HS_DE, the first NOR gate 11314 is connected to the second inverter 11313 and the first logic unit 142 respectively to receive the second inverted signal HS_DE_N and the light load enable signal Lightload_EN, and the second OR gate 11315 is connected to the first NOR gate 11314 and the first inverter 11311 respectively to receive the first logic signal LOG1 and the first inverted signal HS_N.

[0088] For example, the first delayer 11312 may include an RC delay network that delays the high-side drive signal HS to generate a first delayed signal HS_DE.

[0089] In related technologies, when the high-side drive signal HS changes from low to high, Blanking typically needs to delay its transition from high to low to shield the second comparator CP2 for a period of time, thereby preventing the conduction noise of the high-side power transistor HS from affecting the second comparator CP2. By setting the first inverter 11311 to invert the high-side drive signal HS and the second inverter 11313 to invert the first delay signal HS_DE, when the first NOR gate 11314 receives the valid detection signal Lightload, it indicates that the buck circuit is in a light-load state. At this time, the first logic signal LOG1 must be low. When the high-side drive signal HS is high, the first inverted signal HS_N is low, so the delay control signal Blanking is low, immediately activating the second comparator CP2. The first delay unit 11312 does not function at this time, achieving the effect of removing the delay duration. When the buck circuit is under heavy load, the first NOR gate 11314 receives an invalid detection signal. When the high-side drive signal HS is high, the second inverted signal HS_DE_N is high. At this time, the first logic signal LOG1 is low and the delay control signal Blanking is low. However, since the second inverted signal HS_DE_N is obtained after a delay, the second comparator CP2 is activated with a delay, so it does not affect the delay effect under heavy load.

[0090] The above structure enables the accurate and rapid generation of the delay control signal Blanking based on the light load enable signal Lightload_EN, without affecting the delay effect under heavy load conditions.

[0091] It is understandable that when there is only one valid detection signal Lightload, the first NOR gate 11314 is connected to the light load detection module 120 and directly accesses the valid detection signal Lightload.

[0092] In some embodiments, refer to Figure 12 , Figure 12 This illustration shows a schematic diagram of a delay control subunit 1131 provided in an embodiment of this application. The first delay unit 11312 includes a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a fourth resistor R4, and a third capacitor C3. Exemplarily, the second transistor M2 and the third transistor M3 can be PMOS transistors, and the fourth transistor M4 and the fifth transistor M5 can be NMOS transistors.

[0093] Among them, the control terminal of the second transistor M2 is connected to the control terminal of the fourth transistor M4. The control terminal of the second transistor M2 is used to receive the first inverting signal HS_N. The first terminal of the second transistor M2 is connected to the power supply terminal. The second terminal of the second transistor M2 is connected to the first terminal of the fourth resistor R4. The first terminal of the fourth transistor M4 is connected to the second terminal of the fourth resistor R4 and the first plate of the third capacitor C3, respectively. The second terminal of the fourth transistor M4 is connected to the second plate of the third capacitor C3 and the ground terminal, respectively. The control terminal of the third transistor M3 is connected to the second terminal of the fourth resistor R4, the first terminal of the third transistor M3 is connected to the power supply terminal, and the second terminal of the third transistor M3 is connected to the first terminal of the fifth transistor M5. The control terminal of the fifth transistor M5 is connected to the second terminal of the fourth resistor R4, and the second terminal of the fifth transistor M5 is connected to the ground terminal.

[0094] The fourth resistor R4 and the third capacitor C3 form an RC delay network. The delay effect is achieved by charging and discharging the third capacitor C3, which has the advantages of simple structure and low power consumption.

[0095] In some embodiments, refer to Figure 13 , Figure 13 This diagram illustrates a partial structure of the DC-DC module 110 provided in an embodiment of this application. The logic subunit 1132 includes a second NOR gate 11321 and an RS flip-flop 11322. In addition, the drive control signal generation unit 113 also includes a temperature protection subunit 1133 and a refresh subunit 1134. The DC-DC module 110 also includes a level conversion unit 118.

[0096] The second NOR gate 11321 is used to generate a second logic signal LOG2 based on the comparison signal COMP. The RS flip-flop 11322 is used to generate a first control signal CTRL1 and a second control signal CTRL2 based on the second logic signal LOG2 and the reference clock signal CLK_SET. In addition to the comparison signal COMP, the second NOR gate 11321 can also input an overvoltage signal OV, a temperature protection signal TP output from the temperature protection subunit 1133, and a disable signal Disable. The disable signal Disable is used to control whether the second NOR gate 11321 operates. The S terminal of the RS flip-flop 11322 is connected to the reference clock signal CLK_SET, and the R terminal of the RS flip-flop 11322 is connected to the second logic signal LOG2. The first control signal CTRL1 is output from the terminal, and the RS flip-flop 11322... The terminal outputs the second control signal CTRL2. When any one of the overvoltage signal OV, temperature protection signal TP, disable signal Disable, and comparison signal COMP is high, the second logic signal LOG2 is low. The refresh subunit 1134 is used to reset the RS flip-flop 11322.

[0097] The level conversion unit 152 is used to perform level conversion on the first control signal CTRL1 to obtain the control conversion signal CTRL1_LS, and to perform level conversion on the valid detection signal Lightload to obtain the detection conversion signal Lightload_LS; the high-side drive unit 114 is used to generate the high-side drive signal HS according to the control conversion signal CTRL1_LS and the detection conversion signal Lightload_LS.

[0098] Specifically, the second NOR gate 11321 is connected to the current comparison module 140 to receive the comparison signal COMP. The level conversion unit 152 is connected to the light load detection module 120 and the second NOR gate 11321 to receive the first control signal CTRL1 and the valid detection signal Lightload. The high-side drive unit 114 is connected to the level conversion unit 152 to receive the control conversion signal CTRL1_LS and the detection conversion signal Lightload_LS. The level conversion unit 152 can convert the voltage domain of the first control signal CTRL1 and the valid detection signal Lightload, so that the first control signal CTRL1 and the valid detection signal Lightload are converted to the voltage domain adapted to the high-side drive unit 114. The high-side drive unit 114 is connected to the power supply terminal to receive the input voltage VIN, the high-side drive unit 114 is connected to the high-side power transistor MHS to provide the high-side drive signal HS to the high-side power transistor MHS, and the high-side drive unit 114 is also connected to the ground terminal HS_GND.

[0099] In addition, the DC-DC module 110 also includes a low-side power supply unit 119, which is connected to the power supply terminal to provide a low-side power supply voltage to the low-side drive unit 154. The low-side drive unit 154 is also connected to the ground terminal PGND.

[0100] It is understandable that when there are multiple valid detection signals Lightload, the level conversion unit 152 performs voltage domain conversion on each valid detection signal Lightload and outputs the detection conversion signal Lightload_LS corresponding to each valid detection signal Lightload.

[0101] In some embodiments, refer to Figure 14 , Figure 14 A schematic diagram of a high-side driving unit 114 provided in an embodiment of this application is shown. The high-side driving unit 114 includes a buffer 1141, a second delay 1142, and a selector 1143.

[0102] The buffer 1141 is used to generate a buffer signal CTRL1_BUF based on the control conversion signal CTRL1_LS; the second delay 1142 is used to generate a second delay signal CTRL1_DE based on the buffer signal CTRL1_BUF; and the selector 1143 is used to select one of the buffer signal CTRL1_BUF and the second delay signal CTRL1_DE as the high-side drive signal HS based on the detection conversion signal Lightload_LS.

[0103] Specifically, buffer 1141 is connected to level conversion unit 152 to receive control conversion signal CTRL1_LS, second delay unit 1142 is connected to buffer 1141 to receive buffer signal CTRL1_BUF, and selector 1143 is connected to second delay unit 1142, buffer 1141 and level conversion unit 152 respectively to receive detection conversion signal Lightload_LS, buffer signal CTRL1_BUF and second delay signal CTRL1_DE, wherein detection conversion signal Lightload_LS is used as selection control signal for selector 1143.

[0104] For example, buffer 1141 can be a buffer obtained by cascading multiple inverters, second delay 1142 can be an RC delay network, and selector 1143 can be a two-way selector.

[0105] The control conversion signal CTRL1_LS is first amplified by buffer 1141 to generate a buffer signal CTRL1_BUF. The buffer signal CTRL1_BUF is then delayed by the second delay unit 1142 to generate a second delayed signal CTRL1_DE. When selector 1143 receives the detection conversion signal Lightload_LS, selector 1143 selects the buffer signal CTRL1_BUF for output. When selector 1143 does not receive the detection conversion signal Lightload_LS, selector 1143 selects the second delayed signal CTRL1_DE for output. It can be seen that when the buck circuit is in a light load state, it can shorten the logic delay to increase the slew rate of the drive unit and improve the driving capability of the high-side drive unit 114.

[0106] In some embodiments, when there are multiple valid detection signals Lightload, there are also multiple buffers 1141, second delays 1142, and selectors 1143. The buffers 1141, second delays 1142, and selectors 1143 form a single driving component, creating a cascaded structure where the selector 1143 of the previous driving component is connected to the buffer 1141 of the next driving component. Taking two valid detection signals Lightload as an example (the two detection conversion signals Lightload_LS are Lightload100mA_LS and Lightload200mA_LS, respectively), see [reference]. Figure 15 , Figure 15 Another schematic diagram of the high-side driving unit 114 provided in this application embodiment is shown. The control conversion signal CTRL1_LS is input to the high-side driving unit 114 corresponding to the detection conversion signal Lightload200mA_LS. The output of the high-side driving unit 114 corresponding to the detection conversion signal Lightload200mA_LS is used as the input of the high-side driving unit 114 corresponding to the detection conversion signal Lightload100mA_LS. Finally, the high-side driving unit 114 corresponding to the detection conversion signal Lightload100mA_LS outputs the high-side driving signal HS.

[0107] Specifically, when both selectors 1143 simultaneously receive the detection conversion signal Lightload_LS, neither of the two high-side drive units 114 performs a delay; when one of the selectors 1143 does not receive the detection conversion signal Lightload_LS, its corresponding high-side drive unit 114 does not perform a delay; when neither of the two selectors 1143 receives the detection conversion signal Lightload_LS, neither of the two high-side drive units 114 performs a delay. The second delay unit 1142 (Delay1 in the figure) corresponding to the detection conversion signal Lightload100mA_LS and the second delay unit 1142 (Delay2 in the figure) corresponding to the detection conversion signal Lightload200mA_LS can be configured with different delay durations, thereby improving the flexibility and fineness of delay control.

[0108] In some embodiments, refer to Figure 16 , Figure 16Another schematic diagram of the step-down circuit provided in this application embodiment is shown. When there are multiple valid detection signals Lightload, the first current comparison unit 121 may further include a light load detection switch SL. The first terminal of the light load detection switch SL is connected to the output terminal of the first comparator CP1, and the second terminal of the light load detection switch SL is used to output a valid detection signal Lightload. The light load detection switch SL is controlled by a detection switch enable signal S_EN. When the switch enable signal S_EN controls the light load detection switch SL to be turned on, the corresponding first current comparison unit 121 outputs a valid detection signal Lightload. The light load detection switch SL allows for flexible selection of a corresponding preset threshold current for light load state detection.

[0109] Specifically, the switch enable signal S_EN can be determined by detecting the output voltage VOUT. When the detected output voltage VOUT is larger, a larger preset threshold current IR is selected for light load detection, thereby making the light load state detection more accurate.

[0110] Furthermore, this application also provides a chip, wherein the chip includes the aforementioned step-down circuit. A chip (Integrated Circuit, IC) is also called a chip, and this chip can be, but is not limited to, a System-on-Chip (SoC) chip or a System-in-Package (SIP) chip. Since the chip of this application possesses the step-down circuit of the above embodiments, it has all the beneficial effects of the step-down circuit in the above embodiments, and will not be repeated here.

[0111] In addition, this application also provides an electronic device, which includes a device body and a step-down circuit or chip as described above disposed within the device body. The electronic device may be, but is not limited to, a weight scale, body fat scale, nutrition scale, infrared electronic thermometer, pulse oximeter, body composition analyzer, power bank, wireless charger, fast charger, car charger, adapter, display, USB (Universal Serial Bus) docking station, stylus, true wireless earphones, car infotainment screen, automobile, smart wearable device, mobile terminal, and smart home device. Smart wearable devices include, but are not limited to, smartwatches, smart bracelets, and neck massagers. Mobile terminals include, but are not limited to, smartphones, laptops, tablets, and POS (point of sales terminal) machines. Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart robot vacuums, and smart lights. Since the electronic device of this application possesses the step-down circuit or chip described in the above embodiments, it has all the beneficial effects of the step-down circuit or chip described in the above embodiments, which will not be repeated here.

[0112] It should also be understood that the various implementation methods provided in this application can be combined arbitrarily to achieve different beneficial effects.

[0113] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Although this application has disclosed preferred embodiments as above, it is not intended to limit this application. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this application. Any indirect modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A voltage reduction circuit, characterized by comprising: include: A DC-DC module is used to step down an input voltage to generate an output voltage, and the DC-DC module includes a current detection unit for detecting load current. A light load detection module is used to compare the load current with a preset threshold current, and generate a valid detection signal when the load current is less than the preset threshold current. The current detection unit is used to increase the on-resistance value of the current detection unit based on the valid detection signal.

2. The voltage reduction circuit of claim 1, wherein, The light load detection module includes a first transistor, a first comparator, and a current source; The first terminal of the first transistor is connected to the power supply terminal, the second terminal of the first transistor is connected to the first terminal of the current source, and the control terminal of the first transistor is connected to the ground terminal. The current source is used to generate the preset threshold current, and the second end of the current source is connected to the grounding end; The first input terminal of the first comparator is connected to the first terminal of the current source, the second input terminal of the first comparator is connected to the load current, and the output terminal of the first comparator is used to output the valid detection signal.

3. The voltage reduction circuit of claim 1, wherein, The current detection unit includes multiple detection transistors, and the current detection unit is used to reduce the number of detection transistors turned on when the valid detection signal is received.

4. The voltage reduction circuit of claim 1, wherein, The DC-DC module further includes a feedback unit, a drive control signal generation unit, a high-side drive unit, and a high-side power transistor; the feedback unit is connected to the current detection unit and the drive control signal generation unit. The feedback unit is used to generate an error detection signal based on the output voltage and the reference signal, and to generate a detection current based on the error detection signal. The drive control signal generation unit is used to compare the detected current and the load current, and perform logical processing on the comparison result to generate a first control signal. The high-side drive unit is used to output a high-side drive signal to the high-side power transistor according to the first control signal and the valid detection signal, so that the DC-DC module generates the output voltage.

5. The step-down circuit according to claim 4, characterized in that, The drive control signal generation unit includes a second comparator, a delay control subunit, and a logic subunit; The delay control subunit is used to generate a delay control signal based on the valid detection signal and the high-side drive signal; The second comparator is used to compare the load current with the detected current according to the delay control signal to generate a comparison signal; The logic subunit is used to perform logic processing based on the comparison signal to generate the first control signal.

6. The step-down circuit according to claim 5, characterized in that, The number of valid detection signals is multiple, and the drive control signal generation unit further includes a first OR gate; The first OR gate is used to generate a light-load enable signal based on a plurality of the valid detection signals; The delay control subunit is used to generate the delay control signal based on the light load enable signal and the high-side drive signal.

7. The step-down circuit according to claim 6, characterized in that, The delay control subunit includes a first delay unit, a first inverter, a second inverter, a first NOR gate, and a second OR gate; The first inverter is used to invert the high-side drive signal to obtain a first inverted signal; The first delay unit is used to generate a first delay signal based on the first inverted signal; The second inverter is used to invert the first delayed signal to obtain a second inverted signal; The first NOR gate is used to generate a first logic signal based on the second inverted signal and the light load enable signal; The second OR gate is used to generate the delay control signal based on the first logic signal and the first inverted signal.

8. The step-down circuit according to claim 4, characterized in that, The high-side driving unit includes a buffer, a second delay, and a selector; The buffer is used to generate a buffer signal according to the first control signal; The second delay unit is used to generate a second delay signal based on the buffer signal; The selector is used to select one of the buffer signal and the second delay signal as the high-side drive signal based on the valid detection signal.

9. The step-down circuit according to claim 1, characterized in that, The number of light load detection modules is multiple, and each light load detection module corresponds to a different preset threshold current. Each light load detection module outputs its own corresponding valid detection signal.

10. A chip, characterized in that, Includes the step-down circuit as described in any one of claims 1 to 9.

11. An electronic device, characterized in that, It includes a device body and a step-down circuit as described in any one of claims 1 to 9 disposed on the device body, or it includes a device body and a chip as described in claim 10 disposed on the device body.

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