A digital phased array operating state health management system

Abstract

The application relates to a digital phased array working state health management system, and belongs to the technical field of satellite communication and phased array antennas. The system takes a baseband processing unit as a carrier, comprises a monitoring FPGA, a service FPGA, a radio frequency transceiver, an ADC sampling module and a multi-path power supply switch, cooperatively collects digital phased array working state data through the ADC sampling module and the radio frequency transceiver, uniformly returns the satellite platform after being analyzed by the service FPGA, realizes remote control of the load, and can individually stop and restart and repair the faulty radio frequency channel by matching the branch controllable power supply switch. And by independently distributing power among the monitoring FPGA, the service FPGA and the radio frequency transceiver and following the step-by-step power-on sequence, hardware support can be provided for single particle latch grading disposal. The system can realize the whole-process closed-loop health management and control of early discovery, on-site disposal and fault isolation of the digital phased array.

Description

Technical Field

[0001] This application relates to the fields of satellite communication and phased array antenna technology, and in particular to a digital phased array operational status health management system. Background Technology

[0002] With the rapid development of the satellite communication industry, direct satellite-to-ground communication for mobile phones has become an important supplement to terrestrial mobile communication, with broad application prospects. S / S and S / C digital phased arrays are core components of direct satellite-to-ground communication for mobile phones. Their stability and health in orbit directly determine the quality of the satellite-to-ground communication link and the smooth execution of communication missions, serving as a core foundation for ensuring the long-term operation of satellite communication systems.

[0003] Spaceborne digital phased arrays operate in unique environments, constantly exposed to the complex conditions of high vacuum, strong radiation, and significant temperature variations inherent in space. Their core components, such as transceiver modules, baseband processing chips, and FPGA (Field-Programmable Gate Array) processors, are highly susceptible to single-event upsets, total dose ionization damage, and thermal fatigue. Due to the inherent limitations of on-orbit physical repair, there is a lack of precise real-time health monitoring and performance prediction methods. Consequently, localized performance degradation of components cannot be identified in a timely manner, easily leading to issues such as beam pointing deviation and abnormal link gain, ultimately causing communication disruptions between space and ground.

[0004] Meanwhile, digital beamforming technology has a complex architecture. Compared to traditional analog beamforming, it features independent operation of multiple channels. Faults often manifest as subtle soft errors and slow performance degradation, and various faults exhibit correlation effects, making them difficult to accurately diagnose and identify. Currently, the industry lacks sophisticated health management solutions adapted to spaceborne digital phased arrays, making it impossible to effectively monitor and predict equipment degradation faults, and thus failing to meet the requirements of long-life, high-reliability on-orbit missions for satellites. Summary of the Invention

[0005] Therefore, it is necessary to provide a digital phased array working status health management system to address the aforementioned technical problems.

[0006] A digital phased array operational status health management system, the system using a baseband processing unit as a carrier, including a monitoring FPGA, a service FPGA, an RF transceiver, an ADC sampling module, and a multi-channel power supply switch, wherein the monitoring FPGA, service FPGA, and RF transceiver are independently powered and execute hierarchical power supply timing; wherein, the first-level power supply timing is that the power network of the monitoring FPGA is enabled by an external OC, so that it outputs power to the monitoring FPGA; the second-level power supply timing is that the power network of the service FPGA is enabled by the power-on of the monitoring FPGA, so that it outputs power to the service FPGA; and the third-level power supply timing is that the power network of the RF transceiver is enabled by the power-on of the service FPGA, so that it outputs power to the RF transceiver. When the monitoring FPGA is configured to perform status monitoring, it is used to obtain the status analysis results reported by the service FPGA and report them to the satellite platform to realize remote management and control of the digital phased array; when the monitoring FPGA is configured to perform anomaly recovery, it is used to power off and restart the abnormal service FPGA through the second-level power supply timing. When the service FPGA is configured to perform status monitoring, it is used to acquire and parse multi-dimensional status information uploaded by the RF transceiver and ADC sampling module, generate status parsing results, and report them to the monitoring FPGA periodically. It is also used to independently control the power supply enable of each power supply switch, so as to achieve independent power supply for each RF transceiver channel in conjunction with each power supply switch. When the service FPGA is configured to perform anomaly recovery, it is used to power off and restart the RF transceiver channel that is abnormal for the first time by stopping the power supply switch that is enabled, and to disable and mark and isolate the RF transceiver channel that is abnormal again or fails to restart. It also uses the third-level power supply timing to power off and restart the abnormal RF transceiver. The radio frequency transceiver is used to monitor the power of the radio frequency receiving channel and complete the sampling of multi-channel S-band baseband signals, record the working mode and internal register status and upload them to the service FPGA; The ADC sampling module is used to collect status information of the RF transceiver channel, temperature telemetry values ​​of the T / R component, and status information of the core chip in the baseband processing unit, and upload the collection results to the service FPGA.

[0007] In one embodiment, the power-on of the baseband processing unit is controlled by an external OC command.

[0008] In one embodiment, the power networks of the monitoring FPGA, the service FPGA, and the RF transceiver within the baseband processing unit are powered by the baseband processing unit power supply bus. The power network of the monitoring FPGA only outputs power to the monitoring FPGA after receiving an external OC command to enable it. The multiplex power supply switch within the baseband processing unit is powered by the RF receive / transmit power supply bus. The baseband processing unit power supply bus and the RF receive / transmit power supply bus are independent of each other and do not affect each other.

[0009] In one embodiment, the multi-channel power supply switch is classified into an RF transmit channel power supply switch and an RF receive channel power supply switch; wherein, the RF transmit channel power supply switch is powered by the RF transmit channel power supply bus, and each RF transmit channel power supply switch independently controls the power supply of one RF transmit channel; the RF receive channel power supply switch is powered by the RF receive channel power supply bus, and each RF receive channel power supply switch independently controls the power supply of one RF receive channel.

[0010] In one embodiment, when the monitored FPGA is abnormal, the system is also configured to shut down the power supply of the baseband processing unit power supply bus to the power network of the monitored FPGA by an external OC command through the first-level power supply timing, and at the same time shut down the power supply of the RF receive / transmit power supply bus to the multiple power supply switch, and attempt to power off and restart. If the restart fails, the baseband processing unit is directly powered off to avoid affecting other baseband processing units or individual units on the satellite bus.

[0011] In one embodiment, the monitoring FPGA dynamically loads and refreshes the service FPGA through a refresh interface, and periodically obtains the status analysis results reported by the service FPGA; the monitoring FPGA also reports the obtained status analysis results to the satellite platform through a low-speed interface to realize remote control of the digital phased array.

[0012] In one embodiment, the service FPGA interacts with the RF transceiver and ADC sampling module via an SPI interface; The business FPGA is also used to receive the power telemetry value of the RF transmission channel uploaded by the ADC sampling module through the SPI interface, analyze the power telemetry value to obtain the health status of the corresponding RF transmission channel, and dynamically adjust the power of the corresponding RF transmission channel by combining the power telemetry value with the temperature telemetry value of the T / R component. When the RF transmission channel first becomes abnormal, the power supply enable of the corresponding power supply switch of the RF transmission channel is independently controlled to restart the RF transmission channel. When the RF transmission channel becomes abnormal again or fails to restart, the RF transmission channel is disabled and marked for isolation. The business FPGA is also used to receive the power of the RF receiving channel uploaded by the RF transceiver through the SPI interface, obtain the health status of the corresponding RF receiving channel through power analysis, and when the RF receiving channel first becomes abnormal, it independently controls the power supply enable of the power supply switch corresponding to the RF receiving channel to power off and restart the RF receiving channel. When the RF receiving channel becomes abnormal again or fails to restart, it disables and marks the RF receiving channel for isolation. The service FPGA also has the function of monitoring the status of each high-speed interface in the baseband processing unit, and uses registers to report the status information of the high-speed interface in real time for service allocation and scheduling.

[0013] In one embodiment, the radio frequency transceiver consists of one or more radio frequency transceiver chips, depending on the number of radio frequency channels in the T / R component.

[0014] In one embodiment, the ADC sampling module consists of multiple low-speed, multi-channel ADC chips, classified as a first ADC sampling module and a second ADC sampling module. The first ADC sampling module is used to collect the status information of the core chip in the baseband processing unit. The core chip includes a monitoring FPGA, a service FPGA, and an RF transceiver. The status information of the core chip includes the voltage, current, and temperature telemetry values ​​of the core chip. The second ADC sampling module is used to collect the status information of the RF transceiver channel and the temperature telemetry value of the T / R component. The status information of the RF transceiver channel includes the bus voltage / current of the RF transmit link, the bus voltage / current of the RF receive link, and the power telemetry value of the RF transmit channel.

[0015] In one embodiment, the monitoring FPGA is a FLASH FPGA, which is immune to single-particle interference.

[0016] The aforementioned digital phased array health management system firstly acquires multi-dimensional operating parameters of the digital phased array in real time using an ADC sampling module and an RF transceiver. The acquired data is then analyzed by the service FPGA and aggregated and reported to the satellite platform by the monitoring FPGA for remote online management on the satellite. In conjunction with independent controllable power supply switches for multiple channels, it achieves separate control of the RF transceiver channel hardware power supply. If a single channel experiences a device malfunction or single-event latch-up fault, the faulty transceiver channel can be individually powered off and restarted for recovery, without requiring a complete array shutdown. This device-level self-healing significantly improves the on-orbit anomaly recovery capabilities of the digital phased array. The primary recovery capability significantly improves the overall array reliability and channel fault tolerance redundancy. Secondly, the monitoring FPGA, service FPGA, and RF transceiver are equipped with independent power supply networks and follow a tiered power-on sequence, powering on in the order of "monitoring FPGA → service FPGA → RF transceiver," suppressing power-on surges at the source and avoiding device damage risks caused by timing errors. The mutually isolated multi-level power supply architecture allows for step-by-step fault location, troubleshooting, and single-point power-off isolation based on branch power supplies. Faults are confined to abnormal branches, preventing the spread of faults to other normal devices from the physical power supply level, providing hardware loop support for tiered handling of single-event latch-up faults. In summary, this system, by integrating real-time status monitoring, tiered fault handling, and hardware isolation power-off capabilities, constructs a full-lifecycle on-orbit health autonomous management system for digital phased arrays, achieving closed-loop health control throughout the entire process of early fault detection, on-site handling, and fault isolation. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the structure of a digital phased array working status health management system in one embodiment; Figure 2 This is a schematic diagram of the hierarchical power supply timing for the monitoring FPGA, service FPGA, and RF transceiver in one embodiment. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0019] In one embodiment, such as Figure 1 As shown, a digital phased array operational status health management system is provided. This system uses a baseband processing unit as its carrier and includes a monitoring FPGA, a service FPGA, an RF transceiver, an ADC sampling module, and a multi-channel power supply switch. The monitoring FPGA, service FPGA, and RF transceiver are independently powered and perform operations such as... Figure 2 The diagram illustrates a hierarchical power supply sequence. The first stage power supply sequence involves an external OC enabling the power network of the monitoring FPGA, causing it to supply power to the monitoring FPGA. The second stage power supply sequence involves the monitoring FPGA powering on and enabling the power network of the service FPGA, causing it to supply power to the service FPGA. The third stage power supply sequence involves the service FPGA powering on and enabling the power network of the RF transceiver, causing it to supply power to the RF transceiver. The third stage power supply sequence also applies to other peripheral chips such as the clock chip of the service FPGA and their corresponding power networks.

[0020] It should be understood that by having separate power networks for the monitoring FPGA, service FPGA, and RF transceiver, and adhering to a tiered power-on sequence, the monitoring FPGA can load its program and enable the service FPGA's power network after initial load (OC). Once the service FPGA has completed its normal loading, the power networks of peripheral clock chips, RF transceivers, and other peripheral devices are then sequentially enabled to complete the power-on initialization. This effectively reduces the impact on the power supply bus during power-on and avoids the risk of device damage caused by timing errors. Furthermore, the mutually isolated multi-level power supply architecture allows for step-by-step fault location, troubleshooting, and single-point power-off isolation based on branch power supplies. Faults are confined to abnormal branches, preventing the fault from spreading to other normal devices at the physical power supply level, and providing hardware loop support for tiered handling of single-event latch-up faults.

[0021] Combination Figure 1 The system structure shown is as follows: Figure 2 The hierarchical power supply timing shown in this application illustrates the specific functions of each component in a digital phased array operational health management system, including: When the monitoring FPGA is configured to perform status monitoring, it is used to obtain the status analysis results reported by the service FPGA and report them to the satellite platform to realize remote control of the digital phased array; when the monitoring FPGA is configured to perform anomaly recovery, it is used to power off and restart the abnormal service FPGA (due to single-event latch-up) through the second-level power supply timing.

[0022] It should be understood that by configuring the monitoring FPGA with dual working logic of status monitoring and anomaly recovery, on the one hand, the monitoring FPGA summarizes the status analysis results after the service FPGA is parsed and sends them to the satellite platform, thus establishing a data link for remote control between the satellite and the ground, and realizing remote visual monitoring of the digital phased array's operating status; on the other hand, with the help of the hierarchical power supply timing control link, the faulty service FPGA can be independently powered off and restarted, and the service FPGA can be restored locally without affecting the normal power supply and operation of other RF channels and peripheral devices. This balances the convenience of remote operation and maintenance of the array with the independence of fault handling, effectively improving the on-orbit fault self-healing capability of the digital phased array.

[0023] When the service FPGA is configured to perform status monitoring, it is used to acquire and parse multi-dimensional status information uploaded by the RF transceiver and ADC sampling module, generate status parsing results, and report them to the monitoring FPGA periodically. It is also used to independently control the power supply enable of each power supply switch to achieve independent power supply for each RF transceiver channel in conjunction with the power supply switches. When the service FPGA is configured to perform anomaly recovery, it is used to power off and restart the RF transceiver channel that is abnormal for the first time by stopping the power supply switch that is enabled, and to disable and mark and isolate the RF transceiver channel that is abnormal again or fails to restart. It also uses the third-level power supply timing to power off and restart the abnormal RF transceiver.

[0024] It should be understood that the business FPGA forms a closed-loop management and control link in the dual working modes of status monitoring and anomaly recovery. In the status monitoring stage, it can collect and analyze the multi-dimensional operating status data uploaded by the ADC sampling module and RF transceiver, and send the analysis results to the monitoring FPGA for aggregation and reporting to the satellite platform. At the same time, it can realize the power supply control of the RF transceiver channel by relying on the independent and controllable power supply switch of each channel. In the anomaly recovery stage, it can handle the fault in layers according to the severity of the fault. For the initial fault channel, the corresponding switching power supply is cut off to realize the single channel power-off restart. For channels with repeated faults or restart failures, the corresponding switching power supply is blocked, disabled and isolated by fault marking. It can also complete the power-off reset of the entire faulty RF transceiver by using the third-level hierarchical power supply timing. The layered and differentiated handling method can not only ensure the uninterrupted operation of the normal RF path, but also accurately complete the repair or physical isolation of the faulty channel, effectively reduce the scope of the fault, and improve the fault tolerance and autonomous repair performance of the digital phased array channel.

[0025] The radio frequency transceiver is used to monitor the power of the radio frequency receiving channel and complete the sampling of multi-channel S-band baseband signals, record the operating mode and internal register status, and upload them to the service FPGA.

[0026] It should be understood that the radio frequency transceiver is a bridge for converting between analog and digital signals and is a key component of digital beamforming technology. Relying on its own hardware acquisition capabilities, it collects radio frequency channel power in real time, completes S-band baseband signal sampling, and simultaneously stores device operating mode and register configuration information and uploads it to the service FPGA. This provides the service FPGA with raw measured data support for status analysis and fault identification, ensures the data integrity of phased array status monitoring, and lays the data foundation for subsequent accurate location of channel faults and implementation of graded power outage recovery.

[0027] The ADC sampling module is used to collect status information of the RF transceiver channel, temperature telemetry values ​​of the T / R component, and status information of the core chip in the baseband processing unit, and upload the collection results to the service FPGA.

[0028] It should be understood that the ADC sampling module is the core of realizing the health management of digital phased arrays. It can realize the full-domain acquisition of multiple status parameters of the core chips of RF transceiver channels, T / R components, and baseband processing units, and uniformly transmit various types of measured data such as temperature and hardware operating conditions back to the service FPGA. This fills the status data source beyond the acquisition dimension of RF transceivers, improves the data coverage of the entire link status monitoring of digital phased arrays, and facilitates the service FPGA to comprehensively analyze the causes of faults and accurately locate abnormal points. It also provides complete data basis for carrying out abnormal recovery operations such as channel power failure restart and fault isolation in a layered manner.

[0029] In summary, the aforementioned digital phased array operational health management system, on the one hand, utilizes an ADC sampling module and RF transceiver to collaboratively collect multi-dimensional operational data of the phased array. After parsing by the service FPGA, the data is uniformly transmitted back to the satellite platform by the monitoring FPGA, enabling remote payload control. Coupled with a branch-controlled power supply switch, it can independently shut down and restart faulty RF channels without requiring a complete array shutdown, effectively enhancing the equipment's on-orbit self-healing level and channel fault tolerance. On the other hand, the monitoring FPGA, service FPGA, and RF transceiver are independently powered and follow a step-by-step power-on sequence. This not only suppresses power-on surges and prevents device damage caused by timing errors, but also relies on an isolated power supply architecture to systematically troubleshoot and isolate faulty branches, preventing fault propagation across circuits and providing hardware support for graded single-event latch-up handling. In conclusion, this application integrates online status acquisition, layered fault repair, and hardware isolation power-off mechanisms to establish a closed-loop autonomous health management system for the entire on-orbit lifecycle of the digital phased array, achieving timely fault identification, on-site processing, and zoned isolation.

[0030] In one embodiment, the power-on of the baseband processing unit is controlled by an external OC command.

[0031] Among them, OC is a hardware switching circuit that cuts off the power supply circuit of the baseband processing unit by outputting a high-impedance state, thereby realizing hardware-level power failure recovery and avoiding the risk of damage to the chip inside the baseband processing unit caused by the large current of long-term single-event latch-up and the risk of chip function and performance degradation due to the cumulative effect of total dose.

[0032] In one embodiment, the power networks of the monitoring FPGA, the service FPGA, and the RF transceiver within the baseband processing unit are powered by the baseband processing unit power supply bus. The power network of the monitoring FPGA only outputs power to the monitoring FPGA after receiving an external OC command to enable it. The multiplex power supply switch within the baseband processing unit is powered by the RF receive / transmit power supply bus. The baseband processing unit power supply bus and the RF receive / transmit power supply bus are independent of each other and do not affect each other.

[0033] It should be understood that the baseband processing unit power supply bus and the RF receiving / transmitting power supply bus adopt a separate power distribution architecture. The two power supply links are electrically isolated and powered independently. When an electrical abnormality such as a short circuit or overcurrent occurs on either bus, it will not interfere with the other power supply line. This can avoid the baseband side fault from affecting the RF path or the RF fault from backflowing into the baseband processing unit. Fault isolation is achieved from the power supply head, further improving the power supply stability and fault tolerance of the entire phased array system.

[0034] In one embodiment, the multi-channel power supply switch is classified into an RF transmit channel power supply switch and an RF receive channel power supply switch; wherein, the RF transmit channel power supply switch is powered by the RF transmit channel power supply bus, and each RF transmit channel power supply switch independently controls the power supply of one RF transmit channel; the RF receive channel power supply switch is powered by the RF receive channel power supply bus, and each RF receive channel power supply switch independently controls the power supply of one RF receive channel.

[0035] It should be understood that each power supply switch corresponds to a radio frequency transceiver channel and has independent power distribution and control. This allows for the separate switching of power supply to a single faulty channel. When performing fault restart or channel blocking operations, the power supply to other normal transceiver channels will not be affected. This facilitates precise isolation of single-point faults and local self-healing, further enhancing the independent fault tolerance capability of the phased array channels.

[0036] In one embodiment, when the monitored FPGA is abnormal, the system is also configured to shut down the power supply of the baseband processing unit power supply bus to the power network of the monitored FPGA by an external OC command through the first-level power supply timing, and at the same time shut down the power supply of the RF receive / transmit power supply bus to the multiple power supply switch, and attempt to power off and restart. If the restart fails, the baseband processing unit is directly powered off to avoid affecting other baseband processing units or individual units on the satellite bus.

[0037] It should be understood that in extreme cases where the monitoring FPGA malfunctions, the system can rely on the first-level power supply sequence and external OC commands to simultaneously cut off the power supply from the baseband processing unit power supply bus to the monitoring FPGA power network and the power supply from the RF receiving / transmitting power supply bus to the power supply switches of each channel. The system can then attempt to repair the fault by powering down and then powering up the entire system. If the restart operation fails to eliminate the fault, the baseband processing unit will remain in a power-off and isolated state to prevent the fault from being transmitted through the satellite bus to other baseband units and onboard units connected to the same bus. This achieves fault isolation at the overall power supply level and improves the operational safety of the entire satellite payload.

[0038] In one embodiment, the monitoring FPGA dynamically loads and refreshes the service FPGA through a refresh interface, and periodically obtains the status analysis results reported by the service FPGA; the monitoring FPGA also reports the obtained status analysis results to the satellite platform through a low-speed interface to realize remote control of the digital phased array.

[0039] It should be understood that the data collected on the working status of the digital phased array is analyzed by the service FPGA, then summarized and reported to the satellite platform by the monitoring FPGA, and finally managed and scheduled by the satellite platform. This makes it easier for the platform to dynamically adjust the work tasks based on the health status, and improves the rationality of the overall array resource scheduling and the convenience of on-orbit operation and maintenance.

[0040] In one embodiment, the service FPGA interacts with the RF transceiver and ADC sampling module via an SPI (Serial Peripheral Interface) interface. The service FPGA also receives power telemetry values ​​of the RF transmit channel (TX) uploaded by the ADC sampling module via the SPI interface, analyzes these power telemetry values ​​to obtain the health status of the corresponding RF transmit channel, and dynamically adjusts the power of the corresponding RF transmit channel by combining the power telemetry values ​​with the temperature telemetry values ​​of the T / R components. When the RF transmit channel first experiences an anomaly, it independently controls the power supply enable of the corresponding power switch to restart the RF transmit channel. If the RF transmit channel experiences another anomaly or fails to restart, it then... The RF transmit channel is disabled and isolated by marking. The service FPGA is also used to receive the power of the RF receive channel (RX) uploaded by the RF transceiver through the SPI interface. The power analysis of the RF receive channel is used to obtain the health status of the corresponding RF receive channel. When the RF receive channel first becomes abnormal, the power supply enable of the corresponding power supply switch is independently controlled to restart the RF receive channel. When the RF receive channel becomes abnormal again or fails to restart, the RF receive channel is disabled and isolated by marking. The service FPGA also has the function of monitoring the status of each high-speed interface in the baseband processing unit. The status information of the high-speed interface is reported in real time through registers for service allocation and scheduling.

[0041] It should be understood that the business FPGA relies on power telemetry values ​​to analyze and obtain the health status of the corresponding RF transmit channels. It then dynamically adjusts the power of the corresponding RF transmit channels by combining power telemetry values ​​with temperature telemetry values ​​from the T / R components. The power of the RF receive channels uploaded via the SPI interface can dynamically compensate for the gain of the RF transmit channels, achieving more precise beam adjustment. Furthermore, by obtaining the power of the RF receive channels uploaded by the RF transceivers, the health status of the corresponding RF receive channels can be analyzed, enabling synchronous health diagnostics for both transmit and receive channels. Simultaneously, by controlling the hardware power supply of the RF transceiver channels, if a single channel experiences a device malfunction or single-event latch-up fault, the fault can be isolated, and the faulty transceiver channel can be individually powered off and restarted for recovery, without requiring a full array shutdown and avoiding impact on the operating status of other devices.

[0042] In one embodiment, the RF transceiver is composed of one or more RF transceiver chips depending on the number of RF channels in the T / R component, thereby adapting to phased array hardware layouts with different channel sizes and improving the flexibility of system hardware configuration and the versatility of the solution.

[0043] In one embodiment, the ADC sampling module consists of multiple low-speed, multi-channel ADC chips, classified into a first ADC sampling module and a second ADC sampling module. The first ADC sampling module is used to collect the status information of the core chip within the baseband processing unit. The core chip includes a monitoring FPGA, a service FPGA, and an RF transceiver. The status information of the core chip includes its voltage, current, and temperature telemetry values. The second ADC sampling module is used to collect the status information of the RF transceiver channel and the temperature telemetry values ​​of the T / R component. The status information of the RF transceiver channel includes the bus voltage / current of the RF transmit link (RF-TX), the bus voltage / current of the RF receive link (RF-RX), and the power telemetry values ​​of the RF transmit channel.

[0044] In one embodiment, the monitoring FPGA is a FLASH FPGA, which is immune to single-particle interference.

[0045] It should be understood that FLASH-type FPGAs, based on FLASH technology, store configuration data in internal FLASH cells, making them inherently immune to single-event upsets (SEE) and highly suitable for high-radiation environments such as spacecraft. Using a FLASH-type FPGA as the monitoring FPGA ensures reliable generation of mode-switching signals in aerospace environments, preventing erroneous commands due to SEE, thereby improving the reliability of the entire digital phased array health management system and enhancing its radiation resistance in complex aerospace environments.

[0046] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0047] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application.

Claims

1. A digital phased array operational status health management system, characterized in that, The system uses a baseband processing unit as its carrier and includes a monitoring FPGA, a service FPGA, an RF transceiver, an ADC sampling module, and a multi-channel power supply switch. The monitoring FPGA, service FPGA, and RF transceiver are independently powered and execute hierarchical power supply timing. The first-level power supply timing is achieved by an external OC enabling the power network of the monitoring FPGA, causing it to output power to the monitoring FPGA. The second-level power supply timing is achieved by the monitoring FPGA powering on and enabling the power network of the service FPGA, causing it to output power to the service FPGA. The third-level power supply timing is achieved by the service FPGA powering on and enabling the power network of the RF transceiver, causing it to output power to the RF transceiver. When the monitoring FPGA is configured to perform status monitoring, it is used to obtain the status analysis results reported by the service FPGA and report them to the satellite platform to realize remote management and control of the digital phased array; when the monitoring FPGA is configured to perform anomaly recovery, it is used to power off and restart the abnormal service FPGA through the second-level power supply timing. When the service FPGA is configured to perform status monitoring, it is used to acquire and parse the multi-dimensional status information uploaded by the RF transceiver and the ADC sampling module, generate status parsing results, and report them to the monitoring FPGA periodically. Simultaneously, it is used to independently control the power supply enable of each power supply switch, thereby enabling independent power supply to each RF transceiver channel in conjunction with the power supply switches. When the service FPGA is configured to perform anomaly recovery, it is used to power-off and restart the RF transceiver channel that experiences its first anomaly by stopping the corresponding power supply switch, and to disable and mark isolated RF transceiver channels that experience another anomaly or fail to restart. Furthermore, it uses the third-level power supply timing to power-off and restart the abnormal RF transceiver. The radio frequency transceiver is used to monitor the power of the radio frequency receiving channel and complete multi-channel S-band baseband signal sampling, record the working mode and internal register status and upload them to the service FPGA; The ADC sampling module is used to collect status information of the RF transceiver channel, temperature telemetry values ​​of the T / R component, and status information of the core chip in the baseband processing unit, and upload the collection results to the service FPGA.

2. The digital phased array working status health management system according to claim 1, characterized in that, The power-on of the baseband processing unit is controlled by an external OC command.

3. The digital phased array working status health management system according to claim 2, characterized in that, The power networks of the monitoring FPGA, the service FPGA, and the RF transceiver within the baseband processing unit are powered by the baseband processing unit power supply bus. The power network of the monitoring FPGA only outputs power to the monitoring FPGA after receiving an external OC command to enable it. The multiple power supply switch within the baseband processing unit is powered by the RF receive / transmit power supply bus. The baseband processing unit power supply bus and the RF receive / transmit power supply bus are independent of each other and do not affect each other.

4. The digital phased array operational status health management system according to claim 3, characterized in that, The multi-channel power supply switches are classified into RF transmit channel power supply switches and RF receive channel power supply switches. The RF transmit channel power supply switches are powered by the RF transmit channel power supply bus, and each RF transmit channel power supply switch independently controls the power supply of one RF transmit channel. The RF receive channel power supply switches are powered by the RF receive channel power supply bus, and each RF receive channel power supply switch independently controls the power supply of one RF receive channel.

5. The digital phased array operational status health management system according to claim 3, characterized in that, When the monitoring FPGA malfunctions, the system is also configured to shut down the power supply from the baseband processing unit power supply bus to the monitoring FPGA via an external OC command through the first-level power supply timing, and simultaneously shut down the power supply from the RF receive / transmit power supply bus to the multiple power supply switch, and attempt a power-off restart. If the restart fails, the baseband processing unit is directly powered off to avoid affecting other baseband processing units or individual units on the satellite bus.

6. The digital phased array working status health management system according to claim 1, characterized in that, The monitoring FPGA dynamically loads and refreshes the service FPGA through a refresh interface, and periodically acquires the status analysis results reported by the service FPGA. The monitoring FPGA also reports the acquired status analysis results to the satellite platform through a low-speed interface to achieve remote management and control of the digital phased array.

7. The digital phased array working status health management system according to claim 1, characterized in that, The service FPGA interacts with the RF transceiver and ADC sampling module via an SPI interface; The service FPGA is also used to receive the power telemetry value of the RF transmission channel uploaded by the ADC sampling module through the SPI interface, analyze the power telemetry value to obtain the health status of the corresponding RF transmission channel, and dynamically adjust the power of the corresponding RF transmission channel by combining the power telemetry value with the temperature telemetry value of the T / R component. When the RF transmission channel first becomes abnormal, the power supply enable of the corresponding power supply switch of the RF transmission channel is independently controlled to restart the RF transmission channel. When the RF transmission channel becomes abnormal again or fails to restart, the RF transmission channel is disabled and marked for isolation. The service FPGA is also used to receive the power of the RF receiving channel uploaded by the RF transceiver through the SPI interface, obtain the health status of the corresponding RF receiving channel through power analysis, and when the RF receiving channel first becomes abnormal, it independently controls the power supply enable of the power supply switch corresponding to the RF receiving channel to power off and restart the RF receiving channel. When the RF receiving channel becomes abnormal again or fails to restart, it disables and marks the RF receiving channel for isolation. The service FPGA also has the function of monitoring the status of each high-speed interface in the baseband processing unit, and performs service allocation and scheduling by reporting the status information of the high-speed interface in real time through registers.

8. The digital phased array working status health management system according to claim 1, characterized in that, The radio frequency transceiver is composed of one or more radio frequency transceiver chips, depending on the number of radio frequency channels in the T / R component.

9. The digital phased array working status health management system according to claim 1, characterized in that, The ADC sampling module consists of multiple low-speed, multi-channel ADC chips, and is classified into a first ADC sampling module and a second ADC sampling module. The first ADC sampling module is used to collect the status information of the core chip in the baseband processing unit. The core chip includes a monitoring FPGA, a service FPGA and an RF transceiver. The status information of the core chip includes the voltage, current and temperature telemetry values ​​of the core chip. The second ADC sampling module is used to collect the status information of the RF transceiver channel and the temperature telemetry value of the T / R component. The status information of the RF transceiver channel includes the bus voltage / current of the RF transmit link, the bus voltage / current of the RF receive link, and the power telemetry value of the RF transmit channel.

10. A digital phased array working status health management system according to claim 1, 3, 5, 6, or 9, characterized in that, The monitoring FPGA is a FLASH type FPGA, which is immune to single particles.

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