Voltage-time conversion circuit, analog-to-digital converter, chip and electronic device

Abstract

The application belongs to the field of electronic circuits, and provides a voltage-time conversion circuit, an analog-to-digital converter, a chip and an electronic device. The circuit comprises a sampling module, a linear voltage reduction module, a charging module, an acceleration module and a comparison module, the linear voltage reduction module is connected with the sampling module, the charging module, the acceleration module and the comparison module respectively, and the acceleration module is connected with the charging module and the comparison module respectively. The application introduces a linear voltage reduction stage between a sampling stage and a conversion stage: linear voltage reduction is performed on a sampling signal, so that the charging module, the acceleration module and the comparison module all work in a saturation region under full-swing input from rail to rail, the circuit has high linearity; meanwhile, the acceleration module is introduced in the conversion stage, so that "useless time" in the charging process of the input signal is greatly shortened, and the circuit enters a target conversion interval more quickly. Therefore, the voltage-time conversion circuit provided by the application can realize high voltage-time conversion speed and linearity when realizing high input swing.

Claims

1. A voltage-time conversion circuit, characterized in that, The system includes a sampling module, a linear buck module, a charging module, an acceleration module, and a comparison module. The linear buck module is connected to the sampling module, the charging module, the acceleration module, and the comparison module, respectively. The acceleration module is connected to the charging module and the comparison module, respectively. The sampling module is used to receive a first clock signal, the linear buck module is used to receive a second clock signal, and both the charging module and the acceleration module are used to receive a third clock signal. When the first clock signal is high, the second clock signal is low, and the third clock signal is high, the sampling module is used to sample the input signal to obtain the sampled signal. When the first clock signal is low, the second clock signal is high, and the third clock signal is high, the sampling module stops sampling; the linear buck module is used to linearly buck the sampled signal to obtain the first signal. When the first clock signal is low, the second clock signal is high, and the third clock signal is low, the sampling module stops sampling; the linear buck module continues to output the first signal; the charging module outputs a first charging current and mirrors the first charging current to the acceleration module; the acceleration module outputs a second charging current based on the first time signal, the second time signal, and the mirrored first charging current; the first charging current and the second charging current jointly charge the first signal; the comparison module outputs a first time signal and a second time signal based on the threshold voltage and the first signal; when the first time signal or the second time signal flips to a high level, the acceleration module stops working, and the charging module continues working until both the first time signal and the second time signal flip to a high level.

2. The voltage-time conversion circuit according to claim 1, characterized in that, The sampling module includes a first sampling unit and a second sampling unit; the linear buck module includes a first linear buck unit and a second linear buck unit; the charging module includes a first charging unit and a second charging unit; the acceleration module includes a first acceleration unit and a second acceleration unit; and the comparison module includes a first comparison unit and a second comparison unit. The first linear buck unit is connected to the first sampling unit, the first charging unit, the first acceleration unit, and the first comparison unit, respectively. The second linear buck unit is connected to the second sampling unit, the second charging unit, the second acceleration unit, and the second comparison unit, respectively. The first comparison unit is connected to the first acceleration unit and the second acceleration unit, respectively. The second comparison unit is connected to the first acceleration unit and the second acceleration unit, respectively. The acceleration unit is connected to the first charging unit, and the second acceleration unit is connected to the second charging unit. Both the first and second sampling units are used to receive a first clock signal, both the first and second linear buck units are used to receive a second clock signal, and the first, second, first, and second acceleration units are all used to receive a third clock signal. The input signal includes a first input sub-signal and a second input sub-signal. The first signal includes a first sub-signal and a second sub-signal. The sampling signal includes a first sampling sub-signal and a second sampling sub-signal. The first charging current includes a first charging sub-current and a second charging current. The second charging current includes a third charging sub-current and a fourth charging sub-current. When the first clock signal is high, the second clock signal is low, and the third clock signal is high, the first sampling unit is used to sample the first input sub-signal to obtain the first sampled sub-signal; the second sampling unit is used to sample the second input sub-signal to obtain the second sampled sub-signal. When the first clock signal is low, the second clock signal is high, and the third clock signal is high, the first sampling unit and the second sampling unit stop sampling; the first linear buck unit is used to linearly buck the first sampled sub-signal to obtain the first sub-signal; the second linear buck unit is used to linearly buck the second sampled sub-signal to obtain the second sub-signal; When the first clock signal is low, the second clock signal is high, and the third clock signal is low, the first sampling unit and the second sampling unit stop sampling; the first linear buck unit continues to output the first sub-signal; the second linear buck unit continues to output the second sub-signal; the first charging unit outputs the first charging sub-current and mirrors the first charging sub-current to the first accelerating unit; the second charging unit outputs the second charging sub-current and mirrors the second charging sub-current to the second accelerating unit; the first accelerating unit outputs the third charging sub-current based on the first time signal, the second time signal, and the mirrored first charging sub-current; the second accelerating unit outputs the third charging sub-current based on the first time signal, the second time signal, and the mirrored first charging sub-current; the second accelerating unit outputs the third charging sub-current based on the first time signal, the second time signal, and the mirrored first charging sub-current. The first charging current is output from the second charging current, the second time signal, and the mirrored second charging current; the first charging current and the third charging current jointly charge the first sub-signal; the second charging current and the fourth charging current jointly charge the second sub-signal; the first comparison unit is used to output a first time signal based on the threshold voltage and the first sub-signal; the second comparison unit is used to output a second time signal based on the threshold voltage and the second sub-signal; when the first time signal or the second time signal flips to a high level, the first acceleration unit and the second acceleration unit stop working, and the first charging unit and the second charging unit continue working until both the first time signal and the second time signal flip to a high level.

3. The voltage-time conversion circuit according to claim 2, characterized in that, The first acceleration unit includes a first transistor, a second transistor, a third transistor, and a first OR gate. The gate of the first transistor is connected to the first charging unit. The source of the first transistor receives a power supply voltage. The drain of the first transistor is connected to the source of the second transistor. The gate of the second transistor receives a first bias voltage. The drain of the second transistor is connected to the source of the third transistor. The gate of the third transistor is connected to the output of the first OR gate. The drain of the third transistor is connected to the first linear buck unit, the first charging unit, and the first comparator unit. The first input of the first OR gate is used to receive a third clock signal. The second input of the first OR gate is connected to the first comparator unit and the second acceleration unit. The third input of the first OR gate is connected to the second comparator unit and the second acceleration unit.

4. The voltage-time conversion circuit according to claim 2, characterized in that, The first sampling unit includes a first switch and a first capacitor. The first terminal of the first switch is used to receive a first input sub-signal. The second terminal of the first switch is connected to the upper plate of the first capacitor and the first linear buck unit, respectively. The control terminal of the first switch is used to receive a first clock signal. The lower plate of the first capacitor is grounded.

5. The voltage-time conversion circuit according to claim 2, characterized in that, The first linear buck unit includes a second switch and a second capacitor. The first end of the second switch is connected to the first sampling unit, and the second end of the second switch is connected to the upper plate of the second capacitor, the first charging unit, the first acceleration unit, and the first comparison unit, respectively. The control terminal of the second switch is used to receive a second clock signal, and the lower plate of the second capacitor is grounded.

6. The voltage-time conversion circuit according to claim 2, characterized in that, The first charging unit includes a fourth transistor, a fifth transistor, and a sixth transistor. The gate of the fourth transistor is connected to the drain of the fifth transistor, the source of the sixth transistor, and the first acceleration unit. The source of the fourth transistor receives a power supply voltage, the drain of the fourth transistor is connected to the source of the fifth transistor, the gate of the fifth transistor receives a first bias voltage, the gate of the sixth transistor receives a third clock signal, and the drain of the sixth transistor is connected to the first linear buck unit, the first acceleration unit, and the first comparator unit.

7. The voltage-time conversion circuit according to claim 2, characterized in that, The first comparison unit includes a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, and an eighteenth transistor. The sources of the seventh, fifteenth, sixteenth, and seventeenth transistors all receive a power supply voltage. The gate of the seventh transistor receives a second bias voltage. The drain of the seventh transistor is connected to the source of the eighth transistor. The drain of the eighth transistor is connected to the sources of the ninth and eleventh transistors, respectively. The gate of the ninth transistor is connected to the first linear buck unit, the first charging unit, and the first acceleration unit, respectively. The gate of the eleventh transistor receives a threshold voltage. The drain of the ninth transistor is connected to... The drain, gate, and gate of the tenth transistor are connected. The drain of the eleventh transistor is connected to the drain, gate, and gate of the twelfth transistor, respectively. The drain of the thirteenth transistor is connected to the drain, gate, and gate of the fifteenth transistor, respectively. The drain of the sixteenth transistor is connected to the drain, gate, and gate of the fourteenth transistor, respectively. The drain of the sixteenth transistor is connected to the drain, gate, and gate of the fourteenth transistor, respectively. The drain of the seventeenth transistor is connected to the drain of the eighteenth transistor, the first acceleration unit, and the second acceleration unit, respectively. The sources of the tenth, twelfth, thirteenth, fourteenth, and eighteenth transistors are all grounded.

8. An analog-to-digital converter, characterized in that, Includes the voltage-time conversion circuit according to any one of claims 1-7.

9. A chip, characterized in that, Includes the analog-to-digital converter as described in claim 8.

10. An electronic device, characterized in that, Includes the chip described in claim 9.

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