A duty cycle adjustment circuit that maintains a fixed delay on the rising edge

Abstract

The application relates to the technical field of integrated circuits, in particular to a duty cycle adjustment circuit capable of keeping the rising edge fixed delay. The duty cycle adjustment circuit comprises a first delay line module, a second delay line module, a logic operation unit, a first or logic operation unit and a multiplexer. The first input end and the second input end of the first delay line module are connected with a first delay control signal and an external input clock signal respectively, and the output of the first delay line module is a first delay clock signal. The first input end and the second input end of the second delay line module are connected with a second delay control signal and the external input clock signal respectively, and the output of the second delay line module is a second delay clock signal. The first input end and the second input end of the logic operation unit are connected with the first delay clock signal and the second delay clock signal respectively, and the output end of the logic operation unit is a clock and signal. The first input end and the second input end of the first or logic operation unit are connected with the first delay clock signal and the second delay clock signal respectively, and the output end of the first or logic operation unit is a clock or signal. The first input end and the second input end of the multiplexer are connected with the clock and signal and the clock or signal respectively, and the multiplexer is used for controlling the output of the clock and signal or the clock or signal according to a symbol bit signal. The application can accurately correct the duty cycle.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a duty cycle adjustment circuit that maintains a fixed rise time delay. Background Technology

[0002] In high-speed integrated circuit systems, dual-edge clock sampling architectures impose stringent requirements on the duty cycle accuracy of the clock signal, ideally maintaining a standard 50% duty cycle. However, in practical applications, the rising and falling edge transmission characteristics of devices such as clock buffers and transmission links are unbalanced. Furthermore, the delay differences introduced by long-distance wiring within the chip can cause the on-chip clock signal to deviate from the 50% duty cycle. This directly affects the sampling accuracy and system timing margin of the dual-edge sampling circuit, and may even lead to logic sampling errors, thus limiting the stability and reliability of the system under high-frequency operating conditions.

[0003] Existing duty cycle correction (DCC) circuits mostly employ a technique of generating narrow / wide pulse interpolation. This involves first generating a signal to be interpolated with a significantly different duty cycle from the input clock using a delay unit, and then interpolating the two to obtain a 50% duty cycle clock. However, in high-frequency clock scenarios, the clock period is drastically shortened, making it difficult for conventional circuits to generate ultra-narrow pulse interpolation signals that meet timing requirements. Furthermore, narrow pulse signals are susceptible to process variations and noise interference, leading to amplitude and timing instability, making high-precision duty cycle correction impossible. Simultaneously, they struggle to meet the core requirement of maintaining a fixed rise time delay, thus failing to adapt to the clock correction needs of high-frequency, highly integrated integrated circuits. Summary of the Invention

[0004] The purpose of this invention is to provide a duty cycle adjustment circuit that maintains a fixed rise time, so as to solve the problem that the above-mentioned technical path of generating narrow pulses / wide pulses for interpolation cannot achieve high-precision duty cycle correction.

[0005] According to the present invention, a duty cycle adjustment circuit that maintains a fixed delay of the rising edge is provided, the adjustment circuit comprising: The first delay line module has its first input terminal connected to a first delay control signal and an external input clock signal, respectively. The first delay line module is used to delay the external input clock signal according to the first delay control signal, and its output is the first delay clock signal.

[0006] The second delay line module has its first and second input terminals connected to the second delay control signal and the external input clock signal, respectively. The second delay line module is used to delay the external input clock signal according to the second delay control signal, and its output is the second delay clock signal.

[0007] The AND logic unit has its first and second input terminals connected to a first delayed clock signal and a second delayed clock signal, respectively, and its output terminal is a clock AND signal.

[0008] The first OR logic operation unit has its first input terminal and second input terminal connected to the first delayed clock signal and the second delayed clock signal, respectively, and its output terminal is a clock OR signal.

[0009] A multiplexer has its first and second inputs connected to a clock AND signal and a clock OR signal, respectively. The selection control terminal of the multiplexer is connected to a sign bit signal. The multiplexer is used to control the output clock AND signal or clock OR signal based on the sign bit signal.

[0010] Compared with the prior art, the present invention has at least the following beneficial effects: In this invention, the first delay line module and the second delay module constitute two independent delay lines. The input clock is delayed for different durations by the two independent delay lines, generating two clock signals with a time delay difference. The two signals are then fused through logical operations to obtain a clock with duty cycle correction. This avoids the technical bottleneck of the difficulty in generating and the instability of ultra-narrow pulses at high frequencies. It solves the problem that the existing technology of using narrow pulse / wide pulse interpolation cannot achieve high-precision duty cycle correction. It can achieve accurate correction of the duty cycle of high-frequency clocks (especially at the GHz level), with a correction accuracy of within ±1%, which is better than the correction accuracy of conventional circuits.

[0011] Furthermore, when the duty cycle of the external input clock signal is greater than the preset duty cycle threshold, the delay corresponding to the first delay control signal belongs to [0, t / 2), and the multiplexer outputs a clock and signal; when the duty cycle of the external input clock signal is less than the preset duty cycle threshold, the delay corresponding to the first delay control signal belongs to (t / 2, t], and the multiplexer outputs a clock and signal, while the delay corresponding to the second delay control signal is t / 2; thus, the rising edge of the obtained duty cycle corrected clock is always dominated by the single-path delay control signal (i.e., the second delay control signal), which can ensure that the rising edge timing is fixed at high frequencies, eliminate the influence of interpolation signal timing fluctuations on the rising edge in conventional circuits, and ensure the timing consistency of rising edge sampling in the dual-edge sampling system; at the same time, through the linkage of the sign bit signal and the first delay control signal, the duty cycle can be continuously adjusted bidirectionally, which can adapt to the clock duty cycle correction requirements in different scenarios, with fast adjustment response speed and no additional timing delay.

[0012] Furthermore, the present invention also includes an overflow detection module, which can monitor in real time whether the adjustment range exceeds the input pulse width limit and issue an alarm when the input pulse width limit is exceeded; thereby, the present invention avoids clock signal distortion caused by abnormal logic operation and improves circuit reliability and fault tolerance.

[0013] Moreover, the circuit structure of this invention adopts a modular design, containing only conventional components such as delay lines, basic logic gates, frequency dividers, and D flip-flops, without complex analog / digital mixed circuits. It is easy to integrate under CMOS technology, with small area overhead, and can adapt to the duty cycle correction requirements of scenarios such as chip internal clock trees and high-speed interfaces. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 A schematic diagram of a duty cycle adjustment circuit that maintains a fixed delay on the rising edge, provided in an embodiment of the present invention; Figure 2 A schematic diagram of the working waveform of the duty cycle adjustment circuit in the duty cycle reduction mode provided in an embodiment of the present invention; Figure 3 A schematic diagram of the working waveform of the duty cycle adjustment circuit in the duty cycle increase mode provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the overflow detection module provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of the working waveform of the overflow detection module provided in an embodiment of the present invention. Detailed Implementation

[0016] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0017] It should be noted that the terms "first," "second," etc., in the specification and claims of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0018] According to this embodiment, a duty cycle adjustment circuit that maintains a fixed rise time delay is provided, such as... Figure 1 As shown, the adjustment circuit includes: The first delay line module has its first input terminal connected to a first delay control signal and an external input clock signal, respectively. The first delay line module is used to delay the external input clock signal according to the first delay control signal, and its output is the first delay clock signal.

[0019] The second delay line module has its first and second input terminals connected to the second delay control signal and the external input clock signal, respectively. The second delay line module is used to delay the external input clock signal according to the second delay control signal, and its output is the second delay clock signal.

[0020] The AND logic unit has its first and second input terminals connected to a first delayed clock signal and a second delayed clock signal, respectively, and its output terminal is a clock AND signal.

[0021] The first OR logic operation unit has its first input terminal and second input terminal connected to the first delayed clock signal and the second delayed clock signal, respectively, and its output terminal is a clock OR signal.

[0022] A multiplexer has its first and second inputs connected to a clock AND signal and a clock OR signal, respectively. The selection control terminal of the multiplexer is connected to a sign bit signal. The multiplexer is used to control the output clock AND signal or clock OR signal based on the sign bit signal.

[0023] In this embodiment, the first delay line module and the second delay module constitute two independent delay lines. The input clock is delayed for different durations by the two independent delay lines, generating two clock signals with a time delay difference. The two signals are then fused through logic operations to obtain the clock with duty cycle correction. This avoids the technical bottleneck of the difficulty in generating and the instability of ultra-narrow pulses at high frequencies. It solves the problem that the existing technology of generating narrow pulses / wide pulses through interpolation cannot achieve high-precision duty cycle correction. It can achieve accurate correction of the duty cycle of high-frequency clocks (especially at the GHz level), with a correction accuracy of within ±1%, which is better than the correction accuracy of conventional circuits.

[0024] In this embodiment, when the duty cycle of the external input clock signal is greater than a preset duty cycle threshold, the sign bit signal is a first preset value, and the multiplexer outputs a clock AND signal; when the duty cycle of the external input clock signal is less than the preset duty cycle threshold, the sign bit signal is a second preset value, and the multiplexer outputs a clock OR signal. Optionally, the first preset value is 0, and the second preset value is 1. Optionally, the preset duty cycle threshold is 50%.

[0025] As a preferred embodiment, the delay range corresponding to the first delay control signal is [0, t], and the delay corresponding to the second delay control signal is t / 2, where t is the preset maximum delay.

[0026] As a specific implementation, when the duty cycle of the external input clock signal is greater than the preset duty cycle threshold, the delay corresponding to the first delay control signal belongs to [0, t / 2); when the duty cycle of the external input clock signal is less than the preset duty cycle threshold, the delay corresponding to the first delay control signal belongs to (t / 2, t).

[0027] In this embodiment, when the duty cycle of the external input clock signal is greater than the preset duty cycle threshold, the delay corresponding to the first delay control signal belongs to [0, t / 2), and the multiplexer outputs a clock and signal; when the duty cycle of the external input clock signal is less than the preset duty cycle threshold, the delay corresponding to the first delay control signal belongs to (t / 2, t], and the multiplexer outputs a clock and signal, while the delay corresponding to the second delay control signal is t / 2; thus, the rising edge of the obtained duty cycle corrected clock is always dominated by the single-path delay control signal (i.e., the second delay control signal), which can ensure that the rising edge timing is fixed at high frequencies, eliminate the influence of interpolation signal timing fluctuations on the rising edge in conventional circuits, and ensure the timing consistency of rising edge sampling in the dual-edge sampling system; at the same time, through the linkage of the sign bit signal and the first delay control signal, the duty cycle can be continuously adjusted bidirectionally, which can adapt to the clock duty cycle correction requirements in different scenarios, with fast adjustment response speed and no additional timing delay.

[0028] In this embodiment, the working principle of the duty cycle adjustment circuit is as follows: like Figure 2As shown, when the duty cycle of the external input clock signal is greater than the preset duty cycle threshold, the sign bit signal is 0, and the delay corresponding to the first delay control signal is less than the delay corresponding to the second delay control signal. That is, the rising edge of the first delayed clock signal (CLK_DLY1) obtained after the external input clock signal (CLK_IN) is delayed by the first delay line module is earlier than the rising edge of the second delayed clock signal (CLK_DLY2) obtained after the external input clock signal is delayed by the second delay line module. By performing a logical AND operation on CLK_DLY1 and CLK_DLY2, the corrected clock signal CLK_AND can be obtained. By adjusting the overlap range of the high-level regions of CLK_DLY1 and CLK_DLY2, the high-level duration of the CLK_AND signal can be changed, thereby adjusting the degree of reduction of the duty cycle of CLK_AND compared to the duty cycle of the external input clock signal. The rising edge of CLK_AND is determined by CLK_DLY2.

[0029] like Figure 3 As shown, when the duty cycle of the external input clock signal is less than the preset duty cycle threshold, the sign bit signal is 1, and the delay corresponding to the first delay control signal is greater than the delay corresponding to the second delay control signal. That is, the rising edge of the first delayed clock signal (CLK_DLY1) obtained after the external input clock signal is delayed by the first delay line module is later than the rising edge of the second delayed clock signal (CLK_DLY2) obtained after the external input clock signal is delayed by the second delay line module. By performing a logical OR operation on CLK_DLY1 and CLK_DLY2, the corrected clock signal CLK_OR can be obtained. By adjusting the delay difference between CLK_DLY1 and CLK_DLY2, the high-level duration of the CLK_OR signal can be changed, thereby adjusting the increase in the duty cycle of CLK_OR relative to the duty cycle of the external input clock signal. The rising edge of CLK_OR is determined by CLK_DLY2.

[0030] In a preferred embodiment, the adjustment circuit further includes an overflow detection module, which includes, for example: Figure 4 As shown: The first inverter has its input connected to the first delayed clock signal.

[0031] The first frequency divider unit has its input terminal connected to the output signal of the first inverter.

[0032] The first buffer has its input terminal being the output signal of the first frequency divider unit. In this embodiment, the first buffer includes at least one buffer, such as two buffers connected in series.

[0033] The second frequency divider unit has its input terminal connected to the second delayed clock signal.

[0034] The second inverter's input is connected to the output signal of the second divider unit.

[0035] The second buffer has its input connected to the output signal of the second inverter. In this embodiment, the second buffer has the same structure as the first buffer, and the second buffer includes at least one buffer, such as two buffers connected in series.

[0036] The second OR logic operation unit has its first and second input terminals connected to the output signals of the second inverter and the second buffer, respectively.

[0037] The D flip-flop unit has its data input connected to the output signal of the second OR logic unit, its clock input connected to the output signal of the first buffer, and its output used to output an overflow signal. When the overflow signal is high, an alarm is triggered.

[0038] In this embodiment, the overflow detection module works as follows: like Figure 5 As shown, CLK_DLY1 is sequentially inverted by the first inverter, down-clocked to half-cycle clock by the first divider unit (for easier timing comparison), and processed by the first buffer to obtain the signal CLK_DLY1_div2_buf; CLK_DLY2 is sequentially down-clocked to half-cycle clock by the second divider unit (for easier timing comparison), inverted by the second inverter, and processed by the second buffer to obtain the signal CLK_DLY2_div2_buf; then CLK_DLY2_div2_buf and the output signal CLK_DLY2_div2 of the second inverter are processed by the second OR logic operation. After performing an OR logic operation on the arithmetic unit, CLK_DLY2_div2_or is obtained. Finally, CLK_DLY2_div2_or and CLK_DLY1_div2_buf are input to the D trigger unit. The level state of CLK_DLY2_div2_or is sampled along the clock trigger edge using CLK_DLY1_div2_buf as the clock, resulting in the overflow signal OverFlow_Flag. If OverFlow_Flag=0, it means that the duty cycle adjustment range does not exceed the input pulse width, and the logic operation is normal. If OverFlow_Flag=1, it means that the adjustment range exceeds the limit, the logic operation will be abnormal, and an overflow alarm will be triggered.

[0039] In this embodiment, an overflow detection module is also included. This overflow detection module can monitor in real time whether the adjustment range exceeds the input pulse width limit and issue an alarm when the input pulse width limit is exceeded. Thus, this embodiment avoids clock signal distortion caused by abnormal logic operation and improves circuit reliability and fault tolerance.

[0040] In one specific implementation, when the duty cycle of the external input clock signal is greater than a preset duty cycle threshold, the sign bit signal is set to 0, the delay corresponding to the second delay control signal is fixed at t / 2, and the delay corresponding to the first delay control signal is increased from 0 according to a preset step size. If no overflow alarm occurs, it is gradually increased to t / 2. The first delay control signal corresponding to the signal whose duty cycle output from the multiplexer is closest to the preset duty cycle threshold during this process is determined as the optimal first delay control signal. This optimal first delay control signal is then selected as the first delay control signal for duty cycle correction of the external input clock signal. The preset step size affects the correction accuracy and correction duration. A smaller preset step size results in higher correction accuracy but a longer correction duration; a larger preset step size may not meet user requirements in terms of accuracy but results in a shorter correction duration. In practical applications, the preset step size can be set based on experience or test results.

[0041] If an overflow alarm occurs when the delay corresponding to the first delay control signal is 0, the delay corresponding to the first delay control signal is increased by a preset step size until the overflow alarm disappears. The delay corresponding to the first delay control signal when the overflow alarm disappears is defined as t0. The first delay control signal whose duty cycle is closest to the preset duty cycle threshold during the process of increasing the delay corresponding to the first delay control signal from t0 to t / 2 is defined as the optimal first delay control signal. This optimal first delay control signal is then selected as the first delay control signal for duty cycle correction of the external input clock signal.

[0042] In one specific implementation, when the duty cycle of the external input clock signal is less than a preset duty cycle threshold, the sign bit signal is set to 1, the delay corresponding to the second delay control signal is fixed at t / 2, and the delay corresponding to the first delay control signal is increased from t / 2 according to a preset step size. If no overflow alarm occurs, it is gradually increased to t. The first delay control signal corresponding to the signal whose duty cycle output by the multiplexer is closest to the preset duty cycle threshold during this process is determined as the optimal first delay control signal. This optimal first delay control signal is then determined as the first delay control signal selected when performing duty cycle correction on the external input clock signal.

[0043] If an overflow alarm occurs during the process of increasing the delay signal by a preset step size starting from t / 2, the increase is stopped, and the delay corresponding to the first delay control signal at the time of the overflow alarm is determined as t1. The first delay control signal corresponding to the signal whose duty cycle output by the multiplexer is closest to the preset duty cycle threshold during the process of increasing the delay signal corresponding to the first delay control signal from t / 2 to t1 is determined as the optimal first delay control signal. This optimal first delay control signal is then determined as the first delay control signal selected when performing duty cycle correction on the external input clock signal.

[0044] The circuit structure of this embodiment adopts a modular design, containing only conventional components such as delay lines, basic logic gates, frequency dividers, and D flip-flops. It does not have complex analog / digital mixed circuits, making it easy to integrate under CMOS technology. It also has a small area overhead and can adapt to the duty cycle correction requirements of scenarios such as chip internal clock trees and high-speed interfaces.

[0045] While specific embodiments of the invention have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. It should also be understood that various modifications can be made to the embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. A duty cycle adjustment circuit that maintains a fixed rise time delay, characterized in that, The regulating circuit includes: The first delay line module has its first input terminal connected to a first delay control signal and an external input clock signal, respectively. The first delay line module is used to delay the external input clock signal according to the first delay control signal, and the output of the first delay line module is the first delay clock signal. The second delay line module has its first input terminal connected to the second delay control signal and the external input clock signal, respectively. The second delay line module is used to delay the external input clock signal according to the second delay control signal, and the output of the second delay line module is the second delay clock signal. The AND logic unit has its first and second input terminals connected to a first delayed clock signal and a second delayed clock signal, respectively, and its output terminal is a clock AND signal. The first OR logic operation unit has its first input terminal and second input terminal connected to the first delayed clock signal and the second delayed clock signal, respectively, and its output terminal is a clock OR signal. A multiplexer has its first and second inputs connected to a clock AND signal and a clock OR signal, respectively. The selection control terminal of the multiplexer is connected to a sign bit signal. The multiplexer is used to control the output clock AND signal or clock OR signal based on the sign bit signal.

2. The duty cycle adjustment circuit with a fixed rise time delay according to claim 1, characterized in that, When the duty cycle of the external input clock signal is greater than the preset duty cycle threshold, the sign bit signal is the first preset value, and the multiplexer outputs a clock AND signal; when the duty cycle of the external input clock signal is less than the preset duty cycle threshold, the sign bit signal is the second preset value, and the multiplexer outputs a clock OR signal.

3. The duty cycle adjustment circuit with a fixed rise time delay according to claim 2, characterized in that, The delay range corresponding to the first delay control signal is [0, t], and the delay corresponding to the second delay control signal is t / 2, where t is the preset maximum delay.

4. The duty cycle adjustment circuit with a fixed rise time delay according to claim 3, characterized in that, When the duty cycle of the external input clock signal is greater than the preset duty cycle threshold, the delay corresponding to the first delay control signal belongs to [0, t / 2); when the duty cycle of the external input clock signal is less than the preset duty cycle threshold, the delay corresponding to the first delay control signal belongs to (t / 2, t).

5. The duty cycle adjustment circuit with a fixed rise time delay according to claim 1, characterized in that, The regulating circuit further includes an overflow detection module, which includes: The first inverter has its input connected to the first delayed clock signal. The first frequency divider unit has its input terminal connected to the output signal of the first inverter. The first buffer has its input terminal being the output signal of the first frequency divider unit. The second frequency divider unit has its input terminal connected to the second delayed clock signal; The second inverter is connected to the output signal of the second frequency divider unit. The second buffer has its input connected to the output signal of the second inverter. The second OR logic operation unit has its first and second input terminals connected to the output signal of the second inverter and the output signal of the second buffer, respectively. The D flip-flop unit has its data input connected to the output signal of the second OR logic unit, its clock input connected to the output signal of the first buffer, and its output used to output an overflow signal. When the overflow signal is high, an alarm is triggered.

6. The duty cycle adjustment circuit with a fixed rise time delay according to claim 1, characterized in that, The preset duty cycle threshold is 50%.

7. The duty cycle adjustment circuit with a fixed rise time delay according to claim 2, characterized in that, The first preset value is 0, and the second preset value is 1.

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