Apparatus for manufacturing cover window, method for manufacturing cover window, and electronic device including cover window

Abstract

Provided are an apparatus for manufacturing a cover window, a method for manufacturing a cover window, and an electronic device including a cover window. The apparatus for manufacturing a cover window includes a light source outputting an original laser beam, a beam splitter splitting the original laser beam into a main beam and at least one sub-beam, a first phase mask diffracting the main beam to convert the main beam into a straight beam, a second phase mask diffracting the sub-beam to convert the sub-beam into a dot-line beam including a plurality of dot beams, a beam combiner combining the main beam and the sub-beam to form a single combined beam, and an objective lens focusing the combined beam onto a focal plane, wherein the beam splitter sets extension directions of polarization axes of the main beam and the sub-beam to be different from each other.

Description

Technical Field

[0001] This disclosure relates to equipment for manufacturing cover windows, methods for manufacturing cover windows, and / or electronic devices including cover windows. Background Technology

[0002] With the advancement of the information society, the demand for display devices for displaying images in various ways is increasing. Display devices can be such as liquid crystal displays, field emission displays, or light-emitting displays. Light-emitting displays can include organic light-emitting display devices that use organic light-emitting diodes (OLEDs) as light-emitting elements, or inorganic light-emitting display devices that use inorganic light-emitting diodes (LEDs) as light-emitting elements.

[0003] To improve the mechanical strength of cover windows included in or attached to display devices, processes such as machining the side surfaces of the cover windows using computer numerical control (CNC) grinding equipment and performing wet etching are implemented. However, during CNC machining, defects such as wedge-shaped defects and / or chipping may occur on the side surfaces of the cover windows, leading to an increase in the manufacturing cost of the cover windows. Summary of the Invention

[0004] Some exemplary embodiments of this disclosure may provide equipment and / or methods for manufacturing cover windows, which can reduce manufacturing costs without substantially degrading mechanical strength.

[0005] Some example embodiments of this disclosure may provide electronic devices including cover windows that can reduce manufacturing costs without substantially degrading mechanical strength.

[0006] However, the exemplary embodiments of this disclosure are not limited to those set forth herein. The above and other exemplary embodiments of this disclosure will become more apparent to those skilled in the art to which this disclosure pertains from the following detailed description of the disclosure.

[0007] According to an example embodiment of this disclosure, an apparatus for manufacturing a cover window may include: a light source configured to output a raw laser beam; a beam splitter configured to split the raw laser beam into a main beam and at least one sub-beam; a first phase mask configured to diffract the main beam to convert the main beam into a straight beam; a second phase mask configured to diffract the sub-beams to convert the sub-beams into a dotted-line beam comprising a plurality of point beams; a beam combiner configured to combine the main beam and the sub-beams to form a single combined beam; and an objective lens configured to focus the combined beam onto a focal plane, wherein the beam splitter is configured to set the extension directions of the polarization axes of the main beam and the sub-beams to be different from each other.

[0008] In an example embodiment, the polarization axis of the main beam and the polarization axis of the sub-beam can be orthogonal to each other.

[0009] In an example embodiment, the device may also include an optical delayer between the beam splitter and the first phase mask or between the beam splitter and the second phase mask, wherein the optical delayer is configured to delay the time it takes for the main beam or sub-beam to arrive at the beam combiner.

[0010] In an example embodiment, the time delay of the optical retarder can range from 1 ps to 10 ps.

[0011] In an example embodiment, the first phase mask may have a shape in which concentric circles having the same single center are arranged radially, and the second phase mask may have a shape in which concentric circles having at least two different centers are arranged radially.

[0012] In an example embodiment, at least two centers of the second phase mask may include a first center and a second center, and a first set of concentric circles with the first center and a second set of concentric circles with the second center may be symmetrical to each other with respect to a first straight line extending in one direction.

[0013] In an example embodiment, the main beam and sub-beams, transformed by the first phase mask and the second phase mask respectively, can have Bessel beam shapes.

[0014] In an example embodiment, the original laser beam may be a Gaussian beam.

[0015] In the example embodiment, the numerical aperture of the objective lens may be 0.4 or greater.

[0016] In an example embodiment, the main beam and sub-beams may be spaced apart in a first direction in the focal plane.

[0017] In an example embodiment, the main beam and sub-beams may extend in a second direction different from the first direction in the focal plane.

[0018] In an example embodiment, the sub-beams may extend in a second direction and may include a plurality of point beams spaced apart from each other in the second direction.

[0019] In an example embodiment, in the second direction, the focal depth of the main beam can be greater than the focal depth of each of the plurality of point beams.

[0020] In an example embodiment, the width of the main beam in the first direction and the width of the sub-beam in the first direction can be 1 μm or less.

[0021] In an example embodiment, the aspect ratio of a sub-beam can be defined as the ratio of the depth of focus of the sub-beam in the second direction to the width of the sub-beam in the first direction, and the aspect ratio of the sub-beam can be 20 or greater.

[0022] In an example embodiment, the beam intensity of the sub-beam can be 30% to 80% of the beam intensity of the main beam.

[0023] According to an example embodiment of this disclosure, a method for manufacturing a cover window may include: forming a sketch line for forming the cover window by irradiating a mother glass with a laser beam; and etching the cover window using an etchant, wherein the sketch line includes a first sketch line and a second sketch line positioned inside the first sketch line, the cover window is separated from the mother glass through the first sketch line, and the etchant penetrates into the interior of the cover window through the second sketch line.

[0024] In the example embodiment, the first sketch line can penetrate the mother glass in the thickness direction, the second sketch line can extend from the top and bottom surfaces of the mother glass toward the interior of the mother glass, and the length of the second sketch line can be less than the thickness of the mother glass.

[0025] In an example embodiment, the sketch line may further include a third sketch line positioned inward from the second sketch line, and the length of the third sketch line may be less than the length of the second sketch line.

[0026] According to an example embodiment of this disclosure, the electronic device may include: a display device including a cover window manufactured by the cover window manufacturing equipment described above and a display panel located below the cover window; a processor configured to provide drive signals to the display device; and a power module configured to supply power to the display device.

[0027] According to the cover window manufacturing apparatus and / or cover window manufacturing method according to some example embodiments of the present disclosure, it is possible to manufacture cover windows that can reduce manufacturing costs without substantially degrading mechanical strength.

[0028] Electronic devices according to some example embodiments of this disclosure may include cover windows that can reduce manufacturing costs without substantially degrading mechanical strength.

[0029] It should be noted that the effects of this disclosure are not limited to those described above, and other effects of this disclosure will be apparent to those skilled in the art based on the following description. Attached Figure Description

[0030] The above and other aspects and features of this disclosure will become more apparent from the detailed description of some exemplary embodiments with reference to the accompanying drawings, in which: Figure 1 This is a schematic perspective view illustrating an electronic device according to an example embodiment; Figure 2 This is a perspective view showing a display device included in an electronic device according to an example embodiment; Figure 3 This is a block diagram illustrating a display device according to an example embodiment; Figure 4 This is an equivalent circuit diagram showing the pixels of a display device according to an example embodiment; Figure 5 and Figure 6 This is a cross-sectional view showing a display device according to some example embodiments; Figure 7 This is a cross-sectional view showing a display area of ​​a display device according to an example embodiment; Figure 8 This is a front perspective view of the cover window according to an example embodiment; Figure 9 This is a perspective view of the rear of the cover window according to an example embodiment; Figure 10 This is a plan view showing the cover window according to an example embodiment; Figure 11 It is along Figure 10 A cross-sectional view taken by line X1-X1'; Figure 12 This is a flowchart illustrating a method for manufacturing a cover window according to an example embodiment; Figure 13 and Figure 14 It is shown Figure 12 A three-dimensional diagram of the operation of S110; Figure 15 It is shown Figure 12 A cross-sectional view of operation S120; Figure 16 and Figure 17 It is shown Figure 12 A cross-sectional view of operation S110; Figure 18 yes Figure 15 A magnified view of region A; Figure 19 and Figure 20 This is a cross-sectional view showing operation S110 of the cover window manufacturing method according to an example embodiment; Figure 21 This is a cross-sectional view showing operation S120 of the cover window manufacturing method according to an example embodiment; Figure 22 This is a schematic side view showing a cover window manufacturing apparatus according to an example embodiment; Figure 23 It is a planar diagram showing the diffraction pattern of the first phase mask in the XY plane; Figure 24 This is a planar diagram showing the diffraction pattern of the second phase mask in the XY plane; Figure 25A It is a photograph showing the two-dimensional shapes of the main beam and sub-beams formed by the cover window manufacturing apparatus according to the example embodiment in the XY plane; Figure 25B It is a photograph showing the two-dimensional shapes of the main beam and sub-beams formed by the cover window manufacturing equipment according to the comparative example in the XY plane; Figure 26A This is a photograph showing the two-dimensional shapes of the main beam and sub-beams formed by the cover window manufacturing apparatus according to an example embodiment in the YZ plane; Figure 26B It is a photograph showing the two-dimensional shapes of the main beam and sub-beams formed by the cover window manufacturing equipment according to the comparative example in the YZ plane; Figure 27 It is a graph showing the beam intensity of the main beam and sub-beams according to the Z-axis position; Figure 28 This is a schematic diagram showing the sketch lines formed on the mother glass by the main beam and the sub-beams; Figure 29 This is a block diagram of an electronic device according to an example embodiment; and Figure 30 These are schematic diagrams of electronic devices according to various example embodiments. Detailed Implementation

[0031] The inventive concept will now be described more fully below with reference to the accompanying drawings, in which some exemplary embodiments of the inventive concept are illustrated. However, the inventive concept may be embodied in different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be comprehensive and complete, and will fully convey the scope of the inventive concept to those skilled in the art.

[0032] As used herein, expressions such as “one of…”, “one or more of…”, “any one of…”, “at least one of…”, and “selected from at least one of…” modify the entire list of elements when following a list of elements, without modifying any individual element in that list. Thus, for example, “at least one of A, B, and C” means any one of A, B, C, and any combination thereof. Similarly, A and / or B means A, B, or A and B.

[0033] Although the terms “identical,” “equal,” or “consistent” are used in the description of the example embodiments, it should be understood that some imprecision may exist. Therefore, when an element is described as identical to another element, it should be understood that the element is identical to the other element within the required manufacturing or operating tolerance range (e.g., ±10%).

[0034] When the terms “about,” “substantially,” or “approximately” are used in conjunction with numerical values ​​in this specification, it is intended that the associated numerical values ​​include manufacturing or operational tolerances (e.g., ±10%) around the stated values. Furthermore, when the terms “about,” “substantially,” or “approximately” are used in conjunction with geometry, it is intended not to require precision in the geometry, but rather to indicate tolerances for the shape within the scope of this disclosure. Moreover, whether a numerical value or shape is modified with “about” or “substantially,” it should be understood that these values ​​and shapes should be interpreted as including manufacturing or operational tolerances (e.g., ±10%) around the stated numerical values ​​or shapes.

[0035] It should also be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or an intervening layer may also be present. Throughout the specification, the same reference numerals denote the same components.

[0036] In the following, some exemplary embodiments of this disclosure will be described in detail with reference to the accompanying drawings.

[0037] Figure 1 This is a schematic perspective view illustrating an electronic device according to an example embodiment.

[0038] refer to Figure 1 Electronic device 1 displays moving or still images. Electronic device 1 can refer to any electronic device that provides a display screen. Examples of electronic device 1 may include televisions, laptops, monitors, billboards, Internet of Things devices, mobile phones, smartphones, tablet PCs, electronic watches, smartwatches, watch phones, head-mounted displays, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation devices, game consoles, digital cameras, camcorders, etc.

[0039] Electronic device 1 may include display device 10 that provides a display screen (see Figure 2 Examples of display devices may include inorganic light-emitting diode (LED) display devices, organic light-emitting diode (OLED) display devices, quantum dot (QD) light-emitting diode (OLED) display devices, plasma display devices, and field emission display devices. In the following description, the use of OLED display devices as display devices will be described as exemplary, but the exemplary embodiments of this disclosure are not limited thereto. In some exemplary embodiments, other display devices may be applied within the same technical spirit.

[0040] The shape of electronic device 1 can be modified in various ways. For example, electronic device 1 can have a shape such as a rectangle extending in the horizontal direction, a rectangle extending in the vertical direction, a square shape, a quadrilateral shape with rounded corners (vertices), other polygonal shapes, or a circular shape in a plan view. The shape of the display area DA of electronic device 1 can also be similar to the overall shape of electronic device 1. Figure 1 An electronic device 1 with a rectangular shape is shown, wherein the length in the second direction DR2 is longer than the length in the first direction DR1.

[0041] In the diagram shown, the first direction DR1 and the second direction DR2 intersect each other as horizontal directions. For example, the first direction DR1 and the second direction DR2 may be orthogonal to each other. Additionally, the third direction DR3 intersects the first direction DR1 and the second direction DR2, and may be, for example, a vertical direction orthogonal to the first direction DR1 and the second direction DR2. Unless otherwise defined, in this specification, the direction indicated by the arrows of the first direction DR1, the second direction DR2, and the third direction DR3 may be referred to as one side, and the opposite direction may be referred to as the other side. Furthermore, as used herein, the terms "above," "upper side," "upper part," "top," and "top surface" refer to the direction indicated by the arrows in the accompanying drawings on the third direction DR3, while the terms "below," "lower side," "lower part," "bottom," and "bottom surface" refer to the direction opposite to the direction indicated by the arrows on the third direction DR3, based on the accompanying drawings.

[0042] Electronic device 1 may include a display area DA and a non-display area NDA. The display area DA is the area capable of displaying an image, while the non-display area NDA is the area where no image is displayed. The display area DA may also be referred to as an active area, and the non-display area NDA may also be referred to as a non-active area. The display area DA may substantially occupy the center of electronic device 1. In other words, the display area DA may occupy the central area of ​​electronic device 1 and may be surrounded by the non-display area NDA.

[0043] Figure 2 This is a perspective view showing a display device included in an electronic device according to an example embodiment.

[0044] Apart from Figure 1 In addition, it also refers to Figure 2According to an example embodiment, the electronic device 1 may include a display device 10. The display device 10 can provide an image displayed by the electronic device 1. The display device 10 may have a planar shape similar to the shape of the electronic device 1. For example, the display device 10 may have a shape similar to a rectangle having a short side (e.g., a relatively short side) in a first direction DR1 and a long side (e.g., a relatively long side) in a second direction DR2. The edge where the short side in the first direction DR1 intersects the long side in the second direction DR2 may be rounded to have curvature, but is not limited thereto and may be formed as a right angle. The planar shape of the display device 10 is not limited to a quadrilateral shape, but may be formed as a shape similar to other polygonal shapes, circular shapes, or elliptical shapes.

[0045] The display device 10 may include a cover window CW, a display panel 100, a driving circuit 200, a circuit board 300, a touch driver 400, and a power supply unit (or alternatively, a power supply circuit) 500.

[0046] Display panel 100 may include a main area MA and a sub-area SBA.

[0047] The main area MA may include a display area DA and a non-display area NDA surrounding the display area DA. The display area DA includes pixels for displaying images. The display area DA may be located at the center of the main area MA, and the non-display area NDA may surround the display area DA. The display area DA may emit light from multiple emission areas or multiple aperture areas. For example, the display panel 100 may include pixel circuitry containing switching elements, a pixel defining film defining the emission area or aperture area, and self-emissive elements.

[0048] For example, a self-emissive element may include at least one of an organic light-emitting diode (LED) containing an organic light-emitting layer, a quantum dot LED containing a quantum dot light-emitting layer, an inorganic LED containing an inorganic semiconductor, and a micro LED, but is not limited thereto.

[0049] The non-display area NDA can be a region outside the display area DA. The non-display area NDA can be defined as the edge region of the main area MA of the display panel 100. The non-display area NDA may include a gate driver that supplies gate signals to the gate lines, and a fan-out line that connects the drive circuit 200 to the display area DA.

[0050] A sub-region SBA can be a region extending from one side of a main region MA. A sub-region SBA can include a flexible material capable of being bent, folded, or rolled. For example, when a sub-region SBA is bent, it can overlap with the main region MA in the thickness direction (e.g., third direction DR3). A sub-region SBA can include drive circuitry 200 and pads connected to a circuit board 300.

[0051] In another example embodiment, the sub-region SBA can be omitted, and the drive circuitry 200 and the pad portion can be located in the non-display area NDA. In this case, as will be described later... Figure 6 As shown, the circuit board 300 can be bent instead of the sub-region SBA.

[0052] The driving circuit 200 can output signals and voltages for driving the display panel 100. The driving circuit 200 can supply data voltage to the data lines. The driving circuit 200 can supply power voltage to the power lines and can supply gate control signals to the gate driver.

[0053] The driving circuit 200 can be formed as an integrated circuit (IC) and mounted on the display panel 100 by a chip-on-glass (COG) method, a chip-on-plastic (COP) method, or an ultrasonic bonding method. For example, the driving circuit 200 can be located in a sub-region SBA and can overlap with the main region MA in the thickness direction by bending the sub-region SBA. As another example, the driving circuit 200 can be mounted on a circuit board 300.

[0054] The circuit board 300 can be attached to the pad portion of the display panel 100 using an anisotropic conductive film (ACF). The leads of the circuit board 300 can be electrically connected to the pad portion of the display panel 100. The circuit board 300 can be a flexible printed circuit board, a rigid printed circuit board, or a flexible film such as a flip-chip film.

[0055] The touch driver 400 can be mounted on the circuit board 300. The touch driver 400 can be connected to the touch sensing unit (or alternatively, a touch sensor) of the display panel 100. The touch driver 400 can supply touch drive signals to multiple touch electrodes of the touch sensing unit and can sense changes in capacitance between the multiple touch electrodes. For example, the touch drive signal can be a pulse signal with a selected frequency. The touch driver 400 can calculate whether an input has occurred and the input coordinates based on the changes in capacitance between the multiple touch electrodes. The touch driver 400 can be formed as an integrated circuit (IC).

[0056] A power supply unit 500 may be located on circuit board 300 to supply power voltage to driving circuit 200 and display panel 100. The power supply unit 500 may generate a driving voltage to supply to a driving voltage line and a common voltage to supply to a common electrode. For example, the driving voltage may be a relatively high potential voltage for driving the light-emitting element, while the common voltage may be a relatively low potential voltage for driving the light-emitting element. The power supply unit 500 may generate an initialization voltage to supply to an initialization voltage line, a reference voltage to supply to a reference voltage line, a bias voltage to supply to a bias voltage line, and a reset voltage to supply to a reset voltage line.

[0057] A cover window (CW) can be positioned on the front surface of the display panel 100 to protect the front surface of the display panel 100 from external impacts. The cover window (CW) can include a transparent material. For example, the cover window (CW) can be glass. In this case, to give the cover window (CW) foldable and flexible properties, the cover window (CW) can be ultra-thin glass (UTG) with a thickness of approximately 500 μm or less.

[0058] Figure 3 This is a block diagram illustrating a display device according to an example embodiment.

[0059] refer to Figure 3 The display device 10 according to the example embodiment may include a display panel 100, a scanning drive circuit unit SDC, a drive circuit 200, and a power supply unit 500.

[0060] The display panel 100 includes data lines DL, scan lines SL, and pixels PX. The scan lines SL can extend in a first direction DR1 and can be arranged in a second direction DR2. The data lines DL can extend in the second direction DR2 and can be arranged along the first direction DR1.

[0061] Each pixel PX can be connected to at least one data line DL and at least one scan line SL. For example... Figure 4 As shown, each of the pixels PX may include a light-emitting element LE (see...) Figure 4 ) and includes components for feeding light-emitting elements (LE) (see Figure 4 The pixel circuit section PXC (see also) supplies drive current to multiple transistors. Figure 4 (See below for reference) Figure 4 Provide a detailed description of pixel PX.

[0062] The scan drive circuit unit SDC and the drive circuit 200 can be referred to as a display panel driver. The drive circuit 200 may include a timing control circuit unit (or alternatively, a timing control circuit or timing controller) TIC and a data drive circuit unit (or alternatively, a data drive circuit) DIC.

[0063] The scan drive circuit unit SDC is connected to the scan line SL and applies a scan signal to the scan line SL. The scan drive circuit unit SDC can generate a scan signal based on the scan timing control signal SCS input from the timing control circuit unit TIC, and output the scan signal to the scan line SL.

[0064] The scan drive circuit unit SDC may include multiple transistors. In some example embodiments, the scan drive circuit unit SDC may be located in the non-display area NDA on the left side of the display panel 100. However, the example embodiments of this disclosure are not limited thereto, and the scan drive circuit unit SDC may be located in the non-display area NDA on the right side of the display panel 100 or on both the left and right sides.

[0065] The data drive circuit unit (DIC) is connected to the data line DL and supplies data voltage to the data line DL. The DIC can receive digital video data DATA and data timing control signals (DCS) from the timing control circuit unit (TIC). The DIC can convert the digital video data DATA into data voltage according to the data timing control signals (DCS) and output the data voltage to the data line DL.

[0066] The timing control circuit unit (TIC) can receive digital video data (DATA) and timing signals (TS). Timing signals (TS) may include vertical synchronization signals, horizontal synchronization signals, data enable signals, and clock signals such as dot clocks.

[0067] The timing control circuit unit (TIC) can generate control signals for controlling the operating timing of the data drive circuit unit (DIC) and the scan drive circuit unit (SDC). These control signals may include a data timing control signal (DCS) for controlling the operating timing of the data drive circuit unit (DIC) and a scan timing control signal (SCS) for controlling the operating timing of the scan drive circuit unit (SDC).

[0068] The timing control circuit unit TIC can output digital video data DATA and data timing control signal DCS to the data drive circuit unit DIC, and output scan timing control signal SCS to the scan drive circuit unit SDC.

[0069] The power supply unit 500 can generate a first power supply voltage VSS corresponding to a relatively low potential voltage and a second power supply voltage VDD corresponding to a relatively high potential voltage, based on the main power supply applied from the outside. Furthermore, the power supply unit 500 can supply various drive voltages to the data drive circuit unit DIC, the scan drive circuit unit SDC, and the timing control circuit unit TIC.

[0070] Figure 4 This is an equivalent circuit diagram showing the pixels of a display device according to an example embodiment.

[0071] refer to Figure 4 According to the example embodiment, a pixel PX may include a pixel circuit section PXC and a light-emitting element LE.

[0072] The light-emitting element (LE) emits light according to the driving current Ids. The emission amount of the light-emitting element (LE) can be proportional to the driving current Ids.

[0073] The light-emitting element LE can be an organic light-emitting element, which includes an anode electrode, a cathode electrode, and an organic light-emitting layer located between the anode electrode and the cathode electrode. In some example embodiments, the light-emitting element LE can be an inorganic light-emitting element, which includes an anode electrode, a cathode electrode, and an inorganic semiconductor located between the anode electrode and the cathode electrode.

[0074] The anode of the light-emitting element LE can be connected to the first electrode of the fourth transistor ST4 and the second electrode of the sixth transistor ST6, and its cathode can be connected to the first power line VSL. A parasitic capacitance Cel can be formed between the anode and cathode of the light-emitting element LE.

[0075] The pixel circuit section PXC includes a driving transistor DT, switching elements, and a capacitor C1. The switching elements include a first transistor ST1, a second transistor ST2, a third transistor ST3, a fourth transistor ST4, a fifth transistor ST5, and a sixth transistor ST6. The first transistor ST1 may include two sub-transistors ST1-1 and ST1-2. The third transistor ST3 may include two sub-transistors ST3-1 and ST3-2. The scan line SL may include a write scan line GWL, a gate initialization scan line GIL, and an anode initialization scan line GCL. The gate electrode of each of the fifth transistor ST5 and the sixth transistor ST6 is connected to the emitter control line EL.

[0076] The driving transistor DT includes a gate electrode, a first electrode, and a second electrode. The driving transistor DT controls the driving current flowing between the first electrode and the second electrode based on the data voltage applied to the gate electrode.

[0077] Capacitor C1 is formed between the gate electrode of the driving transistor DT and the second power supply line VDL. One electrode of capacitor C1 can be connected to the gate electrode of the driving transistor DT, while the other electrode of capacitor C1 can be connected to the second power supply line VDL.

[0078] When the first electrode of the driving transistor DT and each of the first transistors ST1 to ST6 is a source electrode, its second electrode can be a drain electrode. Alternatively, when the first electrode of the driving transistor DT and each of the first transistors ST1 to ST6 is a drain electrode, its second electrode can be a source electrode.

[0079] The active layer of each of the driving transistor DT and the first transistor ST1 to the sixth transistor ST6 may include any one of polycrystalline silicon, amorphous silicon, and oxide semiconductor. When the semiconductor layer of each of the driving transistor DT and the first transistor ST1 to the sixth transistor ST6 includes polycrystalline silicon, the process used to form the semiconductor layer may be a low-temperature polycrystalline silicon (LTPS) process.

[0080] In addition, Figure 4 In this disclosure, the driving transistor DT and the first transistors ST1 to ST6 are described as being formed as p-type metal-oxide-semiconductor field-effect transistors (MOSFETs), but the exemplary embodiments of this disclosure are not limited thereto. In some exemplary embodiments, the driving transistor DT and the first transistors ST1 to ST6 may be formed as n-type MOSFETs.

[0081] In addition, the first power supply voltage VSS of the first power supply line VSL (see...) Figure 3 ), the second power supply voltage VDD of the second power supply line VDL (see Figure 3 The third power supply voltage (or initialization voltage) of the third power supply line VIL can be set by taking into account the characteristics of the driving transistor DT, the characteristics of the light-emitting element LE, etc.

[0082] Pixel PX according to an exemplary embodiment of this disclosure (see also...) Figure 3 (Not limited to) Figure 4 The pixels shown. In addition to the pixels PX according to some exemplary embodiments of this disclosure. Figure 4 In addition to the embodiments shown, other known circuit structures that can be employed by those skilled in the art may also be used.

[0083] Figure 5 and Figure 6 This is a cross-sectional view showing a display device according to some example embodiments. Figure 5 The diagram shows the unfolded state of circuit board 300, and... Figure 6 The circuit board 300 is shown in a bent state.

[0084] refer to Figure 5 and Figure 6 According to some example embodiments, the display device 10 may include a display panel 100, a polarizing film PF, a cover window CW, and a lower cover PB. The display panel 100 may include a substrate SUB, a display layer DISL, an encapsulation layer ENC, and a sensor electrode layer SENL.

[0085] The substrate SUB can be a stretchable, flexible substrate. The substrate SUB can include an insulating material. For example, the substrate SUB can include polymeric resins such as acrylic resins, epoxy resins, phenolic resins, polyamide resins, or polyimide resins.

[0086] In another example embodiment, the substrate SUB can be made of a relatively rigid material. For example, the substrate SUB can include glass. The substrate SUB can include ultrathin glass (UTG) having a thickness of about 500 μm or less. For example, the thickness of the substrate SUB can be about 200 μm.

[0087] The display layer DISL can be located on the first surface of the substrate SUB. The display layer DISL can be a layer for displaying images. The display layer DISL may include a thin-film transistor layer (TFTL) in which thin-film transistors are formed (see [link to DISL]). Figure 7 ) and the light-emitting element located in the light-emitting region in the light-emitting element layer EML (see Figure 7 ).

[0088] In the display area DA of the display layer DISL (see...) Figure 2 Within this area, scan lines, data lines, power lines, etc., used for emitting light in the emission area can be located. In the non-display area NDA of the display layer DISL (see...),... Figure 2 In the ), the scanning drive circuit unit that outputs scanning signals to the scan line, the fan-out line that connects the data line and the drive circuit 200 can be located.

[0089] The encapsulation layer ENC can be a layer used to encapsulate the light-emitting element layer (EML) of the display layer (DISL) to reduce or prevent oxygen or moisture penetration into the EML of the display layer (DISL). The encapsulation layer ENC can be located on the display layer (DISL). The encapsulation layer ENC can be located on the top surface and side surface of the display layer (DISL). The encapsulation layer ENC can be positioned to cover the display layer (DISL).

[0090] The sensor electrode layer (SENL) can be located on the display layer (DISL). The SENL can include sensor electrodes. The SENL can use these sensor electrodes to sense the user's touch.

[0091] A polarizing film PF can be positioned on the display panel 100 to reduce or prevent a decrease in the visibility of the image displayed on the display panel 100 due to reflection of external light from the display panel 100. The polarizing film PF may include a first base component, a linear polarizer, a phase retardation film such as a quarter-wave plate (λ / 4), and a second base component. The first base component, the phase retardation film, the linear polarizer, and the second base component of the polarizing film PF may be sequentially stacked on the display panel 100.

[0092] In another example embodiment, an optical layer including color filters instead of a polarizing film PF can be positioned between the display panel 100 and the cover window CW. The optical layer may include multiple color filters to reduce or prevent a decrease in the visibility of the image displayed on the display panel 100 due to reflection of external light from the display panel 100.

[0093] The cover window (CW) can be located on the polarizing film (PF). The cover window (CW) can be attached to the polarizing film (PF) using a transparent adhesive component such as an optically clear adhesive (OCA) film or an optically clear resin (OCR).

[0094] The lower panel cover PB can be located on the second surface of the substrate SUB of the display panel 100. The second surface of the substrate SUB can be the surface opposite to the first surface. The lower panel cover PB can be attached to the second surface of the substrate SUB of the display panel 100 by an adhesive member. The adhesive member can be a pressure-sensitive adhesive (PSA).

[0095] The panel bottom cover PB may include at least one of a light-blocking member for absorbing light incident from the outside, a buffer member for absorbing impacts from the outside, and a heat dissipation member for effectively dissipating heat from the display panel 100.

[0096] A light-blocking component may be located below the display panel 100. The light-blocking component blocks light transmission, thereby reducing or preventing the observation of components (e.g., circuit board 300, etc.) located below the light-blocking component from the top of the display panel 100. The light-blocking component may include a light-absorbing material, such as black pigment, black dye, etc.

[0097] The buffer member can be located below the light-blocking member. The buffer member absorbs external impacts to reduce or prevent damage to the display panel 100. The buffer member can be formed as a single layer or multiple layers. For example, the buffer member can include polymer resins such as polyurethane (PU), polycarbonate (PC), polypropylene (PP), or polyethylene (PE), or can include elastic materials such as foam sponges obtained from rubber, urethane-based materials, or acrylic materials.

[0098] The heat dissipation component may be located below the buffer component. The heat dissipation component may include a first heat dissipation layer comprising graphite, carbon nanotubes, etc., and a second heat dissipation layer formed as a metal thin film capable of shielding electromagnetic waves and having excellent or relatively high thermal conductivity, the metal thin film comprising, for example, copper, nickel, ferrite, or silver.

[0099] The circuit board 300 can be bent toward the bottom of the display panel 100, such as... Figure 6 As shown in the diagram, the circuit board 300 can be attached to the bottom surface of the panel cover PB via an adhesive member 310. The adhesive member 310 can be a pressure-sensitive adhesive.

[0100] Figure 7 This is a cross-sectional view showing a display area of ​​a display device according to an example embodiment.

[0101] refer to Figure 7 According to the example embodiment, the display panel 100 (see Figure 5 It can be an organic light-emitting display panel having light-emitting elements LE including an organic light-emitting layer.

[0102] The above has been referenced Figure 5 and Figure 6 The substrate SUB is described, and therefore its description will be omitted.

[0103] The display layer DISL may include a thin film transistor layer TFTL containing multiple thin film transistors (TFTs) and a light-emitting element layer EML containing multiple light-emitting elements (LEs).

[0104] The thin-film transistor layer (TFTL) may include a first buffer film (BF1), an active layer, a gate insulating film (130), a first gate metal layer, a first interlayer insulating film (141), a second gate metal layer, a second interlayer insulating film (142), a first data metal layer, a first organic film (160), a second data metal layer, and a second organic film (180). The TFTL may also include thin-film transistors (TFTs) and capacitors (Cst).

[0105] The first buffer film BF1 may be located on the substrate SUB. The first buffer film BF1 may include an inorganic film, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. In some example embodiments, the first buffer film BF1 may be formed as a multilayer in which multiple layers selected from silicon nitride layers, silicon oxynitride layers, silicon oxide layers, titanium oxide layers, and aluminum oxide layers are alternately stacked.

[0106] The active layer, including the channel region TCH, source region TS, and drain region TD of the thin-film transistor (TFT), can be located on the first buffer film BF1. The active layer can include polycrystalline silicon, monocrystalline silicon, low-temperature polycrystalline silicon, amorphous silicon, or oxide semiconductor materials. When the active layer includes polycrystalline silicon or oxide semiconductor materials, the source region TS and drain region TD of the active layer can be conductive regions doped with ions or impurities and possessing conductivity.

[0107] The gate insulating film 130 may be located on the active layer of the thin-film transistor (TFT). The gate insulating film 130 may be formed as or include an inorganic film such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0108] The gate electrode TG of the thin-film transistor TFT, the first capacitor electrode CAE1 of the capacitor Cst, and the first gate metal layer of the scan line can be located on the gate insulating film 130. The gate electrode TG of the thin-film transistor TFT can overlap with the channel region TCH on the third-direction DR3. The first gate metal layer can be formed as a single layer or multiple layers containing any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and their alloys.

[0109] The first interlayer insulating film 141 may be located on the first gate metal layer. The first interlayer insulating film 141 may be formed as an inorganic film, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The first interlayer insulating film 141 may include multiple inorganic films.

[0110] The second gate metal layer, including the second capacitor electrode CAE2 of capacitor Cst, can be located on the first interlayer insulating film 141. The second capacitor electrode CAE2 can overlap with the first capacitor electrode CAE1 on the third-direction DR3. Therefore, capacitor Cst can be formed by the first capacitor electrode CAE1, the second capacitor electrode CAE2, and an inorganic insulating dielectric film (e.g., the first interlayer insulating film 141) located between the first capacitor electrode CAE1 and the second capacitor electrode CAE2 to serve as a dielectric film. The second gate metal layer can be formed as a single layer or multiple layers containing any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and their alloys.

[0111] The second interlayer insulating film 142 may be located on the second gate metal layer. The second interlayer insulating film 142 may be formed as an inorganic film, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The second interlayer insulating film 142 may include multiple inorganic films.

[0112] The first data metal layer, including the first connection electrode CE1 and the data line, can be located on the second interlayer insulating film 142. The first connection electrode CE1 can be connected to the drain region TD through a first contact hole CT1 that penetrates the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142. The first data metal layer can be formed as a single layer or multiple layers containing any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and their alloys.

[0113] The first organic film 160 for planarizing the steps caused by the thin-film transistor (TFT) can be located on the first connection electrode CE1. The first organic film 160 can be formed as or include an organic film containing, for example, acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0114] The second data metal layer, including the second connecting electrode CE2, can be located on the first organic film 160. The second data metal layer can be connected to the first connecting electrode CE1 through the second contact hole CT2 penetrating the first organic film 160. The second data metal layer can be formed as a single layer or multiple layers containing any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and their alloys.

[0115] The second organic film 180 may be located on the second connecting electrode CE2. The second organic film 180 may be formed as an organic film containing materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0116] The light-emitting element layer (EML) is located on the thin-film transistor layer (TFTL). The EML may include a light-emitting element (LE) and a diaphragm (190).

[0117] Each of the light-emitting elements LE may include a pixel electrode 171, a light-emitting layer 172, and a common electrode 173. Each of the emitting regions EA is a region in which the pixel electrode 171, the light-emitting layer 172, and the common electrode 173 are sequentially stacked such that holes from the pixel electrode 171 and electrons from the common electrode 173 recombine with each other to emit light. In this case, the pixel electrode 171 may be an anode electrode, and the common electrode 173 may be a cathode electrode.

[0118] A pixel electrode layer, including pixel electrode 171, can be formed on the second organic film 180. Pixel electrode 171 can be connected to the second connection electrode CE2 through a third contact hole CT3 penetrating the second organic film 180. The pixel electrode layer can be formed as a single layer or multiple layers containing any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and their alloys.

[0119] In the top-emitting structure that emits light toward the common electrode 173 relative to the light-emitting layer 172, the pixel electrode 171 can be formed as a single layer of molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al), or it can be formed as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, or a stacked structure of APC alloy and ITO (ITO / APC / ITO) to increase reflectivity. The APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0120] The dam 190 is used to define the emission region EA of a pixel. For example, the dam 190 can be formed as a portion of the pixel electrode 171 exposed on the second organic film 180. The dam 190 can cover the edge of the pixel electrode 171. The dam 190 can be located in the third contact hole CT3. That is, the third contact hole CT3 can be filled with the dam 190. The dam 190 can be formed as or include an organic film containing, for example, acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0121] Spacer 191 may be located on dam 190. Spacer 191 may be used to support the mask during the process of manufacturing the light-emitting layer 172. Spacer 191 may be formed as or comprise an organic film containing, for example, acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0122] A light-emitting layer 172 is formed on the pixel electrode 171. The light-emitting layer 172 may include an organic material to emit light of a selected color. For example, the light-emitting layer 172 may include a hole transport layer, an organic material layer, and an electron transport layer. The organic material layer may include a host and a dopant. The organic material layer may include a material that emits selected light and may be formed using phosphorescent or fluorescent materials.

[0123] A common electrode 173 is formed on the light-emitting layer 172. The common electrode 173 may be formed to cover the light-emitting layer 172. The common electrode 173 may be a common layer formed in the emission region EA. A capping layer may be formed on the common electrode 173.

[0124] In the top-emitting structure, the common electrode 173 may include a transparent conductive material (TCO) capable of transmitting light, such as ITO or IZO, or a semi-transmissive conductive material, such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the common electrode 173 includes a semi-transmissive conductive material, the light emission efficiency can be improved due to the microcavity effect.

[0125] An encapsulation layer ENC can be formed on the light-emitting element layer EML. The encapsulation layer ENC may include at least one inorganic film TFE1 and TFE2 to reduce or prevent oxygen or moisture penetration into the light-emitting element layer EML. Furthermore, the encapsulation layer ENC may include at least one organic film to protect the light-emitting element layer EML from foreign matter such as dust. For example, the encapsulation layer ENC may include a first encapsulation inorganic film TFE1, an encapsulation organic film TFE2, and a second encapsulation inorganic film TFE3.

[0126] A first encapsulating inorganic film TFE1 may be located on the common electrode 173, an encapsulating organic film TFE2 may be located on the first encapsulating inorganic film TFE1, and a second encapsulating inorganic film TFE3 may be located on the encapsulating organic film TFE2. The first encapsulating inorganic film TFE1 and the second encapsulating inorganic film TFE3 may be formed as a multilayer film in which one or more inorganic films selected from silicon nitride layers, silicon oxynitride layers, silicon oxide layers, titanium oxide layers, and aluminum oxide layers are alternately stacked. The encapsulating organic film TFE2 may be an organic film containing materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0127] The sensor electrode layer SENL is located on the encapsulation layer ENC. The sensor electrode layer SENL may include sensor electrodes TE and RE.

[0128] The second buffer film BF2 may be located on the encapsulation layer ENC. The second buffer film BF2 may include at least one inorganic film. For example, the second buffer film BF2 may be formed as a multilayer film in which one or more inorganic films selected from silicon nitride layer, silicon oxynitride layer, silicon oxide layer, titanium oxide layer and aluminum oxide layer are alternately stacked. The second buffer film BF2 may be omitted.

[0129] The first connecting portion BE1 can be located on the second buffer film BF2. The first connecting portion BE1 can be formed as a single layer containing molybdenum (Mo), titanium (Ti), copper (Cu) or aluminum (Al), or it can be formed as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and indium tin oxide (ITO) (ITO / Al / ITO), an Ag-Pd-Cu (APC) alloy, or a stacked structure of APC alloy and ITO (ITO / APC / ITO).

[0130] The first sensor insulating film TINS1 may be located on the first connection portion BE1. The first sensor insulating film TINS1 may be formed as or include an inorganic film comprising, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0131] The sensor electrodes, namely the driving electrode TE and the sensing electrode RE, can be located on the first sensor insulating film TINS1. Furthermore, a dummy pattern can be located on the first sensor insulating film TINS1. The driving electrode TE, the sensing electrode RE, and the dummy pattern do not overlap with the emission region EA. The driving electrode TE, the sensing electrode RE, and the dummy pattern can be formed as a single layer comprising molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al), or can be formed as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and indium tin oxide (ITO) (ITO / Al / ITO), an Ag-Pd-Cu (APC) alloy, or a stacked structure of APC alloy and ITO (ITO / APC / ITO).

[0132] The second sensor insulating film TINS2 can be located on the driving electrode TE, the sensing electrode RE, and the dummy pattern. The second sensor insulating film TINS2 can include at least one of inorganic and organic films. The inorganic film can be a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The organic film can include acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0133] The above has been referenced Figure 5 and Figure 6 The polarizing film PF and the cover window CW are described, and therefore their descriptions will be omitted.

[0134] Display device 10 according to an exemplary embodiment of the present disclosure (see also...) Figure 2 (Not limited to) Figure 7 The display device 10 shown includes an organic light-emitting layer. For example, the display device 10 according to an exemplary embodiment of this disclosure may be a display device including inorganic light-emitting diodes, quantum dot light-emitting diodes, etc.

[0135] Figure 8 This is a front perspective view of the cover window according to an example embodiment. Figure 9 This is a perspective view of the rear of the cover window according to an example embodiment. Figure 10 This is a plan view showing the cover window according to an example embodiment.

[0136] Reference Figures 8 to 10The cover window CW includes a front surface FS, a rear surface BS, a first side surface SS1, a second side surface SS2, a third side surface SS3 and a fourth side surface SS4, as well as a first corner surface CS1, a second corner surface CS2, a third corner surface CS3 and a fourth corner surface CS4.

[0137] The front surface FS may have a short side in a first direction DR1 and a long side in a second direction DR2. The angle at which the short side in the first direction DR1 intersects the long side in the second direction DR2 in the front surface FS may be rounded with a selected radius of curvature, or it may be a right angle. The front surface FS may be formed as a flat surface, or it may include a curved surface portion with a selected radius of curvature.

[0138] The first side surface SS1 can extend from the first side S1 of the front surface FS, and the first side S1 of the front surface FS can be the left side of the front surface FS. The second side surface SS2 can extend from the second side S2 of the front surface FS, and the second side S2 of the front surface FS can be the lower side of the front surface FS. The third side surface SS3 can extend from the third side S3 of the front surface FS, and the third side S3 of the front surface FS can be the right side of the front surface FS. The fourth side surface SS4 can extend from the fourth side S4 of the front surface FS, and the fourth side S4 of the front surface FS can be the upper side of the front surface FS.

[0139] The first corner surface CS1 can be a corner side surface located between the first side surface SS1 and the second side surface SS2. The second corner surface CS2 can be a corner side surface located between the second side surface SS2 and the third side surface SS3. The third corner surface CS3 can be a corner side surface located between the third side surface SS3 and the fourth side surface SS4. The fourth corner surface CS4 can be a corner side surface located between the first side surface SS1 and the fourth side surface SS4.

[0140] Figure 11 It is along Figure 10 The cross-sectional view taken by line X1-X1'. Figure 11 This is a cross-sectional view showing the first side surface SS1 of the cover window CW. Since the shapes of the second side surface SS2, the third side surface SS3, and the fourth side surface SS4 of the cover window CW can be substantially the same except for their orientation, only the first side surface SS1 will be described.

[0141] refer to Figure 11 The first side surface SS1 of the cover window CW can have a curved shape with a selected radius of curvature. The radius of curvature of the first side surface SS1 of the cover window CW can be approximately 15R to 25R. Since the radius of curvature of the first side surface SS1 of the cover window CW is 15R to 25R, the impact strength of the first side surface SS1 can be increased.

[0142] The radius of curvature of the first side surface SS1 can be the same or different at each point on the first side surface SS1. When the radius of curvature of the first side surface SS1 is different at each point on the first side surface SS1, the radius of curvature of the first side surface SS1 can be defined as the average value of the radius of curvature at each point on the first side surface SS1.

[0143] In the example embodiment, the width Wss1 of the first side surface SS1 of the cover window CW (e.g., the length in the first direction DR1) can be approximately 10 μm to 20 μm, and the thickness Tcw of the cover window CW can be approximately 30 μm to 60 μm.

[0144] The following describes a method for manufacturing a cover window according to an example embodiment.

[0145] Figure 12 This is a flowchart illustrating a method for manufacturing a cover window according to an example embodiment. Figure 13 and Figure 14 It is shown Figure 12 A three-dimensional view of the operation of S110. Figure 15 It is shown Figure 12 A cross-sectional view of operation S120. Figure 16 and Figure 17 It is shown Figure 12 A cross-sectional view of operation S110. Figure 18 yes Figure 15 A magnified view of region A. Figure 16 It is along Figure 13 The cross-sectional view intercepted by line X2-X2', and Figure 17 It is along Figure 14 The cross-sectional view taken by line X3-X3'.

[0146] refer to Figures 12 to 18 According to the example embodiment, the cover window manufacturing method S10 may include: forming sketch lines for forming a plurality of cover windows by irradiating a mother glass with a laser beam (operation S110), and etching a plurality of cover windows using an etchant (operation S120).

[0147] First, such as Figure 13 and Figure 16 As shown, sketch lines LS for forming multiple cover windows CW can be formed by irradiating the mother glass MSUB with a laser beam BM. Figure 12 Operation S110).

[0148] The laser processing equipment LD can scan a laser beam BM along a selected imaginary line to form multiple cover windows CW. The laser processing equipment LD can scan along the first side surface SS1 of any of the multiple cover windows CW (see... Figure 9The hypothetical line-scanning laser beam BM corresponds to the first of the four cover windows CW. Then, the laser processing equipment LD can scan along the second side surface SS2, the third side surface SS3, and the fourth side surface SS4 (see...) Figure 9 The laser processing equipment LD scans the laser beam BM along the imaginary line corresponding to any one of the multiple cover windows CW. When the laser processing equipment LD completes scanning the laser beam BM along the imaginary line corresponding to another cover window CW, it can begin scanning the laser beam BM along the imaginary line corresponding to another cover window CW. The laser processing equipment LD can sequentially complete scanning the laser beam BM of all the multiple cover windows CW.

[0149] Then, as Figure 14 and Figure 17 As shown, multiple cover windows (CWs) can be separated from the mother glass (MSUB) by multiple sketch lines (LS) formed by scanning with a laser beam (BM). Furthermore, the multiple sketch lines (LS) formed by scanning with the laser beam (BM) can be positioned along the respective edges of the multiple cover windows (CWs) within the side surfaces of the multiple cover windows (CWs). Figure 12 Operation S110).

[0150] For example, multiple sketch lines LS may include multiple first sketch lines LS1 and multiple second sketch lines LS2.

[0151] Multiple first sketch lines LS1 are cutting lines used to separate multiple cover windows CW from the mother glass MSUB. In a cross-sectional view taken along a plane defined by a second direction DR2 and a third direction DR3 or a plane defined by a first direction DR1 and a third direction DR3, the multiple first sketch lines LS1 may have a straight line shape extending in the third direction DR3, such as a 1-shape or an I-shape.

[0152] Multiple second sketch lines LS2 can be partial cut lines used to form the side surfaces SS1, SS2, SS3, and SS4 of multiple cover windows CW with selected radii of curvature. For example, multiple second sketch lines LS2 may not be cut lines that completely separate the mother glass MSUB or the multiple cover windows CW, but may be processing lines that provide paths through which their etchant ETL can penetrate to form the shapes of the first side surface SS1, the second side surface SS2, the third side surface SS3, and the fourth side surface SS4.

[0153] Multiple second sketch lines LS2 may be spaced apart from multiple first sketch lines LS1 along a first direction DR1 or a second direction DR2. In a cross-sectional view taken along a plane defined by the second direction DR2 and a third direction DR3, or a plane defined by the first direction DR1 and the third direction DR3, the multiple second sketch lines LS2 may have a straight line shape extending along the third direction DR3, such as a 1-shape or an I-shape. The multiple second sketch lines LS2 may have a half-line (or dotted line) shape extending from the top and bottom surfaces of the mother glass MSUB or cover window CW along the third direction DR3 toward the interior of the mother glass MSUB or cover window CW.

[0154] Among the multiple second sketch lines LS2, the second sketch line LS2 extending from the top surface of the mother glass MSUB or cover window CW can be spaced apart on the third direction DR3 from the second sketch line LS2 extending from the bottom surface of the mother glass MSUB or cover window CW. That is, the second sketch line LS2 may not completely penetrate the interior of the mother glass MSUB or cover window CW, but may only partially penetrate from the top and bottom surfaces inward.

[0155] Therefore, multiple cover windows CW can be separated from the mother glass MSUB by multiple first sketch lines LS1, and multiple second sketch lines LS2 can be formed along the various edges of the multiple cover windows CW.

[0156] In some example embodiments, multiple first sketch lines LS1 and multiple second sketch lines LS2 can be simultaneously formed by scanning the laser beam BM of the laser processing equipment LD. For example, the laser processing equipment LD can scan the mother glass MSUB while outputting laser beams BM multiple times, and can simultaneously form multiple first sketch lines LS1 and multiple second sketch lines LS2 in each laser beam BM.

[0157] Next, as Figure 15 and Figure 18 As shown, multiple cover windows (CWs) can be etched using an etchant ETL. Figure 12 Operation S120).

[0158] Multiple cover windows CWs in which the second sketch line LS2 is formed can be etched using an etchant ETL. For example, the cover windows CWs can be immersed in an etchant ETL stored in an etchant storage tank STK.

[0159] Therefore, the thickness of the cover window CW can be reduced by decreasing the thickness from the first thickness T1 to the second thickness T2. The thickness of the cover window CW can be reduced by approximately 20% to 50%.

[0160] Furthermore, the etchant ETL can penetrate the second sketch line LS2, thereby allowing etching to occur not only in the thickness direction of the cover window CW (e.g., the third direction DR3), but also in the direction from the second sketch line LS2 toward the cover window CW due to the isotropic nature of the etchant ETL. Therefore, the first side surface SS1, the second side surface SS2, the third side surface SS3, and the fourth side surface SS4 of the cover window CW can be formed along the shape of the second sketch line LS2.

[0161] Each of the multiple cover windows (CWs) can be formed with side surfaces SS1, SS2, SS3, and SS4 having selected curved shapes using only a laser process with a laser processing equipment (LD) and an etching process using an etchant (ETL). Therefore, when manufacturing multiple cover windows (CWs), defects such as wedge-shaped defects or chipping caused by CNC machining can be reduced or prevented, thereby reducing manufacturing costs.

[0162] In the following, a cover window manufacturing method S10 according to another example embodiment will be described, wherein each of a plurality of cover windows CW is formed having as referenced Figure 11 The side surfaces SS1, SS2, SS3 and SS4 described above have curved shapes with selected radii of curvature.

[0163] Figure 19 and Figure 20 This is a cross-sectional view illustrating operation S110_1 of a cover window manufacturing method according to another example embodiment. Figure 21 This is a cross-sectional view illustrating operation S120_1 of a cover window manufacturing method according to another example embodiment.

[0164] Apart from Figure 12 In addition, refer to Figures 19 to 21 The cover window manufacturing method S10 according to another example embodiment and according to reference Figure 16 The difference between the cover window manufacturing method S10 of the example embodiments described above and the other example embodiments is that another example embodiment also includes a third sketch line LS3.

[0165] For example, the cover window manufacturing method S10 according to another example embodiment may include forming sketch lines for forming a plurality of cover windows by irradiating a laser beam onto the mother glass (operation S110_1) and etching a plurality of cover windows using an etchant (operation S120_1).

[0166] Multiple sketch lines LS can include multiple first sketch lines LS1, multiple second sketch lines LS2, and multiple third sketch lines LS3.

[0167] The descriptions of the multiple first sketch lines LS1 and the multiple second sketch lines LS2 are the same as those described above, and therefore will be omitted.

[0168] Multiple third sketch lines LS3, together with multiple second sketch lines LS2, can be used to form the side surfaces SS1, SS2, SS3, and SS4 of multiple cover windows CW (see...). Figure 8 and Figure 9 ( ) A partial cut line with a selected radius of curvature. For example, multiple third sketch lines LS3 may not be cut lines that completely separate the mother glass MSUB or multiple cover window CWs, but may be provided with etchant ETL (see ) Figure 15 A processing line that can penetrate into a path to form the shape of the first side surface SS1, the second side surface SS2, the third side surface SS3, and the fourth side surface SS4.

[0169] Multiple third sketch lines LS3 may be spaced apart from multiple second sketch lines LS2 in a first direction DR1 or a second direction DR2. For example, multiple third sketch lines LS3 may be positioned on opposite sides of multiple first sketch lines LS1, wherein multiple second sketch lines LS2 are located between multiple third sketch lines LS3 and multiple first sketch lines LS1. In a cross-sectional view taken along a plane defined by the second direction DR2 and the third direction DR3 or a plane defined by the first direction DR1 and the third direction DR3, multiple third sketch lines LS3 may have a straight line shape extending along the third direction DR3, such as a 1-shape or an I-shape. Multiple third sketch lines LS3 may have a half-line (e.g., dotted line) shape extending from the top and bottom surfaces of the mother glass MSUB or cover window CW along the third direction DR3 toward the interior of the mother glass MSUB or cover window CW.

[0170] Among the multiple third sketch lines LS3, the third sketch line LS3 extending from the top surface of the mother glass MSUB or cover window CW can be spaced apart from the third sketch line LS3 extending from the bottom surface of the mother glass MSUB or cover window CW on the third direction DR3. That is to say, the third sketch line LS3 may not completely penetrate the interior of the mother glass MSUB or cover window CW, but may only partially penetrate from the top and bottom surfaces inward.

[0171] In some example embodiments, the depth to which each of the plurality of third sketch lines LS3 penetrates into the mother glass MSUB or cover window CW may be less than the depth to which each of the plurality of second sketch lines LS2 penetrates into the mother glass MSUB or cover window CW.

[0172] Therefore, multiple cover windows CW can be separated from the mother glass MSUB by multiple first sketch lines LS1, and multiple second sketch lines LS2 and multiple third sketch lines LS3 can be formed along the various edges of the multiple cover windows CW.

[0173] In some example embodiments, the laser beam BM of the laser processing equipment LD (see...) Figure 13The scanning of a laser simultaneously forms multiple first sketch lines LS1, multiple second sketch lines LS2, and multiple third sketch lines LS3. For example, a laser processing device LD can scan the mother glass MSUB while outputting multiple laser beams BM, and can simultaneously form multiple first sketch lines LS1, multiple second sketch lines LS2, and multiple third sketch lines LS3 in each laser beam BM.

[0174] Multiple cover windows CWs, in which the second sketch line LS2 and the third sketch line LS3 are formed, can be etched using an etchant ETL. For example, the cover window CWs can be immersed in an etchant storage tank STK (see [link to etchant storage tank]). Figure 15 In the etchant ETL in ).

[0175] Therefore, the thickness of the cover window CW can be reduced by decreasing the thickness from the first thickness T1 to the second thickness T2. The thickness of the cover window CW can be reduced by approximately 20% to 50%.

[0176] Furthermore, the etchant ETL can penetrate the second sketch line LS2 and the third sketch line LS3, thereby allowing etching to occur not only in the thickness direction of the cover window CW (e.g., the third direction DR3), but also, due to the isotropic nature of the etchant ETL, in the direction from the second sketch line LS2 toward the cover window CW and in the direction from the third sketch line LS3 toward the cover window CW. Therefore, the first side surface SS1, the second side surface SS2, the third side surface SS3, and the fourth side surface SS4 of the cover window CW can be formed along the shapes of the second sketch line LS2 and the third sketch line LS3.

[0177] In the preceding text, the cover window manufacturing method S10 was described using two or three sketch lines LS as an example. However, the number of sketch lines LS used for shape processing, in addition to the first sketch line LS1 used to separate the cover window CW, can be modified in various ways. As the number of sketch lines LS used for shape processing increases, the first side surface SS1, the second side surface SS2, the third side surface SS3, and the fourth side surface SS4 of the cover window CW can become closer to a curved surface shape with a selected radius of curvature.

[0178] In the following text, an apparatus for manufacturing a cover window according to an example embodiment will be described.

[0179] Figure 22 This is a schematic side view showing a cover window manufacturing apparatus according to an example embodiment.

[0180] refer to Figure 22 The laser processing equipment LD (or cover window manufacturing equipment) according to the example embodiment can be used for manufacturing cover windows CW (see Figure 2 For example, laser processing equipment (LD) can utilize a laser beam (BM) to form a process for processing master glass (MSUB) from a mother glass substrate (see [reference]). Figure 13The sketch line LS that forms the cover window CW (see...) Figure 13 ).

[0181] The laser processing apparatus LD according to the example embodiment may include a light source LR, a beam splitter BST, a first phase mask DE1, a second phase mask DE2, an optical delay unit OTD, a beam combiner BC, a relay lens RLNS, and an objective lens OLNS.

[0182] The laser source (LR) can be any known laser generating device. The laser source (LR) can emit a raw laser beam (RLB). The laser source (LR) can emit the raw laser beam (RLB) continuously or discontinuously. The laser source (LR) can output a single pulse of raw laser beam (RLB) or a pulse train of raw laser beam (RLB) consisting of multiple pulses.

[0183] The source LR can adjust the pulse duration, pulse train, pulse energy, repetition rate, etc. of the original laser beam RLB. For example, the pulse duration of the original laser beam RLB can be approximately 300 femtoseconds (fs) to 10 picoseconds (ps). The repetition rate of the original laser beam RLB can be approximately 10 kHz to 1000 kHz. When the source LR outputs a pulse train of the original laser beam RLB, the pulse train of the original laser beam RLB can be approximately 2 to 5 pulses.

[0184] Various laser beams can be used as the original laser beam RLB according to the example embodiment, but the original laser beam RLB can have a wavelength band of approximately 300 nm to 2 μm. For example, the original laser beam RLB can be an infrared Gaussian beam with a wavelength band of approximately 800 nm to 1100 nm.

[0185] A beam splitter (BST) can split the original laser beam RLB incident from the light source LR into a main beam MB and a sub-beam SB. In some example embodiments, the beam splitter BST can be an optical element that reflects part of the light and transmits another portion. For example, the beam splitter BST may include a semi-transparent mirror or a diffractive optical element (DOE).

[0186] Reference Figure 12 In the cover window manufacturing method S10 described above, the main beam MB can form the first sketch line LS1 (see...). Figure 13 ), and the sub-beam SB can form the second sketch line LS2 (and the third sketch line LS3) (see Figure 19 ).

[0187] In some example embodiments, the beam splitter BST can adjust the polarization state of the master beam MB and the sub-beam SB. For example, the beam splitter BST can set the extension directions of the polarization axes of the master beam MB and the sub-beam SB, or the angles of the polarization axes relative to a specific direction, to be different from each other. In one example, the polarization axes of the master beam MB and the sub-beam SB can be made orthogonal to each other by the beam splitter BST.

[0188] In the accompanying drawings, the original laser beam RLB is shown as split into two beams (e.g., a main beam MB and a sub-beam SB), but is not limited thereto. The number of beams formed by splitting the original laser beam RLB using a beam splitter BST can be modified in various ways. For example, the original laser beam RLB can be split into a main beam MB and two or more sub-beams SB using a beam splitter BST.

[0189] In the laser processing apparatus LD according to this example embodiment, the paths of the main beam MB and the sub-beam SB can be spatially separated by the beam splitter BST. Here, spatial separation includes not only the case where the paths of the main beam MB and the sub-beam SB do not completely overlap as shown in the accompanying drawings, but also the case where the main beam MB and the sub-beam SB propagate along the same path with different vibration directions due to the different angles of their polarization axes.

[0190] The paths of the main beam MB and the sub-beam SB can be spatially separated by the beam splitter BST and incident on the first phase mask DE1 and the second phase mask DE2 respectively, thereby allowing adjustment of the shape and imaging position of each of the main beam MB and the sub-beam SB that are ultimately incident on the focal plane FF. (See below for further details.) Figure 25A and Figure 25B Describe the shape and imaging position of the main beam MB and the sub-beam SB.

[0191] Furthermore, by spatially separating the paths of the main beam MB and the sub-beam SB via the beam splitter BST, the diffraction interference between the main beam MB and the sub-beam SB can be reduced or minimized when the main beam MB and the sub-beam SB are diffracted by the first phase mask DE1 and the second phase mask DE2, respectively.

[0192] The first phase mask DE1 can be positioned on the path of the master beam MB between the beam splitter BST and the beam combiner BC. The first phase mask DE1 can be an optical diffraction element used to convert the shape of the incident master beam MB. For example, the master beam MB can be converted into a Bessel beam through the first phase mask DE1. In some example embodiments, the first phase mask DE1 can be a diffractive optics (DOE) with a fixed diffraction pattern or a spatial light modulator (SLM) capable of actively changing the diffraction pattern.

[0193] The second phase mask DE2 can be positioned on the path of the sub-beam SB between the beam splitter BST and the beam combiner BC. The second phase mask DE2 can be an optical diffraction element used to convert the shape of the incident sub-beam SB. For example, the sub-beam SB can be converted into a Bessel beam by the second phase mask DE2. In some example embodiments, the second phase mask DE2 can be a diffractive optics (DOE) with a fixed diffraction pattern or a spatial light modulator (SLM) capable of actively changing the diffraction pattern.

[0194] In the accompanying drawings, the laser processing apparatus LD is shown as including two phase masks, but the number of phase masks is not limited to this. The number of phase masks included in the laser processing apparatus LD can vary depending on the number of the main beam (MB) and sub-beams (SB). For example, the number of phase masks included in the laser processing apparatus LD can be the same as the number of the main beam (MB) and sub-beams (SB).

[0195] The laser processing apparatus LD according to this example embodiment may include phase masks that participate in the diffraction of the main beam MB and the sub-beam SB, respectively, thereby reducing or minimizing the diffraction interference between the main beam MB and the sub-beam SB when the main beam MB and the sub-beam SB are diffracted by the first phase mask DE1 and the second phase mask DE2, respectively.

[0196] The optical retarder OTD can be positioned on the path of the sub-beam SB between the beam splitter BST and the second phase mask DE2. However, the exemplary embodiments of this disclosure are not limited thereto, and the optical retarder OTD can be positioned on the path of the main beam MB. For example, the optical retarder OTD can be positioned on the path of the main beam MB between the beam splitter BST and the first phase mask DE1.

[0197] An optical delay unit (OTD) can be positioned on the path of either the main beam (MB) or the sub-beam (SB) to adjust the path length of either the main beam (MB) or the sub-beam (SB), thereby delaying the arrival time. For example, as... Figure 22 As shown, the optical delayer (OTD) can adjust the path length of the sub-beam SB to delay its arrival time, so that the sub-beam SB arrives at the beam combiner BC later than the main beam MB. In some example embodiments, the optical delayer (OTD) may include a mirror or a fiber optic loop.

[0198] In an example embodiment, the time delay range of the optical delay unit (OTD) can be approximately 1 ps to 10 ps. For example, one of the main beam (MB) and the sub-beam (SB) may arrive at the beam combiner (BC) approximately 1 ps to 10 ps later than the other.

[0199] In the laser processing apparatus LD according to this example embodiment, the main beam MB and the sub-beam SB can be temporally separated by using an optical retarder OTD to delay the arrival time of either the main beam MB or the sub-beam SB. Therefore, when the main beam MB and the sub-beam SB are diffracted by the first phase mask DE1 and the second phase mask DE2, respectively, the diffraction interference between the main beam MB and the sub-beam SB can be reduced or minimized.

[0200] The beam combiner BC can be positioned between the first phase mask DE1 and the second phase mask DE2 and the relay lens RLNS (or objective lens OLNS). The beam combiner BC can combine the main beam MB and the sub-beam SB to form a single combined beam CB. In some example embodiments, the beam combiner BC may include a semi-transparent mirror, a prism, or a diffractive optics (DOE).

[0201] Even when the main beam MB and the sub-beam SB are combined into a single combined beam CB as described above, the beam can still be imaged at different positions on the focal plane FF because the main beam MB and the sub-beam SB are separated in space and time.

[0202] A relay lens RLNS can be positioned between the beam combiner BC and the objective lens OLNS. The relay lens RLNS can transmit light at a ratio of n (where n is a positive integer):1 or 1:n. For example, the relay lens RLNS can transmit the combined beam CB incident from the beam combiner BC to the objective lens OLNS at a ratio of n:1 or 1:n. In some example embodiments, the relay lens RLNS may be omitted.

[0203] The relay lens RLNS may include a first lens LNS1 and a second lens LNS2. The first lens LNS1 may be positioned adjacent to the beam combiner BC, and the second lens LNS2 may be positioned adjacent to the objective lens OLNS.

[0204] In some example embodiments, the first lens LNS1 may be a convex lens convex to the beam combiner BC, and the second lens LNS2 may be a convex lens convex to the objective lens OLNS.

[0205] Objective lens OLNS can image the combined beam CB passing through relay lens RLNS at a selected distance. For example, objective lens OLNS can image the combined beam CB passing through relay lens RLNS onto focal plane FF.

[0206] In some example embodiments, the objective OLNS can have a relatively high numerical aperture (NA). For example, the numerical aperture of the objective OLNS can be approximately 0.4 or greater.

[0207] Figure 23It is a planar diagram showing the diffraction pattern of the first phase mask in the XY plane. Figure 24 This is a planar diagram showing the diffraction pattern of the second phase mask in the XY plane.

[0208] refer to Figure 23 and Figure 24 In order to form main beam MB and sub-beam SB of different shapes (see...) Figure 22 The shapes of the first phase mask DE1 and the second phase mask DE2 can be different from each other.

[0209] like Figure 23 As shown, the first phase mask DE1 may include a phase modulation structure (or diffraction pattern) arranged radially relative to a single center P0. For example, the first phase mask DE1 may include a phase modulation structure in the form of multiple concentric circles having the same single center P0. Figure 23 In the illustration, the dark areas (black parts) represent the valleys of the phase modulation structure, while the bright areas (white parts) represent the ridges. The main beam MB can be incident on such a phase modulation structure and can be converted into a single, relatively long line beam in a 1-shape or I-shape through diffraction and interference effects.

[0210] like Figure 24 As shown, the second phase mask DE2 may include a phase modulation structure (or diffraction pattern) arranged radially relative to two or more centers P1 and P2. For example, the second phase mask DE2 may include multiple concentric circles having the same single first center P1, multiple concentric circles having the same single second center P2, and a phase modulation structure wherein these concentric circles are symmetrically divided into left and right sides relative to a reference line L1 extending along the Y-axis direction. In other words, a first set of concentric circles with the first center P1 and a second set of concentric circles with the second center P2 can be provided as symmetrical to each other relative to a first straight line extending in one direction. Figure 24 In the illustration, the dark areas (black parts) represent the valleys of the phase modulation structure, while the bright areas (white parts) represent the ridges. The sub-beam SB can be incident on such a phase modulation structure and can be converted into a dot-line beam containing multiple short dot beams in a 1-shape or I-shape through diffraction and interference effects.

[0211] The following will refer to Figure 25A and Figure 25B The shapes of the main beam MB and sub-beam SB, transformed by the first phase mask DE1 and the second phase mask DE2, are described below. The formation of one main beam MB and two sub-beams SB will be described by way of example.

[0212] Figure 25AIt is a photograph showing the two-dimensional shapes of the main beam and sub-beams formed by the cover window manufacturing apparatus according to an example embodiment in the XY plane. Figure 25B It is a photograph showing the two-dimensional shapes of the main beam and sub-beams formed by the cover window manufacturing equipment according to the comparative example in the XY plane. Figure 26A It is a photograph showing the two-dimensional shapes of the main beam and sub-beams formed by the cover window manufacturing apparatus according to an example embodiment in the YZ plane. Figure 26B It is a photograph showing the two-dimensional shapes of the main beam and sub-beams formed by the cover window manufacturing equipment according to the comparative example in the YZ plane. Figure 27 It is a graph showing the beam intensity of the main beam and sub-beams according to the Z-axis position.

[0213] Figure 25A , Figure 25B , Figure 26A and Figure 26B The photograph shown illustrates the focal plane FF (see Figure 22 The shape of each beam of light on the beam.

[0214] refer to Figure 25A , Figure 25B , Figure 26A , Figure 26B and Figure 27 The main beam MB and sub-beams SB1 and SB2 formed by the cover window manufacturing equipment can be spaced apart from each other in the Y-axis direction.

[0215] For example, such as Figure 25A As shown, the main beam MB and the first sub-beam SB1 can be spaced apart from each other by a first Y-axis distance dy1 in the Y-axis direction, and the first sub-beam SB1 and the second sub-beam SB2 can be spaced apart from each other by a second Y-axis distance dy2 in the Y-axis direction. In some example embodiments, the first Y-axis distance dy1 and the second Y-axis distance dy2 can each be in the range of about 5 μm to about 20 μm. The first Y-axis distance dy1 and the second Y-axis distance dy2 can be the same as or different from each other.

[0216] The main beam MB formed by the cover window manufacturing apparatus according to the example embodiment can be a single, relatively long line beam in a 1-shape or I-shape extending in the Z-axis direction. In the example embodiment, the depth of focus (DOF_M) of the main beam MB can be approximately several hundred micrometers. The depth of focus (DOF_M) of the main beam MB is based on... Figure 27 The beam intensity of each beam shown is the full width at half maximum (FWHM) value in the Z-axis direction.

[0217] The sub-beams SB1 and SB2 formed by the cover window manufacturing apparatus according to the example embodiment can be dot-line beams comprising a plurality of short dot beams in a 1-shape or I-shape extending in the Z-axis direction. The plurality of dot beams included in each of the sub-beams SB1 and SB2 can be spaced apart from each other in the Z-axis direction. For example, the plurality of dot beams can be spaced apart from each other by a first interval dz (see [link to example]). Figure 26A The first interval dz refers to the distance between the centers of multiple point beams along the Z-axis.

[0218] In the example embodiment, the depth of focus (DOF)_S1 of each of the plurality of point beams of the first sub-beam SB1 and the depth of focus (DOF)_S2 of each of the plurality of point beams of the second sub-beam SB2 can be approximately 20 μm or greater. The depth of focus (DOF)_S1 of each of the plurality of point beams of the first sub-beam SB1 and the depth of focus (DOF)_S2 of each of the plurality of point beams of the second sub-beam SB2 are based on... Figure 27 The beam intensity of each beam shown is the full width at half maximum (FWHM) value in the Z-axis direction.

[0219] In some example embodiments, the focal depth DOF_S1 of each of the plurality of point beams of the first sub-beam SB1 and the focal depth DOF_S2 of each of the plurality of point beams of the second sub-beam SB2 may be less than half of the first interval dz. Therefore, as will be referred to later... Figure 28 The multiple point beams can be positioned adjacent to the top and bottom surfaces of the mother glass MSUB, but will not penetrate the mother glass MSUB in the same way as the main beam MB.

[0220] The width W_M of the main beam MB in the Y-axis direction, the width W_S1 of the first sub-beam SB1 in the Y-axis direction, and the width W_S2 of the second sub-beam SB2 in the Y-axis direction can be approximately 1 μm or less. The width W_M of the main beam MB in the Y-axis direction, the width W_S1 of the first sub-beam SB1 in the Y-axis direction, and the width W_S2 of the second sub-beam SB2 in the Y-axis direction are based on the full width at half maximum (FWHM) value of the beam intensity of each beam in the Y-axis direction.

[0221] In some example embodiments, the aspect ratio (AR) of sub-beams SB1 and SB2 can be greater than 20. For example, the AR of sub-beams SB1 and SB2 can be defined as the ratio of the depths of focus (DOF) DOF_S1 and DOF_S2 of sub-beams SB1 and SB2 to their widths (W_S1 and W_S2) in the Y-axis direction. Therefore, as described above, since the widths (W_S1 and W_S2) of sub-beams SB1 and SB2 in the Y-axis direction are approximately 1 μm or less, and the values ​​of the depths of focus (DOF) DOF_S1 and DOF_S2 of sub-beams SB1 and SB2 are approximately 20 μm or greater, the AR can be approximately 20 or greater.

[0222] Figure 27 The diagram shows the beam intensities of the main beam MB and sub-beams SB1 and SB2 according to their Z-axis positions. The first curve G1 represents the beam intensity of the main beam MB, the second curve G2 represents the beam intensity of the first sub-beam SB1, and the third curve G3 represents the beam intensity of the second sub-beam SB2.

[0223] like Figure 27 As shown, the beam intensities of sub-beams SB1 and SB2 can be approximately 30% to 80% of the beam intensity of the main beam MB. In some example embodiments, the beam intensity of the second sub-beam SB2 can be less than the beam intensity of the first sub-beam SB1. Here, the beam intensity of the main beam MB and the beam intensities of sub-beams SB1 and SB2 each refer to the average value within the range of 0 μm to approximately 500 μm in the Z-axis direction.

[0224] Figure 25B and Figure 26B The shapes of the master beam MB and sub-beam SB formed by the laser processing apparatus LD according to the comparative example are shown. The laser processing apparatus LD according to the comparative example forms the master beam MB and sub-beam SB by using a single phase mask instead of separate phase masks. Furthermore, unlike the laser processing apparatus LD according to the exemplary embodiment, the laser processing apparatus LD according to the comparative example does not include a beam splitter BST for adjusting the polarization state (see [link to example]). Figure 22 This also does not include optical delayers (OTDs) that delay the arrival time of either the main beam (MB) or the sub-beam (SB) (see [link]). Figure 22 Therefore, when the main beam MB and the sub-beam SB are diffracted by a single phase mask, they may interfere with each other. As a result, as shown in the attached figure, the imaging positions of the main beam MB and the sub-beam SB may not be clearly separated, thus making it impossible to accurately machine the side shape of the cover window CW, and the severe fluctuations of each beam itself may degrade the surface roughness characteristics of the side surfaces of the cover window CW.

[0225] Conversely, in the laser processing apparatus LD according to the example embodiment, the main beam MB and the sub-beam SB can be respectively shielded by a first phase mask DE1 and a second phase mask DE2 (see... Figure 22 The laser beams can be diffracted individually and can be spatially separated by having different polarization states via a beam splitter (BST) or by a completely separated path, and temporally separated by an optical delay device (OTD). Therefore, interference between the main beam (MB) and the sub-beams (SB) can be reduced or minimized, resulting in relatively high-quality processing lasers.

[0226] Figure 28 This is a schematic diagram showing the sketch lines formed on the mother glass by the main beam and the sub-beams.

[0227] refer to Figure 28 The main beam MB can form a first sketch line LS1 on the mother glass MSUB, the first sub-beam SB1 can form a second sketch line LS2 on the mother glass MSUB, and the second sub-beam SB2 can form a third sketch line LS3 on the mother glass MSUB.

[0228] The main beam MB can be positioned across the entire thickness of the mother glass MSUB, from its top to bottom surface. Therefore, the first sketch line LS1 can completely penetrate the mother glass MSUB. Among the multiple point beams of each of the sub-beams SB1 and SB2, two point beams adjacent to each other in their extension direction can be positioned adjacent to the top and bottom surfaces of the mother glass MSUB, respectively. Therefore, the second sketch line LS2 and the third sketch line LS3 can not completely penetrate the mother glass MSUB.

[0229] The processing depth Dh1 of the mother glass MSUB via the main beam MB can be greater than the processing depth Dh2 of the mother glass MSUB via the first sub-beam SB1, and the processing depth Dh2 of the mother glass MSUB via the first sub-beam SB1 can be greater than the processing depth Dh3 of the mother glass MSUB via the second sub-beam SB2.

[0230] The display device 10 including the cover window CW according to the above example embodiment can be applied to various electronic devices 1. The electronic device 1 according to the example embodiment may include the display device 10 including the cover window CW, and in addition to the display device 10 including the cover window CW, it may also include modules or devices with other additional functions.

[0231] Figure 29 This is a block diagram of an electronic device according to an example embodiment.

[0232] refer to Figure 29The electronic device 1 according to the example embodiment may include a display module 11, a processor 12, a memory 13, and a power module (or alternatively, a power supply circuit) 14.

[0233] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0234] The memory 13 can store the data information required for the operation of the processor 12 or the display module 11. When the processor 12 runs the application stored in the memory 13, image data signals and / or input control signals are transmitted to the display module 11, and the display module 11 can process the received signals and output image information through the display screen.

[0235] The power module 14 may include a power supply module (such as a power adapter or battery device) and a power conversion module that converts the power supplied by the power supply module to generate the power required for the operation of the electronic device 1.

[0236] At least one of the components of the electronic device 1 described above may be included in the display device 10 according to the above example embodiment (see above). Figure 2 Furthermore, some of the individual modules that are functionally contained within a single module may be included in the display device 10, while other individual modules may be provided separately from the display device 10. For example, the display device 10 may include a display module 11, while the processor 12, memory 13, and power module 14 may be provided in the electronic device 1 as other devices besides the display device 10.

[0237] Any functional block shown in the figure and described above can be implemented as processing circuitry, such as hardware including logic circuitry, a hardware / software combination (such as a processor running software), or a combination thereof. For example, processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0238] Figure 30 These are schematic diagrams of electronic devices according to various example embodiments.

[0239] refer to Figure 30 The display device 10 according to various example embodiments (see...) Figure 2The various electronic devices 1 may include not only image display electronic devices (such as smartphones 1_1a, tablet PCs 1_1b, laptop computers 1_1c, TVs 1_1d, and desktop monitors 1_1e), but also wearable electronic devices containing display modules (such as smart glasses 1_2a, head-mounted displays 1_2b, smartwatches 1_2c, etc.) and vehicle electronic devices 1_3 containing display modules (such as the center console and dashboard of a car, the central information display (CID) placed on the dashboard, the interior mirror display, etc.).

[0240] In concluding this detailed description, those skilled in the art will understand that many variations and modifications can be made to the disclosed exemplary embodiments without substantially departing from the principles of this disclosure. Therefore, the exemplary embodiments of the inventive concept disclosed herein are used in a general and descriptive sense only and are not intended for limiting purposes.

Claims

1. Equipment for manufacturing window covers, including: The light source is configured to output a raw laser beam; A beam splitter is configured to split the original laser beam into a main beam and at least one sub-beam; A first phase mask is configured to diffract the main beam to convert the main beam into a straight beam; A second phase mask is configured to diffract the sub-beam to convert the sub-beam into a dot-line beam comprising a plurality of point beams; A beam combiner is configured to combine the main beam and the sub-beams to form a single combined beam; as well as The objective lens is configured to focus the combined beam onto the focal plane. The beam splitter is configured to set the extension direction of the polarization axis of the main beam to be different from the extension direction of the polarization axis of the sub-beam.

2. The device according to claim 1, wherein, The polarization axis of the main beam and the polarization axis of the sub-beam are orthogonal to each other.

3. The device according to claim 1, further comprising: An optical retarder, located between the beam splitter and the first phase mask, or between the beam splitter and the second phase mask. The optical delayer is configured to delay the arrival time of the main beam or the sub-beam at the beam combiner.

4. The device according to claim 3, wherein, The time delay range of the optical retarder is 1 ps to 10 ps.

5. The device according to claim 1, wherein, The first phase mask has a radially arranged shape of concentric circles with the same single center, and The second phase mask has a radially arranged shape of concentric circles with at least two different centers.

6. The device according to claim 5, wherein, The at least two centers of the second phase mask include a first center and a second center, and The first set of concentric circles having the first center and the second set of concentric circles having the second center are symmetrical to each other with respect to a first straight line extending in one direction.

7. The device according to claim 1, wherein, The main beam and the sub-beam, transformed by the first phase mask and the second phase mask respectively, have Bessel beam shapes.

8. The device according to claim 1, wherein, The original laser beam is a Gaussian beam.

9. The device according to claim 1, wherein, The numerical aperture of the objective lens is 0.4 or greater.

10. The device according to claim 1, wherein, In the focal plane, the main beam and the sub-beam are spaced apart in a first direction.

11. The device according to claim 10, wherein, In the focal plane, the main beam and the sub-beam extend in a second direction different from the first direction.

12. The device according to claim 11, wherein, The sub-beams include the plurality of point beams spaced apart from each other in the second direction.

13. The device according to claim 12, wherein, In the second direction, the focal depth of the main beam is greater than the focal depth of each of the plurality of point beams.

14. The device according to claim 13, wherein, The width of the main beam in the first direction and the width of the sub-beam in the first direction are 1 μm or less.

15. The device according to claim 12, wherein, The aspect ratio of the sub-beam is defined as the ratio of the depth of focus of the sub-beam in the second direction to the width of the sub-beam in the first direction, and The aspect ratio of the sub-beam is 20 or greater.

16. The device according to claim 1, wherein, The beam intensity of the sub-beam is 30% to 80% of the beam intensity of the main beam.

17. A method for manufacturing a window cover, comprising: The sketch lines for forming the cover window are created by shining a laser beam onto the mother glass. as well as The cover window was etched using an etchant. The sketch lines include a first sketch line and a second sketch line positioned inside the first sketch line. The cover window is separated from the mother glass by the first sketch line, and The etchant penetrates into the interior of the cover window through the second sketch line.

18. The method according to claim 17, wherein, The first sketch line penetrates the mother glass in the thickness direction. The second sketch lines extend from the top and bottom surfaces of the mother glass towards the interior of the mother glass, and The length of the second sketch line is less than the thickness of the mother glass.

19. The method of claim 17, wherein, The sketch lines also include a third sketch line positioned inward from the second sketch line, and The length of the third sketch line is less than the length of the second sketch line.

20. Electronic devices, including: The display device includes: A cover window manufactured by the device described in claim 1, and The display panel is located below the cover window; The processor is configured to provide drive signals to the display device; and A power module is configured to supply power to the display device.

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