Ultra-precision polishing control method for compound semiconductor substrates

Abstract

The application relates to the technical field of grinding control, in particular to a super-precision grinding control method for a compound semiconductor substrate, which carries out risk index evaluation on a compound semiconductor chip, analyzes the safety weight of each region of the compound semiconductor chip, collects a shaking characteristic parameter of a grinding device and a vulnerable parameter of a chip substrate structure, evaluates the crack initiation probability of each region of the compound semiconductor chip in a next time window, judges the running state of current grinding parameters according to the evaluation result of the crack initiation probability of each region of the compound semiconductor chip in the next time window, adjusts the grinding state of the compound semiconductor substrate based on the judgment result of the running state of the current grinding parameters, reflects the local connection quality of the adhesive layer between the substrate and the chip in real time, provides basic data for subsequent risk index evaluation, comprehensively reflects the dynamic vibration risk and thermal risk of each region in the grinding process, and accurately predicts the crack initiation probability of the compound semiconductor chip.

Description

Technical Field

[0001] This application relates to the field of polishing control technology, and more particularly to an ultra-precision polishing control method for compound semiconductor substrates. Background Technology

[0002] Compound semiconductor substrates, such as silicon carbide, gallium nitride, and gallium arsenide, are widely used in power devices, radio frequency devices, and optoelectronic devices. During device manufacturing, the substrate typically needs to be bonded to the chip or carrier sheet via an adhesive layer and undergo ultra-precision grinding, thinning, or planarization. Because compound semiconductor materials are generally brittle, highly anisotropic, have low fracture toughness, and exhibit a significant difference in thermal expansion coefficient compared to chip materials, defects such as cracks, edge chipping, debonding, and uneven residual stress are easily generated during the grinding process, severely impacting device performance, reliability, and yield.

[0003] Existing compound semiconductor substrate polishing control technologies typically suffer from the following problems: The quality of the adhesive layer, interface debonding, and cracks often rely on post-grinding inspection, making it difficult to detect risks in real time during the grinding process and preventing early intervention. Furthermore, existing methods often rely on threshold control based on single or limited parameters such as spindle current, grinding pressure, and temperature, failing to regionally integrate factors like substrate-chip adhesion, localized vibration, localized heating, equipment vibration, and inherent material vulnerability. During grinding, the stress, heating, and interface state vary across different areas of the chip, making it difficult for existing technologies to calculate safety weights and crack initiation risks for each area separately. They typically only determine whether an anomaly is currently present, making it difficult to predict the probability of crack initiation in each area within the next time window, thus hindering predictive control. When the grinding state becomes abnormal, existing methods often rely on manual adjustments based on experience, resulting in a delayed response and a lack of closed-loop control to restart from the perspectives of adhesion state, localized activity, and heat generation after adjustment. To address the problems raised in this background, this application presents an ultra-precision grinding control method for compound semiconductor substrates. Summary of the Invention

[0004] In order to overcome the defects and shortcomings of the existing technology and achieve the above objectives, this application adopts the following technical solution: In a first aspect, this application provides an ultra-precision polishing control method for compound semiconductor substrates, comprising the following specific steps: Step 1: Collect parameters of the substrate and chip bonding layer to assess the local activity and heat generation in different regions of the compound semiconductor chip; Step 2: Use the collected data to assess the risk index of each region of the compound semiconductor chip, and analyze the safety weight of each region of the compound semiconductor chip based on the risk index assessment results. Step 3: Collect the vibration characteristic parameters of the grinding equipment and the vulnerability parameters of the chip substrate structure to assess the probability of crack initiation in each region of the compound semiconductor chip in the next time window; Step 4: Determine the current grinding parameter operating status based on the crack initiation probability assessment results for each region of the compound semiconductor chip in the next time window; Step 5: Adjust the grinding state of the compound semiconductor substrate based on the current grinding parameter operation status determination results.

[0005] In one implementation of this application, step one includes the following specific contents: The first step is to use an ultrasonic C-scanning device to scan and divide the adhesive layer between the compound semiconductor substrate and the chip to obtain the parameters of the substrate-chip adhesive layer. The parameters of the substrate-chip adhesive layer include the thickness of the adhesive layer in each region of the compound semiconductor chip, the uniformity of the adhesive layer thickness, the area ratio of the edge debonding region, and the acoustic reflection coefficient of the connection interface. The second step is to calculate the adhesive layer thickness, adhesive layer thickness uniformity, edge debonding area area, and acoustic reflection coefficient of the connection interface for each region based on the echo time difference. The third step involves pre-embedding piezoelectric MEMS sensors in various regions of the non-polished surface of the compound semiconductor chip. The vibration displacement signals obtained from these sensors are then subjected to bandpass filtering and wavelet packet decomposition to obtain the local activity corresponding to the i-th region of the compound semiconductor chip's piezoelectric MEMS sensor. , Where i is the number corresponding to each region of the compound semiconductor chip, i is any one of 1 to m, and m is the maximum value of the number corresponding to each region of the compound semiconductor chip. The length of the data collection time window. This represents the vibration displacement signal of the i-th region of the compound semiconductor chip. Let be the average vibration displacement signal of the i-th region of the compound semiconductor chip; use an infrared thermal imager to acquire the surface temperature field of each region of the compound semiconductor chip, calculate the temperature change rate and temperature gradient of each region, and obtain the local heat generation of the i-th region of the compound semiconductor chip. , ,in, Let be the temperature of the i-th region of the compound semiconductor chip. Let be the temperature change rate of the i-th region of the compound semiconductor chip, and k be the dimension compatibility coefficient between the temperature change rate term and the temperature gradient term. Let be the temperature gradient of the i-th region of the compound semiconductor chip.

[0006] In one implementation of this application, step two includes the following specific content: The first step is to obtain the parameters of the substrate-chip adhesive layer, local activity, and heat generation. These parameters are then normalized using the following method: Where x is the original parameter, This is the result of normalizing the original parameters. This is the lower limit of the original parameters. This represents the lower limit of the original parameters; The second step is to use the normalized data to assess the risk index of each region of the compound semiconductor chip. The specific assessment method for the risk index of the i-th region of the compound semiconductor chip is as follows: ,in, This represents the risk index assessment result for the i-th region of the compound semiconductor chip. This is the weight coefficient vector. Let i be the risk feature vector of the i-th region of the compound semiconductor chip; Step 3: Analyze the safety weight of each region based on the risk index of each region of the compound semiconductor chip. The method for analyzing the safety weight of the i-th region of the compound semiconductor chip is as follows: ,in, This represents the security weight analysis result for the i-th region of a compound semiconductor chip.

[0007] In one implementation of this application, step three includes the following specific steps: The first step is to collect real-time vibration characteristic parameters of the polishing equipment and vulnerable parameters of the chip substrate structure, and evaluate the polishing slurry flow fluctuation index; The second step is to predict and assess the risk rate of crack initiation in each region of the compound semiconductor chip in the next time window. The third step is to assess the probability of crack initiation in each region within the next time window using the crack initiation risk rate of each region of the compound semiconductor chip.

[0008] In one implementation of this application, the first step of step three includes the following specific content: Real-time acquisition of grinding equipment vibration characteristic parameters and chip substrate structural vulnerability parameters. Grinding equipment vibration characteristic parameters include spindle radial runout amplitude, grinding disk axial vibration dominant frequency, axial vibration dominant frequency amplitude, grinding slurry flow rate standard deviation, and average flow rate. Spindle radial runout amplitude is obtained by calculating the peak-to-peak value of displacement signals acquired by an eddy current displacement sensor in two orthogonal directions of the spindle. The grinding disk axial vibration dominant frequency and amplitude are obtained by Fourier transform extraction after acquiring the axial vibration of the grinding disk using a laser vibrometer. The grinding slurry flow rate standard deviation and average flow rate are calculated by acquiring the flow rate using a flow meter. Chip substrate structural vulnerability parameters include the fracture toughness of the compound semiconductor chip substrate material, anisotropic cleavage plane angle, and the difference in thermal expansion coefficients between the substrate and the chip. The fracture toughness of the compound semiconductor chip substrate material and the difference in thermal expansion coefficients between the substrate and the chip are obtained from a material database. The anisotropic cleavage plane angle is obtained through crystal orientation calibration and mapped to various regions of the compound semiconductor chip. The grinding slurry flow rate fluctuation index is evaluated using the grinding slurry flow rate standard deviation and average flow rate. Specifically, the grinding slurry flow rate fluctuation index is obtained by dividing the grinding slurry flow rate standard deviation by the average flow rate.

[0009] In one implementation of this application, the second step of step three includes the following specific content: The safety weight analysis results for each region of the compound semiconductor chip, the vibration characteristic parameters of the polishing equipment, and the vulnerability parameters of the chip substrate structure are obtained. These results are then used to predict and assess the crack initiation risk rate of each region of the compound semiconductor chip in the next time window. The specific assessment method for the crack initiation risk rate of the i-th region of the compound semiconductor chip in the next time window is as follows:

[0010] ,in, The crack initiation risk rate for the i-th region of a compound semiconductor chip in the next time window. Let i be the security weight of the i-th region of the compound semiconductor chip. This is the comprehensive correction factor for the i-th region of the compound semiconductor chip. , and These are the crack initiation risk rate intercept coefficient, the safety weight influence coefficient, and the comprehensive correction factor influence coefficient, respectively. This is the benchmark risk rate.

[0011] In one implementation of this application, the third step of step three includes the following specific content: The probability of crack initiation in the next time window is evaluated for each region of the compound semiconductor chip using the crack initiation risk rate of each region in the next time window. The evaluation method for the probability of crack initiation in the i-th region of the compound semiconductor chip in the next time window is as follows:

[0012] ,in, Let be the probability of crack initiation in the i-th region of the compound semiconductor chip in the next time window. This is the length of the next time window.

[0013] In one implementation of this application, step four includes the following specific content: The crack initiation probability of each region of the compound semiconductor chip in the next time window is obtained. The crack initiation probabilities of each region of the compound semiconductor chip in the next time window are summed and averaged to obtain the crack initiation probability of the compound semiconductor chip in the next time window. The crack initiation probability of the compound semiconductor chip in the next time window is compared with a set crack initiation probability threshold. If the crack initiation probability of the compound semiconductor chip in the next time window is greater than or equal to the set crack initiation probability threshold, it is determined that the current grinding parameters do not allow grinding to continue. If the crack initiation probability of the compound semiconductor chip in the next time window is less than the set crack initiation probability threshold, it is determined that the current grinding parameters allow grinding to continue.

[0014] In one implementation of this application, step five includes the following specific content: Obtain the current grinding parameter operation status determination result. If the current grinding parameter operation status determination result allows to continue, maintain or fine-tune the current grinding parameters and enter the next time window; if the current grinding parameter operation status determination result does not allow to continue grinding, execute the adjusted grinding strategy and re-enter the closed-loop control from step one.

[0015] Secondly, this application also provides an ultra-precision polishing control method for compound semiconductor substrates, including the following specific modules: The module includes a regional activity assessment module, a safety weight analysis module, a crack probability assessment module, a grinding state judgment module, and a grinding parameter adjustment module. The regional activity assessment module is used to collect parameters of the substrate and chip adhesive layer and to assess the local activity and heat generation in each region of the compound semiconductor chip. The security weight analysis module is used to evaluate the risk index of each region of the compound semiconductor chip using the collected data, and to analyze the security weight of each region of the compound semiconductor chip based on the risk index evaluation results. The crack probability assessment module is used to collect the vibration characteristic parameters of the grinding equipment and the vulnerability parameters of the chip substrate structure, and to assess the crack initiation probability of each region of the compound semiconductor chip in the next time window. The grinding state judgment module is used to determine the current grinding parameter operation status based on the crack initiation probability assessment result of each region of the compound semiconductor chip in the next time window. The grinding parameter adjustment module is used to adjust the grinding state of the compound semiconductor substrate based on the current grinding parameter operation status determination result.

[0016] Thirdly, this application provides an electronic device comprising: a processor and a memory, wherein the memory stores a computer program that can be called by the processor, and the processor executes an ultra-precision grinding control method for a compound semiconductor substrate by calling the computer program stored in the memory.

[0017] Fourthly, this application provides a computer-readable storage medium storing instructions that, when executed on a computer, cause the computer to perform an ultra-precision grinding control method for a compound semiconductor substrate.

[0018] Compared with the prior art, this application has the following advantages: 1. By using an ultrasonic C-scan device to obtain the thickness of the adhesive layer, the uniformity of the adhesive layer thickness, the area ratio of the debonded area at the edge, and the acoustic reflection coefficient of the connection interface in various regions of the compound semiconductor chip, the local connection quality of the adhesive layer between the substrate and the chip can be reflected in real time, providing basic data for subsequent risk index assessment.

[0019] 2. Pre-embed piezoelectric MEMS sensors in each area of ​​the non-polished surface of the chip, and obtain the local activity of each area through bandpass filtering and wavelet packet decomposition; at the same time, use an infrared thermal imager to obtain the surface temperature field of each area, calculate the temperature change rate and temperature gradient, and obtain the local heat generation of each area, thereby comprehensively reflecting the dynamic vibration risk and thermal risk of each area during the polishing process.

[0020] 3. Real-time acquisition of spindle radial runout amplitude, grinding disk axial vibration main frequency, axial vibration main frequency amplitude, grinding slurry flow standard deviation and average flow rate, and calculation of grinding slurry flow fluctuation index; simultaneously acquiring chip substrate structural vulnerability parameters such as substrate material fracture toughness, anisotropic cleavage plane angle, and difference in thermal expansion coefficient between substrate and chip; by integrating external factors of equipment and internal factors of materials, it is possible to more accurately predict the crack initiation risk rate and crack initiation probability of each region of compound semiconductor chip in the next time window.

[0021] 4. When it is determined that grinding can continue, maintain or fine-tune the current grinding parameters and enter the next time window; when it is determined that grinding cannot continue, execute the adjusted grinding strategy and restart the closed-loop control from step one. This can reduce the risks of cracks, debonding, edge chipping, and uneven residual stress in a timely manner, and improve grinding consistency and yield. Taking into full account the characteristics of compound semiconductor materials such as high brittleness, strong anisotropy, and large differences in thermal expansion coefficients, through regionalized safety weights, crack initiation probability prediction, and closed-loop adjustment, it can effectively reduce grinding damage, improve surface quality, uniformity of material removal rate, and uniformity of residual stress distribution, and is suitable for ultra-precision grinding control of compound semiconductor substrates. Attached Figure Description

[0022] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 This is a schematic diagram of the overall process structure of the method in this application; Figure 2 This is a flowchart illustrating step three of the method described in this application; Figure 3 This is a schematic diagram of the system structure of this application; Figure 4 This is a flowchart illustrating step two of the method described in this application. Detailed Implementation

[0023] The technical solution of this application will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments and specific features in the embodiments are detailed descriptions of the technical solution of this application, rather than limitations thereof. In the absence of conflict, the embodiments and technical features in the embodiments can be combined with each other.

[0024] Example 1 Please see Figure 1 , Figure 1 This is a schematic flowchart of the ultra-precision polishing control method for compound semiconductor substrates provided in this application embodiment, which specifically includes the following steps: Step 1: Collect parameters of the substrate and chip bonding layer to assess the local activity and heat generation in different regions of the compound semiconductor chip; In this embodiment, step one includes the following specific contents: The first step is to use an ultrasonic C-scanning device to scan and divide the adhesive layer between the compound semiconductor substrate and the chip to obtain the parameters of the substrate-chip adhesive layer. The parameters of the substrate-chip adhesive layer include the thickness of the adhesive layer in each region of the compound semiconductor chip, the uniformity of the adhesive layer thickness, the area ratio of the edge debonding region, and the acoustic reflection coefficient of the connection interface. The second step is to calculate the adhesive layer thickness, adhesive layer thickness uniformity, edge debonding area area, and acoustic reflection coefficient of the connection interface for each region based on the echo time difference. The third step involves pre-embedding piezoelectric MEMS sensors in various regions of the non-polished surface of the compound semiconductor chip. The vibration displacement signals obtained from these sensors are then subjected to bandpass filtering and wavelet packet decomposition to obtain the local activity corresponding to the i-th region of the compound semiconductor chip's piezoelectric MEMS sensor. , Where i is the number corresponding to each region of the compound semiconductor chip, i is any one of 1 to m, and m is the maximum value of the number corresponding to each region of the compound semiconductor chip. The length of the data collection time window. This represents the vibration displacement signal of the i-th region of the compound semiconductor chip. Let be the average vibration displacement signal of the i-th region of the compound semiconductor chip; use an infrared thermal imager to acquire the surface temperature field of each region of the compound semiconductor chip, calculate the temperature change rate and temperature gradient of each region, and obtain the local heat generation of the i-th region of the compound semiconductor chip. , ,in, Let be the temperature of the i-th region of the compound semiconductor chip. Let be the temperature change rate of the i-th region of the compound semiconductor chip, and k be the dimension compatibility coefficient between the temperature change rate term and the temperature gradient term. This represents the temperature gradient of the i-th region of the compound semiconductor chip. It should be noted that the ultrasonic C-scan device operates on the principle of pulse-echo detection; the formula for calculating the adhesive layer thickness (the thickness of which affects stress distribution, heat dissipation, and grinding support stiffness, and localized thickness abnormalities may lead to uneven stress during grinding, chip warping, or cracking) is as follows: ,in, Let be the thickness of the adhesive layer in the i-th region of the compound semiconductor chip. The velocity of sound in the adhesive layer. Here, represents the ultrasonic echo time difference of the i-th region of the compound semiconductor chip, and 2 is the round-trip coefficient (the ultrasonic wave travels twice the path, so it needs to be divided by 2); the formula for calculating the adhesive layer thickness uniformity (the larger the value, the more uniform the local connection, and the more stable the support during polishing; the smaller the value, the more excessively thick or thin the local area, which is prone to stress concentration, debonding, or cracking) is as follows. ,in, For the local thickness uniformity of the i-th region of a compound semiconductor chip, The average thickness of the entire adhesive layer; the ratio of the edge debonding area (edge ​​debonding reduces the mechanical constraint of the substrate-chip composite structure, making the edges more prone to lifting, chipping, or crack propagation during polishing) is calculated using the following formula: ,in, This represents the debonding area ratio of the i-th region of the compound semiconductor chip. Let be the number of pixels in the i-th region of the compound semiconductor chip that were determined to be debonded. The total number of pixels in the edge band of the i-th region of the compound semiconductor chip; the formula for calculating the acoustic reflection coefficient of the interface (when the adhesion is good, the interface reflection coefficient is close to the reference reflection coefficient of a standard defect-free interface) is as follows. ,in, Let be the acoustic reflection coefficient of the interface of the i-th region of the compound semiconductor chip. Let be the amplitude of the reflected echo from the interface of the i-th region of the compound semiconductor chip. The incident wave amplitude is the i-th region of the compound semiconductor chip; the spacing between the pre-embedded piezoelectric MEMS sensors can be 1-5mm, and the sampling frequency is 10-100kHz; the dimensional compatibility coefficient k between the temperature change rate term and the temperature gradient term is used to convert the unit of the temperature gradient term to the same unit as the temperature change rate term, with the dimension of m / s. It is determined by the ratio of the statistical quantity of the temperature change rate to the temperature gradient under normal operating conditions, or it can be obtained through data fitting optimization so that the two terms can be directly added; the stronger the local heating and the larger the temperature gradient, the more serious the frictional heat, plastic deformation or interface damage, which is prone to thermal stress cracks and uneven residual stress.

[0025] Step 2: Use the collected data to assess the risk index of each region of the compound semiconductor chip, and analyze the safety weight of each region of the compound semiconductor chip based on the risk index assessment results. like Figure 4 As shown, in this embodiment, step two includes the following specific contents: The first step is to obtain the parameters of the substrate-chip adhesive layer, local activity, and heat generation. These parameters are then normalized using the following method: Where x represents the original parameters (i.e., the parameters of the substrate and chip adhesive layer, local activity, and heat generation). This is the result of normalizing the original parameters. This is the lower limit of the original parameters. This represents the lower limit of the original parameters; The second step is to use the normalized data to assess the risk index of each region of the compound semiconductor chip. The specific assessment method for the risk index of the i-th region of the compound semiconductor chip is as follows: ,in, This represents the risk index assessment result for the i-th region of the compound semiconductor chip. This is the weight coefficient vector. Let i be the risk feature vector of the i-th region of the compound semiconductor chip; Step 3: Analyze the safety weight of each region based on the risk index of each region of the compound semiconductor chip. The method for analyzing the safety weight of the i-th region of the compound semiconductor chip is as follows: ,in, This represents the security weight analysis result for the i-th region of a compound semiconductor chip. It should be noted that in the second step ,in, , , , and These are weight vectors corresponding to adhesive layer thickness uniformity, edge debonding area ratio, acoustic reflection coefficient of the bonding interface, local activity, and heat generation, respectively. ,in, The reference reflection coefficient for a standard defect-free interface. For reference of local activity levels, The reference local heating gradient; the reference reflection coefficient, reference local activity, and reference local heating gradient of the standard defect-free interface.

[0026] Step 3: Collect the vibration characteristic parameters of the grinding equipment and the vulnerability parameters of the chip substrate structure to assess the probability of crack initiation in each region of the compound semiconductor chip in the next time window; like Figure 2 As shown, in this embodiment, step three includes the following specific steps: The first step is to collect real-time vibration characteristic parameters of the polishing equipment and vulnerable parameters of the chip substrate structure, and evaluate the polishing slurry flow fluctuation index; In this embodiment, the first step of step three includes the following specific contents: Real-time acquisition of grinding equipment vibration characteristic parameters and chip substrate structural vulnerability parameters. Grinding equipment vibration characteristic parameters include spindle radial runout amplitude, grinding disk axial vibration frequency, axial vibration frequency amplitude, grinding slurry flow rate standard deviation, and average flow rate. Spindle radial runout amplitude is obtained by calculating peak-to-peak values ​​from displacement signals acquired by an eddy current displacement sensor in two orthogonal directions of the spindle. The grinding disk axial vibration frequency and amplitude are obtained by Fourier transform extraction after acquiring the axial vibration of the grinding disk using a laser vibrometer. The grinding slurry flow rate standard deviation and average flow rate are calculated from the flow rate acquired by a flow meter. Chip substrate structural vulnerability parameters include the fracture toughness of the compound semiconductor chip substrate material, anisotropic cleavage plane angles, and the difference in thermal expansion coefficients between the substrate and the chip. The fracture toughness of the compound semiconductor chip substrate material and the difference in thermal expansion coefficients between the substrate and the chip are obtained from a material database. The anisotropic cleavage plane angles are obtained through crystal orientation calibration and mapped to different regions of the compound semiconductor chip. The grinding slurry flow rate fluctuation index is evaluated using the grinding slurry flow rate standard deviation and average flow rate. Specifically, the grinding slurry flow rate fluctuation index is obtained by dividing the grinding slurry flow rate standard deviation by the average flow rate. It should be noted that the vibration characteristic parameters of the grinding equipment reflect the external factors affecting the current operational stability of the grinding equipment; the chip substrate structure vulnerability parameters reflect the internal factors affecting the resistance of the compound semiconductor chip and substrate to damage; the axial vibration main frequency of the grinding disc reflects the vibration source, such as the spindle rotation frequency, bearing characteristic frequency, grinding fluid pulsation, etc.; the axial vibration main frequency amplitude reflects the axial impact intensity. The larger the axial vibration main frequency amplitude, the greater the grinding pressure fluctuation, the uneven abrasive cutting, and the easier it is to produce surface damage and cracks; the standard deviation of the grinding fluid flow rate indicates the degree of fluid supply fluctuation. The larger the standard deviation, the more unstable the flow rate, which will lead to uneven abrasive distribution, local overheating, and uneven material removal; the average flow rate reflects the average fluid supply level and affects the lubrication, cooling, and chip removal capabilities. The second step is to predict and assess the risk rate of crack initiation in each region of the compound semiconductor chip in the next time window. In this embodiment, the second step in step three includes the following specific contents: The safety weight analysis results for each region of the compound semiconductor chip, the vibration characteristic parameters of the polishing equipment, and the vulnerability parameters of the chip substrate structure are obtained. These results are then used to predict and assess the crack initiation risk rate of each region of the compound semiconductor chip in the next time window. The specific assessment method for the crack initiation risk rate of the i-th region of the compound semiconductor chip in the next time window is as follows:

[0027] ,in, The crack initiation risk rate for the i-th region of a compound semiconductor chip in the next time window. Let i be the security weight of the i-th region of the compound semiconductor chip. This is the comprehensive correction factor for the i-th region of the compound semiconductor chip. , and These are the crack initiation risk rate intercept coefficient, the safety weight influence coefficient, and the comprehensive correction factor influence coefficient, respectively. The benchmark risk rate; It should be noted here that the comprehensive correction factors for each region are explained. The form is the maximum value after normalizing all data of the grinding equipment vibration characteristic parameters and the chip substrate structure vulnerability parameters. This is used to aggregate the additional risks of equipment vibration and material fragility into a scalar. (The larger the value, the stronger the promoting effect of equipment and material factors on crack initiation.) Intensity of the impact on crack initiation risk rate; baseline risk rate This represents the basic rate of crack initiation per unit time under standard operating conditions, obtained from historical experimental data. This rate can vary depending on different material systems, equipment, and grinding parameters; it also represents the crack initiation risk rate intercept coefficient. Used to adjust the overall risk level. When it is 0, the benchmark risk rate is When the value is greater than 0, the overall risk rate increases; when the value is less than 0, the overall risk rate decreases. As a safety weighting factor in the crack initiation risk rate, The greater the safety weight (indicating the rate at which the risk rate increases as the safety weight decreases), the stronger the impact of the safety weight on the crack initiation risk rate. The third step is to assess the probability of crack initiation in each region of the compound semiconductor chip in the next time window using the crack initiation risk rate in each region. In this embodiment, the third step in step three includes the following specific contents: The probability of crack initiation in the next time window is evaluated for each region of the compound semiconductor chip using the crack initiation risk rate of each region in the next time window. The evaluation method for the probability of crack initiation in the i-th region of the compound semiconductor chip in the next time window is as follows:

[0028] ,in, Let be the probability of crack initiation in the i-th region of the compound semiconductor chip in the next time window. The length of the next time window; It should be noted that the higher the probability of crack initiation in each region of a compound semiconductor chip within the next time window, the more dangerous the current operating condition in that region. The significance of the crack initiation probability assessment method is that, under an exponential distribution, the risk rate is converted into the probability of at least one crack initiation within the time window; the length of the next time window... One grinding disc rotation cycle.

[0029] Step 4: Determine the current grinding parameter operating status based on the crack initiation probability assessment results for each region of the compound semiconductor chip in the next time window; In this embodiment, step four includes the following specific contents: The probability of crack initiation in each region of the compound semiconductor chip in the next time window is obtained. The summation of the probability of crack initiation in each region of the compound semiconductor chip in the next time window is then averaged to obtain the probability of crack initiation in the next time window of the compound semiconductor chip. The probability of crack initiation in the next time window of the compound semiconductor chip is compared with a set crack initiation probability threshold. If the probability of crack initiation in the next time window of the compound semiconductor chip is greater than or equal to the set crack initiation probability threshold, it is determined that the current grinding parameters do not allow grinding to continue. If the probability of crack initiation in the next time window of the compound semiconductor chip is less than the set crack initiation probability threshold, it is determined that the current grinding parameters allow grinding to continue. It should be noted that the summation operation accumulates the crack initiation probability of all regions, reflecting the total risk of the entire chip, while the averaging operation obtains the average risk level, avoiding incomparability of values ​​due to different numbers of regions; the higher the crack initiation probability, the higher the probability that the entire chip will develop cracks in the next time window; a crack initiation probability threshold is set (which can be dynamically adjusted according to different material systems and different process stages), and the value can be determined based on process requirements or historical data.

[0030] Step 5: Adjust the grinding state of the compound semiconductor substrate based on the current grinding parameter operation status determination results; In this embodiment, step five includes the following specific contents: Obtain the current grinding parameter operation status determination result. If the current grinding parameter operation status determination result allows continued grinding, maintain or fine-tune the current grinding parameters and enter the next time window; if the current grinding parameter operation status determination result does not allow grinding to continue, execute the adjusted grinding strategy and re-enter the closed-loop control from step one. It should be noted that maintaining or fine-tuning the current grinding parameters can optimize grinding efficiency and quality while ensuring safety. The purpose of the current grinding parameter adjustment strategy is to eliminate high-risk conditions and restore safe grinding conditions. When fine-tuning parameters, the adjustment range should be limited within the process window. If it is not allowed to continue after multiple consecutive adjustments, it is determined that the composite structure of the substrate and the chip may be damaged, and grinding should be terminated and transferred to manual inspection.

[0031] The overall benefits of this plan are explained below: 1. By using an ultrasonic C-scan device to obtain the thickness of the adhesive layer, the uniformity of the adhesive layer thickness, the area ratio of the debonded area at the edge, and the acoustic reflection coefficient of the connection interface in various regions of the compound semiconductor chip, the local connection quality of the adhesive layer between the substrate and the chip can be reflected in real time, providing basic data for subsequent risk index assessment.

[0032] 2. Pre-embed piezoelectric MEMS sensors in each area of ​​the non-polished surface of the chip, and obtain the local activity of each area through bandpass filtering and wavelet packet decomposition; at the same time, use an infrared thermal imager to obtain the surface temperature field of each area, calculate the temperature change rate and temperature gradient, and obtain the local heat generation of each area, thereby comprehensively reflecting the dynamic vibration risk and thermal risk of each area during the polishing process.

[0033] 3. Real-time acquisition of spindle radial runout amplitude, grinding disk axial vibration main frequency, axial vibration main frequency amplitude, grinding slurry flow standard deviation and average flow rate, and calculation of grinding slurry flow fluctuation index; simultaneously acquiring chip substrate structural vulnerability parameters such as substrate material fracture toughness, anisotropic cleavage plane angle, and difference in thermal expansion coefficient between substrate and chip; by integrating external factors of equipment and internal factors of materials, it is possible to more accurately predict the crack initiation risk rate and crack initiation probability of each region of compound semiconductor chip in the next time window.

[0034] 4. When it is determined that grinding can continue, maintain or fine-tune the current grinding parameters and enter the next time window; when it is determined that grinding cannot continue, execute the adjusted grinding strategy and restart the closed-loop control from step one. This can reduce the risks of cracks, debonding, edge chipping, and uneven residual stress in a timely manner, and improve grinding consistency and yield. Taking into full account the characteristics of compound semiconductor materials such as high brittleness, strong anisotropy, and large differences in thermal expansion coefficients, through regionalized safety weights, crack initiation probability prediction, and closed-loop adjustment, it can effectively reduce grinding damage, improve surface quality, uniformity of material removal rate, and uniformity of residual stress distribution, and is suitable for ultra-precision grinding control of compound semiconductor substrates.

[0035] Please see Figure 3 , Figure 3 This is a schematic diagram of the structure of the ultra-precision polishing control method for compound semiconductor substrates provided in the embodiments of this application, including the following specific modules: The module includes a regional activity assessment module, a safety weight analysis module, a crack probability assessment module, a grinding state judgment module, and a grinding parameter adjustment module. The regional activity assessment module is used to collect parameters of the substrate and chip bonding layer to assess the local activity and heat generation in various regions of the compound semiconductor chip. The safety weight analysis module is used to assess the risk index of each region of the compound semiconductor chip using the collected data, and to analyze the safety weight of each region of the compound semiconductor chip based on the risk index assessment results. The crack probability assessment module is used to collect the vibration characteristic parameters of the grinding equipment and the vulnerability parameters of the chip substrate structure to assess the crack initiation probability of each region of the compound semiconductor chip in the next time window. The grinding status judgment module is used to determine the current grinding parameter operation status based on the crack initiation probability assessment results of each region of the compound semiconductor chip in the next time window. The grinding parameter adjustment module is used to adjust the grinding state of the compound semiconductor substrate based on the current grinding parameter operation status determination results.

[0036] The parameters and steps for each unit module to achieve their respective functions in the ultra-precision polishing control method for compound semiconductor substrates described above can be found in the embodiments of the ultra-precision polishing control method for compound semiconductor substrates described above, and will not be repeated here.

[0037] Embodiments of this application also provide an electronic device, including a memory, a processor, and a communication bus; the memory and the processor are connected via the communication bus. The memory stores an ultra-precision polishing control method for compound semiconductor substrates, as provided in the above embodiments, which can be loaded and executed by the processor.

[0038] The memory can be used to store instructions, programs, code, code sets, or instruction sets. The memory may include a program storage area and a data storage area. The program storage area may store instructions for implementing an operating system, instructions for at least one function, and instructions for implementing the ultra-precision polishing control method for compound semiconductor substrates provided in the above embodiments, etc. The data storage area may store data involved in the ultra-precision polishing control method for compound semiconductor substrates provided in the above embodiments, etc.

[0039] A processor may include one or more processing cores. The processor executes instructions, programs, code sets, or instruction sets stored in memory, and calls data stored in memory to perform various functions and process data as described in this application. The processor may be at least one of a specific application-specific integrated circuit, a digital signal processor, a digital signal processing device, a programmable logic device, a field-programmable gate array, a central processing unit, a controller, a microcontroller, and a microprocessor. It is understood that, for different devices, the electronic devices used to implement the above-described processor functions may also be other types, and the embodiments of this application do not specifically limit this.

[0040] A communication bus may include a pathway for transmitting information between the aforementioned components. The communication bus can be a PCI bus or an EISA bus, etc. Communication buses can be categorized into address buses, data buses, control buses, etc.

[0041] This application provides a computer-readable storage medium storing a computer program that can be loaded by a processor and executed as described in the above embodiments for an ultra-precision polishing control method for compound semiconductor substrates.

[0042] In this embodiment, a computer-readable storage medium can be a tangible device that holds and stores instructions used by an instruction execution device. The computer-readable storage medium can be, but is not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any combination thereof. Specifically, the computer-readable storage medium can be a portable computer disk, a hard disk, a USB flash drive, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), staging random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory stick, floppy disk, optical disk, magnetic disk, mechanical encoding device, or any combination thereof.

[0043] The term includes, or any other variation thereof, is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0044] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the foregoing application concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions claimed in this application.

Claims

1. A method for controlling ultra-precision grinding of compound semiconductor substrates, characterized in that, The specific steps include the following: Step 1: Collect parameters of the substrate and chip bonding layer to assess the local activity and heat generation in different regions of the compound semiconductor chip; Step one includes the following specific contents: The first step is to use an ultrasonic C-scanning device to scan and divide the adhesive layer between the compound semiconductor substrate and the chip to obtain the parameters of the adhesive layer between the substrate and the chip. The parameters of the adhesive layer between the substrate and the chip include the thickness of the adhesive layer in each region of the compound semiconductor chip, the uniformity of the adhesive layer thickness, the area ratio of the edge debonding region, and the acoustic reflection coefficient of the connection interface. The second step is to calculate the adhesive layer thickness, adhesive layer thickness uniformity, edge debonding area area, and acoustic reflection coefficient of the connection interface for each region based on the echo time difference. The third step involves pre-embedding piezoelectric MEMS sensors in various regions of the non-polished surface of the compound semiconductor chip. The vibration displacement signals obtained from these sensors are then subjected to bandpass filtering and wavelet packet decomposition to obtain the local activity corresponding to each region of the compound semiconductor chip. An infrared thermal imager is then used to acquire the surface temperature field of each region of the compound semiconductor chip, and the temperature change rate and temperature gradient of each region are calculated to obtain the local heat generation in each region of the compound semiconductor chip. Step 2: Use the collected data to assess the risk index of each region of the compound semiconductor chip, and analyze the safety weight of each region of the compound semiconductor chip based on the risk index assessment results. Step 3: Collect the vibration characteristic parameters of the grinding equipment and the vulnerability parameters of the chip substrate structure to assess the probability of crack initiation in each region of the compound semiconductor chip in the next time window; Step 4: Determine the current grinding parameter operating status based on the crack initiation probability assessment results for each region of the compound semiconductor chip in the next time window; Step 5: Adjust the grinding state of the compound semiconductor substrate based on the current grinding parameter operation status determination results.

2. The ultra-precision grinding control method for compound semiconductor substrates according to claim 1, characterized in that, Step two includes the following specific contents: The first step is to obtain the parameters of the substrate-chip adhesive layer, local activity, and heat generation, and then normalize the obtained parameters of the substrate-chip adhesive layer, local activity, and heat generation. The second step is to use the normalized data to assess the risk index of each region of the compound semiconductor chip, and obtain the risk index assessment results of each region of the compound semiconductor chip. The third step is to analyze the safety weight of each region based on the risk index of each region of the compound semiconductor chip, and obtain the analysis results of the safety weight of each region of the compound semiconductor chip.

3. The ultra-precision grinding control method for compound semiconductor substrates according to claim 2, characterized in that, Step three includes the following specific steps: The first step is to collect real-time vibration characteristic parameters of the polishing equipment and vulnerable parameters of the chip substrate structure, and evaluate the polishing slurry flow fluctuation index; The second step is to predict and assess the risk rate of crack initiation in each region of the compound semiconductor chip in the next time window. The third step is to assess the probability of crack initiation in each region within the next time window using the crack initiation risk rate of each region of the compound semiconductor chip.

4. The ultra-precision grinding control method for compound semiconductor substrates according to claim 3, characterized in that, The first step of step three includes the following specific content: Real-time acquisition of vibration characteristic parameters of the polishing equipment and vulnerable parameters of the chip substrate structure. The vibration characteristic parameters of the polishing equipment include the radial runout amplitude of the spindle, the axial vibration frequency of the polishing disk, the amplitude of the axial vibration frequency, the standard deviation of the polishing fluid flow rate, and the average flow rate. The radial runout amplitude of the spindle is obtained by calculating the peak value of the displacement signal collected by the eddy current displacement sensor in two orthogonal directions of the spindle. The axial vibration frequency and amplitude of the polishing disk are obtained by extracting the axial vibration of the polishing disk by Fourier transform after collecting the axial vibration of the polishing disk with a laser vibrometer. The standard deviation of the polishing fluid flow rate and the average flow rate are obtained by calculating the flow rate collected by the flow meter. The vulnerable parameters of the chip substrate structure include the fracture toughness of the compound semiconductor chip substrate material, the anisotropic cleavage plane angle, and the difference in thermal expansion coefficients between the substrate and the chip. The fracture toughness of the compound semiconductor chip substrate material and the difference in thermal expansion coefficients between the substrate and the chip are obtained through a material database, and the anisotropic cleavage plane angle is obtained through crystal orientation calibration and mapped to each region of the compound semiconductor chip. The grinding fluid flow rate fluctuation index is evaluated using the standard deviation and average flow rate of the grinding fluid. Specifically, the standard deviation of the grinding fluid flow rate is divided by the average flow rate to obtain the grinding fluid flow rate fluctuation index.

5. The ultra-precision grinding control method for compound semiconductor substrates according to claim 4, characterized in that, The second step in step three includes the following specific content: The safety weight analysis results of each region of the compound semiconductor chip, the vibration characteristic parameters of the polishing equipment, and the vulnerability parameters of the chip substrate structure are obtained. The safety weight analysis results of each region of the compound semiconductor chip, the vibration characteristic parameters of the polishing equipment, and the vulnerability parameters of the chip substrate structure are used to predict and evaluate the crack initiation risk rate of each region of the compound semiconductor chip in the next time window, and the crack initiation risk rate of each region of the compound semiconductor chip in the next time window is obtained.

6. The ultra-precision grinding control method for compound semiconductor substrates according to claim 5, characterized in that, The third step in step three includes the following specific content: The crack initiation probability of each region in the next time window is evaluated by using the crack initiation risk rate of each region in the compound semiconductor chip in the next time window, and the evaluation results of the crack initiation probability of each region in the next time window of the compound semiconductor chip are obtained.

7. The ultra-precision grinding control method for compound semiconductor substrates according to claim 6, characterized in that, Step four includes the following specific contents: The crack initiation probability of each region of the compound semiconductor chip in the next time window is obtained. The crack initiation probabilities of each region of the compound semiconductor chip in the next time window are summed and averaged to obtain the crack initiation probability of the compound semiconductor chip in the next time window. The crack initiation probability of the compound semiconductor chip in the next time window is compared with a set crack initiation probability threshold. If the crack initiation probability of the compound semiconductor chip in the next time window is greater than or equal to the set crack initiation probability threshold, it is determined that the current grinding parameters do not allow grinding to continue. If the crack initiation probability of the compound semiconductor chip in the next time window is less than the set crack initiation probability threshold, it is determined that the current grinding parameters allow grinding to continue.

8. The ultra-precision grinding control method for compound semiconductor substrates according to claim 7, characterized in that, Step five includes the following specific contents: Obtain the current grinding parameter operation status determination result. If the current grinding parameter operation status determination result allows to continue, maintain or fine-tune the current grinding parameters and enter the next time window; if the current grinding parameter operation status determination result does not allow to continue grinding, execute the adjusted grinding strategy and re-enter the closed-loop control from step one.

9. A method for controlling ultra-precision grinding of compound semiconductor substrates, implemented based on any one of claims 1-8, characterized in that, Includes the following specific modules: The module includes a regional activity assessment module, a safety weight analysis module, a crack probability assessment module, a grinding state judgment module, and a grinding parameter adjustment module. The regional activity assessment module is used to collect parameters of the substrate and chip adhesive layer and to assess the local activity and heat generation in each region of the compound semiconductor chip. The security weight analysis module is used to evaluate the risk index of each region of the compound semiconductor chip using the collected data, and to analyze the security weight of each region of the compound semiconductor chip based on the risk index evaluation results. The crack probability assessment module is used to collect the vibration characteristic parameters of the grinding equipment and the vulnerability parameters of the chip substrate structure, and to assess the crack initiation probability of each region of the compound semiconductor chip in the next time window. The grinding state judgment module is used to determine the current grinding parameter operation status based on the crack initiation probability assessment result of each region of the compound semiconductor chip in the next time window. The grinding parameter adjustment module is used to adjust the grinding state of the compound semiconductor substrate based on the current grinding parameter operation status determination result.

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