Alarm signal generation method, device and equipment based on SoC chip and medium

Abstract

The application discloses a kind of SoC chip-based alarm signal generation method, device, equipment and medium, it is related to digital circuit technical field.The method is applied to system on chip SoC chip, SoC chip built-in algorithm layer, algorithm layer includes multiple alarm models, the method includes: obtaining sampling signal;Based on the signal type corresponding to sampling signal, obtain the target processing logic of sampling signal;According to target processing logic, after sampling signal is handled, it is input into the alarm model corresponding to target processing logic, and the alarm signal corresponding to sampling signal is output using the alarm model corresponding to target processing logic of sampling signal.The method not only eliminates the electromagnetic interference and data distortion problem caused by long-distance data transmission, improves the alarm accuracy;Data transmission delay is saved, and the alarm model is matched with the exclusive processing logic of signal type, and the high-frequency signal, transient fault can be quickly responded and real-time alarm.

Description

Technical Field

[0001] This application relates to the field of digital circuit technology, and in particular to a method, apparatus, device, computer-readable storage medium, and computer program product for generating alarm signals based on a SoC chip. Background Technology

[0002] During the operation of equipment such as photovoltaic power plants, energy storage systems, and power converters, various operating parameters such as current, voltage, and temperature need to be collected and monitored in real time. Analyzing the sampled signals, identifying abnormal operating conditions of the equipment, and generating alarm signals in a timely manner are key aspects of ensuring the safe and stable operation of the system.

[0003] Currently, mainstream equipment monitoring and alarm solutions adopt a distributed architecture. Typically, an independent sampling unit completes signal acquisition and then transmits the data over a long distance to a backend server or host computer. Remote software algorithms then perform signal analysis, feature extraction, and fault identification. However, electromagnetic interference is easily introduced during long-distance signal transmission, causing distortion of the sampled data and resulting in low alarm accuracy. Moreover, data transmission and remote parsing have significant time delays, which cannot meet the real-time alarm requirements of high-frequency signals and transient faults in equipment (such as power equipment). Summary of the Invention

[0004] This application provides an alarm signal generation method, apparatus, device, computer-readable storage medium, and computer program product based on a SoC chip. It can achieve full-process local processing based on a System on Chip (SoC) chip, which not only eliminates electromagnetic interference and data distortion caused by long-distance data transmission and improves alarm accuracy, but also eliminates data transmission delay. By combining signal type matching with dedicated processing logic and alarm model, it can achieve rapid response and real-time alarm for high-frequency signals and transient faults.

[0005] In a first aspect, embodiments of this application provide a method for generating alarm signals based on a SoC chip. The SoC chip has a built-in algorithm layer, which includes multiple alarm models. The method includes: Acquire the sampled signal; Based on the signal type corresponding to the sampled signal, obtain the target processing logic for the sampled signal; According to the target processing logic, the sampled signal is processed and then input into the alarm model corresponding to the target processing logic. The alarm model corresponding to the target processing logic outputs the alarm signal corresponding to the sampled signal.

[0006] In one possible implementation, the SoC chip integrates a pulse width modulation (PWM) module, a hardware trigger, and an analog-to-digital converter (ADC); acquiring the sampled signal includes: A PWM module is used to generate current at multiple frequencies; By using a hardware trigger, currents of multiple frequencies are injected into the lithium battery in sequence, and an ADC with a preset sampling rate is used to synchronously oversample the voltage and current responses of the lithium battery to obtain the sampling signal corresponding to the current at each frequency. The sampling signal includes the voltage response signal and the current response signal.

[0007] In one possible implementation, the signal type is a lithium battery signal type, and the alarm model includes a pre-trained first model; according to the target processing logic, the sampled signal is processed and then input into the alarm model corresponding to the target processing logic, and the alarm model corresponding to the target processing logic outputs the alarm signal corresponding to the sampled signal, including: Based on the recursive operator, feature extraction is performed on the sampled signal to obtain the impedance fingerprint vector, which characterizes the electrochemical fingerprint. The impedance fingerprint vector is input into the pre-trained first model, which is then used to match the impedance fingerprint vector with a preset feature fingerprint vector spectrum. If the offset between the impedance fingerprint vector and the preset feature fingerprint vector spectrum exceeds a preset threshold, an alarm signal corresponding to the sampled signal is output.

[0008] In one possible implementation, the SoC chip integrates a digital signal processor (DSP) core, shared memory, and a neural network processor (NPU); inputting the impedance fingerprint vector into a pre-trained first model includes: Using the DSP core, the impedance fingerprint vector is written to shared memory; Using the NPU, impedance fingerprint vectors are read from shared memory and then input into the pre-trained first model.

[0009] In one possible implementation, the SoC chip has a built-in ADC; acquiring the sampled signal includes: Using an ADC with a preset sampling rate, the photovoltaic DC branch current of the photovoltaic module is oversampled to obtain a sampling signal, which includes the photovoltaic DC branch current signal.

[0010] In one possible implementation, the signal type is a photovoltaic signal type, and the alarm model includes a pre-trained second model; according to the target processing logic, the sampled signal is processed and then input into the alarm model corresponding to the target processing logic, and the alarm model corresponding to the target processing logic outputs the alarm signal corresponding to the sampled signal, including: Feature extraction is performed on the photovoltaic DC branch current signal in the preset frequency band of the sampled signal to obtain a multi-dimensional feature vector in the preset frequency band. The multi-dimensional feature vector includes abrupt entropy, temporal kurtosis and flatness of energy distribution in the wide frequency band. The multidimensional feature vector is input into the pre-trained second model. The classification conditions of the second model are used to match the multidimensional feature vector to obtain the classification result corresponding to the multidimensional feature vector. If the classification result is the target classification result, the alarm information corresponding to the sampling signal is output.

[0011] In one possible implementation, the SoC chip integrates a digital signal processor (DSP) core, shared memory, and a neural network processor (NPU); inputting multidimensional feature vectors into a pre-trained second model includes: Using the DSP core, multidimensional feature vectors are written into shared memory; Using the NPU, multidimensional feature vectors are read from shared memory and input into a pre-trained second model.

[0012] In one possible implementation, the SoC chip has a built-in PWM module; after outputting the alarm information corresponding to the sampled signal, the method further includes: Use the PWM module to lock the registers.

[0013] In one possible implementation, the method further includes: During the oversampling process of the photovoltaic DC branch current of the photovoltaic module, discrete frequency points are filtered out.

[0014] In one possible implementation, acquiring the sampled signal includes: The three-phase power supply circuit of the motor stator is sampled to obtain the sampling signal, which includes the three-phase current signal.

[0015] In one possible implementation, the signal type is a motor signal type, and the alarm model includes a pre-trained third model; the SoC chip has a built-in DSP core, which includes a hardware multiply-accumulate unit and an accelerator, and the DSP core has a parallel bus architecture; according to the target processing logic, the sampled signal is processed and then input into the alarm model corresponding to the target processing logic, and the alarm model corresponding to the target processing logic outputs the alarm signal corresponding to the sampled signal, including: The three-phase current signal is reduced in dimension by using a hardware multiply-accumulate unit to obtain the target three-phase current signal; Using an accelerator, the target three-phase current signal is mapped onto a rotating coordinate system to obtain the current spectrum; The current spectrum is input into the pre-trained third model, which extracts the non-harmonic components from the current spectrum. The non-harmonic components are compared with the preset non-harmonic components to obtain the comparison results. If the comparison results indicate that the non-harmonic components match the target non-harmonic components in the preset non-harmonic components, the alarm signal corresponding to the sampled signal is determined to be the alarm signal corresponding to the target non-harmonic components, and the alarm signal corresponding to the sampled signal is output.

[0016] In one possible implementation, acquiring the sampled signal includes: The power circuit corresponding to the heating element is sampled to obtain a sampling signal, which includes the power circuit current signal.

[0017] In one possible implementation, the signal type is a heating element signal type, and the alarm model includes a pre-trained fourth model; the SoC chip integrates a differential programmable gain amplifier, an ADC, and a hardware multiply-accumulate unit; according to the target processing logic, the sampled signal is processed and then input into the alarm model corresponding to the target processing logic, and the alarm model corresponding to the target processing logic outputs the alarm signal corresponding to the sampled signal, including: A differential programmable gain amplifier is used to map the power loop current signal onto the full range of the ADC to obtain the digital signal corresponding to the power loop current signal. Using a hardware multiply-accumulate unit, autocorrelation operations on digital signals are performed to extract harmonic components from the power loop current signal carrier. The harmonic components are input into the pre-trained fourth model, which is used to identify the high-frequency pulsation entropy of the harmonic components. Based on the high-frequency pulsation entropy, the physical state of the heated medium is generated, and the alarm signal corresponding to the sampled signal is determined as the alarm signal corresponding to the physical state of the heated medium. The alarm signal corresponding to the sampled signal is then output.

[0018] In one possible implementation, acquiring the sampled signal includes: The sensors of the monitored object are oversampled to obtain the sampled signal, which includes the sensor signal.

[0019] In one possible implementation, the signal type is a sensor signal type, and the alarm model includes a pre-trained fifth model; the SoC chip has a built-in accelerator; according to the target processing logic, the sampled signal is processed and then input into the alarm model corresponding to the target processing logic; the alarm model corresponding to the target processing logic outputs the alarm signal corresponding to the sampled signal, including: The physical fingerprint features of sensor signals are extracted using the autocorrelation algorithm of the accelerator. The physical fingerprint features are input into the pre-trained fifth model. The fifth model is used to identify the physical state of the monitored object based on the physical fingerprint features, determine the alarm signal corresponding to the sampling signal as the alarm information corresponding to the physical state, and output the alarm signal corresponding to the sampling signal.

[0020] Secondly, embodiments of this application provide an alarm signal generation device based on a SoC chip. The SoC chip has a built-in algorithm layer, which includes multiple alarm models. The device includes: The acquisition module is used to acquire the sampled signal; The acquisition module is also used to acquire the target processing logic of the sampled signal based on the signal type corresponding to the sampled signal; The generation module is used to process the sampled signal according to the target processing logic and input it into the alarm model corresponding to the target processing logic. The alarm model corresponding to the target processing logic is then used to output the alarm signal corresponding to the sampled signal.

[0021] Thirdly, embodiments of this application provide an electronic device, the device comprising: The processor and the memory storing computer program instructions; when the processor executes the computer program instructions, it implements the above-described alarm signal generation method based on the SoC chip.

[0022] Fourthly, embodiments of this application provide a computer storage medium on which computer program instructions are stored. When the computer program instructions are executed by a processor, they implement the above-described alarm signal generation method based on a SoC chip.

[0023] Fifthly, embodiments of this application provide a computer program product in which instructions are executed by the processor of an electronic device, enabling the electronic device to execute the aforementioned alarm signal generation method based on a SoC chip.

[0024] The alarm signal generation method, apparatus, device, computer-readable storage medium, and computer program product based on SoC chip of this application are applied to a system-on-a-chip (SoC) chip. The SoC chip has a built-in algorithm layer, which includes multiple alarm models. The method includes: acquiring a sampled signal; acquiring the target processing logic of the sampled signal based on the signal type corresponding to the sampled signal; processing the sampled signal according to the target processing logic and inputting it into the alarm model corresponding to the target processing logic; and outputting the alarm signal corresponding to the sampled signal using the alarm model corresponding to the target processing logic.

[0025] This application embodiment implements full-process local processing based on a System-on-Chip (SoC), abandoning the traditional distributed architecture of remote analysis. This not only eliminates the electromagnetic interference and data distortion problems caused by long-distance data transmission and improves alarm accuracy, but also saves data transmission latency. Combined with signal type matching dedicated processing logic and alarm model, it can achieve rapid response and real-time alarm for high-frequency signals and transient faults. Attached Figure Description

[0026] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a schematic flowchart of an alarm signal generation method based on a SoC chip provided in one embodiment of this application; Figure 2 This is a flowchart illustrating a method for generating alarm signals for a lithium battery according to another embodiment of this application; Figure 3 This is a flowchart illustrating a method for generating alarm signals for photovoltaic modules according to another embodiment of this application; Figure 4 This is a flowchart illustrating a method for generating alarm signals for a motor according to another embodiment of this application; Figure 5 This is a flowchart illustrating a method for generating an alarm signal for a heating element according to another embodiment of this application; Figure 6 This is a flowchart illustrating a method for generating alarm signals based on a SoC chip, provided in another embodiment of this application. Figure 7 This is a schematic diagram of the structure of an alarm signal generation device based on a SoC chip provided in another embodiment of this application; Figure 8 This is a schematic diagram of the structure of an electronic device provided in another embodiment of this application. Detailed Implementation

[0028] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0029] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0030] It should be noted that the acquisition, storage, use, and processing of data in this application embodiment all comply with the relevant provisions of national laws and regulations.

[0031] It should be noted that in the embodiments of this application, certain software, components, models and other existing solutions in the industry may be mentioned. These should be regarded as exemplary and are only intended to illustrate the feasibility of implementing the technical solution of this application. However, it does not mean that the applicant has used or necessarily used the solution.

[0032] As described in the background technology above, the current mainstream equipment monitoring and alarm solutions adopt a distributed architecture. Typically, after an independent sampling unit completes signal acquisition, the data is transmitted over a long distance to a backend server or host computer. The signal analysis, feature extraction, and fault identification are completed by remote software algorithms, resulting in low alarm accuracy. Moreover, there is a large time delay in data transmission and remote parsing, which cannot meet the real-time alarm requirements of high-frequency signals and transient faults in equipment (such as power equipment).

[0033] To address the problems of existing technologies, this application provides a method, apparatus, device, computer-readable storage medium, and computer program product for generating alarm signals based on a SoC chip. The alarm signal generation method based on a SoC chip provided in this application uses the SoC chip as its execution entity. This application achieves full-process local processing based on a SoC, abandoning the traditional distributed architecture of remote analysis. This eliminates electromagnetic interference and data distortion problems caused by long-distance data transmission, improving alarm accuracy; it also eliminates data transmission latency. Combined with signal type-matching dedicated processing logic and alarm models, it can achieve rapid response and real-time alarms for high-frequency signals and transient faults.

[0034] The alarm signal generation method based on SoC chip provided in the embodiments of this application will be described in detail below.

[0035] like Figure 1 As shown in the embodiment of this application, the alarm signal generation method based on SoC chip is applied to a system-on-a-chip (SoC) chip. The SoC chip has a built-in algorithm layer, which includes multiple alarm models. The method includes the following steps S110 to S130.

[0036] S110, Acquire the sampling signal.

[0037] In some embodiments, the SoC chip is deployed on the monitoring device, and the SoC chip acquires various sampling signals during the operation of the monitoring device in real time. That is, the SoC chip completes local signal acquisition by relying on its integrated sampling circuit, without transmitting raw data to external devices, thus providing the original data source for subsequent signal processing and fault alarm.

[0038] It should be noted that the type and frequency of the sampling signal can be set in advance according to requirements and can be changed depending on the monitoring equipment.

[0039] In one example, the sampled signals include, but are not limited to, physical signals that can reflect the operating status of equipment, such as current signals, voltage signals, and temperature signals generated during the operation of photovoltaic power plants, energy storage systems, and power converters.

[0040] S120. Based on the signal type corresponding to the sampled signal, obtain the target processing logic of the sampled signal.

[0041] In some embodiments, different types of sampled signals exhibit significant differences in waveform characteristics, interference patterns, and analysis dimensions, and therefore require different signal processing methods. Therefore, the first step is to identify the type of the currently acquired sampled signal to determine its signal type. Then, based on a pre-established correspondence between signal types and processing logic, the target processing logic matching the sampled signal is determined.

[0042] S130. According to the target processing logic, the sampled signal is processed and then input into the alarm model corresponding to the target processing logic. The alarm model corresponding to the target processing logic is used to output the alarm signal corresponding to the sampled signal.

[0043] In some embodiments, the sampled signal is processed according to the target processing logic to obtain processed features. The processed features are then input into the alarm model corresponding to the target processing logic, and the alarm model corresponding to the target processing logic outputs the alarm signal corresponding to the sampled signal.

[0044] In one example, following the target processing logic, the sampled signal is subjected to noise reduction, feature extraction, and dimensional transformation to obtain processed features. The processed features include effective features in the sampled signal that characterize abnormal operating conditions of the equipment.

[0045] It should be noted that the SoC chip has a built-in algorithm layer, which includes multiple alarm models. These alarm models correspond to the target processing logic and are pre-trained. For example, the models can be machine learning models.

[0046] This application embodiment implements full-process local processing based on a System-on-Chip (SoC), abandoning the traditional distributed architecture of remote analysis. This not only eliminates the electromagnetic interference and data distortion problems caused by long-distance data transmission and improves alarm accuracy, but also saves data transmission latency. Combined with signal type matching dedicated processing logic and alarm model, it can achieve rapid response and real-time alarm for high-frequency signals and transient faults.

[0047] In some embodiments, the SoC chip integrates a pulse width modulation (PWM) module, a hardware trigger, and an analog-to-digital converter (ADC); S110 specifically may include: A PWM module is used to generate current at multiple frequencies; By using a hardware trigger, currents of multiple frequencies are injected into the lithium battery in sequence, and an ADC with a preset sampling rate is used to synchronously oversample the voltage and current responses of the lithium battery to obtain the sampling signal corresponding to the current at each frequency. The sampling signal includes the voltage response signal and the current response signal.

[0048] In some embodiments, the monitoring device includes a Battery Management System (BMS) device, with a SoC chip deployed within the BMS device to monitor the lithium battery. The SoC chip's PWM module generates an excitation current signal ranging from 0.1 kHz to 10 kHz. This excitation current signal is then sequentially injected into the lithium battery via a hardware trigger on the SoC chip. After the excitation current signal is injected, the lithium battery generates voltage and current responses. Using an ADC with a preset sampling rate, the voltage and current responses of the lithium battery are synchronously oversampled to obtain a sampled signal corresponding to the current at each frequency. This sampled signal includes both the voltage and current response signals.

[0049] In some embodiments, synchronous oversampling of the voltage and current responses of the lithium battery includes: performing nanosecond-level synchronous continuous oversampling of the voltage and current responses of the lithium battery to capture the dynamic characteristics of the lithium battery at high frequencies and sense the internal chemical reactions of the battery.

[0050] It should be noted that the preset sampling rate of the ADC is set in advance according to the requirements. For example, the preset sampling rate is 4 Msps.

[0051] This application's embodiments employ a PWM module to generate multi-frequency excitation current, enabling comprehensive detection of lithium battery electrical characteristics across a wide frequency range, covering latent fault characteristics in different frequency bands. Furthermore, it eliminates the need for expensive external monitoring modules, reducing costs.

[0052] In some embodiments, the signal type is a lithium battery signal type, and the alarm model includes a pre-trained first model; such as Figure 2 As shown, S130 may specifically include S210 to S220.

[0053] S210. Based on the recursive operator, feature extraction is performed on the sampled signal to obtain the impedance fingerprint vector, which represents the electrochemical characteristic fingerprint.

[0054] In some embodiments, the recursive Goertzel algorithm is used to extract features from the sampled signal based on the recursive operator to obtain the impedance fingerprint vector, which represents the electrochemical fingerprint.

[0055] Specifically, utilizing the recursive computation characteristics of the Goertzel algorithm, the amplitude and phase of the sampled excitation current signal at a specific frequency (e.g., 1kHz kinetic point, 10Hz diffusion point) are analyzed. Then, based on the amplitude and phase, impedance parameters are calculated, including impedance magnitude and impedance phase. Based on these impedance parameters, an impedance fingerprint vector is constructed. This vector characterizes the electrochemical fingerprint, including the real part (resistivity), imaginary part (capacitance), phase shift, and impedance magnitude.

[0056] The formula for the recursive operation of the Goertzel algorithm is shown in formula (1) below. The amplitude and phase of the sampled signal can be calculated based on q[n] and q[n-1]. The formula for calculating the amplitude and phase is existing technology and will not be elaborated here.

[0057] (1) In formula (1), x[n] is the nth input sampled signal, f target f is the frequency of the excitation current signal. s Let q[n] be the sampling rate, and q[n] be the recursive state variable. The initial conditions for the operation are q[-2]=0 and q[-1]=0.

[0058] It should be noted that the Goertzel algorithm compresses tens of thousands of sampling points into a set of complex impedance fingerprint vectors, which greatly saves the space of the chip's static random access memory (SRAM).

[0059] S220. Input the impedance fingerprint vector into the pre-trained first model, and use the first model to match the impedance fingerprint vector with the preset feature fingerprint vector spectrum. If the offset between the impedance fingerprint vector and the preset feature fingerprint vector spectrum exceeds a preset threshold, output the alarm signal corresponding to the sampled signal.

[0060] In some embodiments, the first model includes a binary neural network (BNN) model. The impedance fingerprint vector is input into the pre-trained BNN model, which then matches the impedance fingerprint vector with a preset feature fingerprint vector map. If the offset between the impedance fingerprint vector and the preset feature fingerprint vector map exceeds a preset threshold, an alarm signal corresponding to the sampled signal is output.

[0061] Specifically, an offset exceeding a preset threshold indicates that the solid electrolyte interphase (SEI) film state is characterized by a distortion in the radius of curvature, or an abnormal decrease in charge transfer impedance Rct due to lithium dendrite growth, or a rightward shift in the real intercept Rohm, i.e., internal resistance drift. In other words, an offset exceeding the preset threshold indicates that the lithium battery is in a state of thermal runaway, requiring an alarm.

[0062] Understandably, the BNN model is a lightweight model that can be quickly pre-trained, reducing the difficulty of deployment.

[0063] In some embodiments, the first model may also be an INT8 quantized neural network model.

[0064] In some embodiments, the hard core (HCORE) architecture of the SoC chip isolates the charging and discharging logic control of the lithium battery and the extraction of fault diagnosis features at the physical hardware layer. Through multi-threaded isolation, it can be ensured that the diagnosis process does not affect the real-time control performance.

[0065] This application uses a streaming recursive operator instead of a discrete Fourier transform to achieve full electrochemical impedance spectroscopy (EIS) diagnostics on an embedded chip with small memory. This enables real-time online monitoring of the lithium battery's operating status and allows for faster detection of internal micro-short circuits (relative to temperature sensing, which can detect them 15-30 minutes earlier), thus improving the safety of the lithium battery.

[0066] In some embodiments, the SoC chip integrates a Digital Signal Processor (DSP) core, shared memory, and a Neural Processing Unit (NPU); in S220 above, inputting the impedance fingerprint vector into the pre-trained first model may include: Using the DSP core, the impedance fingerprint vector is written to shared memory; Using the NPU, impedance fingerprint vectors are read from shared memory and then input into the pre-trained first model.

[0067] In this embodiment, the impedance fingerprint vector is normalized, and the normalized impedance fingerprint vector is written to shared memory using the DSP core, where the NPU performs the inference task. Specifically, the NPU reads the impedance fingerprint vector from the shared memory and executes the pre-trained first model in parallel using the NPU's internal systolic array or multiply-accumulate (MAC) array.

[0068] In some embodiments, the training process of the first model is as follows: A sample set is established based on the impedance fingerprint vectors of lithium batteries under different health conditions. The sample set is divided into a training set and a test set according to the sampling method; the training set is used to train the first model, and the test set is used to verify the accuracy of the first model's prediction results. That is, a trained first model and a preset feature fingerprint vector map under different health conditions are obtained by learning the impedance fingerprint vectors using a lightweight first model.

[0069] This application embodiment relies on the division of labor and cooperation between DSP and NPU to achieve decoupling of data flow and model inference, thereby improving the utilization rate of hardware resources.

[0070] In some embodiments, the SoC chip has a built-in ADC; S110 above may specifically include: Using an ADC with a preset sampling rate, the photovoltaic DC branch current of the photovoltaic module is oversampled to obtain a sampling signal, which includes the photovoltaic DC branch current signal.

[0071] The photovoltaic DC branch current includes string current and bus current.

[0072] In some embodiments, the monitoring device includes a photovoltaic module, and a SoC chip is deployed on the photovoltaic module. The SoC chip has a built-in ADC, which uses a preset sampling rate to oversample the photovoltaic DC branch current of the photovoltaic module to obtain a sampled signal, which includes the photovoltaic DC branch current signal.

[0073] It should be noted that the preset sampling rate of the ADC is set in advance according to the requirements. For example, the preset sampling rate is 4 Msps.

[0074] It should be noted that the acquisition of photovoltaic DC branch current signals aims to capture the characteristic fingerprint of the electric arc in the 10kHz to 100kHz frequency band. The electric arc fingerprint is not an independent signal, but a high-frequency component parasitic on the DC branch current, and can only be obtained by sampling the branch current.

[0075] In some embodiments, the SoC chip has a built-in DSP core, which is used to start an ADC with a preset sampling rate. The ADC with the preset sampling rate is used to continuously oversample the photovoltaic DC branch current of the photovoltaic module to obtain a sampling signal.

[0076] The embodiments of this application perform oversampling on the photovoltaic DC branch current using an ADC, which can improve the sampling equivalent accuracy and suppress system noise.

[0077] In some embodiments, the signal type is a photovoltaic signal type, and the alarm model includes a pre-trained second model; such as Figure 3As shown, the above S130 may specifically include S310 to S320.

[0078] S310. Extract features from the photovoltaic DC branch current signal in the preset frequency band of the sampled signal to obtain a multi-dimensional feature vector in the preset frequency band. The multi-dimensional feature vector includes abrupt entropy, time-domain kurtosis and flatness of energy distribution in the wide frequency band.

[0079] In some embodiments, the electric arc is essentially air ionization, and the resulting noise exhibits continuous pink noise characteristics in the frequency domain, with energy decreasing as frequency increases. Therefore, to achieve alarm for DC arcing in photovoltaic modules, it is necessary to extract features from the photovoltaic DC branch current signal in the sampled signal within a preset frequency band to obtain a multi-dimensional feature vector within the preset frequency band.

[0080] Specifically, the uncertainty of the current waveform increases abruptly in a very short time to obtain the abrupt entropy; the sharp pulse pattern generated by the electric arc is captured to obtain the time-domain kurtosis; and the flatness of the energy distribution in the broadband is identified by using a wideband filter bank or Fast Fourier Transform (FFT) to distinguish it from the steep peaks of inverter harmonics.

[0081] Understandably, DC arcing is the leading cause of fires in distributed photovoltaic systems, so it is necessary to promptly issue DC arc warnings for photovoltaic modules to improve safety.

[0082] In some embodiments, the preset frequency band is set in advance according to actual needs, and the frequency band can be dynamically adjusted for different loads, and a learnable wavelet basis is used for feature extraction.

[0083] In some embodiments, the DSP kernel is used to extract features from the photovoltaic DC branch current signal in the sampled signal under a preset frequency band to obtain a multi-dimensional feature vector within the preset frequency band.

[0084] S320. Input the multidimensional feature vector into the pre-trained second model, use the classification conditions of the second model to match the multidimensional feature vector, obtain the classification result corresponding to the multidimensional feature vector, and output the alarm information corresponding to the sampling signal when the classification result is the target classification result.

[0085] It should be noted that the classification criteria include a classification threshold. The classification threshold can be adjusted according to changes in the workload.

[0086] In some embodiments, the second model includes a lightweight convolutional neural network (Tiny-CNN) model, which can be a time-frequency domain fusion CNN model optimized for embedded devices. Multidimensional feature vectors are input into the pre-trained Tiny-CNN model, and the classification conditions of the Tiny-CNN model are used to match the multidimensional feature vectors to obtain the classification result corresponding to the multidimensional feature vectors. The classification conditions are binary classification decision conditions, meaning the classification result can be a target classification result and a normal classification result. The target classification result represents the fault classification result. If the classification result is a fault classification result, the alarm information corresponding to the sampled signal is output.

[0087] In one example, the alarm message is an arc alarm.

[0088] Understandably, the Tiny-CNN model is a lightweight model that can be quickly pre-trained, reducing the difficulty of deployment.

[0089] In some embodiments, the arc detection task is isolated from the control maximum power point tracking (MPPT) thread through a multi-threaded architecture, so that the two do not interfere with each other.

[0090] In some embodiments, a pre-trained second model is executed in parallel using the hardware MAC unit within the DSP core and Single Instruction Multiple Data (SIMD) extended instructions (such as single-cycle vector multiply-add instructions in Ceva or Cadence DSPs), inputting multi-dimensional feature vectors into the pre-trained second model. The second model is pre-processed with INT8 quantization and pruning to adapt to the limited cache and computing power of the DSP, requiring no additional hardware units.

[0091] In this embodiment, the Direct Memory Access (DMA) controller uses a pipelined design to overlap the ADC data stream with the computation process, which can reduce memory access wait times.

[0092] Specifically, the DMA controller leverages the time-sharing parallelism of the pipeline to split the tasks of continuously transferring ADC sampling data streams and DSP computation tasks into different stages of the pipeline for concurrent execution. At the front end of the pipeline, DMA performs a direct pass-through storage of ADC sampling data to the on-chip cache; in the same clock cycle, the subsequent computation unit, the DSP core, reads the data already loaded into the cache and executes the pre-trained second model to perform model inference. This eliminates the need for frequent CPU intervention in read / write operations, avoids idle periods of the computation unit waiting for external memory data, and significantly reduces memory access wait overhead.

[0093] The embodiments of this application use the classification conditions of the second model to complete the feature vector matching and determination. The operation logic is simple and the inference delay is low. It can quickly output the arc fault determination result and trigger the alarm, which meets the application requirements of rapid early warning of photovoltaic DC arc faults and ensures the operational safety of photovoltaic modules and lines.

[0094] In some embodiments, the SoC chip integrates a digital signal processor (DSP) core, shared memory, and a neural network processor (NPU); in the above-described S320, inputting the multidimensional feature vector into the pre-trained second model may include: Using the DSP core, multidimensional feature vectors are written into shared memory; Using the NPU, multidimensional feature vectors are read from shared memory and input into a pre-trained second model.

[0095] In this embodiment, the multidimensional feature vectors are normalized, and the normalized multidimensional feature vectors are written into shared memory using the DSP kernel, where the NPU performs the inference task. Specifically, the NPU reads the multidimensional feature vectors from the shared memory and executes the pre-trained first model in parallel using the NPU's internal systolic array or MAC array.

[0096] The present application embodiment relies on the division of labor and cooperation between DSP and NPU for abnormal alarm of photovoltaic modules, realizing the decoupling of data flow and model inference, and improving the utilization rate of hardware resources.

[0097] In some embodiments, the monitoring device can deploy multiple SoC chips, which share a model but not data, thereby improving generalization performance.

[0098] In some embodiments, the second model can be an INT8 format model pre-trained in the cloud and transmitted to the SoC chip. The second model can be deployed using toolchains such as the photovoltaic arc detection scenario (Edge AI Studio).

[0099] In some embodiments, the probability of arc occurrence can be predicted based on timing characteristics, allowing for pre-action.

[0100] In some embodiments, the SoC chip has a built-in PWM module; after S320 above, the method may further include: Use the PWM module to lock the registers.

[0101] In some embodiments, after an arc alarm, the DSP core immediately sets the emergency block bit of the PWM module (such as forcing high impedance or outputting low level) by writing to the register, cuts off the power stage switching transistor drive signal, and achieves physical disconnection.

[0102] In some embodiments, after an arc alarm, the NPU sends an alarm signal to the DSP core via an interrupt or status register. The DSP core responds immediately, triggering the PWM module inside the SoC chip to urgently block the register, forcibly shutting down the drive pulses of all power switching transistors, achieving millisecond-level active physical disconnection, thereby cutting off the arc energy.

[0103] This application embodiment utilizes a PWM module to block registers and actively physically disconnect branches, reducing safety risks such as fire and device damage caused by arc expansion.

[0104] In some embodiments, the method may further include: During the oversampling process of the photovoltaic DC branch current of the photovoltaic module, discrete frequency points are filtered out.

[0105] In some embodiments, the real-time switching frequency f of the real-time locked inverter is... sw (Typically fluctuating between 16kHz and 32kHz), accurately locking the discrete frequency points of interference that drift with operating conditions, and filtering out discrete frequency points directly on the acquisition link by hardware during the oversampling of the photovoltaic DC branch current of the photovoltaic module.

[0106] The embodiments of this application improve the reliability of arc fault identification by filtering out discrete frequency interference, eliminating inherent fixed frequency noise in photovoltaic systems, preserving the wideband characteristics of electric arcs, and eliminating such interference.

[0107] In some embodiments, the above S110 may specifically include: The three-phase power supply circuit of the motor stator is sampled to obtain the sampling signal, which includes the three-phase current signal.

[0108] In this embodiment, the monitoring device includes a motor, and a SoC chip is deployed on the motor. The SoC chip has a built-in ADC. During the current loop control gap of the motor stator three-phase power supply circuit, the ADC is triggered by a hardware interrupt to sample the motor stator three-phase power supply circuit and obtain the sampled signal.

[0109] This application embodiment obtains a sampling signal by sampling the three-phase power supply circuit of the motor stator, which enables motor fault alarm.

[0110] In some embodiments, the signal type is a motor signal type, and the alarm model includes a pre-trained third model; the SoC chip has a built-in DSP core, which includes a hardware multiply-accumulate unit and an accelerator, and the DSP core uses a parallel bus architecture; such as Figure 4 As shown, the above S130 may specifically include S410 to S430.

[0111] S410. Using a hardware multiply-accumulate unit, the three-phase current signal is reduced in dimension to obtain the target three-phase current signal.

[0112] In some embodiments, when the monitoring device is a motor, the SoC chip is a Motor Current Signature Analysis (MCSA) processing chip, which has a highly parallel DSP core and a single-cycle multi-channel hardware multiply-accumulate (MAC) array, i.e., a hardware multiply-accumulate unit. The hardware multiply-accumulate unit is first used to perform dimensionality reduction processing on the three-phase current signal to obtain the target three-phase current signal.

[0113] It should be noted that the DSP core can execute multiple MAC instructions in a single cycle.

[0114] In some embodiments, when the monitoring device is a motor, the SoC chip integrates a floating-point / fixed-point acceleration unit. Using the hardware multiply-accumulate unit and the floating-point / fixed-point acceleration unit in collaborative computation, the three-phase current signal is reduced in dimensionality to obtain the target three-phase current signal.

[0115] In some embodiments, when the monitoring device is a motor, the SoC chip integrates a floating-point / fixed-point acceleration unit, a hardware multiply-accumulate unit, a Level 1 cache (L1 Cache), and an on-chip SRAM high-speed storage module. The three-phase current signals acquired by the ADC are directly transferred to the L1 Cache or SRAM via DMA in a zero-wait manner. The hardware multiply-accumulate unit and the floating-point / fixed-point acceleration unit work together in parallel to perform filtering, quantization, and dimensionality reduction processing on the three-phase current signals to obtain the target three-phase current signals.

[0116] S420. Using an accelerator, the target three-phase current signal is mapped onto a rotating coordinate system to obtain the current spectrum.

[0117] In some embodiments, the accelerator is a hardware trigonometric accelerator (CORDIC). Using the hardware trigonometric accelerator, nanosecond-level coordinate transformations are achieved, mapping the target three-phase current signal (time-domain signal) to a rotating coordinate system to obtain the current spectrum.

[0118] S430. Input the current spectrum into the pre-trained third model, use the third model to extract the non-harmonic components from the current spectrum, compare the non-harmonic components with the preset non-harmonic components, obtain the comparison result, and if the comparison result indicates that the non-harmonic component matches the target non-harmonic component in the preset non-harmonic components, determine that the alarm signal corresponding to the sampled signal is the alarm signal corresponding to the target non-harmonic component, and output the alarm signal corresponding to the sampled signal.

[0119] In some embodiments, the third model includes a lightweight machine learning (TinyML) model. Taking advantage of DSP characteristics, the weights in the third model are Q-formatted, and a single-cycle MAC instruction is used to efficiently calculate the autocorrelation function to identify the motor bearing fault frequency. Specifically, the third model is used to extract non-harmonic components from the current spectrum. The extracted non-harmonic components are compared with preset non-harmonic components to obtain a comparison result. If the comparison result indicates that the non-harmonic component matches the target non-harmonic component in the preset non-harmonic components, the alarm signal corresponding to the sampled signal is determined to be the alarm signal corresponding to the target non-harmonic component, and the alarm signal corresponding to the sampled signal is output. That is, utilizing the parallel computing power of the DSP, while monitoring the main frequency energy, a digital filter (IIR / FIR) is used to separate the weak signal fault fingerprint near the carrier frequency band in real time.

[0120] The alarm signal corresponding to the target non-harmonic component can be a mechanical alarm signal and / or an electrical alarm signal.

[0121] It should be noted that the parallel computing power of the DSP enables asynchronous parallel execution of fault feature vector extraction and TinyML model inference while executing the motor vector control command stream.

[0122] This application embodiment utilizes the high-speed computing power of a highly parallel DSP core to perform real-frequency domain decomposition of the motor stator current through a hardware-based MAC (multiply-accumulate) array, thereby realizing non-intrusive fault diagnosis of the motor.

[0123] In some embodiments, the above S110 may specifically include: The power circuit corresponding to the heating element is sampled to obtain a sampling signal, which includes the power circuit current signal.

[0124] In some embodiments, such as in fine chemicals, food and pharmaceuticals, and high-end kitchen appliances, monitoring the state of a medium (e.g., viscosity, boiling point, water content) typically requires expensive invasive sensors. These sensors are susceptible to corrosion, have short lifespans, and pose hygiene risks. To address this issue, the monitoring device in this application includes a heating element on which a SoC chip is deployed. The power circuit corresponding to the heating element is sampled to obtain a sampling signal, which is then used to monitor the state of the medium.

[0125] In some embodiments, the SoC chip has a built-in ADC. Using the ADC with a preset sampling rate, the power circuit corresponding to the heating element is sampled to obtain a sampled signal, which includes the power circuit current signal.

[0126] It should be noted that the preset sampling rate of the ADC is set in advance according to requirements. For example, the preset sampling rate is 4Msps. This preset sampling rate allows the ADC to sample even weak signals.

[0127] In some embodiments, during the power loop current signal acquisition stage, a front-end sampling circuit is constructed using a low-resistance, high-precision, low-temperature drift shunt resistor, and the obtained power loop current signal includes a micro current signal.

[0128] This application embodiment considers that the changes in molecular thermal motion of any heating load during the heating process will have a reverse effect on the impedance characteristics of the heating element. Therefore, the power circuit corresponding to the heating element is sampled to obtain the sampling signal, thereby realizing sensorless medium state monitoring.

[0129] In some embodiments, the signal type is a heating element signal type, and the alarm model includes a pre-trained fourth model; the SoC chip integrates a differential programmable gain amplifier, an ADC, and a hardware multiply-accumulate unit; such as Figure 5 As shown, the above S130 may specifically include S510 to S530.

[0130] The S510 uses a differential programmable gain amplifier to map the power loop current signal to the full range of the ADC, thus obtaining the digital signal corresponding to the power loop current signal.

[0131] In some embodiments, a differential programmable gain amplifier is used to map the micro current signal corresponding to the power loop current signal onto the full range of the ADC to obtain the digital signal corresponding to the power loop current signal.

[0132] S520 uses a hardware multiply-accumulate unit to perform autocorrelation calculations on digital signals and extract harmonic components from the power loop current signal carrier.

[0133] In some embodiments, the SoC chip integrates a DSP core, which includes a single-cycle hardware multiply-accumulate unit. Utilizing the hardware multiply-accumulate unit, autocorrelation operations on the digital signal are performed within milliseconds to extract harmonic components from the power loop current signal carrier, thereby achieving background noise removal and load feature fingerprint extraction.

[0134] S530. Input the harmonic components into the pre-trained fourth model, use the fourth model to identify the high-frequency pulsation entropy of the harmonic components, generate the physical state of the heated medium based on the high-frequency pulsation entropy, determine the alarm signal corresponding to the sampled signal as the alarm signal corresponding to the physical state of the heated medium, and output the alarm signal corresponding to the sampled signal.

[0135] In some embodiments, the fourth model includes a lightweight machine learning (TinyML) model. Harmonic components are input into a pre-trained TinyML model, which identifies the high-frequency pulsation entropy of the harmonic components. A correspondence exists between the high-frequency pulsation entropy and the physical state of the heated medium. Based on this correspondence, the physical state of the heated medium corresponding to the high-frequency pulsation entropy of the harmonic components identified by the TinyML model is determined. Furthermore, the alarm signal corresponding to the sampled signal is determined to be the alarm signal corresponding to the physical state of the heated medium, and the alarm signal corresponding to the sampled signal is output.

[0136] It should be noted that when a medium undergoes a physical state change (such as water turning into steam or a fluid becoming more viscous), it will generate a characteristic high-frequency entropy.

[0137] In some embodiments, the SoC chip has a built-in PWM module. The duty cycle of the PWM module is changed using the DSP core, the delay time of the current response is measured, and the thermal inertia of the heated medium is calculated using the first-order thermodynamic equation shown in formula (2): (2) Where P(t) is the instantaneous power loss of the heating element, and C th For thermal inertia parameters, T represents the rate of change of temperature over time, where T represents the real-time thermodynamic temperature of the heated medium. amb R represents the ambient reference temperature. th This indicates the heat dissipation resistance of the heated medium to the environment.

[0138] Thermal inertia parameter acts as a low-pass filter for high-frequency ripple entropy. A larger thermal inertia parameter smooths out high-frequency ripple and reduces high-frequency ripple entropy; conversely, a smaller thermal inertia parameter results in a larger high-frequency ripple entropy. The high-frequency ripple entropy is calculated based on the current response delay time and thermal inertia parameter.

[0139] This application embodiment can achieve sensorless medium state monitoring by processing the sampling signal of the power circuit corresponding to the heating element.

[0140] This application's embodiments achieve a mapping from time-domain fluctuations to physical properties. For industrial reactors, no openings are required; the endpoint of the chemical reaction is determined by the heating power curve. For commercial cooking robots, standardized dishes can be achieved, automatically identifying ingredient quantities and matching optimal heat.

[0141] In some embodiments, the above S110 may specifically include: The sensors of the monitored object are oversampled to obtain the sampled signal, which includes the sensor signal.

[0142] In some embodiments, the SoC chip has a built-in ADC. Using the ADC with a preset sampling rate, the sensor of the monitored object is oversampled to obtain a sampled signal, which includes the sensor signal. The sensor signal includes micro-vibration or electrical characteristic signals.

[0143] It should be noted that the preset sampling rate of the ADC is set in advance according to the requirements. For example, the preset sampling rate is 4 Msps.

[0144] In some embodiments, the monitored object is not limited to electrical equipment. The sensors used to monitor the object include sensors of the types such as current, acoustic, vibration, and piezoelectric sensors.

[0145] In one example, a piezoelectric sensor is used to monitor the pulse of the object being monitored. The pulse from the piezoelectric sensor is oversampled to obtain a sampled signal.

[0146] In another example, an acoustic sensor is used to monitor the ultrasonic characteristics of the object at the moment of friction. The ultrasonic characteristics of the acoustic sensor at the moment of friction are oversampled to obtain a sampled signal.

[0147] In another example, a vibration sensor is used to monitor specific vibration frequencies of the monitored object (e.g., the specific vibration frequencies of esophageal muscle contractions during rumination in cattle) and heart sounds. The specific vibration frequencies of the vibration sensor and the heart sound signals are oversampled to obtain sampled signals.

[0148] The embodiments of this application can sample multimodal sampling signals of different monitoring objects in resource-constrained environments, making the SoC chip versatile and enabling it to be embedded in monitoring objects such as ear tags, rings or drone rotors, thereby reducing resource costs.

[0149] In some embodiments, the signal type is a sensor signal type, and the alarm model includes a pre-trained fifth model; the SoC chip has a built-in accelerator; such as Figure 6 As shown, the above S130 may specifically include S610 to S620.

[0150] S610: Using the autocorrelation algorithm of the accelerator, extract the physical fingerprint features of the sensor signal.

[0151] In some embodiments, high-frequency environmental noise in the sensor signal is removed at the digital front end using a hardware filter to obtain the target sensor signal. The physical fingerprint features of the target sensor signal are then extracted using an autocorrelation algorithm based on the accelerator.

[0152] In one example, the autocorrelation algorithm of the accelerator is used to analyze the higher-order derivatives of the pulse wave and calculate the physical fingerprint features, which are the vascular elasticity coefficients.

[0153] In another example, the autocorrelation algorithm of the accelerator is used to perform time-frequency transformation on the ultrasonic features at the moment of friction to identify physical fingerprint features, which are the microscopic texture information of the object's surface.

[0154] In another example, the physical fingerprint features of the sensor signal are obtained by extracting the specific vibration frequency of the esophageal muscle contraction during rumination in cattle, as well as the variation entropy in the heart sound S1 / S2 signal.

[0155] In the embodiments provided in this application, physical fingerprint feature extraction is offloaded to a hardware accelerator, ensuring that the CPU core is always under low load, thereby achieving stable computing power. The hardware accelerator is capable of extracting microscopic fingerprint features.

[0156] In some embodiments, the hardware accelerator includes a mapping library that maps sensor signals to physical fingerprint features. Based on this, cross-industry applications, from "smart cow collars" to "robot skin," can be achieved simply by replacing the sensor, without modifying the underlying kernel.

[0157] S620. Input the physical fingerprint features into the pre-trained fifth model. Using the fifth model, identify the physical state of the monitored object based on the physical fingerprint features, determine the alarm signal corresponding to the sampling signal as the alarm information corresponding to the physical state, and output the alarm signal corresponding to the sampling signal.

[0158] In some embodiments, the SoC chip integrates a DSP core. Using the DSP core, physical fingerprint features are input into a pre-trained fifth model. The fifth model then identifies the physical state of the monitored object based on the physical fingerprint features, determines the alarm signal corresponding to the sampled signal as the alarm information corresponding to the physical state, and outputs the alarm signal corresponding to the sampled signal. There is a mapping relationship between the physical fingerprint features and the physical state of the monitored object.

[0159] In some embodiments, the SoC chip employs an intermittent computing mode, placing the DSP core in a microampere-level deep sleep state during non-working intervals, retaining only ADC trigger listening, in order to achieve long-term operation in a battery-powered environment.

[0160] It is understood that the embodiments of this application can decouple parasitic high-frequency signals on the surface or in the circuit of the monitored object through sensors, and can realize non-invasive determination of the internal physical state of the monitored object (such as health status, material properties, structural damage).

[0161] The embodiments of this application can identify the physical state of the monitored object based on its physical fingerprint characteristics and issue corresponding alarms, thereby realizing non-intrusive real-time monitoring and intelligent early warning for different monitored objects.

[0162] Based on the alarm signal generation method based on the SoC chip provided in the above embodiments, this application also provides specific implementation methods of the alarm signal generation device based on the SoC chip. Please refer to the following embodiments.

[0163] See Figure 7 The alarm signal generation device 700 based on a SoC chip provided in this application embodiment is applied to a system-on-a-chip (SoC) chip. The SoC chip has a built-in algorithm layer, which includes multiple alarm models. The device 700 includes: Acquisition module 710 is used to acquire the sampled signal; The acquisition module 710 is also used to acquire the target processing logic of the sampled signal based on the signal type corresponding to the sampled signal. The generation module 720 is used to process the sampled signal according to the target processing logic and input it into the alarm model corresponding to the target processing logic, and then use the alarm model corresponding to the target processing logic to output the alarm signal corresponding to the sampled signal.

[0164] In some embodiments, the SoC chip integrates a pulse width modulation (PWM) module, a hardware trigger, and an analog-to-digital converter (ADC); the acquisition module 710 can specifically be used for: A PWM module is used to generate current at multiple frequencies; By using a hardware trigger, currents of multiple frequencies are injected into the lithium battery in sequence, and an ADC with a preset sampling rate is used to synchronously oversample the voltage and current responses of the lithium battery to obtain the sampling signal corresponding to the current at each frequency. The sampling signal includes the voltage response signal and the current response signal.

[0165] In some embodiments, the signal type is a lithium battery signal type, and the alarm model includes a pre-trained first model; the generation module 720 can specifically be used for: Based on the recursive operator, feature extraction is performed on the sampled signal to obtain the impedance fingerprint vector, which characterizes the electrochemical fingerprint. The impedance fingerprint vector is input into the pre-trained first model, which is then used to match the impedance fingerprint vector with a preset feature fingerprint vector spectrum. If the offset between the impedance fingerprint vector and the preset feature fingerprint vector spectrum exceeds a preset threshold, an alarm signal corresponding to the sampled signal is output.

[0166] In some embodiments, the SoC chip integrates a digital signal processor (DSP) core, shared memory, and a neural network processor (NPU); the generation module 720 can specifically be used for: Using the DSP core, the impedance fingerprint vector is written to shared memory; Using the NPU, impedance fingerprint vectors are read from shared memory and then input into the pre-trained first model.

[0167] In some embodiments, the SoC chip has a built-in ADC; the acquisition module 710 can specifically be used for: Using an ADC with a preset sampling rate, the photovoltaic DC branch current of the photovoltaic module is oversampled to obtain a sampling signal, which includes the photovoltaic DC branch current signal.

[0168] In some embodiments, the signal type is a photovoltaic signal type, and the alarm model includes a pre-trained second model; the generation module 720 can specifically be used for: Feature extraction is performed on the photovoltaic DC branch current signal in the preset frequency band of the sampled signal to obtain a multi-dimensional feature vector in the preset frequency band. The multi-dimensional feature vector includes abrupt entropy, temporal kurtosis and flatness of energy distribution in the wide frequency band. The multidimensional feature vector is input into the pre-trained second model. The classification conditions of the second model are used to match the multidimensional feature vector to obtain the classification result corresponding to the multidimensional feature vector. If the classification result is the target classification result, the alarm information corresponding to the sampling signal is output.

[0169] In some embodiments, the SoC chip integrates a digital signal processor (DSP) core, shared memory, and a neural network processor (NPU); the generation module 720 can specifically be used for: Using the DSP core, multidimensional feature vectors are written into shared memory; Using the NPU, multidimensional feature vectors are read from shared memory and input into a pre-trained second model.

[0170] In some embodiments, the SoC chip has a built-in PWM module; the device 700 may further include: The blocking module is used to block the register using the PWM module after the alarm information corresponding to the output sampling signal is received.

[0171] In some embodiments, the device 700 may further include: The filtering module is used to filter out discrete frequency points during the oversampling process of the photovoltaic DC branch current of the photovoltaic module.

[0172] In some embodiments, the acquisition module 710 may be specifically used for: The three-phase power supply circuit of the motor stator is sampled to obtain the sampling signal, which includes the three-phase current signal.

[0173] In some embodiments, the signal type is a motor signal type, and the alarm model includes a pre-trained third model; the SoC chip has a built-in DSP core, which includes a hardware multiply-accumulate unit and an accelerator, and the DSP core is a parallel bus architecture; the generation module 720 can specifically be used for: The three-phase current signal is reduced in dimension by using a hardware multiply-accumulate unit to obtain the target three-phase current signal; Using an accelerator, the target three-phase current signal is mapped onto a rotating coordinate system to obtain the current spectrum; The current spectrum is input into the pre-trained third model, which extracts the non-harmonic components from the current spectrum. The non-harmonic components are compared with the preset non-harmonic components to obtain the comparison results. If the comparison results indicate that the non-harmonic components match the target non-harmonic components in the preset non-harmonic components, the alarm signal corresponding to the sampled signal is determined to be the alarm signal corresponding to the target non-harmonic components, and the alarm signal corresponding to the sampled signal is output.

[0174] In some embodiments, the acquisition module 710 may be specifically used for: The power circuit corresponding to the heating element is sampled to obtain a sampling signal, which includes the power circuit current signal.

[0175] In some embodiments, the signal type is a heating element signal type, and the alarm model includes a pre-trained fourth model; the SoC chip integrates a differential programmable gain amplifier, an ADC, and a hardware multiply-accumulate unit; the generation module 720 can specifically be used for: A differential programmable gain amplifier is used to map the power loop current signal onto the full range of the ADC to obtain the digital signal corresponding to the power loop current signal. Using a hardware multiply-accumulate unit, autocorrelation operations on digital signals are performed to extract harmonic components from the power loop current signal carrier. The harmonic components are input into the pre-trained fourth model, which is used to identify the high-frequency pulsation entropy of the harmonic components. Based on the high-frequency pulsation entropy, the physical state of the heated medium is generated, and the alarm signal corresponding to the sampled signal is determined as the alarm signal corresponding to the physical state of the heated medium. The alarm signal corresponding to the sampled signal is then output.

[0176] In some embodiments, the acquisition module 710 may be specifically used for: The sensors of the monitored object are oversampled to obtain the sampled signal, which includes the sensor signal.

[0177] In some embodiments, the signal type is a sensor signal type, and the alarm model includes a pre-trained fifth model; the SoC chip has a built-in accelerator; the generation module 720 can specifically be used for: The physical fingerprint features of sensor signals are extracted using the autocorrelation algorithm of the accelerator. The physical fingerprint features are input into the pre-trained fifth model. The fifth model is used to identify the physical state of the monitored object based on the physical fingerprint features, determine the alarm signal corresponding to the sampling signal as the alarm information corresponding to the physical state, and output the alarm signal corresponding to the sampling signal.

[0178] Each module of the alarm signal generation device based on SoC chip provided in this application embodiment can realize the functions of each step of the alarm signal generation method based on SoC chip provided above, and can achieve its corresponding technical effects. For the sake of brevity, it will not be described in detail here.

[0179] Based on the same inventive concept, embodiments of this application also provide an electronic device.

[0180] Figure 8 A schematic diagram of the hardware structure of the electronic device provided in an embodiment of this application is shown.

[0181] An electronic device may include a processor 801 and a memory 802 storing computer program instructions.

[0182] Specifically, the processor 801 may include a central processing unit (CPU), an application specific integrated circuit (ASIC), or one or more integrated circuits that can be configured to implement the embodiments of this application.

[0183] Memory 802 may include mass storage for data or instructions. For example, and not limitingly, memory 802 may include a hard disk drive (HDD), floppy disk drive, flash memory, optical disk, magneto-optical disk, magnetic tape, or Universal Serial Bus (USB) drive, or a combination of two or more of these. Where appropriate, memory 802 may include removable or non-removable (or fixed) media. Where appropriate, memory 802 may be internal or external to an electronic device. In a particular embodiment, memory 802 is a non-volatile solid-state memory.

[0184] Memory may include read-only memory (ROM), random access memory (RAM), disk storage media devices, optical storage media devices, flash memory devices, and electrical, optical, or other physical / tangible memory storage devices. Therefore, typically, memory includes one or more tangible (non-transitory) computer-readable storage media (e.g., memory devices) encoded with software including computer-executable instructions, and when the software is executed (e.g., by one or more processors), it is operable to perform the operations described with reference to the methods according to one aspect of this disclosure.

[0185] The processor 801 reads and executes computer program instructions stored in the memory 802 to implement any of the alarm signal generation methods based on the SoC chip in the above embodiments.

[0186] In one example, the electronic device may also include a communication interface 803 and a bus 810. For example, Figure 8 As shown, the processor 801, memory 802, and communication interface 803 are connected through bus 810 and complete communication with each other.

[0187] The communication interface 803 is mainly used to realize communication between various modules, devices, units and / or equipment in the embodiments of this application.

[0188] Bus 810 includes hardware, software, or both, that couples components of an electronic device together. For example, and not limitingly, the bus may include an Accelerated Graphics Port (AGP) or other graphics bus, an Extended Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), a Hyper Transport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an Infinite Bandwidth Interconnect, a Linear Predictive Coding (LPC) bus, a memory bus, a MicroChannel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (Peripheral Component Interconnect-X, PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local Bus (VESA Local Bus, VLB) bus, or other suitable buses, or a combination of two or more of these. Where appropriate, bus 810 may include one or more buses. Although specific buses are described and illustrated in the embodiments of this application, this application contemplates any suitable bus or interconnect. The electronic device can execute the SoC-based alarm signal generation method in the embodiments of this invention, thereby realizing the above-described SoC-based alarm signal generation method.

[0189] Furthermore, in conjunction with the SoC chip-based alarm signal generation method in the above embodiments, this application embodiment can provide a computer storage medium for implementation. This computer storage medium stores computer program instructions; when these computer program instructions are executed by a processor, they implement any of the SoC chip-based alarm signal generation methods in the above embodiments.

[0190] This application also provides a computer program product, wherein the instructions in the computer program product, when executed by the processor of an electronic device, cause the electronic device to perform various processes implementing any of the above-described embodiments of the alarm signal generation method based on a SoC chip.

[0191] It should be clarified that this application is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of this application is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of this application.

[0192] The functional blocks shown in the above-described structural diagram can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application-specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of this application are programs or code segments used to perform the required tasks. Programs or code segments can be stored on a machine-readable medium or transmitted over a transmission medium or communication link via data signals carried on a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, read-only memory (ROM), flash memory, erasable read-only memory (EROM), floppy disks, compact disc read-only memory (CD-ROM), optical disks, hard disks, fiber optic media, radio frequency (RF) links, etc. Code segments can be downloaded via computer networks such as the Internet, intranets, etc.

[0193] It should also be noted that the exemplary embodiments mentioned in this application describe methods or systems based on a series of steps or apparatus. However, this application is not limited to the order of the above steps; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0194] The aspects of this disclosure have been described above with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block in the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that these instructions, executable via the processor of the computer or other programmable data processing apparatus, enable the implementation of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field-programmable logic circuit. It is also understood that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can also be implemented by special-purpose hardware performing the specified functions or actions, or can be implemented by a combination of special-purpose hardware and computer instructions.

[0195] The above are merely specific embodiments of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.

Claims

1. A method for generating alarm signals based on a SoC chip, characterized in that, The SoC chip has a built-in algorithm layer, which includes multiple alarm models, and the method includes: Acquire the sampled signal; Based on the signal type corresponding to the sampled signal, the target processing logic of the sampled signal is obtained; According to the target processing logic, the sampled signal is processed and then input into the alarm model corresponding to the target processing logic. The alarm model corresponding to the target processing logic is then used to output the alarm signal corresponding to the sampled signal.

2. The method according to claim 1, characterized in that, The SoC chip integrates a pulse width modulation (PWM) module, a hardware trigger, and an analog-to-digital converter (ADC); the acquisition of the sampled signal includes: The PWM module is used to generate currents of multiple frequencies. The multi-frequency currents are sequentially injected into the lithium battery through the hardware trigger, and the voltage and current responses of the lithium battery are synchronously oversampled using an ADC with a preset sampling rate to obtain the sampling signal corresponding to the current at each frequency. The sampling signal includes the voltage response signal and the current response signal.

3. The method according to claim 2, characterized in that, The signal type is a lithium battery signal type, and the alarm model includes a pre-trained first model; the step of processing the sampled signal according to the target processing logic and then inputting it into the alarm model corresponding to the target processing logic, and using the alarm model corresponding to the target processing logic to output the alarm signal corresponding to the sampled signal, includes: Based on the recursive operator, feature extraction is performed on the sampled signal to obtain an impedance fingerprint vector, which represents the electrochemical feature fingerprint. The impedance fingerprint vector is input into the pre-trained first model, and the first model is used to match the impedance fingerprint vector with a preset feature fingerprint vector map. If the offset between the impedance fingerprint vector and the preset feature fingerprint vector map exceeds a preset threshold, an alarm signal corresponding to the sampling signal is output.

4. The method according to claim 3, characterized in that, The SoC chip integrates a digital signal processor (DSP) core, shared memory, and a neural network processor (NPU); the step of inputting the impedance fingerprint vector into the pre-trained first model includes: Using the DSP core, the impedance fingerprint vector is written into the shared memory; Using the NPU, the impedance fingerprint vector is read from the shared memory and input into the pre-trained first model.

5. The method according to claim 1, characterized in that, The SoC chip has a built-in ADC; the acquisition of the sampling signal includes: Using an ADC with a preset sampling rate, the photovoltaic DC branch current of the photovoltaic module is oversampled to obtain a sampling signal, which includes the photovoltaic DC branch current signal.

6. The method according to claim 5, characterized in that, The signal type is a photovoltaic signal type, and the alarm model includes a pre-trained second model; the step of processing the sampled signal according to the target processing logic and then inputting it into the alarm model corresponding to the target processing logic, and using the alarm model corresponding to the target processing logic to output the alarm signal corresponding to the sampled signal, includes: Feature extraction is performed on the photovoltaic DC branch current signal in the preset frequency band of the sampled signal to obtain a multi-dimensional feature vector in the preset frequency band. The multi-dimensional feature vector includes abrupt entropy, temporal kurtosis and flatness of energy distribution in the wide frequency band. The multidimensional feature vector is input into the pre-trained second model, and the classification conditions of the second model are used to match the multidimensional feature vector to obtain the classification result corresponding to the multidimensional feature vector. If the classification result is the target classification result, the alarm information corresponding to the sampling signal is output.

7. The method according to claim 6, characterized in that, The SoC chip integrates a digital signal processor (DSP) core, shared memory, and a neural network processor (NPU); the step of inputting the multidimensional feature vector into the pre-trained second model includes: Using the DSP core, the multidimensional feature vector is written into the shared memory; Using the NPU, the multidimensional feature vector is read from the shared memory and input into the pre-trained second model.

8. The method according to claim 6, characterized in that, The SoC chip has a built-in PWM module; after outputting the alarm information corresponding to the sampled signal, the method further includes: The register is locked using the PWM module.

9. The method according to claim 5, characterized in that, The method further includes: During the oversampling process of the photovoltaic DC branch current of the photovoltaic module, discrete frequency points are filtered out.

10. The method according to claim 1, characterized in that, The acquisition of the sampling signal includes: The three-phase power supply circuit of the motor stator is sampled to obtain a sampling signal, which includes the three-phase current signal.

11. The method according to claim 10, characterized in that, The signal type is a motor signal type, and the alarm model includes a pre-trained third model; the SoC chip has a built-in DSP core, which includes a hardware multiply-accumulate unit and an accelerator, and the DSP core is a parallel bus architecture; the step of processing the sampled signal according to the target processing logic and then inputting it into the alarm model corresponding to the target processing logic, and using the alarm model corresponding to the target processing logic to output the alarm signal corresponding to the sampled signal, includes: The three-phase current signal is reduced in dimension using the hardware multiply-accumulate unit to obtain the target three-phase current signal. Using the accelerator, the target three-phase current signal is mapped onto a rotating coordinate system to obtain the current spectrum; The current spectrum is input into the pre-trained third model, and the third model is used to extract the non-harmonic components from the current spectrum. The non-harmonic components are compared with preset non-harmonic components to obtain a comparison result. If the comparison result indicates that the non-harmonic component matches the target non-harmonic component in the preset non-harmonic components, the alarm signal corresponding to the sampled signal is determined to be the alarm signal corresponding to the target non-harmonic component, and the alarm signal corresponding to the sampled signal is output.

12. The method according to claim 1, characterized in that, The acquisition of the sampling signal includes: The power circuit corresponding to the heating element is sampled to obtain a sampling signal, which includes the power circuit current signal.

13. The method according to claim 12, characterized in that, The signal type is a heating element signal type, and the alarm model includes a pre-trained fourth model; the SoC chip has a built-in differential programmable gain amplifier, ADC, and hardware multiply-accumulate unit; the step of processing the sampled signal according to the target processing logic and then inputting it into the alarm model corresponding to the target processing logic, and using the alarm model corresponding to the target processing logic to output the alarm signal corresponding to the sampled signal, includes: The power loop current signal is mapped to the full range of the ADC using the differential programmable gain amplifier to obtain the digital signal corresponding to the power loop current signal. Using the hardware multiply-accumulate unit, autocorrelation operation of the digital signal is performed to extract harmonic components from the power loop current signal carrier. The harmonic components are input into the pre-trained fourth model, which is used to identify the high-frequency pulsation entropy of the harmonic components. Based on the high-frequency pulsation entropy, the physical state of the heated medium is generated, and the alarm signal corresponding to the sampled signal is determined to be the alarm signal corresponding to the physical state of the heated medium. The alarm signal corresponding to the sampled signal is then output.

14. The method according to claim 1, characterized in that, The acquisition of the sampling signal includes: The sensors of the monitored object are oversampled to obtain a sampled signal, which includes the sensor signal.

15. The method according to claim 14, characterized in that, The signal type is a sensor signal type, and the alarm model includes a pre-trained fifth model; the SoC chip has a built-in accelerator; the step of processing the sampled signal according to the target processing logic and then inputting it into the alarm model corresponding to the target processing logic, and using the alarm model corresponding to the target processing logic to output the alarm signal corresponding to the sampled signal, includes: The physical fingerprint features of the sensor signal are extracted using the autocorrelation algorithm of the accelerator. The physical fingerprint features are input into the pre-trained fifth model. Using the fifth model, the physical state of the monitored object is identified based on the physical fingerprint features. The alarm signal corresponding to the sampling signal is determined as the alarm information corresponding to the physical state. The alarm signal corresponding to the sampling signal is then output.

16. An alarm signal generation device based on a SoC chip, characterized in that, The SoC chip has a built-in algorithm layer, which includes multiple alarm models. The device includes: The acquisition module is used to acquire the sampled signal; The acquisition module is further configured to acquire the target processing logic of the sampled signal based on the signal type corresponding to the sampled signal; The generation module is used to process the sampled signal according to the target processing logic and input it into the alarm model corresponding to the target processing logic, and then output the alarm signal corresponding to the sampled signal using the alarm model corresponding to the target processing logic.

17. An electronic device, characterized in that, The device includes: a processor and a memory storing computer program instructions; when the processor executes the computer program instructions, it implements the alarm signal generation method based on a SoC chip as described in any one of claims 1-15.

18. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer program instructions, which, when executed by a processor, implement the alarm signal generation method based on a SoC chip as described in any one of claims 1-15.

19. A computer program product, characterized in that, When the instructions in the computer program product are executed by the processor of the electronic device, the electronic device is able to perform the alarm signal generation method based on the SoC chip as described in any one of claims 1-15.

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