A processing method for improving warp of LTO layer back sealing epitaxial wafer

Abstract

The application relates to the technical field of semiconductor material production, in particular to a processing method for improving warp of a LTO layer back sealing epitaxial wafer, which comprises the following steps: (1) selecting a substrate with bow value and warp value both in a preset range after double-side polishing, and washing the substrate for standby; (2) performing LTO film forming processing on the back surface of the substrate, setting the heating temperature of the two side regions of a tray as 680-760 DEG C, and setting the heating temperature of the middle region as 600-680 DEG C, so that the film forming rate of the edge is lower than that of the middle part; (3) performing single-side mechanical polishing on the front surface of the substrate, so that the surface is smooth and flat, and a polished wafer with bow>10um is obtained; (4) performing epitaxial processing on the polished wafer, so that an epitaxial wafer is obtained; and (5) after processing, the epitaxial wafer is washed and placed, so that a silicon epitaxial wafer with a LTO back sealing layer and with warp value<20um is obtained.

Description

Technical Field

[0001] This invention relates to the field of semiconductor material manufacturing technology, and in particular to a method for improving the processing of LTO layer back-sealed epitaxial wafer warp. Background Technology

[0002] Silicon epitaxial wafers are one of the most important semiconductor substrate materials in the semiconductor industry chain, and the market demand and technical requirements for them are currently very high. However, large-size silicon wafers are prone to edge irregularities during processing, especially in thermal processing, which affects subsequent semiconductor device fabrication. Edge warp, as a parameter reflecting the edge characteristics of silicon wafers, directly affects the yield of processing steps such as photolithography on the silicon wafer. Since heavily doped wafers require back-sealing processes to prevent self-doping effects, LTO back-sealing and epitaxial processing significantly worsen silicon wafer warp, thus impacting device manufacturing yield. Summary of the Invention

[0003] The purpose of this invention is to overcome the shortcomings of the prior art and provide an improved processing method for LTO layer back-sealed epitaxial wafer warp.

[0004] This invention provides the following technical solution: a method for improving the processing of LTO layer back-sealed epitaxial wafer warps, comprising the following steps: (1) Select a substrate whose bow value and warp value are both within the preset range after double-sided polishing, clean it and set it aside; (2) LTO film deposition is performed on the back side of the substrate. The heating temperature of the two sides of the tray is set to 680~760℃, and the heating temperature of the middle area is 600~680℃, so that the film deposition rate at the edge is lower than that in the middle. (3) Perform single-sided mechanical polishing on the front side of the substrate to make its surface flat and smooth, and obtain a polished sheet with bow > 10um; (4) Perform epitaxial processing on the polished sheet to obtain an epitaxial wafer; (5) After processing, the epitaxial wafer is cleaned and left to stand to obtain a silicon epitaxial wafer with a warp value of <20um and an LTO back seal layer.

[0005] Preferably, in step (1), the substrate has a bow value of 1~4µm and a warp value of Preferably, in step (4), the amount of material removed by single-sided mechanical polishing is between 0.3 and 1.1 μm.

[0006] Preferably, in step (5), the epitaxial processing temperature is 1130±10℃, the heating rate before epitaxial processing is 4~8℃ / s, the trichlorosilane (TCS) flow rate is 10±2 SLM, the carrier hydrogen flow rate is 50±10 SLM, and the edge purging hydrogen flow rate is 20±3 SLM.

[0007] The beneficial effects of this invention are: 1. By controlling various parameters in the back sealing and epitaxial process, the warp of the epitaxial wafer was improved; the warp value was reduced from about 48µm to less than 20µm.

[0008] 2. By processing and selecting the substrate (unprocessed LTO substrate, bow is 1~4; after LTO processing and before epitaxy, bow is >10), the deformation of the silicon wafer can be effectively compensated after epitaxial processing, thereby reducing edge warping.

[0009] 3. By purging hydrogen at the edges of the epitaxial process, the warp value of silicon wafer edges is reduced due to thermal warping.

[0010] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of the arrangement structure of the LTO film-forming heater in an embodiment of the present invention.

[0012] Figure 2 This is a schematic diagram of the deformation of the polished sheet before and after epitaxy in an embodiment of the present invention. Detailed Implementation

[0013] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.

[0014] This embodiment provides a method for improving the processing of LTO back-sealed epitaxial wafer warp. The processing technology of LTO back-sealed polished wafer and epitaxial wafer is introduced from the crystal pulling, wire cutting, grinding, chamfering, alkaline etching, double-sided polishing and polishing process.

[0015] (1) After wire cutting, grinding and double-sided polishing, a 12-inch substrate with a bow value of 1~4um and a warp value of 5~12um is preferred. After cleaning, it is ready for back-side LTO back-sealing film formation.

[0016] (2) During LTO film deposition, the temperatures on both sides of the heating tray (left side L and right side R in the substrate travel direction) are set to 680~760℃, and the temperature in the middle region (T1) is set to 600~680℃, so that the film deposition rate at the edge is lower than that in the middle. The higher temperature on both sides can increase the substrate bow value, resulting in greater curvature, which is beneficial for subsequent epitaxial processing. The heater distribution is shown in [reference needed]. Figure 1 .

[0017] (3) Perform single-sided mechanical polishing on the front side of the substrate, removing 0.3~1.1um, so that the substrate surface is smoother and flatter, and obtain a polished sheet with bow>10um. The purpose is to offset the deformation of the polished sheet during subsequent epitaxial high-temperature heating.

[0018] (4) The above-mentioned polished wafer is subjected to epitaxial processing at a processing temperature of 1130±10℃. The heating rate before epitaxial processing is 4~8℃ / s, and the flow rate of trichlorosilane (TCS) is 10±2 SLM. The flow rate of carrier hydrogen is 50±10 SLM, and the flow rate of edge purging hydrogen is 20±3 SLM. The high temperature in the epitaxial cavity will aggravate the deformation of the silicon wafer, resulting in a significant change in bow. The edge height of the polished wafer will be significantly raised, and the +bow value will become the -bow value. Figure 2 (A) If the substrate bow value is large enough, it can offset the epitaxial deformation, resulting in a flatter epitaxial wafer. For example... Figure 2 As shown in (B), the substrate bow is small or even negative, resulting in a large curvature after epitaxy, which leads to a significant deterioration of warp.

[0019] (5) After processing, the epitaxial wafer is cleaned and left to stand for about 3 hours. A silicon epitaxial wafer with an LTO back cover layer and a warp value of <20um can be obtained.

[0020] The above description is only a specific embodiment of the present invention, but the structural features of the present invention are not limited thereto. Any changes or modifications made by those skilled in the art within the scope of the present invention are covered by the patent scope of the present invention.

Claims

1. A method for improving the fabrication of LTO layer back-sealed epitaxial wafer warp, characterized in that, Includes the following steps: (1) Select a substrate whose bow value and warp value are both within the preset range after double-sided polishing, clean it and set it aside; (2) LTO film deposition is performed on the back side of the substrate. The heating temperature of the two sides of the tray is set to 680~760℃, and the heating temperature of the middle area is 600~680℃, so that the film deposition rate at the edge is lower than that in the middle. (3) Perform single-sided mechanical polishing on the front side of the substrate to make its surface flat and smooth, and obtain a polished sheet with bow > 10um; (4) Perform epitaxial processing on the polished sheet to obtain an epitaxial wafer; (5) After processing, the epitaxial wafer is cleaned and left to stand to obtain a silicon epitaxial wafer with a warp value of <20um and an LTO back seal layer.

2. The method for improving the warp of an LTO layer back-sealed epitaxial wafer according to claim 1, characterized in that: In step (1), the bow value of the substrate is 1~4um and the warp value is 5~12um.

3. The method for improving the warp processing of LTO layer back-sealed epitaxial wafers according to claim 1, characterized in that: In step (3), the amount of material removed by single-sided mechanical polishing is 0.3~1.1um.

4. The method for improving the warp of an LTO layer back-sealed epitaxial wafer according to claim 1, characterized in that: In step (4), the epitaxial processing temperature is 1130±10 ℃, the heating rate before epitaxial processing is 4~8 ℃ / s, the flow rate of trichlorosilane is 10±2 SLM, the flow rate of carrier hydrogen is 50±10 SLM, and the flow rate of edge purging hydrogen is 20±3 SLM.

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