An integrated circuit and an electronic device

Abstract

Embodiments of the present application provide an integrated circuit and an electronic device. The integrated circuit includes a first die and a second die. The first die and the second die are stacked and electrically connected. The base of the first die and the base of the second die are oppositely arranged. The second die includes at least one first metal layer. The at least one first metal layer is the topmost metal layer of the second die. The integrated circuit includes a first module and a second module. The first module and the second module belong to different voltage domains. Different device groups of the first module are respectively arranged on the first die and the second die. Different device groups of the second module are respectively arranged on the first die and the second die. The device groups in the first module and the second module form an intersection region. The part of each first metal layer in the intersection region is used to supply power to the device groups of the first module on the first die. The scheme of the embodiments of the present application can improve the power supply capability of the intersection region and avoid power integrity problems.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to an integrated circuit and an electronic device. Background Technology

[0002] In 3D chips, different components of the same module are often placed on the upper die and the lower die, respectively. For example Figure 1 The diagram illustrates that components A1 and A2 of module A are fabricated on die1 and die2, respectively, and components B1 and B2 of module B are fabricated on die1 and die2, respectively. Because it is difficult to guarantee that components A1 and A2, and components B1 and B2, have the same area and shape—for example, the area of ​​component A1 may be larger than that of component A2, and the area of ​​component B1 may be smaller than that of component B2—the projections of components A1 and B2 in the stacking directions of die1 and die2 will partially overlap. This area of ​​partial overlap between the projections of components A1 and B2 is called the intersection region, and is indicated by a dashed box.

[0003] Within this crossover region, the power supply network in the 3D chip needs to supply power to both device A1 and device B2. Since devices A1 and B2 require different voltages, cross-power supply from different power domains occurs within this region. In conventional solutions, the power supply network cannot supply power to die1 and die2 as needed within this crossover region, resulting in excessive voltage drops along the power supply path. Devices in die1 and die2 cannot receive the required voltage, leading to poor power supply capability in the crossover region and causing power integrity (PI) problems. Summary of the Invention

[0004] This application provides an integrated circuit and an electronic device that can provide power to cross-regions on demand and reasonably, improve the power supply capacity of cross-regions, and avoid power integrity issues.

[0005] In a first aspect, embodiments of this application provide an integrated circuit, including a first die and a second die, the first die and the second die being stacked and electrically connected, the substrates of the first die and the second die being disposed opposite to each other; the second die includes at least one first metal layer, the at least one first metal layer being the topmost metal layer of the second die; the integrated circuit includes a first module and a second module, the first module and the second module belonging to different voltage domains; the first module includes a first device group disposed on the first die and a second device group disposed on the second die, the first device group and the second device group belonging to the same voltage domain, the first device group including a first device group sub-section; the second module includes a third device group disposed on the first die and a second device group disposed on the second die. In the fourth device group of the second die, the third device group and the fourth device group belong to the same voltage domain, and the fourth device group includes a fourth device group sub-section; in the stacking direction of the first die and the second die, the projection of the second device group overlaps with the projection of the portion of the first device group excluding the first device group sub-section, the projection of the fourth device group sub-section overlaps with the projection of the first device group sub-section, and the projection of the portion of the fourth device group excluding the fourth device group sub-section overlaps with the projection of the third device group; each first metal layer includes a first overlapping region, the first overlapping region overlaps with the projection of the first device group sub-section in the stacking direction, and the portion of each first metal layer located within the first overlapping region is used to supply power to the first device group.

[0006] In this embodiment, the integrated circuit can be a face-to-face (F2F) architecture 3D chip, where a crossover region is often formed. Both the first device group sub-section and the fourth device group sub-section are located in the crossover region, and the first overlapping region is also located in this crossover region. By using the portion of each first metal layer located within the first overlapping region entirely to power the first device group, more parallel metal strips supplying power to the first device group can be used, resulting in a smaller total resistance of the circuit supplying power to the first device group in the crossover region. This ensures that the voltage drop from the first metal layer to the first device group is not too large, thereby guaranteeing the power supply voltage of the first device group and improving or avoiding the power integrity problem of face-to-face architecture 3D chips.

[0007] In one implementation of the first aspect, the second die further includes a plurality of second metal layers arranged sequentially along the stacking direction, the plurality of second metal layers being located between the at least one first metal layer and the substrate of the second die; each second metal layer includes a second overlapping region, the second overlapping region overlapping the projection of the first overlapping region in the stacking direction, and the portion of each second metal layer located in the second overlapping region being used to supply power to the second device group.

[0008] In this embodiment, the second overlapping region is also located in the intersection region. By using the portion of the second metal layer located in the second overlapping region to supply power to the fourth device group, more parallel metal strips can be supplied to the fourth device group, resulting in a smaller total resistance of the circuit supplying power to the fourth device group in the intersection region. This ensures that the voltage drop between the second metal layer and the fourth device group is not too large, thereby guaranteeing the power supply voltage of the fourth device group and improving or avoiding power integrity issues.

[0009] In one implementation of the first aspect, the first module further includes a fifth device group, the projection of which along the stacking direction falls within the area of ​​a sub-part of the fourth device group; the second die further includes a plurality of second metal layers arranged sequentially along the stacking direction, the plurality of second metal layers being located between the first metal layer and the substrate of the second die; each second metal layer includes a plurality of metal strips arranged in pairs at intervals; each second metal layer includes a second overlapping region, the projection of which overlaps with the projection of the first overlapping region along the stacking direction; each second metal layer includes a first metal layer sub-part and... The second metal layer sub-section, the first metal layer sub-section and the second metal layer sub-section are both located in the second overlapping region. The first metal layer sub-section and the second metal layer sub-section both include multiple metal strips. The first metal layer sub-section is used to supply power to the second device group, and the second metal layer sub-section is used to supply power to the fifth device group. The total length L1 of the metal strips in the first metal layer sub-section, the total length L2 of the metal strips in the second metal layer sub-section, the area S1 of the fourth device group sub-section and the area S2 of the fifth device group satisfy the following relationship: L1 / L2=[(S1-S2)*(1±30%)] / S2.

[0010] In this embodiment, the fifth device group is a device located within the region of the fourth device group sub-section. The operating voltages of the fifth device group and the fourth device group sub-section may be different, and the fifth device group and the fourth device group sub-section belong to different modules. The second overlapping region is also located in this intersection region. The solution in this application allocates the metal strips in the first metal layer sub-section of each second metal layer within the second overlapping region according to the area ratio of the fourth device group sub-section and the fifth device group within the intersection region. This allows the larger device group in the fourth device group sub-section to have a longer total length of metal strips and more parallel metal strips, resulting in a lower resistance in the power supply circuit for the larger device group in the fourth device group sub-section. This ensures the power requirements of the larger device group in the third device sub-section b are met. Conversely, the smaller device group in the third device sub-section b is allocated a shorter total length of metal strips and fewer parallel metal strips, resulting in a higher resistance in the power supply circuit for the smaller device group in the third device sub-section b. This also ensures the power requirements of the smaller device group in the third device sub-section b are met. Therefore, this application embodiment can guarantee the power supply capability to each device group within the second overlapping region, improving or avoiding power integrity issues.

[0011] In one implementation of the first aspect, the second die further includes a third metal layer located between the at least one first metal layer and the substrate of the second die. The third metal layer is adjacent to and electrically connected to the at least one first metal layer. The third metal layer includes a third overlapping region, which overlaps with the projection of the first overlapping region in the stacking direction. The third metal layer includes a plurality of first metal strips and a plurality of second metal strips arranged in pairs at intervals. Each first metal strip includes a first portion, and each second metal strip includes a second portion. The first portions of the plurality of first metal strips and the second portions of the plurality of second metal strips are all located within the third overlapping region. Each first portion is used to power a first device group, and each second portion is used to power a fourth device group. The total length of the plurality of first portions is equal to the total length of the plurality of second portions.

[0012] In this embodiment, the third overlapping region is also located in the intersection region. By making the total length of all the first parts of the third metal layer in the third overlapping region the same or approximately the same as the total length of all the second parts, the total resistance of the circuit supplying power to the first device group and the total resistance of the circuit supplying power to the fourth device group in the third overlapping region can be made close. This ensures that the voltage drop from the third metal layer to the first device group and the voltage drop to the fourth device group are close, thereby ensuring the power supply strength of the first device group and the fourth device group, which is beneficial to ensuring the performance of the integrated circuit.

[0013] In one implementation of the first aspect, the second die further includes multiple metallized vias that penetrate the substrate of the second die and are electrically connected to a plurality of first metal strips and a plurality of second metal strips in the third metal layer, respectively. Through these metallized vias, vertical interconnection between the substrate and the third metal layer can be achieved in a mature and reliable manner.

[0014] In one implementation of the first aspect, the second die further includes a plurality of second metal layers arranged sequentially along the stacking direction, the plurality of second metal layers being located between the third metal layer and the substrate of the second die; the plurality of second metal layers are provided with channels, a plurality of metallized vias passing through the channels, and each metallized via having a gap with the plurality of second metal layers.

[0015] By creating channels within the second metal layer, metallized vias can be easily passed through to achieve vertical interconnection, thereby forming a vertical power supply network in the integrated circuit. The gap between the metallized vias and the second metal layer ensures electrical isolation, preventing abnormal current transmission and guaranteeing the normal operation of the integrated circuit.

[0016] In one implementation of the first aspect, the integrated circuit further includes a back redistribution layer, aluminum pads, and a controllable collapse chip connection packaging substrate that are electrically connected to each other. The back redistribution layer is located on the side of the substrate of the second die facing away from the first die. The substrate of the second die, the back redistribution layer, the aluminum pads, and the controllable collapse chip connection packaging substrate are arranged sequentially along the stacking direction. A plurality of metallized vias are electrically connected to the back redistribution layer.

[0017] In this embodiment, the back redistribution layer, aluminum pads, and controlled collapse chip connection (C4) packaging substrate are all part of the integrated circuit packaging structure. The back redistribution layer and aluminum pads serve to evenly distribute current; the controlled collapse chip connection (C4) packaging substrate is used to electrically connect the bare die to external circuitry. By employing the controlled collapse chip connection (C4) packaging process, this embodiment enables the integrated circuit to possess superior electrical performance, good thermal performance, better packaging reliability, and higher production efficiency.

[0018] In one implementation of the first aspect, the first module further includes a fifth device group, a first isolation structure, and a second isolation structure; the projection of the fifth device group along the stacking direction falls within the range of the fourth device group sub-part; the first isolation structure is arranged around the outside of the fifth device group, and the second isolation structure is arranged along the boundary of the fourth device group sub-part near the fifth device group and is arranged around the outside of the first isolation structure.

[0019] In this embodiment, the fifth device group is a device located within the region of the fourth device group sub-section. The fifth device group and the fourth device group sub-section operate at different voltages and belong to different voltage domains. By setting the first isolation structure and the second isolation structure, electrical isolation between the fifth device group and the fourth device group sub-section can be achieved, preventing short-circuit failure of the integrated circuit.

[0020] In one implementation of the first aspect, the second die further includes an insulating filler medium located between the first isolation structure and the second isolation structure. By providing an insulating filler medium between the first isolation structure and the second isolation structure, the electrical isolation between the third and fifth devices can be strengthened, preventing short-circuit failures in the integrated circuit.

[0021] Secondly, embodiments of this application provide an electronic device, including a circuit board and an integrated circuit as described above, wherein the integrated circuit is electrically connected to the circuit board. The solution of this application embodiment can provide power to the cross-regions in the integrated circuit as needed, improve the power supply capacity of the cross-regions, avoid power integrity issues, and thus ensure the reliability and performance of the electronic device. Attached Figure Description

[0022] Figure 1 This is a cross-sectional view of a conventional integrated circuit.

[0023] Figure 2 This is a schematic diagram of the structure of an electronic device in one embodiment;

[0024] Figure 3 This is a schematic diagram of the structure of an electronic device in another embodiment;

[0025] Figure 4 This is a schematic diagram of the structure of an electronic device in another embodiment;

[0026] Figure 5 A cross-sectional view illustrating the stacked structure of an integrated circuit in one embodiment is shown.

[0027] Figure 6 This is a partial cross-sectional view of an integrated circuit according to one embodiment;

[0028] Figure 7 The structure of the first and third metal layers of the second die is illustrated.

[0029] Figure 8 for Figure 7 A schematic diagram of the structure of the third metal layer in the middle;

[0030] Figure 9 This is a schematic diagram of the structure of the second metal layer in an integrated circuit in one embodiment;

[0031] Figure 10 This is a schematic diagram of the structure of the second metal layer in an integrated circuit in another embodiment;

[0032] Figure 11 for Figure 10 A magnified view of the overlapping areas in the diagram;

[0033] Figure 12 for Figure 11 A partial top view of the second device group sub-section;

[0034] Figure 13 for Figure 12 A magnified view of point A in the diagram;

[0035] Figure 14 This is a partial top view of the first device group sub-section in one embodiment;

[0036] Figure 15 for Figure 14 A magnified view of point B in the diagram.

[0037] Figure Labels

[0038] 1-Electronic device, 11-Part, 12-Part, 13-Part, 111-Circuit board, 112-Integrated circuit, 113-Integrated circuit;

[0039] 2-Electronic device; 21-Circuit board; 22-Integrated circuit; 23-Circuit board; 24-Integrated circuit;

[0040] 3-Electronic devices;

[0041] 4-Integrated circuits;

[0042] 41-First die, 42-Second die, 43-Backside redistribution layer, 44-Aluminum pad, 45-Packaging substrate;

[0043] 411-substrate;

[0044] 412 - Device, 4121 - Third device group, 4122 - First device group, 4122a - Sub-section of the first device group, 4122b - Sub-section, 4122e - Fourth isolation structure, 4123e - Third isolation structure, 4123 - Sixth device group;

[0045] 413 - Metal layer, 414 - Metal layer, 415 - Metal layer, 416 - Metal layer, 417 - Metal layer;

[0046] 421-Substrate, 422-Device, 4221-Fourth Device Group, 4222-Second Device Group, 4223-Fifth Device Group, 4221a-Sub-section, 4221b-Fourth Device Group Sub-section, 4221e-Second Isolation Structure, 4223e-First Isolation Structure;

[0047] 423-Metal layer, 423a-Second overlapping region, 423b-Second metal layer sub-section, 423c-First metal layer sub-section, 4231-Metal strip;

[0048] 424 - Metallic layer;

[0049] 425 - Metal layer, 425a - Second overlapping region, 425b - Second metal layer sub-section, 425c - First metal layer sub-section, 4251 - Metal strip;

[0050] 426 - Metal layer, 4261 - Metal strip, 42611 - First metal strip, 42611a - First part, 42612 - Second metal strip, 42612a - Second part, 426a - Third overlapping area;

[0051] 427 - Metal layer, 427a - First overlapping region, 4271 - Metal strip;

[0052] 428 - Metallized via;

[0053] T - Channel, D1 - Insulating filler medium, D2 - Insulating filler medium. Detailed Implementation

[0054] This application relates to an electronic device with a built-in integrated circuit (IC). This electronic device includes, but is not limited to, mobile phones, tablets, laptops, desktop computers, wearable devices (e.g., headphones, smartwatches, smart bracelets, virtual reality devices, augmented reality devices, mixed reality devices), servers, routers, switches, vehicles (e.g., electric vehicles), and in-vehicle equipment. The type of integrated circuit is not limited; for example, it can be a system-on-a-chip (SoC).

[0055] In one embodiment, such as Figure 2As shown, electronic device 1 can be a foldable phone. Electronic device 1 can be bent and in a folded state, or it can be unfolded into an unfolded state. For example, electronic device 1 can be a tri-fold phone, comprising parts 11, 12, and 13, which can be stacked into a three-layer structure when folded. In another example, electronic device 1 can be folded into two layers; this type of electronic device 1 can be called a bi-fold phone or a split-fold phone. In another embodiment, electronic device 1 can also be a non-foldable candybar phone.

[0056] like Figure 2 As shown, electronic device 1 may include circuit board 111 and integrated circuits disposed on circuit board 111, such as integrated circuit 112 and integrated circuit 113. The location, number, and structure of circuit board 111 are not limited; the number, function, and location of integrated circuits on circuit board 111 are also not limited. It is understood that... Figure 2 The integrated circuits 112 and 113 shown are merely examples.

[0057] In one embodiment, such as Figure 3 As shown, electronic device 2 can be a vehicle. The location of the circuit board and integrated circuits on the circuit board in electronic device 2 is not limited. For example, circuit board 21 and its integrated circuit 22 can be located at the seat position, and circuit board 23 and its integrated circuit 24 can be located at the wheel position. It is understood that... Figure 3 This is merely an illustration. In reality, the location, number, and structure of the circuit boards in electronic device 2 are not limited, nor are the number, function, or location of the integrated circuits on the circuit boards.

[0058] In one embodiment, such as Figure 4 As shown, electronic device 3 can be a server. The location, number, and structure of the circuit boards in electronic device 3 are not limited, nor are the number, function, and location of the integrated circuits on the circuit boards. The structural design scheme of the integrated circuits in the embodiments of this application will be described below.

[0059] The following is an explanation of the technical terms used in the embodiments of this application.

[0060] A device is the smallest functional unit in an integrated circuit that possesses specific electrical characteristics. The functions of a device include, but are not limited to, switching, amplification, and storage. Devices include, but are not limited to, active devices (e.g., transistors, diodes), passive devices (e.g., resistors, capacitors, inductors), memory devices (e.g., DRAM, NAND flash memory), and optoelectronic devices (e.g., laser diodes, photodetectors). The physical structure of a device can be defined using appropriate processes, including but not limited to photolithography, etching, and ion implantation.

[0061] Device layer: refers to the collection of all active and passive devices manufactured in an integrated circuit through semiconductor processes (such as photolithography, doping, etching, etc.). The device layer forms a complete circuit through interconnect layers (metal wiring).

[0062] Device group: A region or collection of devices in a device layer. Multiple device groups can be defined in a device layer.

[0063] Metal layer: A conductive structure located above the device layer for electrical interconnection. It can be composed of multiple layers of metal wires and insulating dielectrics forming an interconnect network. Through vias and / or contacts, it vertically connects the electrodes of the device layer (such as the source / drain / gate of a transistor) to other metal layers, forming complex circuit topologies. The core function of the metal layer is to connect transistors, resistors, capacitors, and other devices in the device layer into complete circuits via metal wires, and to achieve power distribution and signal transmission.

[0064] Module: An independent unit in an integrated circuit, divided by function or structure. It usually contains a group of closely related devices (such as logic gates, memory, analog circuits, etc.) and has the following characteristics: Functional integrity: It can perform specific operations (such as arithmetic, storage, signal processing, etc.); Interface standardization: It connects to the outside world through input / output ports (I / O) and follows predefined electrical or protocol specifications; Reusability: It can be reused in the same chip or different projects (such as IP cores).

[0065] Voltage domain: A collection of circuit modules or regions in an integrated circuit that share the same power supply voltage. Logically, this means sharing the same power network (such as VDD / VSS), and physically, it corresponds to a specific power supply area. All units (such as standard cells and memory) use the same power supply.

[0066] Figure 5 A cross-sectional view illustrating the stacked structure of integrated circuit 4 in one embodiment is shown. Figure 5 As shown, integrated circuit 4 can be a 3D chip. Integrated circuit 4 can include a first die 41 and a second die 42, which are stacked and electrically connected. The direction in which the first die 41 and the second die 42 are stacked can be called the stacking direction, which includes two opposite directions, for example... Figure 5 Both the upward and downward directions are considered stacking directions. "The first die 41 and the second die 42 are stacked" can mean that the projections of the first die 41 and the second die 42 in the stacking direction completely overlap, or that the projections of the first die 41 and the second die 42 in the stacking direction only partially overlap.

[0067] like Figure 5 As shown, for example, the first die 41 may include a substrate 411, a device 412, a metal layer 413, a metal layer 414, a metal layer 415, a metal layer 416, and a metal layer 417, wherein the substrate 411, the metal layer 413, the metal layer 414, the metal layer 415, the metal layer 416, and the metal layer 417 may be arranged sequentially along the stacking direction.

[0068] This application does not limit the material of the substrate 411. For example, the material of the substrate 411 includes, but is not limited to, silicon (e.g., single-crystal silicon), organic materials, glass, silicon carbide (SiC), gallium nitride (GaN), diamond, etc. The substrate 411 can be made of one or more materials. Figure 5 As shown, device 412 is disposed on substrate 411. The number, location, structure, and function of device 412 are not limited. For example, device 412 may include logic gate devices.

[0069] like Figure 5 As shown, metal layers 413 to 415 can all be referred to as lower metal layers, which can be used to supply power to device 412 and transmit signals. The number of lower metal layers can be multiple, for example, 8, 10, 12, etc. The specific number of lower metal layers can be set as needed, and this embodiment does not limit it. Figure 5 As shown, the “…” symbol is used between metal layer 413 and metal layer 414 to indicate that several lower metal layers may be provided between metal layer 413 and metal layer 414.

[0070] like Figure 5 As shown, both metal layers 416 and 417 can be referred to as top metal layers. These top metal layers are primarily used to supply power to device 412 and can also be used to transmit signals to device 412. Specifically, metal layer 417 is the topmost metal layer of the first die 41, and it may include one or more metal layers. When metal layer 417 includes multiple metal layers, these metal layers are adjacent to each other and stacked sequentially, meaning they are distributed together to form the entire metal layer 417.

[0071] like Figure 5 As shown, metal layers 413, 414, 415, 416, and 417 can be electrically connected to each other and form a circuit network. For example, any two adjacent metal layers can be electrically connected through metallized vias. Figure 5 The metallized via is represented by a small shaded block.

[0072] like Figure 5As shown, for example, the second die 42 may include a substrate 421, a device 422, a metal layer 423, a metal layer 424, a metal layer 425, a metal layer 426, a metal layer 427, and a metallized via 428, wherein the substrate 421, the metal layer 423, the metal layer 424, the metal layer 425, the metal layer 426, and the metal layer 427 may be arranged sequentially along the stacking direction.

[0073] like Figure 5 As shown, substrate 421 and substrate 411 are arranged back-to-back, that is, substrate 421 is located on the side of the second die 42 that is away from the first die 41, and substrate 411 is located on the side of the first die 41 that is away from the second die 42. Therefore, integrated circuit 4 is a 3D chip with a face-to-face (F2F) architecture.

[0074] The material of the substrate 421 is not limited in the embodiments of this application. For example, the material of the substrate 421 includes, but is not limited to, silicon (e.g., single crystal silicon), organic materials, glass, silicon carbide (SiC), gallium nitride (GaN), diamond, etc. The substrate 421 can be made of one or more materials.

[0075] like Figure 5 As shown, device 422 is disposed on substrate 421. The number, location, structure, and function of device 422 are not limited. For example, device 422 may include a memory.

[0076] like Figure 5 As shown, metal layers 423 to 425 can all be referred to as lower metal layers. These lower metal layers can be used to supply power to device 422 and transmit signals. The number of lower metal layers can be multiple, for example, 8, 10, 12, etc. The specific number of lower metal layers can be set as needed, and this embodiment does not limit it. Figure 5 As shown, the “…” symbol is used between metal layer 423 and metal layer 424 to indicate that several lower metal layers may be provided between metal layer 423 and metal layer 424.

[0077] like Figure 5 As shown, by way of example, a portion of each of the lower metal layers, such as metal layers 423 to 425, can be cut out to form a channel T in these lower metal layers.

[0078] like Figure 5As shown, both metal layers 426 and 427 can be referred to as top metal layers. Metal layer 426 can be used to distribute current to the first die 41 and the second die 42 to power and transmit signals to device 422; metal layer 427 can be used to receive current from metal layer 426 and power and transmit signals to device 412. Metal layer 427 is the topmost metal layer of the second die 42, and metal layer 427 may include one or more metal layers. When metal layer 427 includes multiple metal layers, these metal layers are adjacent to each other and stacked sequentially, that is, these metal layers are distributed together to form the entire metal layer 427.

[0079] In this application embodiment, the term "transmission current" is used to encompass "power supply and signal transmission".

[0080] like Figure 5 As shown, metal layers 423, 424, 425, 426, and 427 can be electrically connected to each other and form a circuit network. For example, any two adjacent metal layers can be electrically connected through metallized vias. Figure 5 The metallized via is represented by a small shaded block.

[0081] like Figure 5 As shown, exemplarily, the metallized via 428 can penetrate the substrate 421 and be electrically connected to the metal layer 426 through the channel T. When the substrate 421 is made of silicon (e.g., single-crystal silicon), the metallized via 428 can be a through-silicon via (TSV). The metallized via 428 does not contact each lower metal layer of the second die 42, but maintains a certain gap. The size, number, and distribution location of the metallized via 428 can be determined as needed. Figure 5 This is merely an illustration and is not intended to limit the embodiments of this application. The metallized via 428 is a vertical interconnect structure used to transmit current from external circuits (such as circuit boards or other integrated circuits) to the metal layer 426. The metallized via 428 has gaps between it and each lower metal layer of the second die 42, which enables the metallized via 428 to be electrically isolated from each lower metal layer.

[0082] In another embodiment, the electrical connection between the integrated circuit 4 and the external circuit can also be achieved in any other suitable manner, without being limited to using metallized vias 428.

[0083] like Figure 5As shown, the metal layer 417 of the first die 41 and the metal layer 427 of the second die 42 can be electrically connected to form an electrical connection region, thereby enabling the first die 41 and the second die 42 to be vertically interconnected. For example, the metal layers 417 and 427 can be electrically connected using a hybrid bonding (HB) process, thereby forming a hybrid bonding region in the integrated circuit 4, where both metal layers 417 and 427 serve as structures within this hybrid bonding region. The HB process can achieve ultra-high interconnect density; reduce resistance and improve signal transmission speed; avoid solder bumps and reduce package thickness, better meeting the needs of miniaturized electronic devices; and support chip stacking at different process nodes (such as logic layer + memory). It is understood that the HB process is not mandatory, and this application does not limit the vertical interconnection method between the first die 41 and the second die 42. For example, microbumps can also be used to achieve the vertical interconnection between the first die 41 and the second die 42.

[0084] The following describes the packaging structure of integrated circuit 4. This packaging structure is used to encapsulate and protect the first die 41 and the second die 42, ensuring signal integrity, power transmission characteristics, and thermal management, etc.

[0085] like Figure 5 As shown, exemplarily, the packaging structure in integrated circuit 4 may include a backside redistribution layer (BS RDL) 43, aluminum pads 44, and a packaging substrate 45. The backside redistribution layer 43, aluminum pads 44, and packaging substrate 45 can all be located on the side of substrate 421 facing away from the first die 41, and substrate 421, backside redistribution layer 43, aluminum pads 44, and packaging substrate 45 can be arranged sequentially along the stacking direction. The backside redistribution layer 43 can be electrically connected to a metallized via 428 penetrating substrate 421. The aluminum pads 44 are electrically connected to the backside redistribution layer 43, for example, through metallized vias. The packaging substrate 45 is electrically connected to the aluminum pads 44, and the packaging substrate 45 can, for example, form an interconnect with the aluminum pads 44 using a controlled collapse chip connection (C4) packaging process. Figure 5 The shaded sphere between the aluminum pad 44 and the package substrate 45 can represent the C4 solder ball. It is understood that the above package structure is merely an example, and this application does not limit the construction or process of the package structure.

[0086] like Figure 5In one embodiment, the first die 41 can be located away from the package substrate 45, and the first die 41 can be the upper die, while the second die 42 can be the lower die. In another embodiment, the positions of the first die 41 and the second die 42 can be interchanged, with the first die 41 being the lower die and the second die 42 being the upper die. The current path in the integrated circuit 4 will be described below.

[0087] like Figure 5 As shown, current can be transferred from the package substrate 45 to the aluminum pad 44 via the C4 solder ball. The aluminum pad 44 has a current distribution function; its built-in power network can convert the point-distributed current input from the C4 solder ball into a planar distribution current and distribute it to different paths in the back redistribution layer 43. The current, after initial current equalization, enters the back redistribution layer 43, which can further evenly distribute the current to each metallized via 428. The metallized via 428 can then transfer the current to the metal layer 426. The current in metal layer 426 can have two transmission paths: one transmission path is to transmit to metal layer 427, and then through the hybrid bonding region to metal layer 417 of the first die 41. The current is then transmitted sequentially through metallized vias along the hierarchical structure of metal layer 415 → metal layer 414 → … → metal layer 413, finally completing the power supply and signal transmission to device 412 of the first die 41; the other transmission path is to transmit sequentially through metal layer 425, metal layer 424… metal layer 423 of the second die 42 to each device 422 of the second die 42.

[0088] The stack-up structure and current path of integrated circuit 4 have been described in detail above. The design of each metal layer in integrated circuit 4 will be described below.

[0089] In the embodiments of this application, the voltage domain mentioned below refers to the circuit area in an integrated circuit that is powered by an independent voltage. Circuits within the same voltage domain share the same voltage, but the voltages in different voltage domains may be different. The power island refers to the circuit blocks at different locations within a module. A module is a functional unit within an integrated circuit that belongs to a specific voltage domain or power island.

[0090] Figure 6 This is a partial cross-sectional view of integrated circuit 4 in one embodiment. Figure 6 yes Figure 5 simplification, Figure 6 Several devices in the first die 41 and the second die 42 are shown, while other structures such as metal layers are omitted.

[0091] like Figure 6As shown, integrated circuit 4 may include a first module 4a and a second module 4b. The first module 4a and the second module 4b may belong to different voltage domains, that is, their voltages may be different. The first module 4a may include a first device group 4122 disposed on the first die 41 and a second device group 4222 disposed on the second die 12. The first device group 4122 and the second device group 4222 belong to the same voltage domain, and their voltages are the same. The second module 4b may include a third device group 4121 disposed on the first die 41 and a fourth device group 4221 disposed on the second die 12. The third device group 4121 and the fourth device group 4221 belong to the same voltage domain, and their voltages are the same.

[0092] In this embodiment, both the third device group 4121 and the first device group 4122 may include Figure 5 The multiple devices 412, the fourth device group 4221 and the second device group 4222 can all include Figure 5 Multiple devices 422 in the middle.

[0093] like Figure 6 As shown, since it is difficult to ensure that the area and shape of the third device group 4121 and the fourth device group 4221 are consistent, for example, the area of ​​the third device group 4121 is smaller than the area of ​​the fourth device group 4221; and since it is difficult to ensure that the area and shape of the first device group 4122 and the second device group 4222 are consistent, for example, the area of ​​the first device group 4122 is larger than the area of ​​the second device group 4222, the projections of the first device group 4122 and the fourth device group 4221 in the stacking direction of the first bare die 41 and the second screw 42 will partially overlap. The area where the projections of the first device group 4122 and the fourth device group 4221 partially overlap is called the intersection area, which is indicated by a dashed box.

[0094] It is understood that the areas mentioned in the embodiments of this application refer to the projected area along the stacking direction.

[0095] Understandable Figure 6 The dimensions and shapes of the intersection areas shown are merely illustrative and not intended to limit this embodiment. Furthermore, in integrated circuit 4, Figure 6 There can be multiple local structures, and therefore multiple such intersection regions.

[0096] The following description uses a crossover region as an example to illustrate in detail the technical solution of this application embodiment, which improves the power supply capability of the crossover region and improves or avoids power integrity problems by improving the structure of the metal layer in the crossover region. In the following description, metal layer 427 can be referred to as the first metal layer 427, metal layers 423, 424... 425 can all be referred to as the second metal layer, and metal layer 426 can be referred to as the third metal layer 426.

[0097] Figure 7 It indicates that Figure 6 The structure of the third metal layer 426 and the first metal layer 427 of the corresponding second die 42, wherein the substrate 411 and the substrate 421 are not shown.

[0098] like Figure 7 As shown, the first metal layer 427 faces and is adjacent to the first die 41. The first metal layer 427 is the topmost metal layer of the second die 42. The first metal layer 427 may include one or more metal layers. When the first metal layer 427 includes multiple metal layers, these metal layers are adjacent to each other and stacked sequentially, that is, these metal layers are distributed together to form the entire first metal layer 427.

[0099] like Figure 7 As shown, the first device group 4122 may include a first device group sub-section 4122a located within the intersection area and a sub-section 4122b located outside the intersection area. The sub-section 4122b is the portion of the first device group 4122 excluding the first device group sub-section 4122a. Figure 7 The boundaries of the first device group sub-sections 4122a and 4122b are shown in dashed lines. It is understood that the dashed boundaries are merely schematic and do not define the actual shapes of the first device group sub-sections 4122a and 4122b, nor are they actual boundary lines existing within the first device group 4122.

[0100] like Figure 7 As shown, the fourth device group 4221 may include a sub-part 4221a located outside the intersection region and a fourth device group sub-part 4221b located within the intersection region. The sub-part 4221a is the part of the fourth device group 4221 other than the fourth device group sub-part 4221b. Figure 7 The boundaries of sub-section 4221a and sub-section 4221b of the fourth device group are shown by dashed lines. It is understood that the dashed boundary is merely schematic and does not define the actual shape of sub-section 4221a and sub-section 4221b of the fourth device group, nor is it an actual boundary line in the fourth device group 4221.

[0101] like Figure 7As shown, the third device group 4121 and the sub-part 4221a overlap in the stacking direction. "Overlapping in the stacking direction" means that the projections of the third device group 4121 and the sub-part 4221a overlap or approximately overlap in the stacking direction, and the same applies below. The first device group sub-part 4122a overlaps with the fourth device group sub-part 4221b in the stacking direction, and the sub-part 4122b overlaps with the second device group 4222 in the stacking direction.

[0102] like Figure 7 As shown, for example, the first metal layer 427 may include a plurality of metal strips 4271 arranged in pairs at intervals, and these metal strips 4271 are connected in parallel. Figure 7 The shape, size, and spacing of the metal strips 4271 shown are merely illustrative and are not limited in this application embodiment.

[0103] like Figure 7 As shown, the first metal layer 427 may include a first overlapping region 427a that overlaps with the first device group sub-part 4122a in the stacking direction. The first overlapping region 427a is located within the intersection region. The first overlapping region 427a contains a plurality of metal strips 4271. The number and distribution of the metal strips 4271 within the first overlapping region 427a are not limited. For example, the metal strips 4271 may fill or substantially fill the first overlapping region 427a, or they may be concentrated in certain sub-regions within the first overlapping region 427a.

[0104] In this embodiment, the portion of the first metal layer 427 located within the first overlapping region 427a can all be used to transmit current to the first device group 4122. That is, all metal strips 4271 within the first overlapping region 427a are used to transmit current to the first device group 4122, and will not transmit current to other devices. Combined with... Figure 5 and Figure 7 As shown, "the portion of the first metal layer 427 located within the first overlapping region 427a can all be used to transmit current to the first device group 4122" means that the current of all metal strips 4271 in the first overlapping region 427a of the first metal layer 427 enters the metal layer 417 of the first die 41 through the mixed bonding region, and is transmitted layer by layer to the first device group 4122 on the first die 41 through metallized vias.

[0105] like Figure 7As shown, the solution of this application embodiment uses the portion of the first metal layer 427 located in the first overlapping region 427a to transmit current to the first device group 4122. This results in a larger number of parallel metal strips 4271 transmitting current to the first device group 4122, thus reducing the total resistance of the circuit supplying power to the first device group 4122 in the cross region. This ensures that the voltage drop between the first metal layer 427 and the first device group 4122 is not too large, thereby guaranteeing the power supply voltage of the first device group 4122 and improving or avoiding power integrity issues.

[0106] In this embodiment of the application, when the first metal layer 427 includes multiple metal layers, each metal layer in the first metal layer 427 can have the above-described design, that is, the portion of each metal layer located in the first overlapping region 427a is entirely used to supply power to the first device group 4122.

[0107] Figure 8 It indicated Figure 7 The structure of the third metal layer. Combined Figure 7 and Figure 8 As shown, the third metal layer 426 may include a plurality of metal strips 4261 arranged in pairs at intervals. For example, the metal strips 4261 may be arranged in a cross pattern with the metal strips 4271, such that the extension direction of the metal strips 4261 may be horizontal and the extension direction of the metal strips 4271 may be vertical.

[0108] Combination Figure 7 and Figure 8 As shown, the third metal layer 426 may include a third overlapping region 426a that overlaps with the first overlapping region 427a. All metal strips 4261 of the third metal layer 426 may include a plurality of first metal strips 42611 and a plurality of second metal strips 42612.

[0109] In this process, a portion of each first metal strip 42611 falls into the third overlapping region 426a, and the portion of each first metal strip 42611 falling into the third overlapping region 426a can be referred to as the first portion 42611a. Figure 8 The first part 42611a is highlighted with a diamond-shaped shading. This is merely illustrative and does not imply that the construction of the first metal strip 42611 is segmented. In fact, the first metal strip 42611 is a continuous metal strip.

[0110] In this process, a portion of each second metal strip 42612 falls into the third overlapping region 426a, and the portion of each second metal strip 42612 that falls into the third overlapping region 426a can be referred to as the second portion 42612a. Figure 8The second part 42612a is highlighted with dotted shading. This is only for illustration and does not imply that the construction of the first metal strip 42611 is segmented. In fact, the first metal strip 42611 is a continuous metal strip.

[0111] It is understandable that there can be multiple first parts 42611a and second parts 42612a. The sum of the lengths of all first parts 42611a can be equal to or approximately equal to the sum of the lengths of all second parts 42612a. In other words, the ratio of the total length of all first parts 42611a to the total length of all second parts 42612a is 1:1 or approximately 1:1.

[0112] like Figure 8 As shown, the first part 42611a can be used to power the first device group 4122, and the second part 42612a can be used to power the fourth device group 4221. The total length of the metal strips 4261 in the first part 42611a can be equal to the total length of the metal strips 4261 in the second part 42612a.

[0113] Combination Figure 6 and Figure 8 As shown, by making the total length of all the first portions 42611a and the total length of all the second portions 42612a in the third overlapping region 426a of the third metal layer 426 the same or approximately the same, the total resistance of the circuit supplying power to the first device group 4122 and the total resistance of the circuit supplying power to the fourth device group 4221 in the third overlapping region 426a can be made close. This ensures that the voltage drop from the third metal layer 426 to the first device group 4122 and the voltage drop to the fourth device group 4221 are close, thereby ensuring the power supply strength of the first device group 4122 and the fourth device group 4221, which is beneficial to ensuring the performance of the integrated circuit 4.

[0114] Understandable Figure 8 The structural design of the third metal layer 426 shown and described above is merely an example and is not a design necessary for the embodiments of this application. For example, in one embodiment, the ratio of the portion of the third metal layer 426 located in the intersection region used to transmit current to the first device group 4122 and the fourth device group 4221 can be set according to product needs and is not limited to the 1:1 ratio described above.

[0115] Figure 9 This is a schematic diagram of the structure of multiple second metal layers in integrated circuit 4 in one embodiment. For the sake of simplicity, Figure 9Only the second metal layer 423 and the second metal layer 425 are shown. In fact, there can be several second metal layers between the second metal layer 423 and the second metal layer 425. The “…” in the figure represents several second metal layers between the second metal layer 423 and the second metal layer 425.

[0116] like Figure 9 As shown, for example, each second metal layer may include a plurality of metal strips arranged in pairs at intervals. For instance, second metal layer 423 may include a plurality of metal strips 4231 arranged in pairs at intervals, and second metal layer 425 may include a plurality of metal strips 4251 arranged in pairs at intervals. The metal strips of two adjacent second metal layers along the stacking direction may be arranged in a cross pattern. For example, the extension direction of the metal strip of one second metal layer may be transverse, and the extension direction of the metal strip of the adjacent second metal layer may be longitudinal.

[0117] Combination Figure 7 and Figure 9 As shown, each second metal layer may include a second overlapping region that overlaps with the first overlapping region 427a, and each second overlapping region may include multiple complete metal strips, or a portion thereof. For example, the second metal layer 425 may include a second overlapping region 425a that overlaps with the first overlapping region 427a, and multiple metal strips 4251 may be provided within the second overlapping region 425a; the second metal layer 423 may include a second overlapping region 423a that overlaps with the first overlapping region 427a, and a portion thereof may be provided within the second overlapping region 423a.

[0118] like Figure 9 As shown, the portion of each second metal layer located in the second overlapping region is used to transmit current to the fourth device group 4221. For example, all metal strips 4251 of the second metal layer 425 located in the second overlapping region 425a are used to transmit current to the fourth device group 4221, and all metal strips 4231 of the second metal layer 423 located in the second overlapping region 423a are used to transmit current to the fourth device group 4221.

[0119] like Figure 9 As shown, the solution of this application embodiment, by making the portion of the second metal layer located in the second overlapping area entirely used to transmit current to the fourth device group 4221, can result in a larger number of parallel metal strips transmitting current to the fourth device group 4221, thus making the total resistance of the circuit supplying power to the fourth device group 4221 in the cross area smaller. This ensures that the voltage drop between the second metal layer and the fourth device group 4221 is not too large, thereby ensuring the power supply voltage of the fourth device group 4221 and improving or avoiding power integrity issues.

[0120] Understandable Figure 9The structural design of the second metal layer shown is merely an example and is not a design required for the embodiments of this application. For example, in one embodiment, the portion of the second metal layer located in the second overlapping region may not be limited to transmitting current to the fourth device group 4221, but may also transmit current to other devices.

[0121] refer to Figure 6 As shown, in some embodiments, depending on the needs, such as when the space on the first die 41 is insufficient while the space on the second die 42 is relatively ample, the device group of the first module 4a located in the intersection area on the first die 41 can be placed in the area where the device group of the second module 4b located in the intersection area on the second die 42 is located. This architecture can be called an "enclave". The "fly-in" devices include, but are not limited to, power gating devices, switches, etc. The "enclave" arrangement can make reasonable use of the space on the first die 41 and the second die 42, and can also enable the "fly-in" devices to have better performance.

[0122] When an "enclave" architecture exists in integrated circuit 4, the structure of the second metal layer of integrated circuit 4 can be adjusted to improve or avoid power integrity issues, as explained below.

[0123] Figure 10 This is a schematic diagram of the structure of the second metal layer in integrated circuit 4 in another embodiment. For the sake of simplicity, Figure 10 Only the second metal layer 423 and the second metal layer 425 are shown. In fact, there can be several second metal layers between the second metal layer 423 and the second metal layer 425. The “…” in the figure represents several second metal layers between the second metal layer 423 and the second metal layer 425. Figure 11 for Figure 10 A magnified schematic diagram of the overlapping areas in the diagram.

[0124] like Figure 10 As shown, the first module 4a may further include a fifth device group 4223, the projection of which falls within the area of ​​the fourth device group sub-part 4221b along the stacking direction. This can also be understood as the fifth device group 4223 being a device group from the first module 4a that "flies in" into the area of ​​the fourth device group 4221. The fifth device group 4223 operates at a different voltage than the fourth device group 4221, and they belong to different voltage domains.

[0125] It is understandable that the shape, size, location, and number of the "flying-in" device group are not limited to... Figure 10 As shown, there can actually be more than one "flying in" device group, and the "flying in" device group can be located at any position within the range of the fourth device group sub-section 4221b.

[0126] like Figure 10 As shown, each second metal layer may include multiple metal strips arranged in pairs at intervals. For example, second metal layer 423 may include multiple metal strips 4231 arranged in pairs at intervals, and second metal layer 425 may include multiple metal strips 4251 arranged in pairs at intervals. The metal strips of two adjacent second metal layers along the stacking direction may be arranged in a cross pattern. For example, the extension direction of the metal strip of one second metal layer may be transverse, and the extension direction of the metal strip of the adjacent second metal layer may be longitudinal.

[0127] Combination Figure 7 and Figure 10 As shown, each second metal layer may include a second overlapping region that overlaps with the first overlapping region 427a in the stacking direction. For example, the second metal layer 425 may include a second overlapping region 425a that overlaps with the first overlapping region 427a in the stacking direction, and the metal layer 423 may include a second overlapping region 423a that overlaps with the first overlapping region 427a.

[0128] Combination Figure 10 and Figure 11 As shown, the second metal layer 425 may include a first metal layer sub-portion 425c located in the second overlapping region 425a. Figure 11 (Illustrated with dotted shading) and the second metal layer 425b ( Figure 11 (Symbolized by shading in the image) The first metal layer sub-section 425c may include multiple metal strips 4251, and the second metal layer sub-section 425b may include multiple metal strips 4251. The first metal layer sub-section 425c is used to transmit current to the fourth device group 4221, and the second metal layer sub-section 425b is used to transmit current to the fifth device group 4223. The second metal layer 423 may include the first metal layer sub-section 423c located in the second overlapping region 423a. Figure 11 (Illustrated with dotted shading) and the second metal layer 423b ( Figure 11 (Symbolized by slanted lines) The first metal layer sub-section 423c may include multiple metal strips 4231, and the second metal layer sub-section 423b may include multiple metal strips 4231. The first metal layer sub-section 423c is used to transmit current to the fourth device group 4221, and the second metal layer sub-section 423b is used to transmit current to the fifth device group 4223.

[0129] Understandable Figure 10 and Figure 11Only the structural design of the second metal layer 425 and the second metal layer 423 is shown. This is just a schematic diagram. In fact, all the metal strips in each second metal layer in this embodiment can include a first metal layer sub-part and a second metal layer sub-part located in the second overlapping area. The first metal layer sub-part is used to transmit current to the fourth device group 4221, and the second metal layer sub-part is used to transmit current to the fifth device group 4223.

[0130] Combination Figure 10 and Figure 11 As shown, for each second metal layer, the total length L1 of the metal strips in the first metal layer sub-section (e.g., first metal layer sub-section 425c), the total length L2 of the metal strips in the second metal layer sub-section (e.g., second metal layer sub-section 425b), the area S1 of the fourth device group sub-section 4221b, and the area S2 of the fifth device group 4223 can satisfy the following relationship: L1 / L2=[(S1-S2)*(1±30%)] / S2. It can be understood that the second metal layer 425, the second metal layer 423, and other second metal layers all satisfy this relationship.

[0131] In this embodiment, all devices in the fourth device group sub-section 4221b have equal voltages; the larger devices in the fourth device group sub-section 4221b (e.g., Figure 10 and Figure 11 The fourth device group (4221) in the middle has higher power consumption and smaller area (e.g., devices with higher power consumption and smaller area). Figure 10 and Figure 11 The fifth device group (4223) in the series has lower power consumption.

[0132] Combination Figure 6 , Figure 10 and Figure 11 As shown, by allocating the ratio of the total length of the first metal layer sub-section of each second metal layer located in the second overlapping region to the total length of the second metal layer sub-section of each second metal layer located in the second overlapping region according to the area ratio of the fourth device group 4221 and the fifth device group 4223 in the intersection region where the second die 42 is located, it is possible to make the larger device group (e.g., the larger device group in the fourth device group sub-section 4221b) Figure 10 and Figure 11 The fourth device group 4221b has a longer total length of metal strips and more parallel metal strips, which results in a lower resistance in the power supply circuit of the larger device group in the fourth device group sub-section 4221b. This ensures the power requirements of the larger device group in the fourth device group sub-section 4221b are met; it also allows for a lower resistance in the smaller device group (e.g., Figure 10 and Figure 11The third device (4223) has a shorter total length of metal strips and fewer parallel metal strips, which results in a higher resistance in the power supply circuit of the smaller device group in the fourth device group sub-section 4221b. This ensures the power requirements of the smaller device group in the fourth device group sub-section 4221b. Therefore, the embodiments of this application can guarantee the power supply capability of each device group in the second overlapping area, improving or avoiding power integrity issues.

[0133] Understandable Figure 10 and Figure 11 The ratio of the total length of the first and second parts shown is not necessarily required to be allocated according to the area ratio of the fourth device group 4221 and the fifth device group 4223. In another embodiment, the ratio of the total length of the first and second parts can also be set as needed, and is not limited to the relationship described above.

[0134] Understandable Figure 10 and Figure 11 The illustrated embodiments can be used with Figures 7-8 The combination of one or more embodiments shown can simultaneously guarantee the power supply voltage of the first die 41 and the second die 42, improving or avoiding power integrity issues.

[0135] refer to Figure 10 and Figure 11 As shown, when the second die 42 in integrated circuit 4 has an "enclave" architecture, there may be several power islands of the first module 4a within the fourth device group sub-section 4221b. The fourth device group 4221 and the fifth device group 4223 can be electrically isolated by an isolation structure (endcap) to avoid short circuits. This will be explained below.

[0136] Figure 12 for Figure 11 A partial top view of the fourth device group sub-section 4221b. Figure 13 for Figure 12 A magnified view of area A in the diagram. (See attached image.) Figure 12 and Figure 13 As shown, exemplarily, the second die 42 may further include a first isolation structure 4223e and a second isolation structure 4221e. The first isolation structure 4223e is disposed around the outside of the fifth device group 4223, and the second isolation structure 4221e is disposed along the fourth device group sub-part 4221b near the boundary of the fifth device group 4223, and is disposed around the outside of the first isolation structure 4223e. By providing isolation structures on the outside of the fifth device group 4223 and on the edge of the fourth device group 4221 near the fifth device group 4223, short-circuit failure of the integrated circuit 4 can be avoided.

[0137] Understandable Figure 12and Figure 13 The isolation structure between the fourth device group 4221 and the fifth device group 4223 shown is not necessary. In another embodiment, electrical isolation between the fourth device group 4221 and the fifth device group 4223 can also be achieved in other ways.

[0138] like Figure 12 and Figure 13 As shown, for example, a gap may be provided between the first isolation structure 4223e and the second isolation structure 4221e, which may be, for example, about 1 μm. The second die 42 may also include an insulating filling medium D1, which is located between the first isolation structure 4223e and the second isolation structure 4221e, that is, the insulating filling medium D1 is used to fill the gap between the first isolation structure 4223e and the second isolation structure 4221e. By filling the gap between the first isolation structure 4223e and the second isolation structure 4221e with the insulating filling medium D1, the electrical isolation between the fourth device group 4221 and the fifth device group 4223 can be strengthened, and short-circuit failure of the integrated circuit 4 can be avoided.

[0139] like Figure 12 and Figure 13 As shown, the width of the insulating fill medium D1 can be determined by the design rules provided by the foundry to ensure that it does not cause design rule check (DRC) violations.

[0140] Understandable Figure 12 and Figure 13 The insulating filling medium D1 shown is not mandatory. In another embodiment, whether or not an insulating filling medium D1 is provided between the first isolation structure 4223e and the second isolation structure 4221e can be determined according to product requirements.

[0141] Understandable Figure 12 and Figure 13 The illustrated embodiments can be used with Figures 7-11 The combination of one or more embodiments shown can ensure the power supply voltage of the first die 41 and the second die 42 while avoiding short-circuit failure of integrated circuit 4, thereby improving or avoiding power integrity issues.

[0142] Figure 12 and Figure 13 The diagram shown above illustrates an architecture where the second die 42 has an "enclave" structure; this is merely an illustrative example. In some embodiments, the first die 41 can also be designed as an "enclave," meaning that the device group in the second module 4b can "fly into" the first device group sub-section 4122a. This will be explained below.

[0143] Figure 14This is a partial top view of the first device group sub-section 4122a in one embodiment. Figure 15 for Figure 14 A magnified view of point B in the diagram.

[0144] like Figure 14 and Figure 15 As shown, in one embodiment, the sixth device group 4123 of the second module 4b can be disposed on the first die 41. The first die 41 also has a third isolation structure 4123e and a fourth isolation structure 4122e. The projection of the sixth device group 4123 along the stacking direction can fall within the range of the first device group sub-part 4122a. The operating voltage of the sixth device group 4123 is different from that of the first device group sub-part 4122a. The sixth device group 4123, the third device group 4121, and the fourth device group 41221 can all belong to the second module 4b. The third isolation structure 4123e can be disposed around the outside of the sixth device group 4123. The fourth isolation structure 4122e can be disposed along the boundary of the first device group sub-part 4122a on the side close to the sixth device group 4123, and disposed around the outside of the third isolation structure 4123e. By providing an isolation structure on the outside of the sixth device group 4123 and on the edge of the first device group 4122 near the fifth device group 4223, short-circuit failure of the integrated circuit 4 can be avoided.

[0145] Understandable Figure 14 and Figure 15 The isolation structure between the first device group 4122 and the sixth device group 4123 shown is not necessary. In another embodiment, electrical isolation between the first device group 4122 and the sixth device group 4123 can also be achieved in other ways.

[0146] like Figure 14 and Figure 15 As shown, for example, a gap may be provided between the third isolation structure 4123e and the fourth isolation structure 4122e, which may be, for example, about 1 μm. The first die 41 may also include an insulating filling medium D2, which is located between the third isolation structure 4123e and the fourth isolation structure 4122e, that is, the insulating filling medium D2 is used to fill the gap between the third isolation structure 4123e and the fourth isolation structure 4122e. By filling the gap between the third isolation structure 4123e and the fourth isolation structure 4122e with the insulating filling medium D2, the electrical isolation between the fourth device group 4221 and the fifth device group 4223 can be strengthened, and short-circuit failure of the integrated circuit 4 can be avoided.

[0147] like Figure 14 and Figure 15 As shown, the width of the insulating fill medium D2 can be determined by the design rules provided by the wafer foundry to ensure that no design rule violation issues are caused.

[0148] Understandable Figure 14 and Figure 15 The insulating filler medium D2 shown is not required. In another embodiment, whether or not an insulating filler medium D2 is provided between the third isolation structure 4123e and the fourth isolation structure 4122e can be determined according to product requirements.

[0149] Understandable Figure 14 and Figure 15 The illustrated embodiments can be combined with Figures 7-13 The combination of one or more embodiments shown can ensure the power supply voltage of the first die 41 and the second die 42 while avoiding short-circuit failure of integrated circuit 4, thereby improving or avoiding power integrity issues.

[0150] In the embodiments of this application, terms such as "first" and "second" are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but in some embodiments also includes steps or units not listed, or other steps or units inherent to these processes, methods, products, or devices.

[0151] It should be understood that in the embodiments of this application, "at least one item" means one item or more items, and "more than one item" means two items or more.

[0152] For ease of description, embodiments of this application may use spatial relation terms such as "below," "below," "lower than," "below," "above," "upper," etc., to describe the relationship between an element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include orientations of the device in use or operation other than those depicted in the drawings. For example, if the device in the drawings is flipped, the orientation of an element described as "below," "below," or "below" other elements or features will change to "above" said other elements or features. Thus, the exemplary terms "below" and "below" can encompass both up and down directions. The device may also have other orientations (rotated 90 degrees or in other orientations), and therefore the spatial relation descriptors used herein should be interpreted accordingly. Furthermore, it will be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there may be one or more layers in between.

[0153] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0154] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. An integrated circuit, characterized in that, The integrated circuit includes a first die and a second die, the first die and the second die are stacked and electrically connected, and the substrates of the first die and the second die are disposed opposite to each other; the second die includes at least one first metal layer, and the at least one first metal layer is the topmost metal layer of the second die; The integrated circuit includes a first module and a second module, which belong to different voltage domains; the first module includes a first device group disposed on the first die and a second device group disposed on the second die, which belong to the same voltage domain, and the first device group includes a first device group sub-section. The second module includes a third device group disposed on the first die and a fourth device group disposed on the second die. The third device group and the fourth device group belong to the same voltage domain. The fourth device group includes a fourth device group sub-section. In the stacking direction of the first die and the second die, the projection of the second device group overlaps with the projection of the portion of the first device group other than the first device group sub-part, the projection of the fourth device group sub-part overlaps with the projection of the first device group sub-part, and the projection of the portion of the fourth device group other than the fourth device group sub-part overlaps with the projection of the third device group. Each of the first metal layers includes a first overlapping region that overlaps with the projection of the first device group sub-part in the stacking direction, and the portion of each first metal layer located within the first overlapping region is used to supply power to the first device group.

2. The integrated circuit according to claim 1, characterized in that, The second die also includes a plurality of second metal layers arranged sequentially along the stacking direction, wherein each of the plurality of second metal layers is located between the at least one first metal layer and the substrate of the second die; each of the second metal layers includes a second overlapping region, the second overlapping region overlapping the projection of the first overlapping region in the stacking direction, and the portion of each second metal layer located in the second overlapping region is used to supply power to the fourth device group.

3. The integrated circuit according to claim 1, characterized in that, The first module further includes a fifth device group, wherein the projection of the fifth device assembly along the stacking direction falls within the range of the fourth device group sub-part; The second die also includes a plurality of second metal layers arranged sequentially along the stacking direction, the plurality of second metal layers being located between the at least one first metal layer and the substrate of the second die; each second metal layer includes a plurality of metal strips arranged in pairs at intervals; each second metal layer includes a second overlapping region, each second overlapping region overlapping the projection of the first overlapping region in the stacking direction; Each of the second metal layers includes a first metal layer sub-section and a second metal layer sub-section, both of which are located within the second overlapping region. Both the first metal layer sub-section and the second metal layer sub-section include a plurality of the metal strips. The first metal layer sub-section is used to supply power to the fourth device group, and the second metal layer sub-section is used to supply power to the fifth device group. The total length L1 of the metal strips in the first metal layer sub-section, the total length L2 of the metal strips in the second metal layer sub-section, the area S1 of the fourth device group sub-section, and the area S2 of the fifth device group satisfy the following relationship: L1 / L2=[(S1-S2)*(1±30%)] / S2.

4. The integrated circuit according to any one of claims 1-3, characterized in that, The second die further includes a third metal layer located between the at least one first metal layer and the substrate of the second die, the third metal layer being adjacent to and electrically connected to the at least one first metal layer; the third metal layer includes a third overlapping region that overlaps with the projection of the first overlapping region in the stacking direction; The third metal layer includes a plurality of first metal strips and a plurality of second metal strips arranged in pairs at intervals. Each first metal strip includes a first portion and each second metal strip includes a second portion. The first portions of the plurality of first metal strips and the second portions of the plurality of second metal strips are all located in the third overlapping region. Each of the first portions is used to power the first device group, and each of the second portions is used to power the fourth device group; the total length of the plurality of first portions is equal to the total length of the plurality of second portions.

5. The integrated circuit according to claim 4, characterized in that, The second die also includes a plurality of metallized vias that penetrate the substrate of the second die and are electrically connected to a plurality of the first metal strips and a plurality of the second metal strips in the third metal layer, respectively.

6. The integrated circuit according to claim 5, characterized in that, The second die also includes a plurality of second metal layers arranged sequentially along the stacking direction, wherein the plurality of second metal layers are all located between the third metal layer and the substrate of the second die; the plurality of second metal layers are provided with channels, the plurality of metallized vias pass through the channels, and each metallized via has a gap with the plurality of second metal layers.

7. The integrated circuit according to claim 5 or 6, characterized in that, The integrated circuit further includes a back redistribution layer, aluminum pads, and a controllable collapse chip connection package substrate that are electrically connected to each other. The back redistribution layer is located on the side of the second die's substrate facing away from the first die. The substrate of the second die, the back redistribution layer, the aluminum pads, and the controllable collapse chip connection package substrate are arranged sequentially along the stacking direction. The plurality of metallized vias are electrically connected to the back redistribution layer.

8. The integrated circuit according to any one of claims 1-7, characterized in that, The first module further includes a fifth device group, a first isolation structure, and a second isolation structure; the projection of the third device group along the stacking direction falls within the range of the fourth device group sub-part; the first isolation structure is arranged around the outside of the fifth device group, and the second isolation structure is arranged along the boundary of the fourth device group sub-part near the third device group and is arranged around the outside of the first isolation structure.

9. The integrated circuit according to claim 8, characterized in that, The second die also includes an insulating filler medium located between the first isolation structure and the second isolation structure.

10. An electronic device, characterized in that, It includes a circuit board and an integrated circuit as described in any one of claims 1-9, wherein the integrated circuit is electrically connected to the circuit board.

Images