A co-pos packaging structure based on a board-level glass substrate and a preparation method thereof

Abstract

The application provides a CoPoS packaging structure based on a board-level glass substrate and a preparation method thereof, the preparation method forms a through hole and a conductive column on the board-level glass substrate, forms a first conductive layer and a second conductive layer on the upper and lower surfaces and is electrically connected with both ends of the conductive column, patterns the first conductive layer to form a first rewiring layer, then attaches a chip and performs plastic packaging, patterns the second conductive layer to form a second rewiring layer, finally, attaches a printed circuit board and fills a bottom filling layer, so that the chip signal is vertically led out through the first rewiring layer, the conductive column and the second rewiring layer, multi-chip high-density fan-out interconnection is realized, signal transmission loss is reduced, interface thermal stress is reduced, high-frequency signal integrity and temperature cycle reliability are improved, mechanical reliability is improved through the plastic packaging layer and the bottom filling layer, and finally, the CoPoS packaging structure with high electrical performance and high reliability and capable of reducing cost in batches is obtained.

Description

Technical Field

[0001] This invention relates to the field of semiconductor chip packaging, and more particularly to a CoPoS packaging structure based on a plate-level glass substrate and its fabrication method. Background Technology

[0002] TSMC, a leader in semiconductor manufacturing technology, has long relied on silicon interposers to achieve high bandwidth and high I / O density integration in its flagship advanced packaging technology, CoWoS (Chipon Wafer on Substrate). However, with the increasing size of AI GPU chips and the growing number of high-bandwidth memory (HBM) stacks, CoWoS has encountered a bottleneck—the size of the photomask limits the maximum package area of ​​a single module.

[0003] To address this challenge, TSMC proposed the CoPoS (Chip on Panel on Substrate) solution. While architecturally similar to CoWoS, CoPoS replaces the traditional silicon interposer with a panel-sized substrate, enabling larger package sizes and better area utilization, overcoming existing technological limitations. The core concept of CoPoS is to "change the circle to a square"—replacing wafer-level packaging with a large rectangular panel substrate, reducing the incomplete chips typically found at the edges of circular wafers. This design change facilitates the integration of more semiconductors within a single package, thereby improving overall computing performance, achieving higher substrate utilization, greater package density, improved yield efficiency, reduced edge waste, and lower unit area cost. The use of larger panel-level packaging provides significantly more package space, higher I / O (input / output) integration, and improved manufacturing efficiency, making it a natural evolution of the CoWoS platform.

[0004] As a novel type of packaging substrate, glass substrates have a smoother surface than plastic substrates; for the same area, the number of vias on glass substrates is significantly greater than on organic substrates. The spacing between vias on glass substrates can be less than 100µm, directly increasing the interconnect density between chips by 10 times. This increased interconnect density can accommodate a larger number of transistors, enabling more complex designs and more efficient space utilization. Simultaneously, glass substrates exhibit superior thermal properties and physical stability compared to plastic substrates; their superior heat resistance ensures that glass substrates are less prone to warping or deformation at high temperatures. Furthermore, the unique electrical properties of the glass core (glass substrate vias) result in lower dielectric loss, allowing for clearer signal and power transmission. This reduces power loss during signal transmission, naturally improving the overall chip efficiency. Compared to ABF plastic substrates, the thickness of glass core substrates can be reduced by about half; this thinner substrate effectively improves signal transmission speed and power efficiency.

[0005] Given the necessity of CoPoS technology and the advantages of glass substrate technology, combining glass substrate technology with CoPoS technology to develop new advanced chip packaging structures and methods will be one of the popular technologies to meet the needs of more packaging space, higher I / O integration, and higher production efficiency. Summary of the Invention

[0006] The purpose of this invention is to provide a CoPoS packaging structure and method based on a board-level glass substrate. This packaging structure and method utilizes a board-level glass substrate as an interposer layer to connect one or more chips to a circuit substrate such as a printed circuit board (PCB). The fabrication of a glass substrate-based CoPoS packaging structure can meet significant demands for more packaging space, higher I / O integration, and higher production efficiency, while also significantly reducing processing costs.

[0007] To achieve the above-mentioned technical objectives, the present invention is implemented through the following technical solution: In a first aspect, the present invention provides a method for fabricating a CoPoS packaging structure based on a plate-level glass substrate, the method comprising: S10, a plurality of spaced through holes are formed on the plate-level glass substrate; S20, a conductive pillar is formed in the through hole, and a first conductive layer and a second conductive layer are formed on the upper and lower surfaces of the plate-level glass substrate, respectively. The first conductive layer and the second conductive layer are electrically connected to the two ends of the conductive pillar, respectively. S30, the first conductive layer is patterned to form a first overwire layer; the first overwire layer includes a plurality of spaced first conductive patterns, each first conductive pattern covering the top surface of its corresponding conductive post and extending outward from the conductive post. S40 connects multiple chips to the first wiring layer, and then forms a molding layer to completely cover the multiple chips. S50, the second conductive layer is patterned to form a second rewiring layer; the second rewiring layer includes a plurality of spaced second conductive patterns, each second conductive pattern covering the bottom surface of its corresponding conductive post and extending outward from the conductive post. S60, the board-level glass substrate is mounted on the printed circuit board, so that the second wiring layer is electrically connected to the printed circuit board. Then, the bottom filler layer is filled between the board-level glass substrate and the printed circuit board to obtain the CoPoS packaging structure based on the board-level glass substrate.

[0008] Specifically, step S10 establishes vertical interconnect channels for the upper and lower surfaces by processing spaced vias on the board-level glass substrate. The glass material has low dielectric loss and a thermal expansion coefficient close to that of silicon, ensuring high-frequency signal quality and thermal stability. The large board size also supports batch processing to reduce costs. Step S20 fills the vias with conductive pillars and deposits conductive layers on the upper and lower surfaces. The conductive pillars are electrically connected to the conductive layers at both ends, opening up the vertical signal path. The conductive layers also serve as the basis for subsequent rewiring processes. Step S30 patterns the conductive layer on the upper surface as the first rewiring layer. The conductive pattern covers the top surface of the conductive pillars and extends outwards, realizing chip I / O. The fan-out redistribution provides corresponding pads for chip mounting; step S40 mounts multiple chips onto the first wiring layer and completely encapsulates them with plastic, completing the electrical connection between the chips and the board-level glass substrate. The cured plastic layer also provides rigid support for back-side processing; step S50 patterns the lower surface conductive layer into the second wiring layer. The conductive pattern covers the bottom surface of the conductive pillars and extends outward, further fanning the signals to the ball grid array pads. The front-to-back sequence avoids damage to the back-side wiring under the high temperature and pressure of plastic encapsulation; step S60 mounts the package onto the printed circuit board and fills the bottom filler layer, completing the system-level interconnect. The bottom filler disperses the stress of the solder joints and improves temperature cycling and drop reliability.

[0009] Preferably, in step S10, the overall size of the plate-level glass substrate is selected from one of 310mm×310mm, 600mm×600mm or 700mm×700mm.

[0010] Specifically, by using the above-mentioned plate-level glass substrates, hundreds to thousands of packaging units can be processed in parallel in a single batch; these three sizes also correspond to the standard stage specifications of existing plate-level packaging equipment, and mass production can be introduced without modifying the equipment.

[0011] Preferably, in step S10, the through hole is formed by laser-induced chemical etching. The specific process includes: first, modifying a preset area of ​​the plate-level glass substrate with a laser to obtain a modified area, and then selectively removing the modified area with a chemical etching solution to form a through hole.

[0012] Specifically, laser-induced chemical etching is used to prepare through-holes. First, a modified zone is formed inside the glass by a laser, and then the modified material is selectively removed using an etchant. Laser modification is a non-contact process that does not generate mechanical stress, avoiding micro-cracks and edge chipping in the glass. The etchant only attacks the modified area, causing almost no lateral etching to the surrounding unmodified glass. Therefore, the through-hole cone angle is controllable, the sidewalls are smooth, and the hole diameter consistency is good, making it suitable for dense through-hole arrays with high aspect ratios. Compared to dry plasma etching, this process has a higher speed and lower equipment investment, making it more suitable for large-scale batch processing.

[0013] Preferably, in step S20, the conductive pillar, the first conductive layer, and the second conductive layer each comprise one or a combination of two or more of aluminum, copper, gold, platinum, nickel, and tin.

[0014] Specifically, the aforementioned metals are all conventional conductive materials used in semiconductor packaging, with mature processes and stable supply chains. A single metal can meet basic interconnection requirements, while combinations of two or more can accommodate different functions.

[0015] Preferably, in steps S30 and S50, the patterning process is performed sequentially using photolithography, wet etching, and resist removal.

[0016] Specifically, the patterning of the first and second wiring layers is completed sequentially using photolithography, wet etching, and resist removal. This is the most mature pattern transfer process chain in the semiconductor industry. Photolithography precisely defines the wiring pattern using a mask, and the resolution can meet the requirements of fine-pitch wiring. Wet etching has a high selectivity for metal layers, with steep sidewalls and almost no damage to the underlying glass substrate. The resist removal step thoroughly removes residual photoresist, ensuring a clean surface for subsequent processes.

[0017] Preferably, in step S40, the multiple chips are the same type of chip or different types of chips; the material of the molding layer is epoxy resin, silicon oxide insulating material or other insulating material.

[0018] Specifically, multiple chips can be of the same or different types, enabling the packaging structure to support both homogeneous and heterogeneous integration, making it applicable to various scenarios regardless of chip type. The molding layer uses epoxy resin, silicon oxide insulating material, or other insulating materials: epoxy resin has mature technology, good flowability, and low cost, making it suitable for mass production; silicon oxide insulating material has a better match with the thermal expansion coefficient of the glass substrate, which can reduce interfacial thermal stress and has low dielectric loss, making it suitable for high-frequency and high-speed applications.

[0019] Preferably, the molding layer is formed on the upper surface of the board-level glass substrate and fills the gap between the board-level glass substrate and the chip.

[0020] Specifically, the molding compound is formed on the upper surface of the board-level glass substrate and fills the gap between the chip and the substrate. On the one hand, it completely seals and protects the chip, isolating it from moisture and mechanical damage. On the other hand, the filler penetrates beneath the chip, creating a bottom-filling effect on the solder joints or bumps between the chip and the redistribution layer. This alleviates the shear stress caused by the mismatch in thermal expansion coefficients between the chip and the glass substrate, improving interconnect reliability under temperature cycling. Furthermore, the cured molding compound and the glass substrate bond together as a rigid whole, providing mechanical support for the subsequent patterning of the second redistribution layer and suppressing warping deformation of the large board during back-side photolithography and etching.

[0021] Preferably, in step S60, the lower surface of the second wiring layer is electrically connected to the printed pads on the upper surface of the printed circuit board via metal conductive balls; the metal conductive balls include at least one of aluminum, copper, gold, platinum, nickel and tin.

[0022] Specifically, the second wiring layer is electrically connected to the pads of the printed circuit board via metal conductive balls, using a ball grid array configuration. This results in small solder joint spacing and high I / O density, meeting the large signal output requirements of multi-chip packages. The conductive balls themselves have a certain height, forming a uniform gap between the glass substrate and the printed circuit board, reserving space for capillary inflow of the bottom filler. The metal conductive balls are selected from at least one of aluminum, copper, gold, platinum, nickel, and tin, consistent with the aforementioned conductive pillar material system, and compatible with electroplating or ball-planting processes. Tin-based solder balls, after reflow, can form a reliable metallurgical connection.

[0023] Preferably, in step S60, the bottom filler layer fills the gap between the plate-grade glass substrate and the printed circuit board; the material of the bottom filler layer is an epoxy resin-based composite material.

[0024] Specifically, an epoxy resin-based composite material is filled between the board-level glass substrate and the printed circuit board as a bottom filler layer. Before curing, this material has good fluidity and can completely penetrate into the tiny gaps between the ball grid array solder joints through capillary action, without voids. After curing, it has a moderate modulus, which firmly bonds the glass substrate and the printed circuit board together, dispersing the stress generated by thermal cycling and mechanical impact to the entire interface rather than concentrating it on the solder joints, significantly improving the pass rate of temperature cycling and drop tests.

[0025] Secondly, the present invention also provides a CoPoS packaging structure based on a plate-level glass substrate, wherein the CoPoS packaging structure based on the plate-level glass substrate is prepared by the preparation method described in any of the above claims.

[0026] Specifically, the CoPoS packaging structure prepared by the above method uses a glass substrate as the core interposer, which has lower dielectric loss and better dimensional stability compared to traditional organic substrate interposers, making it suitable for high-frequency and high-speed signal transmission. The through-hole conductive pillars, together with the double-sided redistribution layer, realize high-density fan-out interconnection from the chip to the printed circuit board, shortening the signal path. The molding layer completely covers the chip to provide mechanical and environmental protection, and the bottom filler layer disperses the stress of the solder joints. The overall structure is superior to conventional substrate-level packaging in terms of electrical performance, thermal reliability, and mechanical reliability, and is suitable for multi-chip heterogeneous integration and high-bandwidth application scenarios.

[0027] The beneficial effects of this invention are as follows: Unlike existing technologies, this invention provides a CoPoS packaging structure based on a board-level glass substrate and its fabrication method. The fabrication method involves forming through-holes on the board-level glass substrate and forming conductive pillars within the through-holes. A first conductive layer and a second conductive layer are formed on the upper and lower surfaces of the board-level glass substrate, respectively, and electrically connected to the two ends of the conductive pillars. After patterning the first conductive layer to form a first redistribution layer, multiple chips are electrically connected to the first redistribution layer, and a molding compound completely covers the multiple chips. Then, the second conductive layer is patterned to form a second redistribution layer. Finally, the board-level glass substrate is mounted on a printed circuit board and filled with a bottom filler layer, so that chip signals pass through the first redistribution layer, conductive pillars, and the second redistribution layer. The wiring layer is vertically led to the printed circuit board, realizing high-density fan-out interconnection of multiple chips. This reduces signal transmission loss by utilizing the low dielectric loss and short interconnection path of the board-level glass substrate. At the same time, the thermal expansion coefficients of the board-level glass substrate and the chip are close to reduce thermal stress at the packaging interface, thereby improving the integrity of high-frequency and high-speed signals and reducing interconnect failure rate under temperature cycling. Furthermore, the molding layer completely covers multiple chips and fills the gap between the board-level glass substrate and the chips, and the bottom filler layer fills the gap between the board-level glass substrate and the printed circuit board. This comprehensively improves mechanical reliability from the chip side to the substrate side, ultimately resulting in a CoPoS packaging structure with excellent electrical performance, high reliability, and cost reduction through mass production using the board-level glass substrate. Attached Figure Description

[0028] Figures 1-9 This is a schematic diagram of each step in the fabrication method of the CoPoS packaging structure based on a plate-level glass substrate provided in Example 1; Figure 10 This is a schematic diagram of the CoPoS packaging structure based on a board-level glass substrate provided in Example 1; In the accompanying drawings: 10—board-level glass substrate; 11—second conductive layer; 12—first conductive layer; 13—metal connecting pillar; 14—chip conductive structure; 15—chip; 16—molding layer; 17—metal conductive ball; 18—printed circuit board; 19—bottom filler layer; 201—lower surface of board-level glass substrate; 202—upper surface of board-level glass substrate; 203—lower surface of second redistribution layer; 204—upper surface of first conductive layer; 205—upper surface of molding layer. Detailed Implementation

[0029] The technical solutions of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0030] The technical solution of the present invention will now be further described with reference to specific embodiments.

[0031] Example 1: Please see Figures 1-9 , Figures 1 to 9 This is a schematic diagram of each step in the fabrication method of the CoPoS packaging structure based on a plate-level glass substrate provided in Example 1; wherein, the fabrication method of the CoPoS packaging structure based on a plate-level glass substrate specifically includes the following steps: Step (1): Multiple spaced through-holes are formed on the plate-level glass substrate 10 using through-glass via (TGV) technology, resulting in the following... Figure 1 The structure shown is as follows. In this embodiment 1, the plate-level glass substrate 10 can be made of alkali-free glass, quartz glass, or low dielectric loss glass (preferably quartz glass). The overall size can be one of 310mm×310mm, 600mm×600mm, or 700mm×700mm (preferably 600mm×600mm), and the thickness can be 0.3mm to 1.0mm (preferably 1.0mm).

[0032] The aforementioned through holes are formed using a laser-induced chemical etching process: first, a preset area of ​​the plate-level glass substrate 10 is scanned and modified using a picosecond or femtosecond laser to obtain a modified area; then, the plate-level glass substrate 10 is immersed in a hydrofluoric acid-based etching solution, and the modified area is selectively removed by utilizing the difference in etching rates between the modified and unmodified areas; by controlling the laser induction time, induction area, etching solution concentration, and etching time, through holes with different aperture sizes can be formed.

[0033] Step (2), in Figure 1Based on the structure shown, conductive pillars are formed within the vias using physical vapor deposition (PVD) combined with deep-hole electroplating. A second conductive layer 11 is formed on the lower surface 201 of the plate-level glass substrate 10, and a first conductive layer 12 is formed on the upper surface 202 of the plate-level glass substrate 10. The second conductive layer 11 and the first conductive layer 12 are electrically connected to the two ends of the conductive pillars, respectively, to obtain the structure shown. Figure 2 The structure shown.

[0034] Specifically, copper seed layers are first deposited on the inner wall of the through-hole and on the lower surface 201 and upper surface 202 of the plate-level glass substrate 10 using a PVD process. Then, copper is filled into the through-hole from bottom to top using a deep-hole electroplating process to form conductive pillars. A first conductive layer 12 and a second conductive layer 11 are formed by electroplating on the upper and lower surfaces. After electroplating, surface copper overflow can be removed and planarization can be achieved by chemical mechanical polishing (CMP). In this embodiment 1, the conductive pillars, the first conductive layer 12, and the second conductive layer 11 are all made of copper, and the thickness of the first conductive layer 12 and the second conductive layer 11 can be selected from 5μm to 20μm (preferably 10μm).

[0035] Step (3), in Figure 2 Based on the structure shown, the first conductive layer 12 is patterned using photolithography and etching processes to form the first redistribution layer RDL1, resulting in the structure shown. Figure 3 The structure shown.

[0036] Specifically, photoresist is first coated on the upper surface 204 of the first conductive layer 12. After pre-baking, exposure, and development, a photoresist mask with a predetermined wiring pattern is formed. Then, the copper layer not covered by the photoresist is removed by wet etching or dry etching. Finally, the residual photoresist is removed by a photoresist removal process to obtain the first wiring layer RDL1. The first wiring layer RDL1 includes multiple spaced first conductive patterns. Each first conductive pattern covers the top surface of its corresponding conductive pillar and extends outward from the conductive pillar to realize the fan-out redistribution of chip I / O. In this embodiment 1, the line width / line spacing of the first wiring layer RDL1 can be 10μm / 10μm or finer.

[0037] Step (4): Chip 15 is mounted onto the first redistribution layer RDL1 using flip-chip (FC) technology. Chip 15 includes a first chip (Chip 1) and a second chip (Chip 2). Chip 15 is electrically connected to the first redistribution layer RDL1 via metal connection posts 13, resulting in the following... Figure 4The structure is shown. The conductive structure 14 (Al Pad) of chip 15 is electrically connected to the metal connecting post 13. The metal connecting post 13 can be a copper pillar solder cap structure or a solder ball structure, and the material includes at least one of copper, nickel, gold, and tin (in this embodiment 1, it is a copper pillar). The conductive post penetrates the board-level glass substrate 10 and electrically connects the first redistribution layer RDL1 to the second conductive layer 11. In this embodiment 1, the first chip (Chip 1) and the second chip (Chip 2) can be the same type of chip or different types of chips. After mounting, reflow soldering is performed to form a metallurgical connection between the metal connecting post 13 and the first redistribution layer RDL1.

[0038] Step (5), through the molding process... Figure 4 A molding compound 16 is formed above and around the first chip (Chip 1) and the second chip (Chip 2) in the structure shown, to completely cover the chip 15, resulting in the structure shown. Figure 5 The structure shown is illustrated. In this embodiment 1, a transfer molding process is used. The board-level glass substrate 10 after chip mounting is placed into the mold cavity. Epoxy resin-based molding compound is injected into the cavity at 150℃~180℃ and 5MPa~15MPa. Under pressure, the molding compound fills the space around the chip 15 and the gap between the chip 15 and the board-level glass substrate 10. After heating and curing, a molding layer 16 is formed. The upper surface 205 of the molding layer 16 is about 50μm~100μm higher than the top surface of the chip. After curing, post-curing treatment can be performed to release residual stress.

[0039] Step (6), in Figure 5 Based on the structure shown, the second conductive layer 11 is patterned using photolithography and etching processes to form the second redistribution layer RDL2, resulting in the structure shown. Figure 6 The structure shown is as follows. The photolithography, etching, and resist removal processes in this step are the same as in step (3). The second redistribution layer RDL2 includes multiple spaced second conductive patterns. Each second conductive pattern covers the bottom surface of its corresponding conductive pillar and extends outward from the conductive pillar, further fanning out the signal to the BGA (Ball Grid Array) pad position. Since a rigid molding layer 16 has been formed on the upper surface of the board-level glass substrate 10 at this time, substrate warping during the back-side photolithography and etching process can be effectively suppressed.

[0040] Step (7), in Figure 6 The lower surface 203 of the second redistribution layer RDL2 of the structure shown is planted with balls to form metal conductive balls 17, resulting in the structure shown. Figure 7 The structure is shown. Specifically, tin-based solder balls are placed at the pad positions of the second redistribution layer RDL2 by stencil printing or an automatic ball-mounting machine, and then reflow soldering is performed to form metal conductive balls 17. In this embodiment, the material of the metal conductive balls 17 includes at least one of aluminum, copper, gold, platinum, nickel, and tin (tin balls are used in this embodiment 1).

[0041] Step (8), Figure 7 The structure shown is mounted on a printed circuit board (PCB) 18 via metal conductive balls 17. Reflow soldering establishes a metallurgical connection between the metal conductive balls 17 and the printed pads on the upper surface of the PCB 18, electrically connecting the second redistribution layer RDL2 to the PCB 18, resulting in the structure shown. Figure 8 The structure shown.

[0042] Step (9), use underfill material to... Figure 8 In the structure shown, the gap between the board-level glass substrate 10 and the printed circuit board 18 is completely filled, forming a bottom filler layer 19, resulting in the structure shown. Figure 9 The CoPoS packaging structure based on the board-level glass substrate 10 is shown.

[0043] Specifically, adhesive is applied along the edge of the plate-level glass substrate 10, and capillary action is used to allow the bottom filler material to penetrate into and completely fill the gap between the plate-level glass substrate 10 and the printed circuit board 18. After heating and curing, a bottom filler layer 19 is formed. In this embodiment 1, the material of the bottom filler layer 19 is an epoxy resin-based composite material.

[0044] Please see Figure 10 Example 1 also provides a CoPoS packaging structure based on a plate-level glass substrate 10, which is prepared by the above-described preparation method.

[0045] The present invention provides a chip packaging structure based on a board-level glass substrate 11 and its preparation method, which uses the board-level glass substrate 10 as a transition layer, fixes the chip 15 (one or more) on the first side of the board-level glass substrate 10 by flip chip (FC) technology, and then connects the second side of the board-level glass substrate 10 to a printed circuit board 18 to prepare a CoPoS packaging structure based on the board-level glass substrate 10.

[0046] In summary, compared with the prior art, the chip packaging structure based on a plate-level glass substrate 11 and its fabrication method provided by the present invention have the following technical advantages: (1) This technical solution uses a large-size board-level glass substrate 10 as the carrier, which can use board-level packaging technology to complete all processes such as photolithography, electroplating, and molding in parallel. Hundreds to thousands of packaging units can be processed simultaneously in a single batch. Taking a 600mm square board as an example, its effective processing area is more than 5 times that of a 12-inch wafer. Equipment depreciation, consumables and labor costs are all spread to a single package based on the area. At the same time, the square substrate reduces material waste in the corner areas compared to the round wafer, further reducing the unit cost.

[0047] (2) In this technical solution, the board-level glass substrate 10 serves as the transition layer between the chip 15 and the printed circuit board 18. Its coefficient of thermal expansion is close to that of the silicon chip, which can significantly reduce the interfacial thermal stress under temperature cycling and improve the reliability of the package. The glass material has stable dimensions, high flatness, and low moisture absorption, and its physical stability is better than that of traditional organic substrates. More importantly, the dielectric constant and dielectric loss of the glass are much lower than those of organic substrates. Combined with the vertical interconnect path formed by the conductive pillars in the glass via (TGV), the parasitic parameters and power loss during signal transmission are greatly reduced, allowing for faster and clearer signal and power transmission, thereby improving the overall operating efficiency of the chip.

[0048] (3) The CoPoS packaging structure of this technical solution can integrate multiple chips 15 on the same board-level glass substrate 10, which supports both parallel expansion of computing power of the same type of chips and heterogeneous integration of different types of chips 15; with the double-sided redistribution layers (RDL1 / RDL2) and fine-pitch glass vias, high-density I / O fan-out interconnects are achieved. This results in higher substrate utilization, greater packaging density and shorter signal paths, and a significant improvement in overall computing performance; at the same time, the board-level process is mature and stable with controllable yield, and combined with the reduced edge waste of the square substrate, a lower unit area packaging cost is achieved.

[0049] It should be noted that all the above embodiments belong to the same inventive concept, and the descriptions of each embodiment have different focuses. Where the description in a particular embodiment is not detailed, please refer to the description in other embodiments.

[0050] The above embodiments merely illustrate implementation methods of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A method for fabricating a CoPoS packaging structure based on a plate-level glass substrate, characterized in that, The method includes: S10, a plurality of spaced through holes are formed on the plate-level glass substrate; S20, a conductive pillar is formed in the through hole, and a first conductive layer and a second conductive layer are formed on the upper and lower surfaces of the plate-level glass substrate, respectively. The first conductive layer and the second conductive layer are electrically connected to the two ends of the conductive pillar, respectively. S30, the first conductive layer is patterned to form a first redistribution layer; the first redistribution layer includes a plurality of spaced first conductive patterns, each first conductive pattern covering the top surface of the corresponding conductive pillar and extending outward from the conductive pillar. S40, multiple chips are electrically connected to the first redistribution layer, and then a molding compound is formed to completely cover the multiple chips; S50, the second conductive layer is patterned to form a second redistribution layer; the second redistribution layer includes a plurality of spaced second conductive patterns, each second conductive pattern covering the bottom surface of the corresponding conductive post and extending outward from the conductive post; S60, the board-level glass substrate is mounted on the printed circuit board, so that the second redistribution layer is electrically connected to the printed circuit board, and then a bottom filler layer is filled between the board-level glass substrate and the printed circuit board to obtain a CoPoS packaging structure based on the board-level glass substrate.

2. The method for fabricating a CoPoS packaging structure based on a plate-level glass substrate according to claim 1, characterized in that, In step S10, the overall size of the plate-level glass substrate is selected from one of 310mm×310mm, 600mm×600mm, or 700mm×700mm.

3. The method for fabricating a CoPoS packaging structure based on a plate-level glass substrate according to claim 1, characterized in that, In step S10, the through hole is formed by laser-induced chemical etching. The specific process includes: first, modifying a preset area of ​​the plate-level glass substrate with a laser to obtain a modified area, and then selectively removing the modified area with a chemical etching solution to form the through hole.

4. The method for fabricating a CoPoS packaging structure based on a plate-level glass substrate according to claim 1, characterized in that, In step S20, the conductive pillar, the first conductive layer, and the second conductive layer each include one or a combination of two or more of aluminum, copper, gold, platinum, nickel, and tin.

5. The method for fabricating a CoPoS packaging structure based on a plate-level glass substrate according to claim 1, characterized in that, In steps S30 and S50, the patterning process is performed sequentially using photolithography, wet etching, and resist removal.

6. The method for fabricating a CoPoS packaging structure based on a plate-level glass substrate according to claim 1, characterized in that, In step S40, the plurality of chips may be the same type of chip or different types of chips; the material of the molding layer is epoxy resin or silicon oxide insulating material.

7. The method for fabricating a CoPoS packaging structure based on a plate-level glass substrate according to claim 6, characterized in that, The molding layer is formed on the upper surface of the board-level glass substrate and fills the gap between the board-level glass substrate and the chip.

8. The method for fabricating a CoPoS packaging structure based on a plate-level glass substrate according to claim 1, characterized in that, In step S60, the lower surface of the second redistribution layer is electrically connected to the printed pads on the upper surface of the printed circuit board via metal conductive balls; the metal conductive balls include at least one of aluminum, copper, gold, platinum, nickel and tin.

9. The method for fabricating a CoPoS packaging structure based on a plate-level glass substrate according to claim 1, characterized in that, In step S60, the bottom filler layer fills the gap between the board-level glass substrate and the printed circuit board; the material of the bottom filler layer is an epoxy resin-based composite material.

10. A CoPoS packaging structure based on a plate-level glass substrate, characterized in that, The CoPoS packaging structure based on a plate-level glass substrate is prepared by the preparation method described in any one of claims 1 to 9.

Images