Semiconductor package device and electronic apparatus

Abstract

The utility model provides a semiconductor packaging device and electronic equipment. The semiconductor packaging device comprises a lead frame, a plurality of semiconductor chips and an insulating packaging body, the lead frame comprises a plurality of base islands, and the adjacent base islands are arranged at intervals; the semiconductor chips are coupled to the first surfaces of the base islands one by one; the insulating packaging body wraps the lead frame and the plurality of semiconductor chips; the pins arranged on the second surface of the base island extend out of the insulation packaging body, and the second surface and the first surface are oppositely arranged. According to the semiconductor packaging structure, a plurality of semiconductor chips can be integrated in one insulating packaging body, and the semiconductor packaging structure is small in packaging size and high in heat dissipation efficiency.

Description

Technical Field

[0001] The present application relates to the field of chip packaging technology, and in particular to a semiconductor packaging device and an electronic device. Background Art

[0002] As more and more electronic devices are moving towards miniaturization and integration, power devices, as the main components of electronic equipment products, are also committed to miniaturization and integration. Among them, one of the directions of miniaturization of power devices is to adopt a more compact and smaller packaging structure, the structural form of which is to integrate multiple semiconductor chips in an insulating package. The existing packaging structure is usually suitable for a single semiconductor chip, for example, the semiconductor chip is connected to the pins on the lead frame by wire bonding, aluminum tape or metal clips (Clip), and then packaged. In addition, the PDFN packaging technology is currently mostly used, resulting in the need to reserve space on the side of the lead frame to layout the pins, which leads to a larger package volume, especially in the packaging scenario of multiple semiconductor chips. After packaging, each packaged chip needs to be separated by cutting the ribs, resulting in a larger space on the side of the lead frame to layout the side ribs, and the package volume is larger, which also leads to the current difficulty in integrating multiple semiconductor chips into an insulating package. Utility Model Content

[0003] In view of this, the present application provides a semiconductor packaging device and an electronic device, which can improve the problem of the prior art that it is difficult to integrate multiple semiconductor chips into an insulating package and the package volume is large.

[0004] A semiconductor packaging device provided in the present application includes a lead frame, multiple semiconductor chips and an insulating packaging body; the lead frame includes multiple base islands, and adjacent base islands are arranged at intervals; each of the semiconductor chips is coupled one by one to the first surface of each base island; the insulating packaging body wraps the lead frame and the multiple semiconductor chips; the base islands are provided with pins, and the pins extend from the second surface of the base islands to the outside of the insulating packaging body, and the second surface is arranged opposite to the first surface.

[0005] Optionally, an electrical surface of the semiconductor chip faces and is coupled to the first surface of the base island.

[0006] Optionally, the semiconductor packaging device also includes a conductive connector, one end of which is coupled to the back side of the semiconductor chip and the other end of which extends to connect with the source contact portion of the base island; the source contact portion is arranged on a side of the base island that is not adjacent to any base island.

[0007] Optionally, adjacent side edges of any two adjacent base islands are parallel straight edges.

[0008] Optionally, any two adjacent base islands are arranged symmetrically.

[0009] Optionally, the first surface of the base island is provided with a plurality of first grooves, second grooves and gate contact portions; adjacent first grooves are arranged at intervals, and the depths of the first grooves and the second grooves are both less than the thickness of the base island; the second grooves are arranged around the gate contact portion; a conductive layer is arranged in each of the first grooves, and the semiconductor chip contacts the conductive layer to couple to the first surface of the base island.

[0010] Optionally, the conductivity of the conductive layer is greater than the conductivity of the base island.

[0011] Optionally, solder paste is provided on the back side of the conductive layer and the semiconductor chip, the electrical side of the semiconductor chip contacts the conductive layer through the solder paste, and the conductive connector is coupled to the back side of the semiconductor chip through the solder paste.

[0012] Optionally, the base island is a copper plate, and the conductive layer is a silver layer.

[0013] The present application provides an electronic device, comprising a circuit board and a semiconductor packaging device as described in any one of the items, wherein the pins are connected to the circuit board.

[0014] As described above, the lead frame of the present application includes a plurality of base islands arranged at intervals, and each semiconductor chip is coupled one by one to the first surface of each base island. By wrapping the lead frame and the plurality of semiconductor chips with an insulating package, the plurality of semiconductor chips can be integrated into an insulating package. Moreover, the pins of the lead frame are arranged on the second surface of each base island opposite to the first surface and extend outside the insulating package, and do not occupy the side space of each base island, thereby reducing the size of each base island and the lead frame, reducing the package volume, and facilitating the miniaturization of semiconductor package devices.

[0015] In addition, the electrical surface of the semiconductor chip is coupled to the first surface of the base island, that is, the present application adopts FC (Flip chip) technology, which can make the distance between the electrical surface (that is, the heat-generating surface) of the semiconductor chip and the base island smaller. The base island can be used as a heat dissipation substrate, which is equivalent to shortening the heat conduction path between the semiconductor chip and the heat dissipation substrate, thereby improving the heat dissipation efficiency of high-power density semiconductor packaging devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A partial structural stereogram of a semiconductor packaging device provided in an embodiment of the present application;

[0017] Figure 2 for Figure 1 A front plan view of a semiconductor package device is shown;

[0018] Figure 3 A back side plan view of a semiconductor package device provided in an embodiment of the present application;

[0019] Figure 4 for Figure 1 A cross-sectional view of a semiconductor package device along the AA' direction shown;

[0020] Figure 5 for Figure 1 A front plan view of a single base island of a semiconductor package device is shown. DETAILED DESCRIPTION

[0021] In order to solve the above problems existing in the prior art, the present application provides a semiconductor packaging device and an electronic device. These several protection themes are based on the same concept, and the principles of solving the problems are basically the same or similar. The implementation methods of each protection theme can refer to each other, and the repeated parts will not be repeated.

[0022] In order to make the purpose, technical solutions and advantages of the present application clearer, the technical solutions of the present application will be clearly described below in conjunction with specific embodiments and corresponding drawings. Obviously, the embodiments described below are only part of the embodiments of the present application, not all of the embodiments. In the absence of conflict, the following embodiments and their technical features can be combined with each other and also belong to the technical solutions of the present application.

[0023] In the description of the embodiments of the present application, terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", and "counterclockwise" indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the technical solutions of the corresponding embodiments, rather than indicating or implying that a device or element must have a specific orientation, be constructed and operated in a specific orientation, and should not be understood as a limitation on the present application.

[0024] The semiconductor package device provided in the embodiment of the present application includes a lead frame 1, a plurality of semiconductor chips 2, and an insulating package body 3. Figures 1 to 5 , is a schematic diagram of a partial structure of a semiconductor packaging device provided in an embodiment of the present application, for example, Figure 1 and Figure 2 Only the assembly schematic diagram of the lead frame 1 and the plurality of semiconductor chips 2 is shown, while the insulating package 3 is not shown; Figure 3 The diagram shows a back side view of a semiconductor package device provided with an insulating package body 3 .

[0025] The lead frame 1 includes a plurality of base islands 10. The number of base islands 10 can be determined according to the actual adaptability required, for example, the number can be an even number. For ease of description, the embodiment of the present application is described by taking the four base islands 10 shown in the figure as an example. Any adjacent base islands 10 are arranged at intervals. The so-called interval arrangement can be understood as: a gap is arranged between two adjacent base islands 10 so that the two are not connected. Each base island 10 is independently coupled to a semiconductor chip 2, and the corresponding coupled semiconductor chip 2 can work independently.

[0026] Each semiconductor chip 2 is coupled to the first surface 101 of each base island 10. The second surface 102 of each base island 10 is arranged opposite to the first surface 101, and a plurality of pins 11 are arranged on the second surface 102. When the semiconductor package device is mounted on a circuit board, for example, these pins 11 are used for welding with the circuit board, for example, so as to realize the mounting of multiple semiconductor chips 2.

[0027] The insulating package 3 encapsulates the lead frame 1 and the plurality of semiconductor chips 2, thereby integrating the plurality of semiconductor chips 2 into one insulating package 3. The pins 11 extend from the second surface 102 of each base island 10 to the outside of the insulating package 3, so as to be used for welding with, for example, a circuit board.

[0028] According to industry tradition, the first surface 101 of the base island 10 is called the front side, and the second surface 102 of the base island 10 is called the back side. In the present application, the pins 11 are arranged on the back side of the base island 10 and the lead frame 1, and will not occupy the side space of each base island 10. Thus, the size of each base island 10 and the lead frame 1 can be reduced, the package volume can be reduced, and it is beneficial to the miniaturization of semiconductor packaging devices.

[0029] In e.g. Figures 1 to 4 In the scene shown, these base islands 10 and multiple semiconductor chips 2 can be arranged in an array, and the shapes and shapes of the base islands 10 can be the same. Similarly, multiple semiconductor chips 2 can also be the same. Any two adjacent base islands 10 are symmetrically arranged. For example, the two base islands 10 in the upper row are symmetrically arranged along the axis parallel to the first direction x between the two, and the two base islands 10 in the lower row are symmetrically arranged along the axis parallel to the first direction x between the two; the two base islands 10 in the left column are symmetrically arranged along the axis parallel to the third direction z between the two, and the two base islands 10 in the right column are symmetrically arranged along the axis parallel to the third direction z between the two. This regular structural design is conducive to simplifying the manufacturing process of the lead frame 1 and the installation of multiple semiconductor chips 2.

[0030] The first direction x can be regarded as the length direction of the semiconductor package device (of course, including the components including the base island 10), the third direction z can be regarded as the width direction of the semiconductor package device, and the thickness direction of the semiconductor package device is the second direction y. The first direction x, the second direction y and the third direction z are perpendicular to each other and can be regarded as three coordinate axes of a three-dimensional rectangular coordinate system. It should be understood that the so-called perpendicularity in the whole application does not require that the angle between the two must be 90°, but allows a deviation of, for example, ±10°, that is, the angle between the two perpendicular directions is 80° to 100°; similarly, the so-called parallelism does not require that the angle between the two must be 0° or 180°, but allows a deviation of, for example, ±10°, that is, the angle between the two parallel directions is 0° to 10° or 170° to 190°.

[0031] Optionally, the adjacent sides of any two adjacent base islands 10 are parallel straight sides, so that the distance between the two adjacent base islands 10 can be smaller, which is beneficial to further reduce the packaging volume.

[0032] The specific structure of the base island 10 can be determined according to the adaptability of the specific type of the semiconductor chip 2. Taking the semiconductor chip 2 as a MOS chip as an example, the first surface 101 of the base island 10 is provided with a plurality of first grooves 10a, second grooves 10b and a gate contact portion 121. The three first grooves 10a shown in the figure are only exemplary. Adjacent first grooves 10a are arranged at intervals. The first grooves 10a and the second grooves 10b can be made by an etching process, and the depth of either one is less than the thickness of the base island 10, for example, it can be half the thickness of the base island 10. The second groove 10b is arranged around the gate contact portion 121.

[0033] A conductive layer (not shown) is disposed in each first groove 10a, and the semiconductor chip 2 contacts the conductive layer to couple to the first surface 101 of the base island 10. Optionally, the conductivity of the conductive layer may be greater than the conductivity of the base island 10, thereby improving the electrical connection performance between the semiconductor chip 2 and the base island 10. In an actual scenario, the base island 10 may be a copper plate, and the conductive layer may be a silver layer.

[0034] The plurality of first trenches 10 a (and the conductive layers formed in the first trenches 10 a ) can be regarded as drain contact portions of the base island 10 , to which the drain of the semiconductor chip 2 is coupled. The gate of the semiconductor chip 2 is coupled to the gate contact portion 121 .

[0035] The source contact portion 122 of the base island 10 may be a separate component. Specifically, the base island 10 includes a main body, the first trench 10a, the second trench 10b and the gate contact portion 121 are all formed in the main body, and the source contact portion 122 is independent of the main body. Figures 1 to 5In the illustrated scenario, the source contact portion 122 is disposed on a side of the base island 10 that is not adjacent to any base island 10 , thereby preventing the distance between adjacent base islands 10 from being too large, which is beneficial for reducing the package volume.

[0036] The semiconductor packaging device also includes a conductive connector 4, such as a metal clip such as a copper clip, one end of which is coupled to the source of the semiconductor chip 2 and the other end of which extends to connect to the source contact portion 122 of the base island 10, thereby coupling the source of the semiconductor chip 2 to the source contact portion 122.

[0037] The source contact portion 122 , the gate contact portion 121 , and the drain contact portion are respectively connected to the aforementioned pins 11 on the second surface 102 .

[0038] In one implementation scenario, the electrical surface of the semiconductor chip 2 faces and is coupled to the first surface 101 of the base island 10. That is, the present application adopts FC technology, which can make the distance between the electrical surface (that is, the heat-generating surface) of the semiconductor chip 2 and the base island 10 smaller. The base island 10 can be used as a heat dissipation substrate. The present application is equivalent to shortening the heat conduction path between the electrical surface (that is, the heat-generating surface) of the semiconductor chip 2 and the heat-dissipating substrate. For the high-power-density semiconductor packaging device of the present application, the heat dissipation efficiency can be improved.

[0039] Optionally, solder paste is provided on the conductive layer, and the electrical surface of the semiconductor chip 2 contacts the conductive layer through the solder paste; the back side of the semiconductor chip 2 (arranged opposite to the electrical surface) may also be provided with solder paste, and the conductive connector 4 is coupled to the back side of the semiconductor chip 2 through the solder paste. The solder paste can increase the contact surface for achieving electrical connection and ensure stable electrical connection between the corresponding two bodies.

[0040] It should be understood that in other scenarios, the back side of the semiconductor chip 2 can be designed to be coupled to the first surface 101 of the base island 10, that is, the chip face-up technology can be adopted; further, the conductive connecting plate 4 can be a metal clip such as a copper clip, or a structural member composed of any combination of traditional wire bonding, aluminum tape, etc.

[0041] The embodiment of the present application also provides an electronic device, comprising a circuit board and a semiconductor package device as described in any embodiment, wherein the pins 11 of the semiconductor package device are connected to the circuit board. Therefore, the electronic device has the beneficial effects that can be produced by the semiconductor package device of the corresponding embodiment.

[0042] The electronic device may be any electronic product or device such as a tablet computer, a laptop computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a camera, a camcorder, a voice recorder, an MP3, an MP4, a PSP, etc., or any intermediate product including the flash memory device.

[0043] The electronic device provided in the embodiment of the present application is a complete electronic device and also has the structure of a known electronic device. Here, only the part of the electronic device involving the power device of the semiconductor chip packaging is described, and other components are not described in detail.

[0044] The above descriptions are only some embodiments of the present application, and are not intended to limit the patent scope of the present application. For ordinary technicians in this field, all equivalent structural changes made using the contents of this specification and drawings are also included in the patent protection scope of the present application.

[0045] Although the terms "first, second", etc. are used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. In addition, the singular forms "one", "an", and "the" are intended to include plural forms as well. The terms "or" and "and / or" are interpreted as inclusive, or mean any one or any combination. Only when the combination of elements, functions, steps, or operations is inherently mutually exclusive in some way, an exception to this definition will occur.

Claims

1. A semiconductor packaging device, It is characterized in that It includes a lead frame, a plurality of semiconductor chips and an insulating package; The lead frame includes a plurality of base islands, and adjacent base islands are arranged at intervals; Each of the semiconductor chips is coupled to the first surface of each of the base islands one by one; The insulating package wraps the lead frame and the plurality of semiconductor chips; The base island is provided with pins, and the pins extend from the second surface of the base island to the outside of the insulating packaging body, and the second surface is arranged opposite to the first surface.

2. The semiconductor package device according to claim 1, It is characterized in that The electrical surface of the semiconductor chip faces and is coupled to the first surface of the base island.

3. The semiconductor package device according to claim 2, It is characterized in that The semiconductor packaging device also includes a conductive connector, one end of which is coupled to the back side of the semiconductor chip and the other end of which extends to connect with the source contact portion of the base island; the source contact portion is arranged on a side of the base island that is not adjacent to any of the base islands.

4. The semiconductor package device according to claim 1, It is characterized in that The adjacent side edges of any two adjacent base islands are parallel straight edges.

5. The semiconductor package device according to claim 1, It is characterized in that Any two adjacent base islands are symmetrically arranged.

6. The semiconductor package device according to claim 3, It is characterized in that A plurality of first trenches, second trenches and gate contact portions are provided on the first surface of the base island; adjacent first trenches are arranged at intervals, and the depths of the first trenches and the second trenches are both less than the thickness of the base island; The second trench is arranged around the gate contact portion; a conductive layer is arranged in each of the first trenches, and the semiconductor chip contacts the conductive layer to be coupled to the first surface of the base island.

7. The semiconductor package device according to claim 6, It is characterized in that The electrical conductivity of the conductive layer is greater than the electrical conductivity of the base island.

8. The semiconductor package device according to claim 6, It is characterized in that The conductive layer and the back side of the semiconductor chip are both provided with solder paste, the electrical surface of the semiconductor chip is in contact with the conductive layer through the solder paste, and the conductive connector is coupled to the back side of the semiconductor chip through the solder paste.

9. The semiconductor package device according to claim 6, It is characterized in that The base island is a copper plate, and the conductive layer is a silver layer.

10. An electronic device, It is characterized in that The invention comprises a circuit board and the semiconductor package device according to any one of claims 1 to 9, wherein the pins are connected to the circuit board.

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