Asymmetric SiC voltage-resistant MOSFET device

Abstract

The utility model discloses an asymmetric SiC voltage-withstanding MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device, which comprises an epitaxial layer, an integrated region, a first conductive type active region and two grooves, wherein the two grooves are spaced by a certain distance. Wherein the body region is located above the epitaxial layer, the active region is located above the body region, the bottoms of the grooves are located in the epitaxial layer, the grooves extend upwards to penetrate through the body region into the first conduction type active region, and a second conduction type active region is arranged on the outer side of one corner of the two grooves. The doped regions between the adjacent grooves are asymmetric, so that when an ion channel is formed, no large electric field intensity is formed at the corners of the grooves, and the grooves cannot be broken down.

Description

Technical Field

[0001] The utility model belongs to the technical field of semiconductors, and in particular relates to an asymmetric SiC withstand voltage MOSFET device. Background Art

[0002] SiC (silicon carbide) MOSFET device is a new type of semiconductor device. Silicon carbide (SiC) has high thermal conductivity, high critical breakdown electric field and large saturated electron drift velocity, which is very suitable for making high-temperature and high-power devices. However, when the field strength carried by the gate oxide of SiC MOSFET device is higher than 4MV / cm, it is easy to break down, resulting in failure of expensive SiC MOSFET device.

[0003] Chinese patent CN217881521U discloses a pressure-resistant silicon carbide MOS device, in which a strip P+ resistor region is arranged in the P-type base region and below the source region, and the width of this strip P+ resistor region is greater than the width of the P+ source region; the upper surface of the N-drift layer is covered with a first metal layer, and this first metal layer is electrically connected to the first polysilicon N-type block region, and a polysilicon P-type block region is electrically connected to the polysilicon gate layer; the N-drift layer is located in the area between adjacent device cells and has a P+ protective column, and the upper end of this P+ protective column extends to the upper surface of the N-drift layer. Although this pressure-resistant silicon carbide MOS device can theoretically increase the pressure resistance of the device, it is still difficult to realize this function with the current production process, and it is still difficult to solve this layout. Therefore, it is necessary to make changes. Utility Model Content

[0004] Aiming at the technical problem that the gate oxide in the existing SiC MOSFET device is prone to breakdown when the electric field strength is higher than 4MV / cm, resulting in product failure, the utility model aims to provide an asymmetric SiC withstand voltage MOSFET device.

[0005] The asymmetric SiC withstand voltage MOSFET device of the utility model comprises:

[0006] an epitaxial layer;

[0007] a body region, the body region being located above the epitaxial layer;

[0008] an active region of a first conductivity type, the active region being located above the body region;

[0009] Two trenches are spaced a certain distance apart, the bottom of the trench is located in the epitaxial layer, the trench extends upward through the body region to the first conductive type active region, and a second conductive type active region is disposed outside a corner of the two trenches.

[0010] Preferably, the second conductive type active region is wrapped around the outside of a corner of the bottom of the trench, that is, arranged on the outside of a side wall and the outside of the bottom of the trench.

[0011] Preferably, the thickness of the second conductivity type active region outside the trench sidewall is greater than the thickness of the second conductivity type active region outside the trench bottom.

[0012] Preferably, the groove sidewall is inclined outwardly at an angle of 0° to 6° relative to the longitudinal direction, preferably 4°.

[0013] Preferably, the trench extends upward through the body region until approaching the top of the first conductivity type active region.

[0014] Preferably, the groove further comprises:

[0015] Gate polysilicon, the gate polysilicon is located in the trench;

[0016] A gate oxide dielectric layer is located on the inner wall of the trench and between the inner wall of the trench and the gate polysilicon.

[0017] Preferably, the gate oxide dielectric layer is also located above the gate polysilicon to wrap the gate polysilicon.

[0018] Preferably, the device further comprises a dielectric isolation layer, wherein the dielectric isolation layer is located above the gate polysilicon, and the gate oxide dielectric layer separates the dielectric isolation layer from the gate polysilicon.

[0019] Preferably, it also includes:

[0020] A hard mask layer is located above the first conductive type active region, and the dielectric isolation layer passes through the hard mask layer.

[0021] Preferably, it also includes:

[0022] A source metal layer is located above the hard mask layer and covers the dielectric isolation layer.

[0023] Preferably, the top of the dielectric isolation layer extends into the source metal layer.

[0024] Preferably, the body region is a second conductivity type body region.

[0025] Preferably, the first conductivity type is N type, and the second conductivity type is P type;

[0026] Alternatively, the first conductivity type is P type, and the second conductivity type is N type.

[0027] Preferably, it also includes:

[0028] A substrate layer is located below the epitaxial layer.

[0029] The positive and progressive effects of the utility model are:

[0030] 1) The asymmetric SiC voltage-resistant MOSFET device of the utility model forms a second conductive type active area outside a corner of two trenches, and is an asymmetric structure. In the process of forming an ion channel, a strong electric field cannot be formed at the corner on the other side of the trench, thereby avoiding excessive electric field strength at the corner on the other side of the trench and thus being broken down.

[0031] 2) The angle of the groove sidewall inclination relative to the longitudinal direction of the asymmetric SiC withstand voltage MOSFET device of the utility model is 0° to 6°, preferably 4°. When the groove sidewall is 4°, the optimal electron mobility and threshold voltage can be achieved, thereby achieving the optimal ion channel mobility. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The disclosure of the present invention will become more apparent with reference to the accompanying drawings. It should be understood that these drawings are only for illustrative purposes and are not intended to limit the scope of protection of the present invention. In the drawings:

[0033] Figure 1 A cross-sectional schematic diagram of the utility model;

[0034] Figure 2 The utility model is a process flow chart. DETAILED DESCRIPTION

[0035] The following is an explanation of the implementation of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0036] It should be noted that the following embodiments and features therein may be combined with each other if there is no conflict.

[0037] In the description of the present invention, it should be noted that directional words such as the terms "outside", "above", "up", "inside", "outside", etc., which indicate directions and positional relationships, are based on the directions or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and cannot be understood as limiting the specific protection scope of the present invention.

[0038] Reference Figure 1 The utility model provides an asymmetric SiC withstand voltage MOSFET device, comprising:

[0039] Epitaxial layer (Epi) 101;

[0040] A body region 102, such as a P-body, is located on the epitaxial layer 101;

[0041] A first conductive type active region 103, for example, an N+ active region, and the first conductive type active region 103 is located above the body region 102;

[0042] The trenches 104 are spaced apart by a certain distance, the bottom of the trenches 104 is located in the epitaxial layer 101, and the trenches 104 extend upward through the body region 102 to the first conductive type active region 103. For example, the trenches 104 extend upward through the body region 102 to near the top of the first conductive type active region 103.

[0043] In some embodiments, reference Figure 1 , there is a second conductive type active region 105 outside a corner of the two trenches 104, for example, a P+ active region.

[0044] The second conductive type active region 105 is wrapped around the outside of a corner of the bottom of the trench 104 , that is, the second conductive type active region 105 is located outside of a side wall and outside of the bottom of the trench 104 .

[0045] The thickness of the second conductivity type active region 105 outside the sidewall of the trench 104 is greater than the thickness of the second conductivity type active region 105 outside the bottom of the trench 104 .

[0046] The utility model provides a second conductive type active area 105 outside the right corner of the groove 104, and the doping areas between adjacent grooves 104 are asymmetric, so that when an ion channel is formed, a large electric field strength will not be formed at the left corner of the groove 104, and the gate oxide dielectric layer on the inner wall of the groove 104 will not be broken down.

[0047] At the same time, this asymmetric design minimizes the impedance value of the body region 102 connected to the second conductive type active region 105. And there is a continuous supply of the second conductive type active region 105 to supplement, so that the body diode of the device becomes a fast recovery diode. Further, the gate oxide dielectric layer at the corner of the trench 104 can be protected from the influence of the excessive electric field caused by the drain bias.

[0048] In some embodiments, reference Figure 1 The side walls of the two grooves 104 are inclined outwardly at an angle of 0° to 6° relative to the longitudinal direction, preferably 4°.

[0049] The asymmetric SiC withstand voltage MOSFET device of the present invention selects the most favorable orientation for the sidewall direction of the groove 104, that is, an angle of 4° outward from the longitudinal direction. When the sidewall of the groove 104 is inclined outward at an angle of 4°, it has the best electron mobility and threshold voltage, and can achieve the best channel mobility of ions.

[0050] In some embodiments, reference Figure 1 , there is also a gate polysilicon (Gate Poly) 106 inside the trench 104.

[0051] A gate oxide dielectric layer 107 is also provided on the inner wall of the trench 104 , that is, the gate oxide dielectric layer 107 separates the trench 104 from the gate polysilicon (GOX) 106 .

[0052] In some embodiments, reference Figure 1 , the gate oxide dielectric layer 107 is also located above the gate polysilicon 106 .

[0053] Furthermore, the gate oxide dielectric layer 107 wraps the gate polysilicon 106 in the trench 104 .

[0054] The asymmetric SiC withstand voltage MOSFET device further includes a dielectric isolation layer (ILD) 108 . The dielectric isolation layer 108 is located above the gate polysilicon 106 . The gate oxide dielectric layer 107 separates the dielectric isolation layer 108 from the gate polysilicon 106 .

[0055] The asymmetric SiC withstand voltage MOSFET device further includes a hard mask layer (HM) 109 . The hard mask layer 109 is located above the first conductive type active region 103 , and the dielectric isolation layer 108 passes through the hard mask layer 109 .

[0056] The asymmetric SiC withstand voltage MOSFET device further includes a source metal layer (Source Metal) 110 . The source metal layer 110 is located above the hard mask layer 109 , and the source metal layer 110 covers the dielectric isolation layer 108 .

[0057] Furthermore, the top of the dielectric isolation layer 108 extends into the source metal layer 110 .

[0058] The asymmetric SiC withstand voltage MOSFET device further includes a substrate layer 111 (Sub), and the substrate layer 111 is located below the epitaxial layer 101 .

[0059] In some embodiments, the body region 102 is a second conductivity type body region.

[0060] In some embodiments, the first conductivity type is N-type, the second conductivity type is P-type, and the body region 102 is a P-type doped region (P-body) of a P-type doping type, the first conductivity type active region 103 is an N-type doped region (N+) of a V-type doping type, and the second conductivity type active region is a P-type doped region (P+) of a P-type doping type.

[0061] In some embodiments, the first conductivity type may be P type, and the second conductivity type may be N type.

[0062] In some embodiments, reference Figure 2 The following steps can be used to manufacture the asymmetric SiC withstand voltage MOSFET device of the utility model:

[0063] Step ①, the N-type silicon carbide layer and the first conductive type active region 103 are implanted and diffused by IMP implantation, and the body region 102 is implanted and diffused;

[0064] Step ②, growing the hard mask layer 109, and etching the N-type silicon carbide layer using an anisotropic etching method at the top opening of the trench 104, forming a shallow trench 104 in the N-type silicon carbide layer, and the etching angle is 4°;

[0065] Step ③, the trench 104 is further etched using an isotropic etching method to increase the width and depth of the trench 104. It should be noted that the depth of the trench 104 exceeds the depth of the body region 102, and the width of the trench 104 is wider than the contact portion of the hard mask layer 109;

[0066] Step ④, using IMP implantation to implant the second conductive type active area 105 obliquely and vertically and diffuse. It should be noted that the order of vertical and oblique implantation is not fixed. The vertical p-type ion implantation is used to form the second conductive type active area 105 outside the bottom of the trench 104, and the oblique p-type ion implantation is used to form the second conductive type active area 105 outside the sidewall of the gate trench;

[0067] Step ⑤, growing a gate oxide dielectric layer 107 in the trench 104;

[0068] Step ⑥, growing gate polysilicon 106 in the gate oxide dielectric layer 107;

[0069] Step 7, etching the hard mask layer 109 to form an isolation layer;

[0070] Step ⑧, growing a dielectric isolation layer 108 on the gate oxide dielectric layer 107 , and growing a source metal layer 110 on the dielectric isolation layer 108 and the hard mask layer 109 . Specific embodiment:

[0072] Taking a 1200V SiCMOSFET device as an example, the epitaxial layer doping concentration is 8.0E+15, the P-Body AL injection concentration is 3E+13, the critical maximum opening width of the gate trench is 1.0um, the depth of the gate trench is 2.0um, and the thickness of the gate oxide dielectric layer is The N implant concentration of the N+ region (ie, the first conductivity type active region 103 ) is 3E+15, and the AL implant concentration of the P+ active region (ie, the second conductivity type active region 105 ) is 8E+14.

[0073] The utility model is described in detail above in conjunction with the embodiments of the drawings. A person skilled in the art can make various variations of the utility model according to the above description. Therefore, some details in the embodiments should not constitute a limitation of the utility model, and the utility model shall be protected within the scope defined by the attached claims.

Claims

1. An asymmetric SiC withstand voltage MOSFET device, characterized in that: The asymmetric SiC withstand voltage MOSFET device comprises: an epitaxial layer; a body region, the body region being located above the epitaxial layer; an active region of a first conductivity type, the active region being located above the body region; Two trenches are spaced a certain distance apart, the bottom of the trench is located in the epitaxial layer, the trench extends upward through the body region to the first conductive type active region, and a second conductive type active region is disposed outside a corner of the two trenches.

2. The asymmetric SiC withstand voltage MOSFET device according to claim 1, characterized in that: The second conductive type active region is wrapped around the outside of a corner of the bottom of the trench, that is, is arranged outside a side wall and outside the bottom of the trench.

3. The asymmetric SiC withstand voltage MOSFET device according to claim 2, characterized in that: The thickness of the second conductivity type active region outside the trench sidewall is greater than the thickness of the second conductivity type active region outside the trench bottom.

4. The asymmetric SiC withstand voltage MOSFET device according to claim 1, characterized in that: The groove sidewall is inclined outwardly at an angle of 0° to 6° relative to the longitudinal direction.

5. The asymmetric SiC withstand voltage MOSFET device according to claim 1, characterized in that: The groove sidewall is inclined outward at an angle of 4° relative to the longitudinal direction.

6. The asymmetric SiC withstand voltage MOSFET device according to claim 4, characterized in that: The trench extends upward through the body region until near the top of the first conductivity type active region.

7. The asymmetric SiC withstand voltage MOSFET device according to claim 6, characterized in that: The groove also has: Gate polysilicon, the gate polysilicon is located in the trench; A gate oxide dielectric layer is located on the inner wall of the trench and between the inner wall of the trench and the gate polysilicon.

8. The asymmetric SiC withstand voltage MOSFET device according to claim 7, characterized in that: The gate oxide dielectric layer is also located above the gate polysilicon and wraps the gate polysilicon.

9. The asymmetric SiC withstand voltage MOSFET device according to claim 8, characterized in that: The invention also comprises a dielectric isolation layer, wherein the dielectric isolation layer is located above the gate polysilicon, and the gate oxide dielectric layer separates the dielectric isolation layer from the gate polysilicon.

10. The asymmetric SiC withstand voltage MOSFET device according to claim 9, characterized in that: Also includes: A hard mask layer is located above the first conductive type active region, and the dielectric isolation layer passes through the hard mask layer.

11. The asymmetric SiC withstand voltage MOSFET device according to claim 10, characterized in that: Also includes: A source metal layer is located above the hard mask layer and covers the dielectric isolation layer.

12. The asymmetric SiC withstand voltage MOSFET device according to claim 11, characterized in that: The top of the dielectric isolation layer extends into the source metal layer.

13. The asymmetric SiC withstand voltage MOSFET device according to claim 1, characterized in that: The body region is a second conductivity type body region.

14. The asymmetric SiC withstand voltage MOSFET device according to claim 13, characterized in that: The first conductivity type is N type, and the second conductivity type is P type; Alternatively, the first conductivity type is P type, and the second conductivity type is N type.

15. The asymmetric SiC withstand voltage MOSFET device according to claim 1, characterized in that: Also includes: A substrate layer is located below the epitaxial layer.

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