Semiconductor device, electronic apparatus, and vehicle

Abstract

The utility model discloses a semiconductor device, an electronic device and a vehicle, and the semiconductor device comprises an anode metal layer, a P region structure and an I region structure which are arranged along the longitudinal direction of the device. The P region structure comprises a plurality of P-type heavily doped regions, and the plurality of P-type heavily doped regions are arranged at intervals along the transverse direction of the device; an anode N-type region is formed between every two adjacent P-type heavily doped regions; and the anode N-type region is in contact with the anode metal layer so as to compound or extract a hole of the I-region structure when the device is turned off. The semiconductor device provided by the utility model can accelerate elimination of holes generated by the I-region structure during turn-off, thereby shortening the reverse recovery time of the device and reducing the turn-off loss of the device.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a semiconductor device, an electronic device and a vehicle. Background Art

[0002] In the related art, a fast recovery diode (FRD) is a semiconductor diode with good switching characteristics and short reverse recovery time. FRD is also called a freewheeling diode and is anti-parallel connected with an insulated gate bipolar transistor (IGBT) in electronic circuits such as switching power supplies, PWM pulse width modulators, and inverters.

[0003] For a fast recovery diode with a PIN structure, holes are generated in the I region during the device shutdown process, that is, when the FRD switches from the on state to the off state. In order to maintain charge neutrality, these holes need to be discharged through the anode and flow to the external circuit. The process of hole discharge in the I region increases the reverse recovery time of the device, thereby increasing the overall turn-off loss of the device. Utility Model Content

[0004] The utility model aims to solve at least one of the technical problems existing in the prior art. To this end, one purpose of the utility model is to provide a semiconductor device that can accelerate the elimination of holes generated by the I region structure when the device is turned off, thereby shortening the reverse recovery time of the device and reducing the turn-off loss of the device.

[0005] The second objective of the present invention is to provide an electronic device.

[0006] The third objective of the present invention is to provide a vehicle.

[0007] In order to achieve the above-mentioned objectives, the semiconductor device of the first aspect of the utility model embodiment includes: an anode metal layer, a P region structure and an I region structure arranged along the longitudinal direction of the device; the P region structure includes a plurality of P-type heavily doped regions, and the plurality of P-type heavily doped regions are arranged at intervals along the lateral direction of the device; an anode N-type region is formed between two adjacent P-type heavily doped regions; the anode N-type region contacts the anode metal layer to recombine or extract holes in the I region structure when the device is turned off.

[0008] According to the semiconductor device of the embodiment of the utility model, an anode N-type region is formed between two adjacent P-type heavily doped regions. When the device is turned off, the holes generated in the I region move toward the anode, and the electrons in the anode N-type region can recombine with the holes generated in the I region structure, thereby quickly reducing the holes in the I region structure. At the same time, the holes that reach the anode N-type region but do not have time to recombine can also be discharged from the anode metal layer, which helps to assist the anode in extracting holes from the I region structure, thereby shortening the reverse recovery time of the device and reducing the turn-off loss.

[0009] In some embodiments, a P-type lightly doped region is also formed between two adjacent P-type heavily doped regions; along the longitudinal direction of the device, the P-type lightly doped region is located below the anode N-type region, and the P-type lightly doped region is in contact with the anode N-type region and the I region structure respectively.

[0010] In some embodiments, the P-type lightly doped region surrounds the bottom and side surfaces of the anode N-type region; the upper surface of the anode N-type region contacts the anode metal layer; the side surfaces of the P-type lightly doped region contact the P-type heavily doped region, and the lower surface of the P-type lightly doped region contacts the I-region structure.

[0011] In some embodiments, the anode metal layer also covers a portion of the P-type lightly doped region located on a side of the anode N-type region and the P-type heavily doped region.

[0012] In some embodiments, an upper surface of the anode N-type region, an upper surface of a portion of the P-type lightly doped region located on a side of the anode N-type region, and an upper surface of the P-type heavily doped region are all flush.

[0013] In some embodiments, along the longitudinal direction of the device, the upper surface of the anode N-type region contacts the anode metal layer, the lower surface of the anode N-type region contacts the upper surface of the P-type lightly doped region, the lower surface of the P-type lightly doped region contacts the I-region structure, and the side surfaces of the anode N-type region and the side surfaces of the P-type lightly doped region are both in contact with the P-type heavily doped region.

[0014] In some embodiments, the P-type lightly doped regions grow at both ends of the anode N-type region extending laterally along the device.

[0015] In some embodiments, the anode metal layer also covers the P-type heavily doped region, and the upper surface of the anode N-type region is flush with the upper surface of the P-type heavily doped region.

[0016] In some embodiments, a depth of the P-type heavily doped region along a longitudinal direction of the device is greater than a total depth of the anode N-type region and the P-type lightly doped region along the longitudinal direction of the device.

[0017] In some embodiments, the upper surface of the anode N-type region is flush with the upper surface of a portion of the P-type lightly doped region located on the side of the anode N-type region; the upper surface of the anode N-type region and the upper surface of a portion of the P-type lightly doped region located on the side of the anode N-type region both protrude from the upper surface of the P-type heavily doped region toward the anode metal layer, and a portion of the side of the P-type lightly doped region is in contact with the anode metal layer.

[0018] In some embodiments, a groove is formed on the anode metal layer at a position corresponding to the P-type heavily doped region.

[0019] In some embodiments, the I-region structure includes an N-type lightly doped layer, and an upper surface of the N-type lightly doped layer is in contact with both a lower surface of the P-type heavily doped region and a lower surface of the P-type lightly doped region.

[0020] In some embodiments, the semiconductor device further includes: an N-type heavily doped layer, wherein the N-type heavily doped layer is located below the N-type lightly doped layer along the longitudinal direction of the device.

[0021] In some embodiments, the semiconductor device further includes: an N-type buffer layer, wherein the N-type buffer layer is located between the N-type heavily doped layer and the N-type lightly doped layer.

[0022] In some embodiments, the semiconductor device further includes: a cathode metal layer, wherein the cathode metal layer covers the N-type heavily doped layer along a longitudinal direction of the device.

[0023] In order to achieve the above object, an electronic device according to an embodiment of the second aspect of the utility model includes the semiconductor device described in the above embodiment.

[0024] The electronic device according to the embodiment of the utility model can accelerate the elimination of holes generated by the I region structure when turned off by using the semiconductor device described in the above embodiment, thereby shortening the reverse recovery time of the device and reducing the turn-off loss of the device.

[0025] In some embodiments, the electronic device further comprises an insulated gate bipolar transistor connected in reverse parallel to the semiconductor device.

[0026] In order to achieve the above-mentioned object, a vehicle according to a third aspect of an embodiment of the utility model includes the electronic device described in the above embodiment.

[0027] According to the vehicle of the embodiment of the utility model, the holes generated by the I-zone structure can be eliminated faster when the device is turned off, thereby shortening the reverse recovery time of the device, reducing the device turn-off loss, and improving the overall performance of the vehicle.

[0028] Additional aspects and advantages of the present invention will be given in part in the following description, and in part will become apparent from the following description, or will be learned through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0030] Figure 1 is a schematic diagram of a semiconductor device according to an embodiment of the utility model;

[0031] Figure 2 is a schematic diagram of a semiconductor device according to another embodiment of the utility model;

[0032] Figure 3 is a schematic diagram of a semiconductor device according to yet another embodiment of the utility model;

[0033] Figure 4 is a schematic diagram of an N-type heavily doped substrate layer according to an embodiment of the utility model;

[0034] Figure 5 is a schematic diagram of an N-type buffer layer according to an embodiment of the utility model;

[0035] Figure 6 is a schematic diagram of an N-type lightly doped layer according to an embodiment of the utility model;

[0036] Figure 7 is a schematic diagram of a P-type lightly doped region according to an embodiment of the utility model;

[0037] Figure 8 is a schematic diagram of an anode N-type region according to an embodiment of the utility model;

[0038] Fig. 9 is a schematic diagram of a P-type heavily doped region according to an embodiment of the utility model;

[0039] Fig.10 It is a schematic diagram of a well-pushing process for a semiconductor device according to an embodiment of the utility model;

[0040] Fig.11 is a schematic diagram of an anode metal layer according to an embodiment of the utility model;

[0041] Fig.12 is a block diagram of an electronic device according to an embodiment of the utility model;

[0042] Fig.13 is a block diagram of a vehicle according to an embodiment of the present utility model.

[0043] Reference numerals:

[0044] Vehicle 100;

[0045] Electronics 101;

[0046] Semiconductor device 1; Insulated gate bipolar transistor 2;

[0047] Anode metal layer 10; P region structure 20; I region structure 30; N-type heavily doped layer 40; cathode metal layer 50; groove 60;

[0048] P-type heavily doped region 21 ; anode N-type region 22 ; P-type lightly doped region 23 ; N-type lightly doped layer 31 ; N-type buffer layer 32 . DETAILED DESCRIPTION

[0049] The embodiments of the present utility model are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. The embodiments of the present utility model are described in detail below.

[0050] Reference below Figure 1-Figure 11 A semiconductor device according to an embodiment of the present invention is described.

[0051] Figure 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present utility model, such as Figure 1 As shown, the semiconductor device 1 includes: an anode metal layer 10, a P region structure 20 and an I region structure 30 arranged along the longitudinal direction of the device.

[0052] In some embodiments, the P-region structure 20 includes a plurality of P-type heavily doped regions 21, and the doping concentration of the P-type heavily doped regions 21 can be adjusted. The P-type impurity ions of the P-type heavily doped regions 21 can preferably be boron ions, and the doping concentration of the P-type heavily doped regions 21 can be between 1×10 16 cm -3 -1×10 18 cm -3 A plurality of P-type heavily doped regions 21 are arranged at intervals along the lateral direction of the device.

[0053] In the embodiment, for a fast recovery diode device with a PIN structure, the P-type heavily doped region 21 belongs to a P region in the PIN of the device.

[0054] In some embodiments, the anode N-type region 22 may be an N-type semiconductor region formed between two adjacent P-type heavily doped regions 21, which means that the layout of the anode N-type region 22 and the P-type heavily doped region 21 in the semiconductor device 1 may be interlaced, and its doping concentration is lower than that of the P-type heavily doped region 21. The anode N-type region 22 may be implemented by an N-type doping method to ensure that it has good conductivity. For example, the N-type impurity ions of the anode N-type region 22 may preferably be phosphorus ions, and the doping concentration of the anode N-type region 22 may be 1×1016 cm -3 -1×10 19 cm -3 between.

[0055] In some embodiments, the doping sequence of the anode N-type region 22 and the P-type heavily doped region 21 can be flexibly adjusted and changed. This means that it can be decided whether to dope the anode N-type region 22 first and then dope the P-type heavily doped region 21, or vice versa, according to specific design requirements and process requirements. Therefore, this flexibility allows different doping sequences to be selected according to specific preparation processes and performance requirements to optimize device performance.

[0056] In some embodiments, specific parameters such as the injection window size and shape of the anode N-type region 22 and the P-type heavily doped region 21 are not limited, and the selection of these parameters can be adjusted and optimized according to specific design requirements, performance requirements and feasibility of the manufacturing process.

[0057] In some embodiments, all implantation energies are not limited and can be adjusted according to actual needs.

[0058] In some embodiments, the anode metal layer 10 may be a thin film made of a conductive metal material such as copper or aluminum. The thickness of the anode metal layer 10 may be between 2 μm and 6 μm. The anode metal layer 10 may play a role in conducting electricity and heat in the device and is the main conduction channel for current.

[0059] In some embodiments, an anode N-type region 22 is introduced between two adjacent P-type heavily doped regions 21 , and the anode N-type region 22 contacts the anode metal layer 10 to recombine or extract holes in the I-region structure 30 when the device is turned off.

[0060] Specifically, when the device is turned off, the holes in the I-region structure 30 move toward the anode, and the electrons in the anode N-type region 22 recombine with the holes in the I-region structure 30, thereby accelerating the speed of eliminating holes in the I-region structure 30. At the same time, the anode N-type region 22 is in contact with the anode metal layer 10, and the unrecombined holes that reach the anode N-type region 22 can flow to the anode metal layer 10 to assist the anode in extracting the holes in the I-region structure 30, thereby accelerating the discharge of holes in the I-region structure 30. Therefore, by providing the anode N-type region 22 on the anode side, the elimination time of the holes in the I-region when the device is turned off is accelerated, the reverse recovery time of the device is shortened, and the turn-off loss is reduced.

[0061] Furthermore, if Figure 1As shown, a P-type lightly doped region 23 is formed between two adjacent P-type heavily doped regions 21. The P-type impurity ions in the P-type lightly doped region 23 may preferably be boron ions. The doping concentration of the P-type lightly doped region 23 is lower than that of the P-type heavily doped region 21. For example, the doping concentration of the P-type lightly doped region 23 may be between 1×10 15 cm -3 -1×10 17 cm -3 between.

[0062] In some embodiments, Figure 1 As shown, along the longitudinal direction of the device, the P-type lightly doped region 23 is located below the anode N-type region 22, and the P-type lightly doped region 23 is in contact with the anode N-type region 22 and the I region structure 30. The introduction of the P-type lightly doped region 23 can reduce the reverse leakage current during reverse shutdown.

[0063] Specifically, if only the anode N-type region 22 is provided, a large number of holes generated by the I-region structure 30 will move toward the anode during reverse shutdown, which may result in a large leakage current. By adding a P-type lightly doped region 23 between the anode N-type region 22 and the I-region structure 30, the P-type lightly doped region 23 and the I-region structure 30 can form a potential barrier, which has a certain blocking effect on the leakage current during reverse shutdown, thereby effectively reducing the leakage current, helping to improve the reverse static characteristics of the device, and thus improving the performance of the device in the off state.

[0064] In the embodiment of the present utility model, the specific configuration structure of the P-type lightly doped region 23 and the anode N-type region 22 can be adaptively adjusted and laid out according to the specific structure of the device, as illustrated below by way of example.

[0065] In some embodiments, Figure 1 As shown, the P-type lightly doped region 23 surrounds the bottom and side surfaces of the anode N-type region 22, that is, the junction depth of the P-type lightly doped region 23 is deeper than that of the anode N-type region 22. The junction depth here refers to the depth from the anode metal layer 10 to the lower surface of the structure, which can be understood as the diffusion depth. The side surfaces of the P-type lightly doped region 23 are in contact with the P-type heavily doped region 21, and the lower surface of the P-type lightly doped region 23 is in contact with the I-region structure 30.

[0066] The upper surface of the anode N-type region 22 contacts the anode metal layer 10 . This layout design helps to ensure good electrical contact between the anode N-type region 22 and the anode metal layer 10 , thereby forming a channel for electron injection and promoting the flow of electrons.

[0067] Furthermore, in some embodiments, Figure 1 As shown, the anode metal layer 10 also covers the portion of the P-type lightly doped region 23 located on the side of the anode N-type region 22 and the P-type heavily doped region 21 .

[0068] As described above, by adding the P-type lightly doped region 23, the leakage current during reverse shutdown can be reduced and the reverse static characteristics of the device can be improved. In addition, by setting the P-type lightly doped region 23 to surround the anode N-type region 22 and part of the P-type lightly doped region 23 is in contact with the anode metal layer 10, the forward turn-on speed can also be taken into account.

[0069] Specifically, the P-type heavily doped region 21 is in ohmic contact with the anode metal layer 10, while the P-type lightly doped region 23 is in Schottky contact with the anode metal layer 10. When a small current is injected, the voltage drop (Vf value) of the P-type lightly doped region 23 in Schottky contact is relatively small, and the voltage drop of the P-type heavily doped region 21 in ohmic contact is relatively large. Since the weight of the P-type lightly doped region 23 is greater, the forward turn-on process of the device can be accelerated, thereby improving the efficiency of the forward turn-on. When a large current is injected, as the current increases, the weight of the P-type heavily doped region 21 is relatively large, which can provide current, ensure the normal operation of the device, and maintain a stable forward conduction state when a large current is injected.

[0070] Therefore, by adding a P-type lightly doped region 23, and the P-type lightly doped region 23 surrounds the anode N-type region 22 and part of the P-type lightly doped region 23 is in contact with the anode metal layer 10, it is possible to maintain a small reverse leakage current while allowing the device to be turned on faster when a small current is injected during forward turn-on, while maintaining stable current transmission during large current injection, thereby taking into account both reverse static characteristics and forward turn-on characteristics.

[0071] In the embodiment, the upper surface of the anode N-type region 22, the upper surface of the portion of the P-type lightly doped region 23 located on the side of the anode N-type region 22, and the upper surface of the P-type heavily doped region 21 are all flush, ensuring that a flat surface is formed between the regions, providing a more uniform structure. During the manufacturing process, ensuring that the upper surfaces of the regions are flush can simplify process control, reduce complexity in manufacturing, and improve manufacturing consistency.

[0072] In other embodiments, Figure 2 As shown, Figure 2 It is a cross-sectional view of a semiconductor device according to another embodiment of the present invention. Along the longitudinal direction of the device, the upper surface of the anode N-type region 22 contacts the anode metal layer 10, the lower surface of the anode N-type region 22 contacts the upper surface of the P-type lightly doped region 23, the lower surface of the P-type lightly doped region 23 contacts the I-region structure 30, and the side surfaces of the anode N-type region 22 and the P-type lightly doped region 23 are both in contact with the P-type heavily doped region 21. Through the arrangement of these structures and the reasonable design of the contact mode, the reverse leakage current can be reduced and the reverse static characteristics of the device can be improved.

[0073] like Figure 2As shown, both ends of the anode N-type region 22 extending laterally along the device grow P-type lightly doped regions 23. That is, increasing the window of the anode N-type region 22 can increase the contact area between the anode N-type region 22 and the anode metal layer 10, so that when the reverse is turned off, the holes generated by the I-region structure 30 can be made faster, reducing the turn-off loss.

[0074] In the embodiment, the anode metal layer 10 not only covers the anode N-type region 22 , but also covers the P-type heavily doped region 21 , so as to ensure current transmission during forward conduction and achieve normal conduction of the device.

[0075] like Figure 1 and Figure 2 As shown, the depth of the P-type heavily doped region 21 along the longitudinal direction of the device is greater than the total depth of the anode N-type region 22 and the P-type lightly doped region 23 along the longitudinal direction of the device. This can make the process simpler while ensuring the normal performance of the device.

[0076] Figure 3 is a cross-sectional view of a semiconductor device according to another embodiment of the present utility model, such as Figure 3 As shown, the upper surface of the anode N-type region 22 is flush with the upper surface of the portion of the P-type lightly doped region 23 located on the side of the anode N-type region 22. The upper surface of the anode N-type region 22 and the upper surface of the portion of the P-type lightly doped region 23 located on the side of the anode N-type region 22 both protrude from the upper surface of the P-type heavily doped region 21 toward the anode metal layer 10, and a portion of the side of the P-type lightly doped region 23 is in contact with the anode metal layer 10.

[0077] The above-mentioned design structure can be realized through appropriate process steps and manufacturing parameters, for example, by controlling the shape and size of the anode N-type region 22 and the P-type lightly doped region 23, and the deposition method of the anode metal layer 10. These design features jointly affect the electrical characteristics of the device and improve the overall performance of the device.

[0078] Similarly, the above Figure 3 In the structural design shown, the P-type lightly doped region 23 surrounds the side and bottom of the anode N-type region 22, and part of the P-type lightly doped region 23 is in contact with the anode metal layer 10, which can ensure the forward turn-on speed while reducing the reverse leakage current, taking into account the forward conduction characteristics and reverse static characteristics of the device.

[0079] Furthermore, in some embodiments, Figure 3 As shown, a groove 60 is formed on the anode metal layer 10 at a position corresponding to the P-type heavily doped region 21. The presence of the groove 60 helps to increase the area of ​​the anode metal layer 10, thereby increasing the front anode current density.

[0080] In some embodiments, the shape of the groove 60 can be rectangular, trapezoidal, conical or special-shaped. Figure 3The groove 60 shown is a rectangular groove having five inner walls except the opening (since it is a cross-sectional view, the front and rear surfaces of the groove 60 are not shown), and the anode metal layer 10 is adapted to the shape of the groove 60 .

[0081] In some embodiments, the opening width and opening depth of the groove 60 are not required, and it is preferred that the groove 60 does not contact the anode N-type region 22 and is not deeper than the anode N-type region 22 .

[0082] In some embodiments, the formation of the groove 60 can be achieved through appropriate process steps and manufacturing parameters. For example, the formation of the groove 60 can be achieved through process steps such as light shielding mask, photolithography and etching. Specifically, in order to form the groove 60, a photolithography process can be used. First, a layer of photoresist is coated on the anode metal layer 10, and the photoresist is formed into a certain pattern through the steps of exposure and development. Then, part of the material of the anode metal layer 10 is removed through the etching process to form the structure of the groove 60. The design of this step requires precise process control to ensure that the formation position and size of the groove 60 meet the design requirements.

[0083] like Figure 1-Figure 3 As shown, the I region structure 30 includes an N-type lightly doped layer 31. The N-type lightly doped layer 31 can be formed by injecting N-type impurity ions and diffusing. The doping concentration of the N-type lightly doped layer 31 can be between 1×10 13 cm -3 -1×10 17 cm -3 The doping concentration and thickness of the N-type lightly doped layer 31 may be determined by the withstand voltage level, and the thickness may be between 30 μm and 200 μm. For a fast recovery diode of a PIN structure, an N-type lightly doped region may be used as the I region in the PIN.

[0084] In some embodiments, the upper surface of the N-type lightly doped layer 31 is in contact with the lower surface of the P-type heavily doped region 21 and the lower surface of the P-type lightly doped region 23. When forward conduction occurs, the P-type heavily doped region 21 can provide current. When reverse shutdown occurs, the P-type lightly doped region 23 and the anode N-type region 22 can be used to quickly accelerate the discharge of holes in the I region and ensure a small reverse leakage current, thereby improving the reverse static characteristics.

[0085] like Figure 1-Figure 3As shown, the semiconductor device 1 also includes an N-type heavily doped layer 40, which can act as a substrate in the semiconductor device 1, providing a structural basis for the entire semiconductor device 1, and has an N-type conductive property. Moreover, the N-type heavily doped layer 40, as an N-type substrate, plays a fundamental role in the electrical performance of the entire device. In the semiconductor device 1, the N-type substrate can be used to provide a conductive channel for electrons. Moreover, for a fast recovery diode of a PIN structure, the N-type heavily doped layer 40, i.e., the substrate layer, can be used as an N region in the PIN.

[0086] In some embodiments, the N-type heavily doped layer 40 may be formed by doping N-type impurities (e.g., phosphorus ions), and its conductive properties enable the device to transmit current under normal working conditions. The N-type heavily doped layer 40 may be made of silicon (Si), silicon carbide (SiC), gallium nitride (GaN), or other composite materials as semiconductor materials. Taking the semiconductor device 1 in which the N-type heavily doped layer 40 is made of silicon (Si) as an example, the doping concentration of the N-type heavily doped layer 40 may be 1×10 19 cm -3 -1×10 21 cm -3 In the meantime, the thickness and doping concentration of the N-type heavily doped layer 40 can be adjusted through appropriate process steps and parameters.

[0087] In some embodiments, the N-type heavily doped layer 40 is located below the N-type lightly doped layer 31 along the longitudinal direction of the device, so that the P-type heavily doped region 21, the N-type lightly doped layer 31 and the N-type heavily doped region 40 constitute the basic structure of a fast recovery diode of a PIN structure. In addition, in the present application, an anode N-type region and a P-type lightly doped region are added to reduce the turn-off loss and reduce the reverse leakage current.

[0088] like Figure 1-Figure 3 As shown, the semiconductor device 1 further includes an N-type buffer layer 32. The N-type buffer layer 32 is a lightly doped region. The N-type buffer layer 32 can be formed by injecting N-type impurity ions (such as phosphorus ions) and diffusing. The doping concentration of the N-type buffer layer 32 can be between 1×10 15 cm -3 -1×10 18 cm -3 Therefore, the introduction of the N-type buffer layer 32 can be achieved by appropriately adjusting the doping concentration and material properties.

[0089] In some embodiments, the N-type buffer layer 32 is located between the N-type heavily doped layer 40 and the N-type lightly doped layer 31. From a process point of view, the mechanical stress between the two layers can be reduced to avoid defects. From a device perspective, the N-type buffer layer can reduce the device thickness and make the FRD reverse recovery softer.

[0090] In some embodiments, the N-type buffer layer 32 can be formed by appropriate process steps and parameters during the preparation process. The adjustment of parameters such as doping concentration, thickness and shape can be optimized according to design requirements. This helps to ensure that the N-type buffer layer 32 plays its buffering role and smoothes the transition between the N-type heavily doped layer 40 and the N-type lightly doped layer 31.

[0091] like Figure 1-3 As shown, the semiconductor device 1 also includes a cathode metal layer 50. The cathode metal layer 50 can be made of materials such as titanium, nickel, or silver alloy, or any desired metal or metal alloy that can form an ohmic contact with the N-type heavily doped layer 40 according to actual needs, and then alloyed. The thickness of the cathode metal layer 50 can be between 1μm and 4μm. Similarly, the anode metal layer 10 can be any desired metal or metal alloy that can form a Schottky contact with the N-type lightly doped layer 31 according to actual needs, and then alloyed. The thickness of the anode metal layer 10 can be between 2μm and 6μm;

[0092] In some embodiments, the cathode metal layer 50 covers the N-type heavily doped layer 40 along the longitudinal direction of the device, providing a key electrode structure for the semiconductor device 1 .

[0093] Below, as Figure 1 As an example, refer to the semiconductor device structure shown in Figure 4-Figure 11 The process flow of the semiconductor device of the embodiment of the utility model is described. The process flow of the semiconductor device 1 may include the following steps:

[0094] First, provide a doping concentration of 1×10 20 cm -3 The N-type heavily doped layer 40, the resulting structure is as follows Figure 4 shown.

[0095] Second, an N-type buffer layer 32 is epitaxially grown on the upper surface of the N-type heavily doped layer 40. The doping concentration of the N-type buffer layer 32 may be 1×10 17 cm -3 , with a thickness of 10 μm, the resulting structure is as follows Figure 5 shown.

[0096] Third, an N-type lightly doped layer 31 is epitaxially grown on the upper surface of the N-type buffer layer 32. The doping concentration of the N-type lightly doped layer 31 may be 1×10 15 cm -3 , with a thickness of 80 μm, the resulting structure is as follows Figure 6 shown.

[0097] Fourth, boron ions are implanted on the upper surface of the N-type lightly doped layer 31 using an implantation energy of 80 eKV to form a P-type lightly doped region 23. The resulting structure is as follows: Figure 7 shown.

[0098] Fifth, by photolithography, an anode N-type region 22 injection window is formed on the upper surface of the N-type lightly doped layer 31, and phosphorus ions are injected at the injection window with an injection energy of 80eKV to form the anode N-type region 22, and then the resist is removed. The resulting structure is as shown in FIG. Figure 8 shown.

[0099] Sixth, by photolithography, a P-type heavily doped region 21 injection window is formed on the upper surface of the N-type lightly doped layer 31, and boron ions are injected into the injection window at an injection energy of 120 eKV to form the P-type heavily doped region 21, and then the resist is removed. The resulting structure is as shown in FIG. Fig. 9 shown.

[0100] Seventh, the well-pushing process is carried out in a furnace tube at 1200°C for 3 hours. The highest doping concentration of the P-type heavily doped region 21 after well-pushing is 1×10 17 cm -3 , the junction depth is 7 μm, and the highest doping concentration of the P-type lightly doped region 23 is 1×10 16 cm -3 The junction depth is 5 μm, and the highest doping concentration of the anode N-type region 22 is 1×10 17 cm -3 , the junction depth is 3μm, and the resulting structure is as follows Fig.10 shown.

[0101] Eighth, a 4 μm AlSi (aluminum silicide) layer is covered on the upper surface of the N-type lightly doped layer 31 by sputtering process, and an anode metal layer 50 is formed after alloying process in an alloying furnace. The obtained structure is as follows: Fig.11 shown.

[0102] Ninth, an ohmic contact cathode metal layer 50 of Ti (titanium) / Ni (nickel) / Ag (silver) with a covering thickness of 0.2 μm / 0.5 μm / 1.0 μm is formed on the lower surface of the N-type heavily doped layer 40 by sputtering or evaporation, and then an alloying process is performed. The resulting structure is as follows: Figure 1 shown.

[0103] In the embodiment of the present invention, there is no restriction on the specific parameters of the alloy process and the well-pushing process, which can be selected according to actual needs. The temperature of the alloy process is generally greater than 300°C, and the well-pushing temperature is generally greater than 1000°C.

[0104] In the embodiment of the present invention, the anode metal layer 10 and the cathode metal layer 50 may be manufactured by evaporation, sputtering or other processes, and the present application does not limit the formation method of the two metal layers.

[0105] In some embodiments, Figure 2 The process flow of the semiconductor device 1 is the same as that of the above Figure 1 The process flow of the semiconductor device 1 is similar to that of the semiconductor device 1, except that the fifth step and the sixth step are interchanged in order, and the injection window of the anode N-type region 22 in the fifth step is widened so that its edge is wrapped by the P-type heavily doped region 21, and finally a structure as shown in FIG. Figure 2 The structure of the semiconductor device 1 is shown. The specific process will not be described in detail here.

[0106] In some embodiments, Figure 3 The process flow of the semiconductor device 1 is the same as that of the above Figure 1 The process flow of the semiconductor device 1 is similar to that of the semiconductor device 1, except that a step is added between the seventh step and the eighth step, that is, Fig.10 After the device structure shown in the figure is cleaned, a photolithography process is performed on the upper surface of the N-type lightly doped layer 31 using a P-type heavily doped region 21 mask to form a Si etching window, and the upper surface of the N-type lightly doped layer 31 is etched down by 2.5 μm. After the eighth and ninth steps, the structure shown in the figure is finally formed. Figure 3 The structure of the semiconductor device 1 is shown. The specific process will not be described in detail here.

[0107] Reference below Fig.12 An electronic device according to an embodiment of the present invention is described.

[0108] Fig.12 is a block diagram of an electronic device according to an embodiment of the present utility model, such as Fig.12 As shown, the electronic device 101 includes the semiconductor device 1 described in the above embodiment.

[0109] In some embodiments, the electronic device 101 of the embodiment of the utility model can be a power electronic device, such as an inverter, a rectifier, a frequency converter, an electric drive system, an electric vehicle controller, etc. These electronic devices 101 are used to process high-power electrical signals and achieve effective power conversion. By integrating the semiconductor device 1, the electronic device 101 can achieve efficient and reliable power circuit control to meet the requirements of various application fields.

[0110] According to the electronic device 101 of the embodiment of the present invention, by adopting the semiconductor device 1 described in the above embodiment, the holes generated by the I region structure 30 can be eliminated faster when the device is turned off, thereby shortening the reverse recovery time of the device and reducing the device turn-off loss.

[0111] In some embodiments, the electronic device 101 further includes an insulated gate bipolar transistor 2, which can be a semiconductor device 1 that combines the characteristics of a field effect transistor and a bipolar transistor. The insulated gate bipolar transistor 2 can be used in power electronic applications such as power amplifiers and switching power supplies because it has the ability to operate at high current and high voltage.

[0112] In some embodiments, the insulated gate bipolar transistor 2 is connected in reverse parallel with the semiconductor device 1, which means that the current directions of the two devices are opposite. That is, when one device is in the on state, the other device can provide a reverse current path, thereby protecting the entire circuit from unexpected overcurrent or overvoltage to some extent.

[0113] Furthermore, hybrid power control can be achieved by properly configuring the working states of the insulated gate bipolar transistor 2 and the semiconductor device 1. For example, in the positive half cycle, the semiconductor device 1 can be responsible for the conduction of the current, while in the negative half cycle, the insulated gate bipolar transistor 2 can be responsible for the conduction of the current, thereby achieving power control.

[0114] In some embodiments, the stability of the circuit can be enhanced by adding an appropriate protection circuit between the insulated gate bipolar transistor 2 and the semiconductor device 1. This includes functions such as overcurrent protection and overvoltage protection to ensure that the electronic device 101 can operate reliably under various working conditions. In addition, the performance of the entire electronic device 101 can be optimized through appropriate circuit design and control strategies.

[0115] Reference below Fig.13 A vehicle according to an embodiment of the present invention is described.

[0116] Fig.13 is a block diagram of a vehicle according to an embodiment of the present utility model, such as Fig.13 As shown, the vehicle 100 includes the electronic device 101 described in the above embodiment.

[0117] In some embodiments, the vehicle 100 may be various types of vehicles, including but not limited to electric vehicles, hybrid vehicles, electric bicycles, motorcycles, and electric buses.

[0118] According to the vehicle 100 of the embodiment of the utility model, the holes generated by the I region structure 30 can be eliminated faster when the device is turned off, thereby shortening the reverse recovery time of the device and reducing the device turn-off loss, thereby improving the overall performance of the vehicle 100.

[0119] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the utility model. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example.

[0120] Although the embodiments of the present invention have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A semiconductor device, characterized in that: include: An anode metal layer, a P region structure and an I region structure arranged along the longitudinal direction of the device; The P-region structure includes a plurality of P-type heavily doped regions, and the plurality of P-type heavily doped regions are arranged at intervals along the lateral direction of the device; An anode N-type region is formed between two adjacent P-type heavily doped regions; The anode N-type region contacts the anode metal layer to recombine or extract holes from the I-region structure when the device is turned off.

2. The semiconductor device according to claim 1, wherein: A P-type lightly doped region is also formed between two adjacent P-type heavily doped regions; Along the longitudinal direction of the device, the P-type lightly doped region is located below the anode N-type region, and the P-type lightly doped region is in contact with the anode N-type region and the I-region structure respectively.

3. The semiconductor device according to claim 2, characterized in that The P-type lightly doped region surrounds the bottom surface and side surfaces of the anode N-type region; The upper surface of the anode N-type region is in contact with the anode metal layer; The side surface of the P-type lightly doped region contacts the P-type heavily doped region, and the bottom surface of the P-type lightly doped region contacts the I-region structure.

4. The semiconductor device according to claim 3, characterized in that The anode metal layer also covers the portion of the P-type lightly doped region located on the side of the anode N-type region and the P-type heavily doped region.

5. The semiconductor device according to claim 4, characterized in that The upper surface of the anode N-type region, the upper surface of the portion of the P-type lightly doped region located on the side of the anode N-type region, and the upper surface of the P-type heavily doped region are all flush.

6. The semiconductor device according to claim 2, wherein: Along the longitudinal direction of the device, the upper surface of the anode N-type region contacts the anode metal layer, the lower surface of the anode N-type region contacts the upper surface of the P-type lightly doped region, the lower surface of the P-type lightly doped region contacts the I-region structure, and the side surfaces of the anode N-type region and the side surfaces of the P-type lightly doped region are both in contact with the P-type heavily doped region.

7. The semiconductor device according to claim 6, characterized in that The P-type lightly doped regions grow at both ends of the anode N-type region extending in the lateral direction of the device.

8. The semiconductor device according to claim 7, characterized in that The anode metal layer also covers the P-type heavily doped region, and the upper surface of the anode N-type region is flush with the upper surface of the P-type heavily doped region.

9. The semiconductor device according to claim 5 or 8, characterized in that: The depth of the P-type heavily doped region along the longitudinal direction of the device is greater than the total depth of the anode N-type region and the P-type lightly doped region along the longitudinal direction of the device.

10. The semiconductor device according to claim 4, characterized in that The upper surface of the anode N-type region is flush with the upper surface of the portion of the P-type lightly doped region located on the side of the anode N-type region; The upper surface of the anode N-type region and the upper surface of the portion of the P-type lightly doped region located on the side of the anode N-type region both protrude from the upper surface of the P-type heavily doped region toward the anode metal layer, and a portion of the side of the P-type lightly doped region contacts the anode metal layer.

11. The semiconductor device according to claim 10, characterized in that A groove is formed on the anode metal layer at a position corresponding to the P-type heavily doped region.

12. The semiconductor device according to claim 2, characterized in that The I-region structure includes an N-type lightly doped layer, and an upper surface of the N-type lightly doped layer is in contact with both a lower surface of the P-type heavily doped region and a lower surface of the P-type lightly doped region.

13. The semiconductor device according to claim 12, characterized in that The semiconductor device further comprises: An N-type heavily doped layer is located below the N-type lightly doped layer along the longitudinal direction of the device.

14. The semiconductor device according to claim 13, characterized in that The semiconductor device further comprises: An N-type buffer layer is located between the N-type heavily doped layer and the N-type lightly doped layer.

15. The semiconductor device according to claim 13, wherein: The semiconductor device further comprises: A cathode metal layer covers the N-type heavily doped layer along the longitudinal direction of the device.

16. An electronic device, characterized in that: A semiconductor device comprising any one of claims 1 to 15.

17. The electronic device according to claim 16, characterized in that: The electronic device further includes an insulated gate bipolar transistor connected in reverse parallel to the semiconductor device.

18. A vehicle, characterized in that: An electronic device comprising the electronic device described in claim 16 or 17.

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