Inverter output protection circuit

Abstract

The utility model relates to the technical field of inverter systems, and discloses an inverter output protection circuit which specifically comprises a detection circuit and a switching circuit. The detection circuit is used for outputting a protection signal when the inverter breaks down, and the switching circuit is connected to an inverter driving branch in series; when the switching circuit does not receive the protection signal, the driving branch is kept in a conducting state; when the switching circuit receives the protection signal, the driving branch is kept in a cut-off state; through the arrangement of the detection circuit and the switching circuit, when the inverter breaks down, a protection signal capable of enabling the switching circuit to act is sent out, and the driving branch can be disconnected in time when the inverter breaks down.

Description

Technical Field

[0001] The present invention relates to the technical field of inverter systems, and in particular to an inverter output protection circuit. Background Art

[0002] In the inverter system, a protection circuit is set up to realize the emergency shutdown of the inverter output when an abnormal situation occurs in the inverter. Existing inverters are generally driven by PWM signals, and the drive signal is generally output by a DSP unit or an MCU unit. Most of the current protection circuits realize the emergency shutdown of the inverter output by controlling the DSP unit or the MCU unit to stop the output of the drive signal when an abnormality is detected; this form of software protection causes a large time delay from the occurrence of the fault to the complete shutdown of the inverter output, and this delay will seriously reduce the protection effect of the protection circuit. Summary of the invention

[0003] The present invention provides an inverter output protection circuit and method, which can overcome certain defects of the prior art.

[0004] To achieve the above objectives, the present invention is implemented through the following technical solutions, which include:

[0005] An inverter output protection circuit comprises a detection circuit and a switch circuit. The detection circuit is used to output a protection signal when an inverter fails. The switch circuit is connected in series to a drive branch of the inverter. When the switch circuit does not receive a protection signal, the drive branch is kept in an on state. When the switch circuit receives a protection signal, the drive branch is kept in an off state.

[0006] Through the arrangement of the detection circuit and the switch circuit in the present invention, when a fault occurs in the inverter, a protection signal is sent out to activate the switch circuit, thereby realizing that the drive branch can be disconnected in time when a fault occurs.

[0007] Preferably, the inverter adopts a HERIC inverter, which has an inverter main switch tube and an inverter auxiliary switch tube; the drive branch is used to drive the inverter main switch tube and the inverter auxiliary switch tube.

[0008] Through the arrangement of the HERIC inverter, the inverter main switch tube and the inverter auxiliary switch tube in the present invention, when the inverter works normally, the inverter main switch tube inverts the main DC power supply through periodic action, and the complementary auxiliary switch tube is turned off when the main switch tube is turned on. After the main switch tube is turned off, the complementary auxiliary switch tube is turned on as a freewheeling channel for the inductor current, thereby preventing the induced abnormal voltage caused by the sudden change of the inductor current from damaging the circuit components.

[0009] Preferably, the driving branch includes a main driving branch for driving the inverter main switch tube and an auxiliary driving branch for driving the inverter auxiliary switch tube; the switching circuit includes a main switching circuit arranged at the main driving branch and an auxiliary switching circuit arranged at the auxiliary driving branch; the main switching circuit is directly connected to the detection circuit, and the auxiliary switching circuit is connected to the detection circuit through a delay circuit.

[0010] Through the arrangement of the main drive branch, the main switch circuit, the auxiliary drive branch, the auxiliary switch circuit and the delay circuit in the present invention, the inverter main switch tube and the inverter auxiliary switch tube are controlled separately. When the inverter fails, the main switch circuit is disconnected immediately after receiving the protection signal, and the inverter main switch tube driven by the main switch circuit is also immediately turned into the cut-off state after losing the drive. However, the auxiliary switch circuit receives the protection signal only after the preset delay time of the front delay circuit, and the inverter auxiliary switch tube cannot be immediately turned into the cut-off state. At the same time, in the HERIC inverter circuit, the inverter main switch tube is disconnected immediately and the inverter auxiliary switch tube can work normally within the preset delay time to ensure the continuous flow of the inductive current, thereby reducing the risk of the induced voltage generated by the shutdown of the main switch tube being superimposed on the original voltage to exceed the withstand voltage value of the switch tube and causing damage to the switch tube.

[0011] Preferably, the driving signals at the main driving branch and the auxiliary driving branch are both PWM signals, and the main switching circuit and the auxiliary switching circuit both use buffer circuits; the buffer circuit includes a buffer chip, and the detection circuit is connected to the enable pin of the buffer chip through the output control circuit.

[0012] Through the arrangement of the buffer circuit and the buffer chip in the present invention, when the main switch circuit or the auxiliary switch circuit receives a protection signal, the corresponding buffer chip will simultaneously block all the inverter PWM waves and turn off the corresponding switch tube.

[0013] Preferably, the output control circuit includes a main output control circuit corresponding to the main switching circuit and an auxiliary output control circuit corresponding to the auxiliary switching circuit.

[0014] Preferably, the main output control circuit and the auxiliary output control circuit both include a MOS tube, the detection circuit is connected to the gate of the MOS tube, and the enable pin of the buffer chip is connected to the drain of the MOS tube; the source of the MOS tube is grounded, a bias resistor is set between the gate and the source of the MOS tube, and the drain of the MOS tube is connected to the power supply VD through a pull-up resistor.

[0015] Preferably, the delay circuit includes a capacitor C3 disposed between the drain of the corresponding MOS tube and the ground terminal.

[0016] Preferably, the model of the buffer chip is SN74HC245 or SN74HCT244.

[0017] Preferably, there are two inverter auxiliary switch tubes in the HERIC inverter, and the two inverter auxiliary switch tubes are connected in series in opposite directions and connected to the HERIC inverter.

[0018] An inverter output protection method adopts any of the above-mentioned inverter output protection circuits to protect an inverter circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a block diagram of an inverter output protection method in Example 1;

[0020] Figure 2 This is the HERIC inverter circuit diagram;

[0021] Figure 3 is a circuit diagram of an inverter output protection circuit in Example 1;

[0022] Figure 4 is a block diagram of an inverter output protection method in Example 2;

[0023] Figure 5 This is a circuit diagram of an inverter output protection circuit in Example 2. DETAILED DESCRIPTION

[0024] In order to further understand the content of the present invention, the present invention is described in detail in conjunction with the embodiments. It should be understood that the embodiments are only for explaining the present invention and are not intended to limit it.

[0025] Example 1

[0026] The present embodiment provides an inverter output protection circuit, which includes a detection circuit and a switching circuit. The detection circuit is used to output a protection signal when a fault occurs in the inverter, and the switching circuit is connected in series to the inverter drive branch; when the switch circuit does not receive the protection signal, the drive branch is kept in an on state; when the switch circuit receives the protection signal, the drive branch is kept in an off state.

[0027] In this embodiment, by directly setting the switch circuit at the driving branch, when the inverter fails, the switch circuit can directly disconnect the driving branch under the control of the protection signal output by the detection circuit. That is, in this embodiment, the detection circuit and the switch circuit can constitute a fault protection in the form of hardware protection, so that when the inverter fails, the action of the protection circuit can take effect more quickly, so that the time delay from the occurrence of the fault to the complete shutdown of the inverter output can be greatly reduced, thereby preferably improving the protection effect of the protection circuit.

[0028] See Figure 1The driving branch of this embodiment can include a driving signal generating unit (such as a DSP unit or an MCU unit) and a switch tube driving isolation amplifier unit connected in sequence, and the inverter can include a switch tube; wherein the driving signal can be generated at the driving signal generating unit, and output to the switch tube after being isolated and amplified by the switch tube driving isolation amplifier unit, and the switch tube realizes inverter output under the control of the received driving signal.

[0029] In this embodiment, the switch circuit can be provided between the drive signal generating unit and the switch tube drive isolation amplifier unit.

[0030] The inverter in this embodiment can adopt a HERIC inverter (ie, a HERIC inverter topology), and the HERIC inverter has an inverter main switch tube and an inverter auxiliary switch tube; the drive branch is used to drive the inverter main switch tube and the inverter auxiliary switch tube.

[0031] Through the setting of the HERIC inverter, the inverter main switch tube and the inverter auxiliary switch tube in this embodiment, when the inverter is working normally, the inverter main switch tube inverts the main DC power supply through periodic actions. When the inverter main switch tube is turned on, the complementary inverter auxiliary switch tube is turned off. After the main switch tube is turned off, the inverter auxiliary switch tube is turned on as a freewheeling channel for the inductor current, thereby preventing the induced abnormal voltage caused by the sudden change of the inductor current from damaging the circuit components.

[0032] See Figure 2 In this embodiment, the HERIC inverter has four inverter main switch tubes and two inverter auxiliary switch tubes. The drive branch can be used to drive the inverter main switch tubes and the inverter auxiliary switch tubes at the same time, and the drive signal at the drive branch is a PWM signal.

[0033] Among them, there are two inverter auxiliary switch tubes in the HERIC inverter, and the two inverter auxiliary switch tubes are in opposite directions and connected in series to the HERIC inverter.

[0034] Among them, C1 is the bus capacitor, Q1, Q2, Q3, Q4 are the inverter main switch tubes, Q5 and Q6 are the inverter auxiliary switch tubes, inductor L1 and capacitor C2 form the output LC filter circuit, L2 is the parasitic inductance generated on the line, and RLOAD is the power load. Q1 and Q3, Q2 and Q4 work in the positive half-cycle and negative half-cycle of the sine wave respectively, and the positive and negative half-cycles work in the same way. Take the positive half-cycle as an example: in the positive half-cycle, Q2 and Q4 are always in the off state, Q5 is always in the on state, Q6 works in PWM mode and is complementary to Q1 and Q3. Q1 and Q3 work in PWM mode. The conduction current of Q1 and Q3 forms a loop through INV_BUS (C1+) → L2 → Q1 → L1 → C2 / / RLOAD → Q3 → GND (C1-). When Q1 and Q3 are turned off and Q6 is turned on, the inductor current follows Figure 2The loop in the middle direction is L1→C2 / / RLOAD→Q6→Q5→L1.

[0035] See Figure 3 The switch circuit in this embodiment adopts a buffer circuit (i.e. Figure 1 The buffer circuit includes a buffer chip U1, and the model of the buffer chip can be SN74HC245 or SN74HCT244. The detection circuit is connected to the enable pin of the buffer chip through the output control circuit.

[0036] The output control circuit in this embodiment includes a MOS transistor Q7, a detection circuit is connected to the gate of the MOS transistor Q7, an enable pin of the buffer chip U1 is connected to the drain of the MOS transistor Q7; the source of the MOS transistor Q7 is grounded, a bias resistor R1 is provided between the gate and the source of the MOS transistor Q7, and the drain of the MOS transistor Q7 is connected to the power supply VD through a pull-up resistor R2.

[0037] Through the above:

[0038] When the inverter is working normally, the detection circuit does not output a protection signal ( Figure 2 The FAULT signal in the output pin is high level, and the drain and source of the MOS tube Q7 are turned on. Therefore, the signal output by the output control circuit to the enable pin of the buffer chip is low level, so the buffer circuit can remain turned on. At this time, the drive signal can be normally output to the switch tubes Q1-Q6, and the inverter works normally.

[0039] When an abnormal situation occurs, the detection circuit outputs a protection signal. At this time, the FAULT signal is at a low level. At this time, the drain and source of the MOS tube Q7 are cut off, so the signal output by the output control circuit to the enable pin of the buffer chip is quickly pulled up to a high level, so the buffer circuit can remain in the cut-off state. At this time, the drive signal cannot be output normally to the switch tubes Q1-Q6, and the inverter stops working.

[0040] Based on an inverter output protection circuit provided in this embodiment, this embodiment also provides an inverter output protection method, which has the following working process:

[0041] When the inverter is working normally, the driving signal at the driving branch, i.e., the PWM signal, is generated by the signal source DSP / MCU and output to U1. At the same time, the detection circuit outputs a high-level normal signal that can turn on Q7 in the output control circuit. At this time, due to the conduction of Q7, the output control circuit sends a low-level enable signal to the enable pin of U1. U1 outputs the PWM signal to the driving circuit for isolation and amplification. Figure 3The inverter main switch tubes Q1, Q2, Q3 and Q4 and the inverter auxiliary switch tubes Q5 and Q6 in the HERIC inverter circuit receive the PWM signal after isolation and amplification to perform periodic actions to achieve inversion;

[0042] When the detection circuit detects that the inverter has an overvoltage or overcurrent fault, it sends a low-level protection signal to the gate of the MOS tube Q7 in the output control circuit to turn the MOS tube Q7 into a cut-off state. At this time, due to the cut-off of the MOS tube Q7, the output control circuit immediately sends a high-level enable signal to the enable pin of U1, and the buffer U1 immediately stops the output of all PWM signals. The inverter main switch tubes Q1, Q2, Q3 and Q4 and the inverter auxiliary switch tubes Q5 and Q6 in the HERIC inverter circuit also immediately turn into a cut-off state after losing the PWM drive signal, and the inverter circuit stops inverting.

[0043] Example 2

[0044] It is understandable that LC filters and line parasitic inductances are present in general inverter circuits. One of the most important characteristics of inductance is that its current cannot change suddenly. If its current path is suddenly cut off, a very high voltage will be induced (the voltage is proportional to the inductance value and the current change rate). This induced voltage superimposed on the original voltage may exceed the withstand voltage of the switch tube and cause damage to the switch tube. In addition, there are common-mode voltage and current problems. In order to solve these problems, general inverter circuits have corresponding inverter auxiliary switch tubes (Q5 and Q6 in Example 1) as freewheeling channels after the inverter main switch tubes (Q1-Q4 in Example 1) are turned off.

[0045] However, in the scheme of Example 1,

[0046] When there is no fault, the inverter main switch tube and the inverter auxiliary switch tube are turned on alternately. When the inverter main switch tube is turned on, the complementary inverter auxiliary switch tube is turned off. After the inverter main switch tube is turned off, the complementary inverter auxiliary switch tube is turned on as a freewheeling channel for the inductor current.

[0047] When a fault occurs, the main switch tubes Q1-Q4 and the auxiliary switch tubes Q5-Q6 will be turned off at the same time, which causes the inductor current to be unable to continue to flow along the normal freewheeling channel, but to take a tortuous and long freewheeling loop. Since the freewheeling loop becomes tortuous and longer, there is a large parasitic inductance that cannot be ignored on the loop, which causes a much larger peak voltage (induced voltage) than normal to be superimposed on both ends of the switch tube, posing a risk of damaging the switch tube.

[0048] Specifically:

[0049] When there is no fault, it is assumed that the current flowing through the inductor L1 and the inductor L2 at the time when Q1 and Q3 are turned off is +Io, where inductor L1 is the filter inductor in the HERIC inverter and inductor L2 is the parasitic inductor in the HERIC inverter. After Q1 and Q3 are turned off, the current flowing through L1 is still +Io, but the current flowing through the parasitic inductor L2 becomes 0, and the current change on L2 is di=Io-0=Io. Assuming that the time of this turn-off process is dt and the inductance of the parasitic inductor L2 is L, the induced voltage U1=L*Io / dt generated on the parasitic inductor L2;

[0050] When a fault occurs, taking the inverter circuit working in the positive half cycle as an example, the inductor current cannot be normally freewheeling and is forced to change to the path of L1→C2 / / RLOAD→Q2→L2→INV_BUS(C1+)→GND(C1-)→Q4→L1, taking a tortuous long freewheeling loop; for the current change of the parasitic inductor L2, the direction of the current flowing through the parasitic inductor L2 before Q1~Q6 are turned off at the same time is opposite to that after the shutdown, and Q1 and Q3 are turned off. The current flowing through L1 and L2 before turning off is also +Io. After Q1 and Q3 are turned off, the current flowing through L1 is still +Io, but the current flowing through the parasitic inductance L2 becomes -Io. The current change on L2 is di=Io-(-Io)=2Io. Assuming that the conversion process time is still dt and the inductance of the parasitic inductance L2 is still L, the induced voltage U2=L*2Io / dt=2L*Io / dt=2U1 is generated on the parasitic inductance L2.

[0051] That is, under the condition of the same output current, the induced voltage generated by the parasitic inductance caused by the abnormal protection shutdown is twice that of the normal condition. Since the freewheeling loop becomes tortuous and longer, the parasitic inductance on the loop becomes larger and cannot be ignored. This results in the increased induced voltage superimposed on the normal voltage, which may exceed the maximum voltage that the switching tube can withstand. It can be understood by those skilled in the art that semiconductor devices have a very weak ability to withstand overvoltage, and the above problem is likely to cause the switching tube to break down and be damaged.

[0052] In order to solve the problem in Example 1 that after an abnormal situation occurs, all switch tubes are turned off at the same time, causing the voltage stress of the switch tubes to increase significantly, and even causing the switch tubes to be damaged and explode.

[0053] See Figure 4-5 Based on the embodiment 1, this embodiment also provides an inverter output protection circuit. The difference between this embodiment and the embodiment 1 is that:

[0054] The driving branch includes a main driving branch for driving the inverter main switch tube and an auxiliary driving branch for driving the inverter auxiliary switch tube; the switch circuit includes a main switch circuit arranged at the main driving branch and an auxiliary switch circuit arranged at the auxiliary driving branch; the main switch circuit is directly connected to the detection circuit, and the auxiliary switch circuit is connected to the detection circuit through a delay circuit.

[0055] Through the above, when an abnormal situation occurs and the inverter output protection needs to be turned off, the inverter auxiliary switch tube can be controlled to delay the shutdown to complete the current flow in the LC filter inductor, so that it naturally drops to zero, thereby avoiding the current in the filter inductor flowing through INV_BUS to cause the parasitic inductance to generate abnormal induced voltage, thereby avoiding the switch tube from being subjected to additional voltage stress, and greatly reducing the risk of the switch tube being broken down and failing.

[0056] In this embodiment, the driving signals at the main driving branch and the auxiliary driving branch are both PWM signals, and the main switch circuit and the auxiliary switch circuit both use buffer circuits; the buffer circuit includes a buffer chip ( Figure 5 In the embodiment, the buffer chip U1 corresponds to the main switch circuit, the buffer chip U2 corresponds to the auxiliary switch circuit), and the detection circuit is connected to the enable pin of the buffer chip through the output control circuit.

[0057] In this embodiment, the output control circuit includes a main output control circuit corresponding to the main switch circuit ( Figure 5 The output control circuit 1) in the auxiliary output control circuit corresponding to the auxiliary switch circuit ( Figure 5 Output control circuit 2).

[0058] In this embodiment, the main output control circuit and the auxiliary output control circuit both include MOS tubes, the detection circuit is connected to the gate of the MOS tube, and the enable pin of the buffer chip is connected to the drain of the MOS tube; the source of the MOS tube is grounded, a bias resistor is set between the gate and the source of the MOS tube, and the drain of the MOS tube is connected to the power supply VD through a pull-up resistor.

[0059] In this embodiment, the delay circuit includes a capacitor C3 disposed between the drain of the corresponding MOS tube and the ground terminal.

[0060] Through the setting of the output control circuit 1, the main drive branch, the main switch circuit output control circuit 2, the auxiliary drive branch, the auxiliary switch circuit and the delay circuit in this embodiment, when the inverter works normally, the output control circuit 1 outputs a normal signal to U1 so that it can input and output normally; the output control circuit 2 outputs a normal signal to the delay circuit, and the delay circuit then sends the normal signal to U2 so that it can input and output normally. The subsequent inverter process of the HERIC inverter circuit is consistent with that in Example 1.

[0061] Combination Figure 5In the inverter operation process, if the detection circuit detects an abnormal situation, it outputs a protection signal to the output control circuit 1 and the output control circuit 2; after receiving the protection signal, the output control circuit 1 immediately sends an enable signal to turn off U1 and stop the output of U1, then the PWM signal of the inverter main switch tube is immediately blocked, and the inverter main switch tube stops working immediately; after receiving the protection signal, the output control circuit 2 also immediately sends an enable signal to the delay circuit, and the delay circuit will not send the enable signal immediately after receiving it. The circuit will wait until the delay time is up before outputting the enable signal to turn off U2; during the delay period of the enable signal, U2 continues to isolate and amplify the received PWM signal and send it to the inverter auxiliary switch tube, and the inverter auxiliary switch tube can continue to work to realize the same freewheeling mode as in Example 1, and the output of U2 is blocked after the delay time is up.

[0062] In this embodiment, the delay circuit includes a capacitor C3 disposed between the drain of the corresponding MOS tube and the ground terminal.

[0063] Through the setting of capacitor C3 in this embodiment, when capacitor C3 receives a high-level enable signal, capacitor C3 is charged. Capacitor C3 outputs the enable signal only when it is charged to a certain level. The charging time of capacitor C3 depends on the capacitance value of capacitor C3 and the resistance value of the pull-up resistor.

[0064] Combination Figure 5 When capacitor C3 receives a high-level enable signal, enable pin PIN19 of U1 also receives a high-level enable signal at the same time, but U1 stops working first and blocks the output of the PWM signal that can drive the inverter main switch tube. Due to the existence of capacitor C3, the enable pin of U2 can block the output of the PWM signal that can drive the inverter auxiliary switch tube after a certain delay time. During this period, the HERIC inverter circuit stops inverting, while the inductor current on L1 is still flowing, and one of the two inverter auxiliary switch tubes that continues to receive the PWM signal serves as the freewheeling channel for the inductor current.

[0065] This embodiment further provides an inverter output protection method, which uses an inverter output protection circuit described in this embodiment to protect the inverter circuit.

[0066] The specific working process of this embodiment is as follows: when the inverter is working normally, the driving signal at the driving branch, i.e., the PWM signal, is generated by the signal source DSP / MCU and output to U1 and U2 respectively, and at the same time, the detection circuit outputs a normal signal of a high level that can turn on the MOS tubes Q7 and Q8. At this time, due to the conduction of the MOS tube Q7, the output control circuit 1 outputs an enable signal to U1 so that it can input and output normally. At the same time, due to the conduction of the MOS tube Q8, the output control circuit 2 outputs a normal signal to the delay circuit, and the delay circuit then sends the normal signal to U2 so that it can also input and output normally; Figure 3 The inverter main switch tubes Q1, Q2, Q3 and Q4 and the inverter auxiliary switch tubes Q5 and Q6 in the HERIC inverter circuit receive the PWM signal after isolation and amplification and perform periodic action to achieve inversion.

[0067] When the detection circuit detects an overvoltage or overcurrent fault in the inverter, the detection circuit outputs a low-level protection signal (i.e. Figure 5 The FAULT signal in the output control circuit 1 is sent to the gates of the MOS tubes Q7 and Q8 respectively, and the MOS tubes Q7 and Q8 become cut-off states. The output control circuit 1 immediately sends a high-level enable signal to the enable pin PIN19 of U1, and U1 immediately stops the output of all PWM signals. The inverter main switch tubes Q1, Q2, Q3 and Q4 in the HERIC inverter circuit immediately become cut-off states, and the inverter circuit stops inverting. After receiving the protection signal, the output control circuit 2 also immediately sends a shutdown enable signal to the delay circuit, but the delay circuit will not send an enable signal immediately after receiving it. The circuit will wait until the delay time is up before outputting the enable signal to close the buffer U2. During this delayed period, the output buffer 2 continues to isolate and amplify the received PWM signal, and the inverter auxiliary switches Q5 and Q6 of the HERIC inverter circuit continue to work after receiving the isolated and amplified PWM signal. When the inverter main switch is turned off, at least one of the inverter auxiliary switches Q5 and Q6 is in the on state and the conduction direction is consistent with the direction of the inductor current generated by L1. The inductor current continues to flow in the loop composed of L1, RLOAD in parallel with C2, Q6 and Q5. After a delay time that allows the inductor current on L1 to decrease to near zero, the output of the output buffer U2 is blocked, thereby turning off the auxiliary switches Q5 and Q6 to complete the protection of the inverter.

[0068] Compared with Embodiment 1, when the inverter fails, the present embodiment controls the inverter main switches Q1, Q2, Q3 and Q4 to be turned off first through the delay circuit, and then the inverter auxiliary switches Q5 and Q6 are turned off after a certain delay time. When the inverter fails, the auxiliary switches can provide the inverter circuit with a freewheeling channel that lasts for a certain delay time, which better avoids the inductor current on L1 flowing in the long freewheeling loop, thereby better reducing the risk of the induced voltage being superimposed on the original voltage exceeding the withstand voltage value of the switch tube. In addition, the present embodiment can turn off all switches in a relatively timely manner through hardware to stop the inverter process, thereby preventing the components of the inverter from being subjected to voltage and current shocks.

[0069] It is easy to understand that those skilled in the art can combine, split, reorganize, etc. the embodiments of the present application to obtain other embodiments based on one or several embodiments provided in the present application, and these embodiments do not exceed the protection scope of the present application.

[0070] The present invention and its implementation methods are described schematically above, and the description is not restrictive. The embodiments shown in the embodiments are only part of the implementation methods of the present invention, and the actual structure is not limited thereto. Therefore, if a person skilled in the art is inspired by the embodiments and designs a structure and an implementation method similar to the technical solution without creativity without departing from the purpose of the invention, they should all fall within the protection scope of the present invention.

Claims

1. An inverter output protection circuit, Features: It includes a detection circuit and a switch circuit. The detection circuit is used to output a protection signal when the inverter fails. The switch circuit is connected in series to the inverter drive branch. When the switch circuit does not receive the protection signal, the drive branch is kept in the on state. When the switch circuit receives the protection signal, the drive branch is kept in the off state. The inverter adopts the HERIC inverter, which has an inverter main switch tube and an inverter auxiliary switch tube. The driving branch is used to drive the inverter main switch tube and the inverter auxiliary switch tube; the driving branch includes a main driving branch for driving the inverter main switch tube and an auxiliary driving branch for driving the inverter auxiliary switch tube; the switch circuit includes a main switch circuit arranged at the main driving branch and an auxiliary switch circuit arranged at the auxiliary driving branch; the main switch circuit is directly connected to the detection circuit, and the auxiliary switch circuit is connected to the detection circuit through a delay circuit.

2. The inverter output protection circuit according to claim 1, Features: The driving signals at the main driving branch and the auxiliary driving branch are both PWM signals, and the main switching circuit and the auxiliary switching circuit both use buffer circuits; the buffer circuit includes a buffer chip, and the detection circuit is connected to the enable pin of the buffer chip through the output control circuit.

3. The inverter output protection circuit according to claim 2, Features: The output control circuit includes a main output control circuit corresponding to the main switching circuit and an auxiliary output control circuit corresponding to the auxiliary switching circuit.

4. The inverter output protection circuit according to claim 3, Features: The main output control circuit and the auxiliary output control circuit both include MOS tubes, the detection circuit is connected to the gate of the MOS tube, and the enable pin of the buffer chip is connected to the drain of the MOS tube; the source of the MOS tube is grounded, a bias resistor is set between the gate and the source of the MOS tube, and the drain of the MOS tube is connected to the power supply VD through a pull-up resistor.

5. The inverter output protection circuit according to claim 4, Features: The delay circuit includes a capacitor C3 disposed between the drain of the corresponding MOS tube and the ground terminal.

6. The inverter output protection circuit according to claim 2, Features: The model of the buffer chip is SN74HC245 or SN74HCT244.

7. The inverter output protection circuit according to claim 1, Features: There are two inverter auxiliary switch tubes in the HERIC inverter. The two inverter auxiliary switch tubes are in opposite directions and are connected in series to the HERIC inverter.

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