Control circuit of enhanced NMOS (N-channel Metal Oxide Semiconductor) tube

Abstract

The utility model provides a control circuit of an enhanced NMOS (N-channel Metal Oxide Semiconductor) tube. The control circuit comprises a negative voltage generation unit; the conduction unit consists of a first triode and a first diode; the turn-off unit consists of a second triode and a second diode; compared with the prior art, the duty ratio pulse signal output by the load controller and the positive voltage are input to the conduction unit, and the conduction unit controls the conduction of the enhanced NMOS tube. The duty ratio pulse signal output by the load controller and the negative voltage output by the negative voltage generation unit are input into the turn-off unit to control the turn-off of the enhanced NMOS tube, so that the gate junction capacitance current release of the enhanced NMOS tube can be accelerated to achieve the purpose of quick and reliable turn-off, and the turn-off loss of the enhanced NMOS tube is reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of electronic device protection, in particular to a control circuit of an enhanced NMOS tube. Background Art

[0002] MOS tube is the abbreviation of Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). The structural principle of enhancement NMOS is: enhancement NMOS uses a low-doped P-type silicon wafer as the substrate, uses a diffusion process to make two highly doped N+ regions, and introduces two levels, namely the source (Source, S) and the drain (Drain, D). A layer of SiO2 insulating layer is made on the semiconductor, and then a layer of polysilicon lead-out electrode is made on the insulating layer as the gate (Gate, G); the substrate and the source are usually connected together for use, so that the gate and the substrate are equivalent to a plate each, and the intermediate insulating layer forms a junction capacitor; when the gate-source voltage changes, the amount of induced charge on the substrate close to the insulating layer will change, thereby controlling the size of the drain current.

[0003] NMOS tubes belong to power electronic switches. They switch very quickly during operation, and can switch thousands of times per second. High-speed power devices can reach tens of kHz or even hundreds of kHz. Since there is junction capacitance in the device, the faster the switching speed, the greater the voltage change rate dv / dt and current change rate di / dt of the device. The greater the voltage change rate, the greater the switching loss, that is, the greater the heat generation, the lower the efficiency, and the power device is easily damaged. At present, the gate drive voltage range of most NMOS tubes is ±10V. The positive voltage of 4-10V is used for NMOS tube conduction, and the negative voltage is used for NMOS tube more reliably shut down. However, the current existing technology mainly realizes negative voltage shutdown by designing a specific drive power supply and drive chip, which is not only costly but also complex in circuit structure, which is not conducive to promotion. Utility Model Content

[0004] The utility model provides a control circuit for an enhanced NMOS tube, the purpose of which is to turn off the enhanced NMOS tube through negative voltage, thereby improving the turn-off reliability and reducing the turn-off loss.

[0005] In order to achieve the above object, the utility model provides a control circuit of an enhanced NMOS tube, comprising:

[0006] A negative voltage generating unit for generating a negative voltage;

[0007] A conduction unit composed of a first triode and a first diode and used for controlling the conduction of an enhancement-type NMOS tube;

[0008] A turn-off unit composed of a second triode and a second diode and used for controlling the turn-off of the enhancement type NMOS tube by a negative voltage;

[0009] The input end of the negative voltage generating unit, the collector of the first triode, and the power supply end of the load are all connected to the mains end, the output end of the negative voltage generating unit is connected to the collector of the second triode, the base of the first triode and the base of the second triode are both connected to the signal output end of the load controller, the emitter of the first triode is connected to the anode of the first diode, the emitter of the second triode is connected to the anode of the second diode, the cathode of the first diode and the cathode of the second diode are both connected to the gate of the enhancement type NMOS tube, and the drain of the enhancement type NMOS tube is connected to the input end of the load.

[0010] Furthermore, it also includes a first resistor;

[0011] The first end of the first resistor is connected to the signal output end of the load controller, and the second end of the first resistor is connected to the base of the first transistor and the base of the second transistor respectively.

[0012] More specifically, the negative pressure generating unit includes:

[0013] A power management chip, a first inductor, a second inductor, a first capacitor, a second capacitor, a third capacitor, a second resistor, a third resistor, a third diode, a fourth capacitor, a fifth capacitor, and a sixth capacitor;

[0014] The first pin of the power management chip is respectively connected to the first end of the second capacitor, the first end of the first capacitor, the first end of the third capacitor, and the second end of the first inductor; the first end of the first inductor is respectively connected to the mains terminal and the collector of the first transistor; the second end of the first capacitor and the second end of the second capacitor are both connected to the collector of the second transistor; the second end of the third capacitor is connected to the first end of the second resistor;

[0015] The second pin of the power management chip is connected to the third pin of the power management chip and the fourth pin of the power management chip respectively;

[0016] The fifth pin of the power management chip is respectively connected to the second end of the second resistor and the first end of the third resistor, and the second end of the third resistor is connected to the collector of the second transistor;

[0017] The sixth pin of the power management chip is respectively connected to the cathode of the third diode and the first end of the second inductor, and the second end of the second inductor is respectively connected to the first end of the fourth capacitor, the first end of the fifth capacitor, and the first end of the sixth capacitor and grounded;

[0018] The seventh pin of the power management chip is connected to the first end of the sixth capacitor;

[0019] The eighth pin of the power management chip is respectively connected to the anode of the third diode, the second end of the fourth resistor, the second end of the fourth capacitor, the second end of the fifth capacitor, the second end of the sixth capacitor, the collector of the second transistor, and the collector of the second transistor.

[0020] Furthermore, the negative pressure generating unit further includes a fourth resistor, a fifth resistor, and a seventh capacitor;

[0021] The first end of the fourth resistor is respectively connected to the seventh pin of the power management chip, the first end of the seventh capacitor, and the first end of the fifth resistor, and the second end of the fourth resistor is respectively connected to the eighth pin of the power management chip, the anode of the third diode, and the second end of the fourth capacitor;

[0022] The second end of the fifth resistor is connected to the second end of the seventh capacitor and the first end of the sixth capacitor respectively.

[0023] Specifically, the power management chip is a XL1509 step-down DC-DC converter.

[0024] Specifically, the load is a DC motor.

[0025] The above solution of the utility model has the following beneficial effects:

[0026] The utility model comprises a negative voltage generating unit; a conduction unit composed of a first triode and a first diode; and a shutoff unit composed of a second triode and a second diode. Compared with the prior art, the utility model inputs a duty cycle pulse signal and a positive voltage output by a load controller into the conduction unit, and controls the conduction of an enhanced NMOS tube through the conduction unit. When the load needs to adjust the speed, the duty cycle pulse signal output by the load controller and the negative voltage output by the negative voltage generating unit are both input into the shutoff unit to control the shutdown of the enhanced NMOS tube, which can accelerate the release of the gate junction capacitance current of the enhanced NMOS tube to achieve the purpose of fast and reliable shutdown, and reduce the shutdown loss of the enhanced NMOS tube.

[0027] Other beneficial effects of the present invention will be described in detail in the subsequent specific implementation sections. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a principle block diagram of an embodiment of the utility model;

[0029] Figure 2 The schematic diagram of the circuit of the embodiment of the utility model. DETAILED DESCRIPTION

[0030] In order to make the technical problems, technical solutions and advantages to be solved by the utility model clearer, the following will be described in detail with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are part of the embodiments of the utility model, not all of them. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0031] In the description of the present utility model, it should be noted that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside" and the like indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present utility model. In addition, the terms "first", "second", and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance. In addition, the technical features involved in the different embodiments of the present utility model described below can be combined with each other as long as they do not conflict with each other.

[0032] Due to the manufacturing process of the enhanced NMOS tube, there are parasitic capacitors between the three pins, which makes it more troublesome to design or select the drive circuit, but it is unavoidable. Therefore, it is necessary to add a negative voltage within the safe range to the gate to quickly turn off the NMOS tube, so that the next high-level pulse can be turned on in a shorter time to reduce the loss caused by the shutdown delay; however, in order for the enhanced NMOS tube to act as an ideal switching device, it must have the following characteristics:

[0033] 1. There should be no restrictions on the amount of current that can be carried when PWM_IN is in the ON state;

[0034] 2. There should be no restriction on the blocking voltage when PWM_IN is in the OFF state;

[0035] 3. There should be zero voltage drop when the device is in the ON state;

[0036] 4. The off-state resistance should be infinite;

[0037] 5. There is no limit on the running speed of the equipment, and the purpose of speed regulation is ultimately achieved.

[0038] However, semiconductor switches are not so ideal. In actual situations, they can only have the following characteristics:

[0039] During the on state, the power handling capability is limited, i.e., the conduction current is limited. The blocking voltage during the off state is limited by the manufacturing process and the junction capacitance. The limited on and off times limit the switching speed, and the maximum operating frequency is also limited.

[0040] When the device is turned on, there will be a finite on-state resistance resulting in a forward voltage drop, and a finite off-state resistance resulting in a reverse leakage current; real switches experience power outages during the on state, off state, and transition state (from on to off or from off to on), so, for example Figure 1 , 2 As shown, an embodiment of the utility model provides a control circuit of an enhanced NMOS tube, including:

[0041] A negative voltage generating unit for generating a negative voltage;

[0042] A conduction unit composed of a first transistor Q1 and a first diode D1 and used for controlling the conduction of an enhancement-type NMOS tube;

[0043] A turn-off unit composed of a second triode Q2 and a second diode D2 and used for controlling the turn-off of the enhancement type NMOS tube by a negative voltage;

[0044] The input end of the negative voltage generating unit, the collector of the first transistor Q1, and the power supply end of the load are all connected to the mains end, the output end of the negative voltage generating unit is connected to the collector of the second transistor Q2, the base of the first transistor Q1 and the base of the second transistor Q2 are all connected to the signal output end of the load controller, the emitter of the first transistor Q1 is connected to the anode of the first diode D1, the emitter of the second transistor Q2 is connected to the anode of the second diode D2, the cathode of the first diode D1 and the cathode of the second diode D2 are all connected to the gate of the enhanced NMOS tube, the drain of the enhanced NMOS tube is connected to the input end of the load, and the enhanced NMOS tube is Figure 1 Device Q3 in.

[0045] Most preferably, it further includes a first resistor R1 for coupling a PWM speed regulation signal;

[0046] The first end of the first resistor R1 is connected to the signal output end of the load controller, and the second end of the first resistor R1 is connected to the base of the first transistor Q1 and the base of the second transistor Q2 respectively.

[0047] Most preferably, the negative voltage generating unit is used to convert the input +12V voltage into a -8V voltage, comprising:

[0048] Power management chip U1, first inductor L1, second inductor L2, first capacitor C1, second capacitor C2, third capacitor C3, second resistor R2, third resistor R3, third diode D3, fourth capacitor C4, fifth capacitor C5, sixth capacitor C6;

[0049] The first pin of the power management chip U1 is respectively connected to the first end of the second capacitor C2, the first end of the first capacitor C1, the first end of the third capacitor C3, and the second end of the first inductor L1. The first end of the first inductor L1 is respectively connected to the mains terminal and the collector of the first transistor Q1. The second end of the first capacitor C1 and the second end of the second capacitor C2 are both connected to the collector of the second transistor Q2. The second end of the third capacitor C3 is connected to the first end of the second resistor R2.

[0050] The second pin of the power management chip U1 is connected to the third pin of the power management chip U1 and the fourth pin of the power management chip U1 respectively;

[0051] The fifth pin of the power management chip U1 is connected to the second end of the second resistor R2 and the first end of the third resistor R3 respectively, and the second end of the third resistor R3 is connected to the collector of the second transistor Q2;

[0052] The sixth pin of the power management chip U1 is respectively connected to the cathode of the third diode D3 and the first end of the second inductor L2, and the second end of the second inductor L2 is respectively connected to the first end of the fourth capacitor C4, the first end of the fifth capacitor C5, and the first end of the sixth capacitor C6 and grounded;

[0053] The seventh pin of the power management chip U1 is connected to the first end of the sixth capacitor C6;

[0054] The eighth pin of the power management chip U1 is respectively connected to the anode of the third diode D3, the second end of the fourth resistor R4, the second end of the fourth capacitor C4, the second end of the fifth capacitor C5, the second end of the sixth capacitor C6, the collector of the second transistor Q2, and the collector of the second transistor Q2.

[0055] Specifically, the +12V power supply is loaded to the corresponding pin of the power management chip U1 through the first inductor L1, the first capacitor C1 and the second capacitor C2 for power supply, and the fifth pin is charged through the third capacitor C3 and the first resistor R1 to generate a high level. When the charging of the two ends of the third capacitor C3 reaches 12V, the voltage of the third capacitor C3 and one end of the first inductor L1 is released after voltage division by the first resistor R1 and the second resistor R2 to generate a pulse from high to low. This pulse puts the power management chip U1 in a normal working state, outputs a fixed 150kHz 2APWM voltage, and then stores energy through the second inductor L2, and then inputs the third diode D3 for freewheeling, and then filters and outputs a negative voltage through the fourth capacitor C4, the fifth capacitor C5, and the sixth capacitor C6.

[0056] Most preferably, the negative pressure generating unit further includes a fourth resistor R4, a fifth resistor R5, and a seventh capacitor C7 for improving the response speed;

[0057] The first end of the fourth resistor R4 is respectively connected to the seventh pin of the power management chip U1, the first end of the seventh capacitor C7, and the first end of the fifth resistor R5, and the second end of the fourth resistor R4 is respectively connected to the eighth pin of the power management chip U1, the anode of the third diode D3, and the second end of the fourth capacitor C4;

[0058] The second end of the fifth resistor R5 is connected to the second end of the seventh capacitor C7 and the first end of the sixth capacitor C6 respectively; after voltage division by the fourth resistor R4, the fifth resistor R5 and the seventh capacitor C7, the -8V voltage is generated faster.

[0059] Most preferably, the power management chip U1 is an XL1509 step-down DC-DC converter, which has a fixed 150kHz switching frequency and can provide a maximum output current capability of 2A, has low ripple, and excellent linear regulation and load regulation characteristics. The XL1509 has a built-in fixed frequency oscillator and frequency compensation circuit, which simplifies the circuit design.

[0060] Most preferably, the load is a DC motor. In the embodiment of the utility model, the load can be a DC motor in a DC fan. When speed regulation is required, PWM_IN outputs a pulse with adjustable duty cycle through a PWM modulation module in a load controller; when the first resistor R1, the first transistor Q1 and the first diode D1 are turned on, the gate of the enhanced NMOS tube is turned on and the load starts working; when PWM_IN outputs a low-level pulse with adjustable duty cycle, the first transistor Q1 is turned off; since the gate junction capacitance current di / dt of the enhanced NMOS tube cannot suddenly change, a shutdown delay is generated, resulting in losses; when the second transistor Q2 and the second diode D2 output a -8V voltage within a safe range to the enhanced NMOS tube, the enhanced NMOS tube is controlled to be turned off.

[0061] It should be noted that the load controller in the embodiment of the present utility model is a conventional load controller in the technical field, such as a microcontroller unit (MCU).

[0062] The embodiment of the utility model is applied to an enhanced NMOS tube, including a negative voltage generating unit; a conduction unit composed of a first triode and a first diode; and a turn-off unit composed of a second triode and a second diode. Compared with the prior art, the utility model inputs a duty cycle pulse signal and a positive voltage output by a load controller into the conduction unit, and controls the conduction of the enhanced NMOS tube through the conduction unit. When the load needs to adjust the speed, the duty cycle pulse signal output by the load controller and the negative voltage output by the negative voltage generating unit are both input into the turn-off unit to control the turn-off of the enhanced NMOS tube, which can accelerate the release of the gate junction capacitance current of the enhanced NMOS tube to achieve the purpose of fast and reliable turn-off, and reduce the turn-off loss of the enhanced NMOS tube.

[0063] The above is a preferred embodiment of the present invention. It should be pointed out that, for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the protection scope of the present invention.

Claims

1. A control circuit for an enhancement mode NMOS tube, characterized in that: include: A negative voltage generating unit for generating a negative voltage; A conduction unit composed of a first triode and a first diode and used for controlling the conduction of an enhancement-type NMOS tube; A turn-off unit composed of a second triode and a second diode and used for controlling the turn-off of the enhancement-type NMOS tube by the negative voltage; The input end of the negative voltage generating unit, the collector of the first transistor, and the power supply end of the load are all connected to the mains end, the output end of the negative voltage generating unit is connected to the collector of the second transistor, the base of the first transistor and the base of the second transistor are both connected to the signal output end of the load controller, the emitter of the first transistor is connected to the anode of the first diode, the emitter of the second transistor is connected to the anode of the second diode, the cathode of the first diode and the cathode of the second diode are both connected to the gate of the enhancement NMOS tube, and the drain of the enhancement NMOS tube is connected to the input end of the load.

2. The control circuit of the enhancement mode NMOS transistor according to claim 1, characterized in that: Also comprising a first resistor; The first end of the first resistor is connected to the signal output end of the load controller, and the second end of the first resistor is connected to the base of the first transistor and the base of the second transistor respectively.

3. The control circuit of the enhancement mode NMOS transistor according to claim 2, characterized in that: The negative pressure generating unit comprises: A power management chip, a first inductor, a second inductor, a first capacitor, a second capacitor, a third capacitor, a second resistor, a third resistor, a third diode, a fourth capacitor, a fifth capacitor, and a sixth capacitor; The first pin of the power management chip is respectively connected to the first end of the second capacitor, the first end of the first capacitor, the first end of the third capacitor, and the second end of the first inductor; the first end of the first inductor is respectively connected to the mains terminal and the collector of the first transistor; the second end of the first capacitor and the second end of the second capacitor are both connected to the collector of the second transistor; the second end of the third capacitor is connected to the first end of the second resistor; The second pin of the power management chip is connected to the third pin of the power management chip and the fourth pin of the power management chip respectively; The fifth pin of the power management chip is respectively connected to the second end of the second resistor and the first end of the third resistor, and the second end of the third resistor is connected to the collector of the second transistor; The sixth pin of the power management chip is respectively connected to the cathode of the third diode and the first end of the second inductor, and the second end of the second inductor is respectively connected to the first end of the fourth capacitor, the first end of the fifth capacitor, and the first end of the sixth capacitor and grounded; The seventh pin of the power management chip is connected to the first end of the sixth capacitor; The eighth pin of the power management chip is respectively connected to the anode of the third diode, the second end of the fourth capacitor, the second end of the fifth capacitor, the second end of the sixth capacitor, and the collector of the second transistor.

4. The control circuit of the enhancement mode NMOS transistor according to claim 3, characterized in that: The negative pressure generating unit further includes a fourth resistor, a fifth resistor, and a seventh capacitor; The first end of the fourth resistor is respectively connected to the seventh pin of the power management chip, the first end of the seventh capacitor, and the first end of the fifth resistor, and the second end of the fourth resistor is respectively connected to the eighth pin of the power management chip, the anode of the third diode, and the second end of the fourth capacitor; The second end of the fifth resistor is connected to the second end of the seventh capacitor and the first end of the sixth capacitor respectively.

5. The control circuit of the enhancement mode NMOS transistor according to claim 4, characterized in that: The power management chip is an XL1509 step-down DC-DC converter.

6. The control circuit of the enhancement mode NMOS transistor according to claim 5, characterized in that: The load is a DC motor.

Images