Image signal transmission circuit with stable data transmission

Abstract

The utility model relates to the technical field of image transmission, in particular to an image signal transmission circuit with stable data transmission, which comprises a coding and decoding unit and a transmission unit, and the coding and decoding unit comprises a coding module arranged at a transmitting end and a decoding module arranged at a receiving end. The conveying unit comprises a suppression module, a transmitting module and a receiving module. According to the utility model, the transmitting end carries out signal coding processing on generated image data through the coding module, carries out common-mode suppression and radio frequency rectification processing on signals through the suppression module, realizes signal transmission through the transmitting module and the receiving module, and carries out decoding processing on the received signals through the decoding module. The interference influence on the image signal during transmission is reduced, and the transmission data is prevented from being damaged.

Description

Technical Field

[0001] The utility model relates to the technical field of image transmission, in particular to an image signal transmission circuit with stable data transmission. Background Art

[0002] Image transmission refers to the process of transmitting or storing image information in real time or in a timely manner by processing the source and channel according to certain requirements. The image transmission circuit can convert sound, image and other signals into electrical signals, transmit them to the receiving end through the circuit, and then restore the electrical signals to the original signals.

[0003] For example, CN117041457A relates to a high-definition multimedia interface circuit with image superposition function and an image superposition method, wherein the high-definition multimedia interface circuit includes: a matrix switching circuit and an image superposition circuit; the image superposition circuit is connected to both ends of the matrix switching circuit in parallel; the matrix switching circuit is at least used to transmit the received image signal to be superimposed to the image superposition circuit based on the cross-switching of the internal signal transmission path; the image superposition circuit is used to perform superposition processing on the image signal to be superimposed, form a superimposed image signal, and transmit it to the matrix switching circuit; the matrix switching circuit outputs the superimposed image signal accordingly. In this way, on the basis of the cross-switching of the internal signal transmission path in the matrix switching circuit, combined with the parallel connected image superposition circuit, it is beneficial to reduce the complexity and repeatability of the image superposition circuit when it is connected to the circuit, and further ensure the real-time transmission when it is not superimposed. However, due to the interference of the complex electromagnetic environment during the circuit transmission process, the signal data will be distorted, and the image quality will be poor when it is finally restored to the image.

[0004] In order to avoid data damage caused by interference during image signal transmission, an image signal transmission circuit with stable data transmission is proposed. Utility Model Content

[0005] The purpose of the utility model is to provide an image signal transmission circuit with stable data transmission to solve the problems raised in the above background technology.

[0006] To achieve the above object, the utility model provides an image signal transmission circuit with stable data transmission, comprising a coding and decoding unit and a transmission unit, wherein the coding and decoding unit comprises a coding module arranged at a transmitting end and a decoding module arranged at a receiving end, and the transmission unit comprises a suppression module, a transmitting module and a receiving module, wherein the coding module is connected to the suppression module, the suppression module is connected to the transmitting module, and the receiving module is connected to the decoding module;

[0007] The image signal encoded by the encoding module is transmitted outwardly by the transmitting module, and is decoded by the decoding module after being received by the receiving module. The suppression module realizes common mode suppression of the signal and performs radio frequency rectification.

[0008] As a further improvement of the present technical solution, the suppression module includes a low-pass filter circuit for filtering out common mode noise and a radio frequency integration circuit for amplifying the signal, the encoding module is connected to the low-pass filter circuit, the low-pass filter circuit is connected to the radio frequency integration circuit, and the radio frequency integration circuit is connected to the transmitting module.

[0009] As a further improvement of the technical solution, the low-pass filter circuit includes a chip U1,

[0010] The chip U1 is connected to resistors R1 and R2 and capacitors C1, C2 and C3. The resistors R1 and R2 are both connected to the encoding module. The capacitor C1 is connected to the other end of the capacitor C3 and grounded. The capacitors C1 and C3 are connected in parallel with the capacitor C2.

[0011] As a further improvement of the technical solution, the RF integration circuit includes transistors T1 and T2, wherein:

[0012] The base of the transistor T1 is connected to the resistor R11, the resistor R11 is connected to the OUT terminal of the chip U1, the collector of the transistor T1 is connected to the resistor R13 and connected to the resistor R15, the resistor R13 is connected to the resistor R14 and connected to the VCC terminal, the emitter of the transistor T1 is connected to the resistor R16 and connected to the emitter of the transistor T2;

[0013] The base of the transistor T2 is connected to the resistor R12, the resistor R12 is grounded, and the collector of the transistor T2 is connected to the other end of the resistor R14 and the other end of the resistor R15.

[0014] As a further improvement of the technical solution, the transmitting module includes a chip U2,

[0015] The Vss pin of the chip U2 is grounded, the VDD pin of the chip U2 is connected to the VCC terminal, the OSC1 pin of the chip U2 is connected to the resistor R23, and the resistor R23 is connected to the OSC2 pin of the chip U2;

[0016] The Dout pin of the chip U2 is connected to the resistor R21, the resistor R21 is connected to the base of the transistor Q1 and connected to the crystal oscillator SA, the collector of the transistor Q1 is connected to the capacitors C21 and C23 and connected to the inductor L1, the inductor L1 is connected to the VCC terminal, the capacitor C23 is connected to the antenna, the emitter of the transistor Q1 is connected to the resistor R22, the capacitor C22 and the other end of the capacitor C21, the resistor R22 is connected to the other end of the crystal oscillator SA, the other end of the capacitor C22 and grounded.

[0017] As a further improvement of the technical solution, the receiving module includes chips U3 and U4.

[0018] The Vss pin of the chip U3 is grounded, the VDD pin of the chip U3 is connected to the VCC terminal and to the 8th pin of the chip U4, the OSC1 pin of the chip U3 is connected to the resistor R35, and the resistor R35 is connected to the OSC2 pin of the chip U3;

[0019] Pin 1 of the chip U4 is connected to the DIN pin of the chip U3 and connected in parallel to resistor R34, pins 2 and 4 of the chip U4 are connected to resistor R33 and connected in parallel to resistor R34, the resistor R33 is grounded, pin 3 of the chip U4 is connected to resistor R32, the resistor R32 is connected to diode VD, resistor R31 and connected in parallel to capacitor C25, and the diode VD is connected to a filter.

[0020] Compared with the prior art, the utility model has the following beneficial effects:

[0021] In the image signal transmission circuit with stable data transmission, the transmitting end performs signal encoding processing on the generated image data through the encoding module, and the suppression module performs common-mode suppression on the signal and performs radio frequency rectification processing. The transmitting module and the receiving module realize signal transmission, and the decoding module decodes the received signal to reduce the interference effect on the image signal during transmission and avoid damage to the transmitted data. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a schematic diagram of the overall structure of the utility model;

[0023] Figure 2 This is a low-pass filter circuit diagram of the utility model;

[0024] Figure 3 The radio frequency integrated circuit diagram of the utility model;

[0025] Figure 4 This is a circuit diagram of a transmitting module of the utility model;

[0026] Figure 5 This is a circuit diagram of a receiving module of the present utility model. DETAILED DESCRIPTION

[0027] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0028] See also Figure 1-Figure 5 As shown, this embodiment provides an image signal transmission circuit with stable data transmission, including a coding and decoding unit and a transmission unit, the coding and decoding unit includes a coding module arranged at a transmitting end and a decoding module arranged at a receiving end, the transmission unit includes a suppression module, a transmitting module and a receiving module, the coding module is connected to the suppression module, the suppression module is connected to the transmitting module, and the receiving module is connected to the decoding module;

[0029] The image signal encoded by the encoding module is transmitted outward by the transmitting module, and is decoded by the decoding module after being received by the receiving module. The suppression module realizes common-mode suppression of the signal and performs RF rectification.

[0030] Principle: The transmitting end will encode the generated image data through the encoding module, and then suppress the common mode of the signal and perform RF rectification through the suppression module. The transmitting module and the receiving module will realize signal transmission, and the decoding module will decode the received signal.

[0031] The suppression module includes a low-pass filter circuit for filtering common mode noise and a radio frequency integration circuit for amplifying signals. The encoding module is connected to the low-pass filter circuit, the low-pass filter circuit is connected to the radio frequency integration circuit, and the radio frequency integration circuit is connected to the transmitting module.

[0032] The low-pass filter circuit includes chip U1,

[0033] The chip U1 is connected to the resistors R1 and R2 and to the capacitors C1, C2 and C3. The resistors R1 and R2 are both connected to the encoding module. The capacitor C1 is connected to the other end of the capacitor C3 and to the ground. The capacitors C1 and C3 are connected in parallel with the capacitor C2.

[0034] Chip U1 is an AD8221 amplifier chip. Capacitor C2 forms a bypass for capacitors C1 and C3, which can effectively reduce the AC common-mode rejection error caused by component mismatch in the circuit and eliminate the interference error of the signal before the signal is amplified by the RF integration circuit.

[0035] The RF integrated circuit includes transistors T1 and T2, where:

[0036] The base of transistor T1 is connected to resistor R11, resistor R11 is connected to the OUT terminal of chip U1, the collector of transistor T1 is connected to resistor R13 and resistor R15, resistor R13 is connected to resistor R14 and connected to the VCC terminal, the emitter of transistor T1 is connected to resistor R16 and connected to the emitter of transistor T2;

[0037] The base of the transistor T2 is connected to the resistor R12, the resistor R12 is grounded, and the collector of the transistor T2 is connected to the other end of the resistor R14 and in parallel to the other end of the resistor R15.

[0038] This circuit is a differential amplifier circuit with single-ended input and double-ended output. The base of transistor T2 is grounded, and the base of transistor T1 is connected to the input signal. The input signal is transmitted from the emitter circuit of transistor T1 to the emitter of transistor T2 by connecting the emitters to perform emitter coupling.

[0039] The transmitting module includes chip U2,

[0040] The Vss pin of chip U2 is grounded, the VDD pin of chip U2 is connected to the VCC terminal, the OSC1 pin of chip U2 is connected to resistor R23, and the resistor R23 is connected to the OSC2 pin of chip U2;

[0041] The Dout pin of chip U2 is connected to resistor R21, resistor R21 is connected to the base of transistor Q1 and to the crystal oscillator SA, the collector of transistor Q1 is connected to capacitors C21, C23 and to inductor L1, inductor L1 is connected to the VCC terminal, capacitor C23 is connected to the antenna, the emitter of transistor Q1 is connected to resistor R22, capacitor C22 and the other end of capacitor C21, resistor R22 is connected to the other end of crystal oscillator SA, the other end of capacitor C22 and grounded.

[0042] The receiving module includes chips U3 and U4.

[0043] The Vss pin of chip U3 is grounded, the VDD pin of chip U3 is connected to the VCC terminal and to the 8th pin of chip U4, the OSC1 pin of chip U3 is connected to the resistor R35, and the resistor R35 is connected to the OSC2 pin of chip U3;

[0044] Pin 1 of chip U4 is connected to the DIN pin of chip U3 and connected in parallel to resistor R34. Pins 2 and 4 of chip U4 are connected to resistors R33 and R34 in parallel. Resistor R33 is grounded. Pin 3 of chip U4 is connected to resistor R32. Resistor R32 is connected to diode VD, resistor R31 and capacitor C25 in parallel. Diode VD is connected to the filter.

[0045] Chip U2 is a PT2262 transmitter chip, chip U3 is a PT2272 receiver chip, and chip U4 is an LM358 amplifier. The microcontroller outputs a serial pulse signal through the Dout pin of chip U2 as a modulated signal and sends it outward. After being received by the filter, the received signal is detected by diode VD, capacitor C25 and resistor R32, and then sent to the DIN pin of chip U3 through chip U4.

[0046] The present embodiment is an image signal transmission circuit with stable data transmission. When in specific use, the transmitting end performs signal encoding processing on the generated image data through the encoding module, and then performs common-mode suppression on the signal through the low-pass filtering circuit of the suppression module, thereby reducing the AC common-mode suppression error caused by component mismatch in the circuit, eliminating the interference error of the signal before the signal is amplified by the RF integration circuit, and after differential amplification by the RF integration circuit, the transmission module and the receiving module realize signal transmission, and the decoding module decodes the received signal, thereby reducing the interference effect on the image signal during transmission and avoiding damage to the transmitted data.

[0047] The above shows and describes the basic principle, main features and advantages of the utility model. Those skilled in the art should understand that the utility model is not limited by the above embodiments. The above embodiments and descriptions are only preferred examples of the utility model and are not used to limit the utility model. Without departing from the spirit and scope of the utility model, the utility model may have various changes and improvements, which fall within the scope of the utility model to be protected. The scope of protection of the utility model is defined by the attached claims and their equivalents.

Claims

1. An image signal transmission circuit with stable data transmission, characterized in that: It includes a coding unit and a transmission unit, wherein the coding unit includes a coding module arranged at a transmitting end and a decoding module arranged at a receiving end, and the transmission unit includes a suppression module, a transmitting module and a receiving module, wherein the coding module is connected to the suppression module, the suppression module is connected to the transmitting module, and the receiving module is connected to the decoding module; The image signal encoded by the encoding module is transmitted outwardly by the transmitting module, and is decoded by the decoding module after being received by the receiving module. The suppression module realizes common mode suppression of the signal and performs radio frequency rectification.

2. The image signal transmission circuit with stable data transmission according to claim 1, characterized in that: The suppression module includes a low-pass filter circuit for filtering common mode noise and a radio frequency integration circuit for amplifying signals, the encoding module is connected to the low-pass filter circuit, the low-pass filter circuit is connected to the radio frequency integration circuit, and the radio frequency integration circuit is connected to the transmitting module.

3. The image signal transmission circuit with stable data transmission according to claim 2, characterized in that: The low-pass filter circuit includes a chip U1, The chip U1 is connected to resistors R1 and R2 and capacitors C1, C2 and C3. The resistors R1 and R2 are both connected to the encoding module. The capacitor C1 is connected to the other end of the capacitor C3 and grounded. The capacitors C1 and C3 are connected in parallel with the capacitor C2.

4. The image signal transmission circuit with stable data transmission according to claim 3, characterized in that: The radio frequency integrated circuit includes transistors T1 and T2, wherein: The base of the transistor T1 is connected to the resistor R11, the resistor R11 is connected to the OUT terminal of the chip U1, the collector of the transistor T1 is connected to the resistor R13 and connected to the resistor R15, the resistor R13 is connected to the resistor R14 and connected to the VCC terminal, the emitter of the transistor T1 is connected to the resistor R16 and connected to the emitter of the transistor T2; The base of the transistor T2 is connected to the resistor R12, the resistor R12 is grounded, and the collector of the transistor T2 is connected to the other end of the resistor R14 and the other end of the resistor R15.

5. The image signal transmission circuit with stable data transmission according to claim 1, characterized in that: The transmitting module includes a chip U2, The Vss pin of the chip U2 is grounded, the VDD pin of the chip U2 is connected to the VCC terminal, the OSC1 pin of the chip U2 is connected to the resistor R23, and the resistor R23 is connected to the OSC2 pin of the chip U2; The Dout pin of the chip U2 is connected to the resistor R21, the resistor R21 is connected to the base of the transistor Q1 and connected to the crystal oscillator SA, the collector of the transistor Q1 is connected to the capacitors C21 and C23 and connected to the inductor L1, the inductor L1 is connected to the VCC terminal, the capacitor C23 is connected to the antenna, the emitter of the transistor Q1 is connected to the resistor R22, the capacitor C22 and the other end of the capacitor C21, the resistor R22 is connected to the other end of the crystal oscillator SA, the other end of the capacitor C22 and grounded.

6. The image signal transmission circuit with stable data transmission according to claim 1, characterized in that: The receiving module includes chips U3 and U4. The Vss pin of the chip U3 is grounded, the VDD pin of the chip U3 is connected to the VCC terminal and to the 8th pin of the chip U4, the OSC1 pin of the chip U3 is connected to the resistor R35, and the resistor R35 is connected to the OSC2 pin of the chip U3; Pin 1 of the chip U4 is connected to the DIN pin of the chip U3 and connected in parallel to resistor R34, pins 2 and 4 of the chip U4 are connected to resistor R33 and connected in parallel to resistor R34, the resistor R33 is grounded, pin 3 of the chip U4 is connected to resistor R32, the resistor R32 is connected to diode VD, resistor R31 and connected in parallel to capacitor C25, and the diode VD is connected to a filter.

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