Semiconductor device, memory system, and electronic apparatus

Abstract

The utility model discloses a semiconductor device, a storage system and electronic equipment. The semiconductor device comprises a first electrode, a storage layer and a second electrode. The storage layer comprises a first surface and a second surface which are oppositely arranged, and a first side surface connected between the first surface and the second surface, the first electrode is located on one side of the first surface, and the second electrode is located on one side of the second surface; wherein the storage layer is a bidirectional threshold switch layer, and the semiconductor device further comprises a first protection layer covering the first side surface; according to the utility model, the first side surface of the storage layer can be protected, the probability of oxidation, etching damage and electric leakage of the storage layer is reduced, the threshold conversion voltage drift phenomenon of the semiconductor device is improved, and the electrical stability and the yield of the semiconductor device are improved.

Description

Technical Field

[0001] The utility model relates to the field of semiconductor technology, and in particular to a semiconductor device, a storage system and an electronic device. Background Art

[0002] An ovonic threshold switch (OTS) is a switching device designed based on bidirectional materials (e.g., chalcogenides). Currently, OTS has been used in various programmable resistive memories, particularly selector-only memories (SOMs). In SOMs, the OTS gating material serves as the storage medium, enabling the memory's read and write functions.

[0003] However, in SOM memories that use OTS gating materials as storage layers, the sidewalls of the storage layers lack effective protection for the storage cells, making them susceptible to oxidation and etching damage during the manufacturing process. This can easily lead to leakage during testing and use, affecting the electrical properties of the storage layers. Utility Model Content

[0004] The embodiments of the present invention provide a semiconductor device, a storage system, and an electronic device, which can improve the protection of the first side of the storage layer, reduce the probability of oxidation, etching damage, and leakage of the storage layer, improve the threshold transition voltage drift phenomenon of the semiconductor device, and improve the yield of the semiconductor device.

[0005] An embodiment of the present invention provides a semiconductor device comprising a first electrode, a storage layer, and a second electrode;

[0006] The storage layer includes a first surface and a second surface opposite to each other, and a first side surface connected between the first surface and the second surface, the first electrode is located on one side of the first surface, and the second electrode is located on one side of the second surface;

[0007] Wherein, the storage layer is a bidirectional threshold switch layer, and the semiconductor device further includes a first protective layer covering the first side surface.

[0008] In some embodiments of the present invention, the first protection layer is disposed around the storage layer and covers the first side surface.

[0009] In some embodiments of the present invention, the first electrode includes a third surface facing the storage layer and a second side surface connected to the third surface, the second electrode includes a fourth surface facing the storage layer and a third side surface connected to the fourth surface, and the first protective layer also covers the second side surface and the third side surface, and is arranged around the first electrode and the second electrode.

[0010] In some embodiments of the present invention, the semiconductor device further includes a second protection layer, and the second protection layer is located on a side of the first protection layer away from the storage layer.

[0011] In some embodiments of the present invention, the first protective layer includes a first protective sublayer and a second protective sublayer, two second protective sublayers disposed opposite and spaced apart are located between two first protective sublayers disposed opposite and spaced apart, the first electrode, the storage layer, and the second electrode are located in a cavity formed by the first protective sublayer and the second protective sublayer, and the first protective sublayer and the second protective sublayer respectively cover the first side surface;

[0012] The first protective sublayer protrudes from the second protective sublayer at both ends along a first direction, the first direction being the extension direction of the first protective sublayer in a top view, and the second protective layer is located on a side of the first protective sublayer and the second protective sublayer away from the storage layer.

[0013] In some embodiments of the present invention, the second protective layer includes a third protective sublayer and a fourth protective sublayer, the third protective sublayer is located on the side of the first protective sublayer away from the storage layer, the two ends of the third protective sublayer in the first direction are flush with the two ends of the first protective sublayer in the first direction, and the fourth protective sublayer is located on the side of the second protective sublayer away from the storage layer and is connected to the two ends of the first protective sublayer protruding from the second protective sublayer.

[0014] In some embodiments of the present invention, the first electrode is in contact with the first surface, and the second electrode is in contact with the second surface;

[0015] Alternatively, the semiconductor device further includes a barrier layer, wherein the barrier layer is located between the first electrode and the storage layer, and / or the barrier layer is located between the second electrode and the storage layer.

[0016] In some embodiments of the present invention, the semiconductor device further includes a word line and a bit line, the first electrode is connected to one of the word line and the bit line, and the second electrode is connected to the other of the word line and the bit line.

[0017] According to the above-mentioned purpose of the present invention, an embodiment of the present invention further provides a storage system, which includes a controller and the semiconductor device. The controller is coupled to the semiconductor device to control the semiconductor device.

[0018] According to the above-mentioned purpose of the present invention, an embodiment of the present invention further provides an electronic device, which includes the storage system.

[0019] The embodiments of the present invention provide a semiconductor device, a storage system, and an electronic device. A first protective layer is provided on the first side of the storage layer to protect the first side of the storage layer, thereby reducing the probability of oxidation, etching damage, and leakage of the storage layer, improving the threshold transition voltage drift phenomenon of the semiconductor device, and improving the electrical stability and yield of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The technical solutions and other beneficial effects of the present invention will be made apparent by describing in detail the specific embodiments of the present invention in conjunction with the accompanying drawings.

[0021] Figure 1 A schematic structural diagram of a semiconductor device provided by an embodiment of the present utility model;

[0022] Figure 2 A schematic diagram of the circuit structure of a semiconductor device provided in an embodiment of the present utility model;

[0023] Figure 3 Another structural schematic diagram of a semiconductor device provided by an embodiment of the present utility model;

[0024] Figure 4 A schematic diagram of a top view of a semiconductor device provided by an embodiment of the present utility model;

[0025] Figure 5 A schematic diagram of the structure of a storage system provided by an embodiment of the present utility model;

[0026] Figure 6 A schematic structural diagram of an electronic device provided in an embodiment of the present utility model. DETAILED DESCRIPTION

[0027] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0028] The disclosure below provides many different embodiments or examples for realizing different structures of the present invention. In order to simplify the disclosure of the present invention, the components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. In addition, the present invention may repeat reference numbers and / or reference letters in different examples. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present invention provides examples of various specific processes and materials, but a person of ordinary skill in the art will recognize the application of other processes and / or the use of other materials.

[0029] Please refer to Figure 1 An embodiment of the present invention provides a semiconductor device, which includes a first electrode 11 , a storage layer 13 and a second electrode 12 .

[0030] The storage layer 13 includes a first surface 131 and a second surface 132 arranged opposite to each other, and a first side surface 133 connected between the first surface 131 and the second surface 132. The first electrode 11 is located on one side of the first surface 131, and the second electrode 12 is located on one side of the second surface 132.

[0031] In some embodiments, the storage layer 13 is a bidirectional threshold switch layer. It is understood that the storage layer 13 is an ovonic threshold switch (OTS). OTS is used in various programmable memories (e.g., SOMs). In SOMs, the OTS gating material serves as the storage medium to implement the read and write functions of the memory.

[0032] The semiconductor device further includes a first protective layer 21 covering the first side surface 133. During implementation, the embodiment of the utility model provides the first protective layer 21 on the first side surface 133 of the storage layer 13 to protect the first side surface 133 of the storage layer 13, thereby reducing the probability of oxidation, etching damage, and leakage of the storage layer 13, and improving the electrical stability and yield of the semiconductor device.

[0033] Please continue to refer to Figure 1 The semiconductor device provided by the embodiment of the present invention includes a plurality of memory cells 10, and each of the memory cells 10 may include the first electrode 11 and the second electrode 12 arranged opposite to each other, and the storage layer 13 arranged between the first electrode 11 and the second electrode 12.

[0034] It should be noted that when a voltage pulse in a predetermined direction is applied between the first electrode 11 and the second electrode 12, the semiconductor device is in a SET state (low-resistance state) with a low first threshold transition voltage. Subsequently, when a voltage pulse in a direction opposite to the predetermined direction is applied, the semiconductor device is reset to a high-resistance state (RESET state) with a high second threshold transition voltage. Furthermore, during the reading process of the semiconductor device, by applying a value between the first threshold transition voltage and the second threshold transition voltage between the first electrode 11 and the second electrode 12, it is possible to read whether the semiconductor device is in the SET or RESET state.

[0035] In some embodiments, the storage layer 13 contains a chalcogenide, such as a compound of arsenic (As), selenium (Se) and germanium (Ge) (AsSeGe), a compound of arsenic (As), selenium (Se), germanium (Ge) and silicon (Si) (AsSeGeSi), a compound of arsenic (As), selenium (Se), germanium (Ge), silicon (Si) and indium (In) (AsSeGeSiIn), and a compound of arsenic (As), selenium (Se), germanium (Ge) and indium (In) (AsSeGeIn).

[0036] Please continue to refer to Figure 1 、 Figure 2 and Figure 3 In some embodiments, the semiconductor device further includes a bit line 31 and a word line 32, and the first electrode 11 is connected to one of the bit line 31 and the word line 32, and the second electrode 12 is connected to the other of the bit line 31 and the word line 32; the diagram provided in the present invention takes the example of the first electrode 11 being connected to the bit line 31 and the second electrode 12 being connected to the word line 32 for explanation.

[0037] Please combine Figure 1 as well as Figure 2 The bit line 31 and the word line 32 are used to load signals to the first electrode 11 and the second electrode 12, respectively, and in the semiconductor device, the plurality of memory cells 10 can be arranged in an array, and the plurality of memory cells 10 in the same row can be connected to the same word line 32 and to different bit lines 31, and the plurality of memory cells 10 in the same column can be connected to the same bit line 31 and to different word lines 32.

[0038] In some embodiments, the first electrode 11 may be in contact with the first surface 131, and the second electrode 12 may be in contact with the second surface 132, that is, the storage layer 13 is directly arranged between the first electrode 11 and the second electrode 12, the first electrode 11 is directly connected to the storage layer 13, and the second electrode 12 is also directly connected to the storage layer 13.

[0039] In other embodiments, please refer to Figure 3 , the semiconductor device also includes a barrier layer 40, and the barrier layer 40 is located between the first electrode 11 and the storage layer 13, and / or the barrier layer 40 is located between the second electrode 12 and the storage layer 13; that is, the semiconductor device may include one layer of the barrier layer 40, and it may be located between the first electrode 11 and the storage layer 13 or between the second electrode 12 and the storage layer 13; or the semiconductor device may include two layers of the barrier layer 40, and the two layers of the barrier layer 40 are respectively located between the first electrode 11 and the storage layer 13 and between the second electrode 12 and the storage layer 13.

[0040] For example, the barrier layer 40 includes a first barrier layer 41 and a second barrier layer 42 , wherein the first barrier layer 41 is located between the first electrode 11 and the storage layer 13 , and the second barrier layer 42 is located between the second electrode 12 and the storage layer 13 .

[0041] In some embodiments, the barrier layer 40 can be used to prevent materials in the first electrode 11 and the second electrode 12 from diffusing into the storage layer 13, thereby reducing the probability of the semiconductor device short-circuiting or failing to shut down. The barrier layer 40 has a thickness of 5 to 50 nanometers. For example, the barrier layer can be a conductive material layer with a thickness of 20 nanometers. The barrier layer 40 can contain carbon, a combination of silicon and carbon, or other materials. When the barrier layer 40 is made of other materials, it may be a metal nitride, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), niobium nitride (NbN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), titanium boron nitride (TiBN), zirconium silicon nitride (ZrSiN), tungsten silicon nitride (WSiN), tungsten boron nitride (WBN), zirconium aluminum nitride (ZrAlN), molybdenum silicon nitride (MoSiN), molybdenum aluminum nitride (WAIN), tantalum silicon nitride (TaSiN) or tantalum aluminum nitride (TaAlN). In addition to metal nitride, the barrier layer 40 may also include materials such as doped polysilicon, tungsten (W), copper (Cu), titanium (Ti), molybdenum (Mo), tantalum (Ta), titanium silicide (TiSi), tantalum silicide (TaSi), titanium tungsten (TiW), titanium oxynitride (TiON), titanium aluminum oxynitride (TiAlON), tungsten oxynitride (WON), or tantalum oxynitride (TaON).

[0042] In the related art, since the storage unit 10 lacks effective protection at the side wall of the OTS storage layer, leakage is easily generated at the side wall of the OTS storage layer, and oxidation and etching damage are generated during the process, resulting in the drift of the threshold transition voltage of the OTS storage layer, thereby affecting its electrical properties; therefore, the semiconductor device provided by the embodiment of the present invention also includes the first protective layer 21, and the first protective layer 21 covers the first side surface 133 of the storage layer 13 to protect the first side surface 133 of the storage layer 13, reduce the probability of oxidation, etching damage and leakage of the storage layer 13, improve the threshold transition voltage drift phenomenon of the semiconductor device, and improve the electrical stability and yield of the semiconductor device.

[0043] Please combine Figure 1 as well as Figure 4 In some embodiments, the first protective layer 21 is arranged around the storage layer 13 and covers the first side surface 133 , that is, the first protective layer 21 covers the entire first side surface 133 of the storage layer 13 to better protect the storage layer 13 .

[0044] In some embodiments, the first electrode 11 includes a third surface 111 facing the storage layer 13 and a second side 112 connected to the third surface 111, the second electrode 12 also includes a fourth surface 121 facing the storage layer 13 and a third side 122 connected to the fourth surface 121, the first protective layer 21 also covers the second side 112 and the third side 122, and is arranged around the first electrode 11 and the second electrode 12, that is, the first protective layer 21 surrounds the storage unit 10 and covers the side wall of the storage unit 10 to provide protection for the side of the entire storage unit 10.

[0045] In some embodiments, the first protective layer 21 contains a nitride, such as silicon nitride, and the first protective layer 21 can be synthesized using a silicon precursor and an ammonia precursor, wherein the silicon precursor can include SiCl4, silane (SiH4), trimethylsilylamine (TSA, N(SiH3)3), neopentasilane (NPS, (SiH3)4Si), iodosilane, bromosilane, alkylaminosilane (for example, SiH(N(CH3)2)3, (SiH2(NHtBu)2), C9H 29 N3Si3、C6H 17 NSi、C9H 25 N3Si、C8H 22 N2Si) or a combination thereof, and the ammonia precursor may include ammonia (NH3), hydrazine (N2H4) or a combination thereof; further preferably, the ammonia precursor may be ammonia. Since ammonia is more easily reacted, the generated silicon nitride film is denser, which can effectively improve the protective effect of the first protective layer 21, further reduce the probability of oxidation, etching damage and leakage of the storage layer 13, and improve the electrical stability and yield of the semiconductor device.

[0046] In some embodiments, after the first protective layer 21 is formed, in order to obtain a denser film layer, helium gas can be used to form plasma to treat the first protective layer 21, thereby filling the defective gaps in the first protective layer 21 and forming the first protective layer 21 with high quality and high density.

[0047] In some embodiments, the thickness of the first protection layer 21 may be greater than or equal to 0.5 nm and less than or equal to 5 nm.

[0048] The storage unit 10 may be quadrilateral in a top view, and the first protection layer 21 continuously surrounds four sides of the storage unit 10 .

[0049] In some embodiments, the first protective layer 21 includes a first protective sublayer 211 and a second protective sublayer 212, and the two second protective sublayers 212 that are opposite to and spaced apart from each other are located between the two first protective sublayers 211 that are opposite to and spaced apart from each other, and the two first protective sublayers 211 and the two second protective sublayers 212 surround and form a cavity; the first electrode 11, the storage layer 13 and the second electrode 12 are located in the cavity formed by the first protective sublayer 211 and the second protective sublayer 212, and the first protective sublayer 211 and the second protective sublayer 212 respectively cover the first side surface 133.

[0050] In some embodiments, the first protection sublayer 211 is along Figure 4 The second protective sublayer 212 extends in the first direction X. Figure 4 The first direction is the extending direction of the first protective sub-layer 211 in a top view, and the second direction Y is the extending direction of the second protective sub-layer 212 in a top view.

[0051] In some embodiments, the first protective sublayer 211 is made of ammonia, or the second protective sublayer 212 is made of ammonia, or both the first protective sublayer 211 and the second protective sublayer 212 are made of ammonia.

[0052] In some embodiments, please combine Figure 2 as well as Figure 4 , the first direction X may be the extending direction of the word line 32 , and the second direction Y may be the extending direction of the bit line 31 .

[0053] In some embodiments, the first protective sublayer 211 is treated with helium plasma after being formed, or the second protective sublayer 212 is treated with helium plasma after being formed, or both the first protective sublayer 211 and the second protective sublayer 212 are treated with helium plasma after being formed.

[0054] In some embodiments, the first protection layer 21 further covers side surfaces of the bit line 31 and the word line 32 .

[0055] In some embodiments, the semiconductor device further includes a second protection layer 22 , where the second protection layer 22 is located on a side of the first protection layer 21 away from the storage layer 13 .

[0056] Furthermore, the second protection layer 22 covers a side of the first protection layer 21 away from the storage layer 13 , the first electrode 11 , and the second electrode 12 .

[0057] Furthermore, the second protection layer 22 also covers a side of the first protection layer 21 away from the bit line 31 and the word line 32 .

[0058] In some embodiments, the second protective layer 22 is located on the side of the first protective sublayer 211 and the second protective sublayer 212 away from the storage layer 13; specifically, the second protective layer 22 includes a third protective sublayer 221 and a fourth protective sublayer 222, the third protective sublayer 221 is located on the side of the first protective sublayer 211 away from the storage layer 13, and the fourth protective sublayer 222 is located on the side of the second protective sublayer 212 away from the storage layer 13.

[0059] In some embodiments, the second protection layer 22 may continuously cover a side of the first protection layer 21 away from the storage layer 13 .

[0060] In other embodiments, please combine Figure 1 and Figure 4 The second protective layer 22 may also discontinuously cover the side of the first protective layer 21 away from the storage layer 13; wherein, both ends of the first protective sub-layer 211 in the first direction X protrude from the second protective sub-layer 212, both ends of the third protective sub-layer 221 in the first direction X are flush with the both ends of the first protective sub-layer 211 in the first direction, and the fourth protective sub-layer 222 is connected to the both ends of the first protective sub-layer 211 that protrude from the second protective sub-layer 212. The both ends of the first protective sub-layer 211 that protrude from the second protective sub-layer 212 in the first direction X do not extend beyond the surface of the second protective layer 22 away from the first protective layer 21, thereby forming a flat surface on the side of the second protective layer 22 away from the first protective layer 21.

[0061] In some embodiments, the thickness of the second protection layer 22 may be greater than or equal to 0.5 nm and less than or equal to 5 nm.

[0062] It should be noted that a thermal insulation material is also provided between the multiple storage cells 10 in the semiconductor device, that is, between adjacent storage cells 10, the second protective layer 22 surrounding one of the storage cells 10 and the second protective layer 22 surrounding another storage cell 10 are filled with the thermal insulation material. The thermal insulation material is a special material containing carbon (C), nitrogen (N), and (O), which has good filling properties and thermal insulation effects, and can serve to separate and protect the multiple storage cells 10.

[0063] In some embodiments, the second protective layer 22 contains an oxide, such as silicon oxide. The second protective layer 22 can also serve as an adhesion enhancement layer. The second protective layer 22 has high density, which can not only protect the material in the storage unit 10 from oxidation, but also increase the adhesion between the second protective layer 22 and the thermal insulation material.

[0064] Continuing from the above, the present invention provides the first protective layer 21 on the first side surface 133 of the storage layer 13 to protect the first side surface 133 of the storage layer 13, thereby reducing the probability of oxidation, etching damage and leakage of the storage layer 13, and improving the electrical stability and yield of the semiconductor device.

[0065] In addition, the present invention also provides a storage system. Figure 5 The storage system 50 includes the semiconductor device 51 described in the above embodiment, and the semiconductor device 51 can be a memory or a part of a memory. In the embodiment of the present utility model, the semiconductor device 51 is taken as an example of a memory for explanation.

[0066] In some embodiments, the storage system 50 further includes the controller 52, which is coupled to the semiconductor device 51 and is used to control the semiconductor device 51 to store data, and the semiconductor device 51 is a semiconductor device manufactured by the semiconductor device manufacturing method described in the above embodiments or the semiconductor device described in the above embodiments.

[0067] In some embodiments, the controller 52 can control the semiconductor device 51 via a channel CH, and the semiconductor device 51 can perform operations based on the control of the controller 52 in response to a request from the host. The semiconductor device 51 can receive a command CMD and an address ADDR from the controller 52 via the channel CH and access a region selected from the memory array in response to the address. In other words, the semiconductor device 51 can perform internal operations corresponding to the command on the region selected by the address.

[0068] In some embodiments, the storage system 50 may be implemented as a storage device including but not limited to a universal flash storage (UFS) device, a solid-state drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC and micro MMC, a secure digital card in the form of SD, mini SD and micro SD, a Personal Computer Memory Card International Association (PCMCIA) card type, a peripheral component interconnect (PCI) type storage device, a high-speed PCI (PCI-E) type storage device, a compact flash (CF) card, a high-speed computing interconnect (Compute Express Link, CXL), a high-bandwidth memory (High Bandwidth Memory, HBM), a smart media card or a memory stick, etc.

[0069] In some embodiments, the storage system 50 can be used in terminal products such as computers, televisions, set-top boxes, and vehicles.

[0070] Please refer to Figure 6 Some embodiments of the present invention further provide an electronic device 60, which includes the storage system 50, and the storage system 50 is the storage system described in the above embodiments of the present invention. Specifically, the electronic device 60 may include but is not limited to mobile phones, desktop computers, tablet computers, laptops, servers, vehicle-mounted devices, wearable devices, mobile power supplies, and any other device that can store data.

[0071] Some embodiments of the present invention provide an electronic device, which has the same beneficial effects as the above-mentioned storage system due to the provision of the storage system provided by some embodiments of the present invention.

[0072] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0073] The above is a detailed introduction to a semiconductor device, a storage system, and an electronic device provided by the embodiments of the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present invention. Those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor device, characterized in that: comprising a first electrode, a storage layer and a second electrode; The storage layer includes a first surface and a second surface that are opposite to each other, and a first side surface connected between the first surface and the second surface, the first electrode is located on one side of the first surface, and the second electrode is located on one side of the second surface; Wherein, the storage layer is a bidirectional threshold switch layer, and the semiconductor device further includes a first protective layer covering the first side surface.

2. The semiconductor device according to claim 1, wherein: The first protection layer is disposed around the storage layer and covers the first side surface.

3. The semiconductor device according to claim 2, characterized in that The first electrode includes a third surface facing the storage layer and a second side connected to the third surface, the second electrode includes a fourth surface facing the storage layer and a third side connected to the fourth surface, the first protective layer also covers the second side and the third side, and is arranged around the first electrode and the second electrode.

4. The semiconductor device according to claim 1, wherein: The semiconductor device further includes a second protection layer, which is located on a side of the first protection layer away from the storage layer.

5. The semiconductor device according to claim 4, characterized in that The first protective layer includes a first protective sublayer and a second protective sublayer, two second protective sublayers opposite to each other and spaced apart are located between two first protective sublayers opposite to each other and spaced apart, the first electrode, the storage layer and the second electrode are located in a cavity formed by the first protective sublayer and the second protective sublayer, and the first protective sublayer and the second protective sublayer respectively cover the first side surface; Among them, both ends of the first protective sublayer along the first direction protrude from the second protective sublayer, the first direction is the extension direction of the first protective sublayer in a top view, and the second protective layer is located on the side of the first protective sublayer and the second protective sublayer away from the storage layer.

6. The semiconductor device according to claim 5, characterized in that The second protective layer includes a third protective sublayer and a fourth protective sublayer. The third protective sublayer is located on a side of the first protective sublayer away from the storage layer, and both ends of the third protective sublayer in the first direction are flush with both ends of the first protective sublayer in the first direction. The fourth protective sublayer is located on a side of the second protective sublayer away from the storage layer and is connected to both ends of the first protective sublayer protruding from the second protective sublayer.

7. The semiconductor device according to claim 1, wherein: The first electrode is in contact with the first surface, and the second electrode is in contact with the second surface; Alternatively, the semiconductor device further includes a barrier layer, wherein the barrier layer is located between the first electrode and the storage layer, and / or the barrier layer is located between the second electrode and the storage layer.

8. The semiconductor device according to claim 1, wherein: The semiconductor device further includes a word line and a bit line, the first electrode is connected to one of the word line and the bit line, and the second electrode is connected to the other of the word line and the bit line.

9. A storage system, characterized in that: The storage system includes a controller and the semiconductor device according to any one of claims 1 to 8, wherein the controller is coupled to the semiconductor device to control the semiconductor device.

10. An electronic device, characterized in that: The electronic device comprises the storage system according to claim 9.

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